Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49875

1

T1

130

T2

490

T5

28

auto[1]

17640

1

T1

19

T31

3

T32

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49630

1

T1

100

T2

333

T5

15

auto[1]

17885

1

T1

49

T2

157

T5

13

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34874	1			T1	69		T2	243		T5	18
others[1]	5728	1			T1	18		T2	44		T5	1
others[2]	5667	1			T1	12		T2	43		T5	2
others[3]	6347	1			T1	17		T2	41		T5	4
interest[1]	3688	1			T1	3		T2	30		T8	10
interest[4]	22788	1			T1	52		T2	163		T5	12
interest[64]	11211	1			T1	30		T2	89		T5	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16375	1			T1	43		T2	162		T5	10
auto[0]	auto[0]	others[1]	2721	1			T1	11		T2	29		T8	16
auto[0]	auto[0]	others[2]	2692	1			T1	5		T2	32		T8	7
auto[0]	auto[0]	others[3]	3032	1			T1	7		T2	29		T5	3
auto[0]	auto[0]	interest[1]	1759	1			T1	1		T2	22		T8	9
auto[0]	auto[0]	interest[4]	10630	1			T1	31		T2	105		T5	7
auto[0]	auto[0]	interest[64]	5411	1			T1	14		T2	59		T5	2
auto[0]	auto[1]	others[0]	9274	1			T1	7		T31	3		T32	4
auto[0]	auto[1]	others[1]	1500	1			T1	2		T33	30		T35	24
auto[0]	auto[1]	others[2]	1453	1			T1	2		T33	36		T35	17
auto[0]	auto[1]	others[3]	1609	1			T1	4		T33	42		T35	29
auto[0]	auto[1]	interest[1]	975	1			T33	16		T35	14		T85	15
auto[0]	auto[1]	interest[4]	6106	1			T1	5		T31	3		T32	4
auto[0]	auto[1]	interest[64]	2829	1			T1	4		T33	60		T35	43
auto[1]	auto[0]	others[0]	9225	1			T1	19		T2	81		T5	8
auto[1]	auto[0]	others[1]	1507	1			T1	5		T2	15		T5	1
auto[1]	auto[0]	others[2]	1522	1			T1	5		T2	11		T5	2
auto[1]	auto[0]	others[3]	1706	1			T1	6		T2	12		T5	1
auto[1]	auto[0]	interest[1]	954	1			T1	2		T2	8		T8	1
auto[1]	auto[0]	interest[4]	6052	1			T1	16		T2	58		T5	5
auto[1]	auto[0]	interest[64]	2971	1			T1	12		T2	30		T5	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal