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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1130
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T119 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3589916139 Jul 18 06:46:57 PM PDT 24 Jul 18 06:47:01 PM PDT 24 43582815 ps
T1026 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3274725718 Jul 18 06:47:41 PM PDT 24 Jul 18 06:47:44 PM PDT 24 74381984 ps
T1027 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.822050840 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:37 PM PDT 24 19979774 ps
T1028 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3474509235 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:34 PM PDT 24 33125159 ps
T1029 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2083299606 Jul 18 06:47:41 PM PDT 24 Jul 18 06:47:44 PM PDT 24 21911732 ps
T171 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1570449327 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:41 PM PDT 24 208301722 ps
T1030 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3131070593 Jul 18 06:47:43 PM PDT 24 Jul 18 06:47:48 PM PDT 24 12364807 ps
T1031 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1214100226 Jul 18 06:47:47 PM PDT 24 Jul 18 06:47:56 PM PDT 24 33223176 ps
T1032 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1402146704 Jul 18 06:47:29 PM PDT 24 Jul 18 06:47:37 PM PDT 24 71645137 ps
T1033 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.27275064 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:36 PM PDT 24 53578110 ps
T147 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3628544220 Jul 18 06:47:00 PM PDT 24 Jul 18 06:47:04 PM PDT 24 309140593 ps
T148 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2003214062 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:36 PM PDT 24 136343529 ps
T103 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.352105093 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:36 PM PDT 24 158467682 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2232606648 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:26 PM PDT 24 30375184 ps
T1035 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.53200304 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:33 PM PDT 24 113126955 ps
T1036 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.19539238 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:27 PM PDT 24 23453892 ps
T1037 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.370468906 Jul 18 06:47:45 PM PDT 24 Jul 18 06:47:53 PM PDT 24 37401714 ps
T120 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2483070512 Jul 18 06:47:29 PM PDT 24 Jul 18 06:47:40 PM PDT 24 119073810 ps
T1038 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3616589424 Jul 18 06:47:04 PM PDT 24 Jul 18 06:47:05 PM PDT 24 30677131 ps
T1039 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3481963200 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:34 PM PDT 24 133939965 ps
T1040 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.589798856 Jul 18 06:47:39 PM PDT 24 Jul 18 06:47:42 PM PDT 24 11957861 ps
T1041 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3352513109 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:33 PM PDT 24 166521785 ps
T1042 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1062075658 Jul 18 06:47:41 PM PDT 24 Jul 18 06:47:44 PM PDT 24 41069225 ps
T102 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2502797194 Jul 18 06:47:30 PM PDT 24 Jul 18 06:47:41 PM PDT 24 514322754 ps
T1043 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1732345143 Jul 18 06:47:30 PM PDT 24 Jul 18 06:47:40 PM PDT 24 96883943 ps
T1044 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3054429979 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:37 PM PDT 24 115854254 ps
T121 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3221451257 Jul 18 06:47:02 PM PDT 24 Jul 18 06:47:05 PM PDT 24 67191489 ps
T99 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1632488398 Jul 18 06:47:43 PM PDT 24 Jul 18 06:47:49 PM PDT 24 37929546 ps
T1045 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.663830339 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:36 PM PDT 24 125802393 ps
T124 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2438272818 Jul 18 06:47:21 PM PDT 24 Jul 18 06:47:24 PM PDT 24 142520770 ps
T1046 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1787299003 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:25 PM PDT 24 28635868 ps
T100 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1456319561 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:33 PM PDT 24 224011396 ps
T169 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.338458043 Jul 18 06:47:39 PM PDT 24 Jul 18 06:48:03 PM PDT 24 848869229 ps
T1047 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2156159836 Jul 18 06:47:00 PM PDT 24 Jul 18 06:47:02 PM PDT 24 58144272 ps
T149 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3636159895 Jul 18 06:47:21 PM PDT 24 Jul 18 06:47:30 PM PDT 24 5217540021 ps
T1048 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.627554039 Jul 18 06:47:42 PM PDT 24 Jul 18 06:47:46 PM PDT 24 26090673 ps
T1049 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1555821689 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:36 PM PDT 24 238341750 ps
T1050 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.236869162 Jul 18 06:47:38 PM PDT 24 Jul 18 06:47:40 PM PDT 24 13129607 ps
T101 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1890531734 Jul 18 06:47:29 PM PDT 24 Jul 18 06:47:40 PM PDT 24 117221125 ps
T122 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2308043738 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:58 PM PDT 24 1847468495 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2987702310 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:39 PM PDT 24 211645820 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2345180539 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:37 PM PDT 24 57067968 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2566220981 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:36 PM PDT 24 537077345 ps
T170 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2066403917 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:56 PM PDT 24 899164826 ps
T1054 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2982105566 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:36 PM PDT 24 38440276 ps
T125 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3919522688 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:35 PM PDT 24 30779579 ps
T1055 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4174937332 Jul 18 06:47:42 PM PDT 24 Jul 18 06:47:45 PM PDT 24 11338916 ps
T1056 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2496775312 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:39 PM PDT 24 252239905 ps
T1057 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.313949577 Jul 18 06:47:37 PM PDT 24 Jul 18 06:47:39 PM PDT 24 65173357 ps
T1058 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.945399321 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:37 PM PDT 24 408442395 ps
T1059 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4038747172 Jul 18 06:47:46 PM PDT 24 Jul 18 06:47:56 PM PDT 24 60710592 ps
T1060 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3451928063 Jul 18 06:47:45 PM PDT 24 Jul 18 06:47:54 PM PDT 24 303641211 ps
T1061 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3632709854 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:33 PM PDT 24 39847776 ps
T126 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1909837985 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:29 PM PDT 24 34939390 ps
T1062 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4178499303 Jul 18 06:47:44 PM PDT 24 Jul 18 06:47:51 PM PDT 24 85438528 ps
T1063 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2131586479 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:36 PM PDT 24 78277896 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3488999707 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:34 PM PDT 24 89279333 ps
T1065 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3175900707 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:35 PM PDT 24 151498335 ps
T123 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4147258321 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:34 PM PDT 24 67569532 ps
T127 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4132557427 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:38 PM PDT 24 37528629 ps
T1066 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2732953355 Jul 18 06:47:29 PM PDT 24 Jul 18 06:47:39 PM PDT 24 357007877 ps
T1067 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4251716884 Jul 18 06:47:41 PM PDT 24 Jul 18 06:47:45 PM PDT 24 96207584 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3987951706 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:49 PM PDT 24 2702057969 ps
T1069 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2122570596 Jul 18 06:47:00 PM PDT 24 Jul 18 06:47:02 PM PDT 24 12152293 ps
T1070 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.671569717 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:37 PM PDT 24 657665990 ps
T1071 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2673823846 Jul 18 06:47:43 PM PDT 24 Jul 18 06:47:47 PM PDT 24 46503150 ps
T1072 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4027755179 Jul 18 06:47:43 PM PDT 24 Jul 18 06:47:47 PM PDT 24 111363520 ps
T104 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2824581002 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:36 PM PDT 24 65186517 ps
T1073 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2468464675 Jul 18 06:47:45 PM PDT 24 Jul 18 06:47:53 PM PDT 24 22992572 ps
T1074 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3584100438 Jul 18 06:47:30 PM PDT 24 Jul 18 06:47:40 PM PDT 24 144047679 ps
T172 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1717328709 Jul 18 06:47:38 PM PDT 24 Jul 18 06:47:47 PM PDT 24 691790917 ps
T84 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3564406734 Jul 18 06:46:58 PM PDT 24 Jul 18 06:47:01 PM PDT 24 80040914 ps
T1075 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1015816336 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:35 PM PDT 24 107268545 ps
T1076 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1794282602 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:39 PM PDT 24 114963205 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1661409764 Jul 18 06:46:59 PM PDT 24 Jul 18 06:47:02 PM PDT 24 145886794 ps
T1078 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.84416540 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:34 PM PDT 24 90442076 ps
T1079 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1589593158 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:49 PM PDT 24 405819450 ps
T1080 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2237813933 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:27 PM PDT 24 111795873 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.285735493 Jul 18 06:47:01 PM PDT 24 Jul 18 06:47:16 PM PDT 24 976873871 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3184569556 Jul 18 06:46:58 PM PDT 24 Jul 18 06:47:04 PM PDT 24 52772976 ps
T1083 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1673385880 Jul 18 06:47:20 PM PDT 24 Jul 18 06:47:23 PM PDT 24 481325313 ps
T1084 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2921200459 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:32 PM PDT 24 29172545 ps
T1085 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.940467698 Jul 18 06:47:43 PM PDT 24 Jul 18 06:47:50 PM PDT 24 226783694 ps
T1086 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2168277542 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:34 PM PDT 24 1553070428 ps
T1087 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.809828550 Jul 18 06:47:21 PM PDT 24 Jul 18 06:47:27 PM PDT 24 525407201 ps
T1088 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2743688849 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:37 PM PDT 24 62012193 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4208668716 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:35 PM PDT 24 171446630 ps
T1090 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2933189881 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:35 PM PDT 24 15190238 ps
T1091 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2947861985 Jul 18 06:47:46 PM PDT 24 Jul 18 06:47:55 PM PDT 24 34699838 ps
T1092 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3470293030 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:55 PM PDT 24 2255590265 ps
T173 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.527565400 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:53 PM PDT 24 1975855111 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2805081186 Jul 18 06:47:46 PM PDT 24 Jul 18 06:48:19 PM PDT 24 1082442113 ps
T1094 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.798840921 Jul 18 06:47:40 PM PDT 24 Jul 18 06:47:42 PM PDT 24 30198604 ps
T168 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2975225841 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:36 PM PDT 24 158645382 ps
T1095 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3122852583 Jul 18 06:47:00 PM PDT 24 Jul 18 06:47:14 PM PDT 24 187236734 ps
T1096 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1795500930 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:28 PM PDT 24 11882910 ps
T1097 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3865936913 Jul 18 06:47:38 PM PDT 24 Jul 18 06:47:43 PM PDT 24 283619699 ps
T1098 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1776655292 Jul 18 06:47:27 PM PDT 24 Jul 18 06:47:39 PM PDT 24 204762303 ps
T1099 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1073380553 Jul 18 06:47:26 PM PDT 24 Jul 18 06:47:34 PM PDT 24 13858646 ps
T1100 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2416991797 Jul 18 06:47:42 PM PDT 24 Jul 18 06:47:46 PM PDT 24 47987248 ps
T1101 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2959906086 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:33 PM PDT 24 49055275 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3703576365 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:32 PM PDT 24 37534979 ps
T1103 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.921557644 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:34 PM PDT 24 29225807 ps
T1104 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1476977260 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:40 PM PDT 24 152198454 ps
T1105 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2317516693 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:34 PM PDT 24 831858154 ps
T1106 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.463283966 Jul 18 06:47:22 PM PDT 24 Jul 18 06:47:30 PM PDT 24 173017498 ps
T1107 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1927661859 Jul 18 06:47:28 PM PDT 24 Jul 18 06:47:38 PM PDT 24 63923086 ps
T1108 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.55197101 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:34 PM PDT 24 95141825 ps
T1109 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.996160807 Jul 18 06:47:41 PM PDT 24 Jul 18 06:47:43 PM PDT 24 47705600 ps
T1110 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3733420127 Jul 18 06:47:47 PM PDT 24 Jul 18 06:47:56 PM PDT 24 32720310 ps
T1111 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2515556441 Jul 18 06:47:24 PM PDT 24 Jul 18 06:47:33 PM PDT 24 38893724 ps
T1112 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4204388943 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:32 PM PDT 24 81804940 ps
T1113 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.921973125 Jul 18 06:47:39 PM PDT 24 Jul 18 06:47:44 PM PDT 24 96857478 ps
T1114 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3572509700 Jul 18 06:46:57 PM PDT 24 Jul 18 06:47:00 PM PDT 24 37436493 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1127831579 Jul 18 06:46:58 PM PDT 24 Jul 18 06:47:03 PM PDT 24 104216398 ps
T1116 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.15368378 Jul 18 06:47:42 PM PDT 24 Jul 18 06:47:46 PM PDT 24 600465661 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1522647806 Jul 18 06:46:59 PM PDT 24 Jul 18 06:47:02 PM PDT 24 43934491 ps
T1118 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1170596522 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:31 PM PDT 24 86438415 ps
T1119 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1972577180 Jul 18 06:47:39 PM PDT 24 Jul 18 06:47:42 PM PDT 24 21342836 ps
T1120 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3721027654 Jul 18 06:46:59 PM PDT 24 Jul 18 06:47:04 PM PDT 24 208180999 ps
T1121 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2561177153 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:29 PM PDT 24 45040853 ps
T1122 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3107123868 Jul 18 06:47:39 PM PDT 24 Jul 18 06:47:42 PM PDT 24 26552891 ps
T1123 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3291294238 Jul 18 06:47:00 PM PDT 24 Jul 18 06:47:24 PM PDT 24 3490340403 ps
T1124 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3576516381 Jul 18 06:47:38 PM PDT 24 Jul 18 06:47:52 PM PDT 24 2069044729 ps
T1125 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1357602029 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:30 PM PDT 24 24151867 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.281700093 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:31 PM PDT 24 517074863 ps
T1127 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.867339042 Jul 18 06:47:29 PM PDT 24 Jul 18 06:47:41 PM PDT 24 178058340 ps
T1128 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3090563309 Jul 18 06:47:25 PM PDT 24 Jul 18 06:47:35 PM PDT 24 218833713 ps
T1129 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1344231346 Jul 18 06:47:23 PM PDT 24 Jul 18 06:47:36 PM PDT 24 276468892 ps
T1130 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1878659191 Jul 18 06:47:40 PM PDT 24 Jul 18 06:47:43 PM PDT 24 14353761 ps

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2906457117
Short name T5
Test name
Test status
Simulation time 67897340305 ps
CPU time 144.31 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:22:44 PM PDT 24
Peak memory 252440 kb
Host smart-d17f96e9-af3c-42f1-a822-d6e94742db05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906457117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2906457117
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3063298987
Short name T18
Test name
Test status
Simulation time 110242825847 ps
CPU time 718.23 seconds
Started Jul 18 06:17:40 PM PDT 24
Finished Jul 18 06:29:40 PM PDT 24
Peak memory 270992 kb
Host smart-9f36b212-035f-4f29-8889-2f20e1c3e166
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063298987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3063298987
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1178046127
Short name T15
Test name
Test status
Simulation time 282982209890 ps
CPU time 730.37 seconds
Started Jul 18 06:19:09 PM PDT 24
Finished Jul 18 06:31:21 PM PDT 24
Peak memory 286536 kb
Host smart-5d07c797-5d84-44f0-a123-3e7253ad9248
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178046127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1178046127
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1853685040
Short name T63
Test name
Test status
Simulation time 1036595978 ps
CPU time 21.35 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 215960 kb
Host smart-0321d700-97b1-4a40-9aa7-6a51c7dae248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853685040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1853685040
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1811801497
Short name T13
Test name
Test status
Simulation time 26385199007 ps
CPU time 181.93 seconds
Started Jul 18 06:19:44 PM PDT 24
Finished Jul 18 06:22:50 PM PDT 24
Peak memory 256324 kb
Host smart-6e1c46f5-21d7-489e-9899-34e374ea97e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811801497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1811801497
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.836304786
Short name T65
Test name
Test status
Simulation time 35823548 ps
CPU time 0.81 seconds
Started Jul 18 06:15:33 PM PDT 24
Finished Jul 18 06:15:36 PM PDT 24
Peak memory 216572 kb
Host smart-fdfd0e6c-7f52-4ffb-932f-6cb37ab77cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836304786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.836304786
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1919506566
Short name T184
Test name
Test status
Simulation time 35721913047 ps
CPU time 397.21 seconds
Started Jul 18 06:16:13 PM PDT 24
Finished Jul 18 06:22:52 PM PDT 24
Peak memory 254468 kb
Host smart-47835a57-21c0-4c36-9cdf-a029de2f8fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919506566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1919506566
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3520461905
Short name T20
Test name
Test status
Simulation time 797132724694 ps
CPU time 1295.16 seconds
Started Jul 18 06:17:26 PM PDT 24
Finished Jul 18 06:39:03 PM PDT 24
Peak memory 286092 kb
Host smart-71c64c49-ee2a-42b1-bf33-6814a57b0b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520461905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3520461905
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3937423907
Short name T47
Test name
Test status
Simulation time 163885820157 ps
CPU time 431.34 seconds
Started Jul 18 06:18:54 PM PDT 24
Finished Jul 18 06:26:06 PM PDT 24
Peak memory 265900 kb
Host smart-8e9b0c19-fe71-42d0-ba48-288fb836427b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937423907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3937423907
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2967215079
Short name T2
Test name
Test status
Simulation time 12230287175 ps
CPU time 128.84 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:20:32 PM PDT 24
Peak memory 257472 kb
Host smart-02fb3b50-6857-42c4-bc8d-f1136bc99451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967215079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2967215079
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2947718684
Short name T138
Test name
Test status
Simulation time 7957177065 ps
CPU time 73 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:22:31 PM PDT 24
Peak memory 234200 kb
Host smart-6813801b-afa0-4098-bf51-3d6e428e0375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947718684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2947718684
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2255027615
Short name T322
Test name
Test status
Simulation time 26611028 ps
CPU time 0.76 seconds
Started Jul 18 06:18:51 PM PDT 24
Finished Jul 18 06:18:53 PM PDT 24
Peak memory 205380 kb
Host smart-5c600ee3-6b88-41d6-b4c3-b62d79d088d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255027615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2255027615
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.350448850
Short name T98
Test name
Test status
Simulation time 352991952 ps
CPU time 4.96 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 215436 kb
Host smart-fcc98b5a-c612-4a54-9d8e-0a808cd94fb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350448850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.350448850
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4269666746
Short name T21
Test name
Test status
Simulation time 22510689431 ps
CPU time 143.99 seconds
Started Jul 18 06:17:40 PM PDT 24
Finished Jul 18 06:20:05 PM PDT 24
Peak memory 281980 kb
Host smart-f3175abe-a65f-41c4-bc5a-5a89967f531c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269666746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4269666746
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.351421401
Short name T174
Test name
Test status
Simulation time 27980908829 ps
CPU time 237.8 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:26:01 PM PDT 24
Peak memory 256460 kb
Host smart-eddbba50-04df-4fba-93d2-52d377e8a1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351421401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.351421401
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3589916139
Short name T119
Test name
Test status
Simulation time 43582815 ps
CPU time 1.47 seconds
Started Jul 18 06:46:57 PM PDT 24
Finished Jul 18 06:47:01 PM PDT 24
Peak memory 215336 kb
Host smart-614bbc45-de1f-4854-9abf-c3dae25663a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589916139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
589916139
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2846590121
Short name T201
Test name
Test status
Simulation time 132101966079 ps
CPU time 349.93 seconds
Started Jul 18 06:18:57 PM PDT 24
Finished Jul 18 06:24:47 PM PDT 24
Peak memory 256248 kb
Host smart-c201a01d-7aa4-4abe-bce6-dc0a49f7613f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846590121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2846590121
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.632195507
Short name T192
Test name
Test status
Simulation time 48039238598 ps
CPU time 177.44 seconds
Started Jul 18 06:18:34 PM PDT 24
Finished Jul 18 06:21:33 PM PDT 24
Peak memory 265952 kb
Host smart-808db5bf-a95d-4ca9-9c69-15edfc32cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632195507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.632195507
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.610169404
Short name T66
Test name
Test status
Simulation time 158748319 ps
CPU time 0.99 seconds
Started Jul 18 06:15:55 PM PDT 24
Finished Jul 18 06:15:58 PM PDT 24
Peak memory 236592 kb
Host smart-b8de4da7-6863-4a9e-9767-fe17ff3111f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610169404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.610169404
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3732107683
Short name T179
Test name
Test status
Simulation time 429273201271 ps
CPU time 461.17 seconds
Started Jul 18 06:21:59 PM PDT 24
Finished Jul 18 06:29:42 PM PDT 24
Peak memory 262924 kb
Host smart-4b11b1fb-cc8f-4022-8c68-c73582c2a3cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732107683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3732107683
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.108961620
Short name T186
Test name
Test status
Simulation time 30518861467 ps
CPU time 109.21 seconds
Started Jul 18 06:19:10 PM PDT 24
Finished Jul 18 06:21:01 PM PDT 24
Peak memory 266648 kb
Host smart-62071937-3a1c-438b-a9a3-1e0629a7e0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108961620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.108961620
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2811719242
Short name T150
Test name
Test status
Simulation time 14042507684 ps
CPU time 49.22 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:19:27 PM PDT 24
Peak memory 233248 kb
Host smart-8dea726b-22ec-4913-b9ad-c37e0ba3d431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811719242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2811719242
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2714123796
Short name T39
Test name
Test status
Simulation time 63340684242 ps
CPU time 675.42 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:33:00 PM PDT 24
Peak memory 263908 kb
Host smart-91a978fe-6356-4afe-b25e-8bc7a6730d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714123796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2714123796
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2165877117
Short name T275
Test name
Test status
Simulation time 104270156168 ps
CPU time 791.05 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:34:26 PM PDT 24
Peak memory 274136 kb
Host smart-b6c16efc-17b3-45e7-b97f-94e128e4c66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165877117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2165877117
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3506952718
Short name T131
Test name
Test status
Simulation time 28065909430 ps
CPU time 363.25 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:30:34 PM PDT 24
Peak memory 269900 kb
Host smart-6ca5800a-fc2f-417d-b89a-15f64e712ac1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506952718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3506952718
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.4078472377
Short name T7
Test name
Test status
Simulation time 1566021979 ps
CPU time 4.74 seconds
Started Jul 18 06:18:18 PM PDT 24
Finished Jul 18 06:18:24 PM PDT 24
Peak memory 224908 kb
Host smart-d9d52ec7-b0cf-44a6-9cda-d0f0ede24d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078472377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4078472377
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3759337456
Short name T212
Test name
Test status
Simulation time 54423755892 ps
CPU time 202.73 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:25:04 PM PDT 24
Peak memory 257620 kb
Host smart-ad5e871f-905d-4d8a-8986-ec7c49d73c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759337456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3759337456
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1436459239
Short name T112
Test name
Test status
Simulation time 7435642596 ps
CPU time 20.05 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:43 PM PDT 24
Peak memory 216764 kb
Host smart-939d5ad5-f973-4f0c-b1f7-f29c7dd447e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436459239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1436459239
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2404690387
Short name T209
Test name
Test status
Simulation time 3482400036 ps
CPU time 74.95 seconds
Started Jul 18 06:18:58 PM PDT 24
Finished Jul 18 06:20:14 PM PDT 24
Peak memory 264944 kb
Host smart-03e3875e-220d-4466-b8dc-ed6dab6d3137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404690387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2404690387
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.271565902
Short name T279
Test name
Test status
Simulation time 8020464664 ps
CPU time 116.3 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:21:38 PM PDT 24
Peak memory 254072 kb
Host smart-0d984302-2cd3-4a85-94b9-93a0afa89678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271565902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.271565902
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1042663178
Short name T259
Test name
Test status
Simulation time 28340360339 ps
CPU time 83.52 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:25:09 PM PDT 24
Peak memory 253124 kb
Host smart-30876edf-ae28-446c-826f-82ba337889ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042663178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1042663178
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2528358307
Short name T89
Test name
Test status
Simulation time 209432361 ps
CPU time 6.14 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:17 PM PDT 24
Peak memory 220700 kb
Host smart-ff2a378a-58a0-4154-8a9e-cc1637106485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528358307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2528358307
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.2824581002
Short name T104
Test name
Test status
Simulation time 65186517 ps
CPU time 4.17 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 219520 kb
Host smart-0f0ae925-8be3-4512-aabe-f3e8e76657a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824581002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.2
824581002
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2066403917
Short name T170
Test name
Test status
Simulation time 899164826 ps
CPU time 24.34 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 215332 kb
Host smart-deb24772-69ff-4cc4-9866-cf20d05b4c41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066403917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2066403917
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3786178005
Short name T750
Test name
Test status
Simulation time 21880257525 ps
CPU time 74.97 seconds
Started Jul 18 06:20:19 PM PDT 24
Finished Jul 18 06:21:36 PM PDT 24
Peak memory 236620 kb
Host smart-f9959297-cdae-4d36-b444-127b6652a99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786178005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3786178005
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1105963444
Short name T286
Test name
Test status
Simulation time 2005386626 ps
CPU time 8.44 seconds
Started Jul 18 06:21:38 PM PDT 24
Finished Jul 18 06:21:48 PM PDT 24
Peak memory 233112 kb
Host smart-3328ab59-29c8-44f3-9190-999b18324fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105963444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1105963444
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2994271075
Short name T190
Test name
Test status
Simulation time 21695078306 ps
CPU time 152.76 seconds
Started Jul 18 06:23:20 PM PDT 24
Finished Jul 18 06:25:55 PM PDT 24
Peak memory 256224 kb
Host smart-c02b1ec6-a71e-46fd-88ff-e48755c575c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994271075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2994271075
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4052077903
Short name T948
Test name
Test status
Simulation time 2056269538 ps
CPU time 46.82 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:24:32 PM PDT 24
Peak memory 265112 kb
Host smart-27c2549a-df14-4646-8190-705182d2e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052077903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4052077903
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1717328709
Short name T172
Test name
Test status
Simulation time 691790917 ps
CPU time 7.79 seconds
Started Jul 18 06:47:38 PM PDT 24
Finished Jul 18 06:47:47 PM PDT 24
Peak memory 215268 kb
Host smart-8a2160bc-eda9-4333-9692-427560dff25f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717328709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1717328709
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.24383001
Short name T721
Test name
Test status
Simulation time 191162617 ps
CPU time 8.42 seconds
Started Jul 18 06:18:39 PM PDT 24
Finished Jul 18 06:18:49 PM PDT 24
Peak memory 235552 kb
Host smart-7e10d502-108b-46cc-8758-eb7484114b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24383001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.24383001
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3174399469
Short name T85
Test name
Test status
Simulation time 4346443389 ps
CPU time 10.13 seconds
Started Jul 18 06:18:51 PM PDT 24
Finished Jul 18 06:19:02 PM PDT 24
Peak memory 216776 kb
Host smart-66875c0a-ec89-48a9-a8c0-99e873c5fbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174399469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3174399469
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.501602897
Short name T156
Test name
Test status
Simulation time 179609123886 ps
CPU time 276.43 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:24:41 PM PDT 24
Peak memory 265260 kb
Host smart-ff723eae-3e9a-4e12-b856-eb84e2ec681d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501602897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.501602897
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2783255670
Short name T244
Test name
Test status
Simulation time 89400035954 ps
CPU time 409.04 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:27:46 PM PDT 24
Peak memory 263380 kb
Host smart-b98e6216-1c63-47e4-9616-d098197f436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783255670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2783255670
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.554293866
Short name T273
Test name
Test status
Simulation time 183737222355 ps
CPU time 816.32 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:36:10 PM PDT 24
Peak memory 282400 kb
Host smart-53e37428-68ee-401a-b891-b0cdbea9ad82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554293866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.554293866
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1509622794
Short name T256
Test name
Test status
Simulation time 690845676 ps
CPU time 7.74 seconds
Started Jul 18 06:18:24 PM PDT 24
Finished Jul 18 06:18:37 PM PDT 24
Peak memory 233088 kb
Host smart-b1d95371-65f3-4498-9811-caea95559a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509622794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1509622794
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3564406734
Short name T84
Test name
Test status
Simulation time 80040914 ps
CPU time 1.48 seconds
Started Jul 18 06:46:58 PM PDT 24
Finished Jul 18 06:47:01 PM PDT 24
Peak memory 207092 kb
Host smart-34322a3d-c38b-4e4d-9076-56174ad23aa1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564406734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3564406734
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1279390374
Short name T118
Test name
Test status
Simulation time 1877549659 ps
CPU time 22.96 seconds
Started Jul 18 06:47:01 PM PDT 24
Finished Jul 18 06:47:25 PM PDT 24
Peak memory 215232 kb
Host smart-6a9dfe7c-011a-43bb-915b-6555b0a9cf5d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279390374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1279390374
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.285735493
Short name T1081
Test name
Test status
Simulation time 976873871 ps
CPU time 13.85 seconds
Started Jul 18 06:47:01 PM PDT 24
Finished Jul 18 06:47:16 PM PDT 24
Peak memory 207128 kb
Host smart-59bbad77-e75d-417a-81a3-b86528aeb351
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285735493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.285735493
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3184569556
Short name T1082
Test name
Test status
Simulation time 52772976 ps
CPU time 3.65 seconds
Started Jul 18 06:46:58 PM PDT 24
Finished Jul 18 06:47:04 PM PDT 24
Peak memory 218112 kb
Host smart-0ed6b6a3-ab4a-4b86-ba56-eb16fef5ec32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184569556 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3184569556
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3221451257
Short name T121
Test name
Test status
Simulation time 67191489 ps
CPU time 2.48 seconds
Started Jul 18 06:47:02 PM PDT 24
Finished Jul 18 06:47:05 PM PDT 24
Peak memory 215256 kb
Host smart-c86a5cb0-1696-4772-9099-b7ea22406f5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221451257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
221451257
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2156159836
Short name T1047
Test name
Test status
Simulation time 58144272 ps
CPU time 0.77 seconds
Started Jul 18 06:47:00 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 204244 kb
Host smart-01893d9c-ec9e-45f0-a5cf-d0723f161592
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156159836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
156159836
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.4290272395
Short name T116
Test name
Test status
Simulation time 241336345 ps
CPU time 2.36 seconds
Started Jul 18 06:46:57 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 215376 kb
Host smart-486afea4-a15a-4ffc-8833-3149563c5517
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290272395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.4290272395
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2122570596
Short name T1069
Test name
Test status
Simulation time 12152293 ps
CPU time 0.71 seconds
Started Jul 18 06:47:00 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 203696 kb
Host smart-4c1f72ad-7622-49ba-84f6-4f5ca7ca0fa7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122570596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2122570596
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1661409764
Short name T1077
Test name
Test status
Simulation time 145886794 ps
CPU time 1.97 seconds
Started Jul 18 06:46:59 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 215344 kb
Host smart-9daf969d-9b36-4e90-a9a5-a071d3d0a00d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661409764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1661409764
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.51592742
Short name T94
Test name
Test status
Simulation time 164444854 ps
CPU time 2.93 seconds
Started Jul 18 06:46:57 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 215492 kb
Host smart-8a31a162-7402-41f5-af41-6f38e5966e58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51592742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.51592742
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1148016342
Short name T64
Test name
Test status
Simulation time 372082160 ps
CPU time 12.4 seconds
Started Jul 18 06:46:58 PM PDT 24
Finished Jul 18 06:47:12 PM PDT 24
Peak memory 215412 kb
Host smart-1c1e20ea-26b9-4e85-ba9c-238285e4f799
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148016342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1148016342
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3291294238
Short name T1123
Test name
Test status
Simulation time 3490340403 ps
CPU time 22.76 seconds
Started Jul 18 06:47:00 PM PDT 24
Finished Jul 18 06:47:24 PM PDT 24
Peak memory 215296 kb
Host smart-33f70a4b-cb3f-494d-bc21-b707238f2744
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291294238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3291294238
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3122852583
Short name T1095
Test name
Test status
Simulation time 187236734 ps
CPU time 12.72 seconds
Started Jul 18 06:47:00 PM PDT 24
Finished Jul 18 06:47:14 PM PDT 24
Peak memory 207104 kb
Host smart-4704a999-1bf6-4455-b4ad-af1d4a591e7c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122852583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3122852583
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3593323867
Short name T83
Test name
Test status
Simulation time 134230974 ps
CPU time 1.4 seconds
Started Jul 18 06:46:58 PM PDT 24
Finished Jul 18 06:47:01 PM PDT 24
Peak memory 207032 kb
Host smart-8ce6769d-69dd-41e0-bae5-2d68518e6341
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593323867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3593323867
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2845154783
Short name T1020
Test name
Test status
Simulation time 84137858 ps
CPU time 2.57 seconds
Started Jul 18 06:46:57 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 216788 kb
Host smart-ffcf2aad-5ea7-488a-94ff-670f116c531e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845154783 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2845154783
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3616589424
Short name T1038
Test name
Test status
Simulation time 30677131 ps
CPU time 0.7 seconds
Started Jul 18 06:47:04 PM PDT 24
Finished Jul 18 06:47:05 PM PDT 24
Peak memory 203824 kb
Host smart-4680e4eb-0b13-40c1-9b4d-0ab652222434
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616589424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
616589424
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1522647806
Short name T1117
Test name
Test status
Simulation time 43934491 ps
CPU time 1.65 seconds
Started Jul 18 06:46:59 PM PDT 24
Finished Jul 18 06:47:02 PM PDT 24
Peak memory 215392 kb
Host smart-a9a41a8a-7776-4076-9ae7-8f34f1ec6fd8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522647806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1522647806
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3572509700
Short name T1114
Test name
Test status
Simulation time 37436493 ps
CPU time 0.72 seconds
Started Jul 18 06:46:57 PM PDT 24
Finished Jul 18 06:47:00 PM PDT 24
Peak memory 203644 kb
Host smart-d0ae72f4-0bb5-460d-b605-5a9ac1fbad8c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572509700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3572509700
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3628544220
Short name T147
Test name
Test status
Simulation time 309140593 ps
CPU time 2.14 seconds
Started Jul 18 06:47:00 PM PDT 24
Finished Jul 18 06:47:04 PM PDT 24
Peak memory 215304 kb
Host smart-028ef045-e4fc-4035-9576-5fc634cd86f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628544220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3628544220
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1127831579
Short name T1115
Test name
Test status
Simulation time 104216398 ps
CPU time 2.76 seconds
Started Jul 18 06:46:58 PM PDT 24
Finished Jul 18 06:47:03 PM PDT 24
Peak memory 215664 kb
Host smart-b0fbba6c-a25e-41bc-96db-c91f55d06cde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127831579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
127831579
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.438708113
Short name T105
Test name
Test status
Simulation time 1140601568 ps
CPU time 16.03 seconds
Started Jul 18 06:47:02 PM PDT 24
Finished Jul 18 06:47:19 PM PDT 24
Peak memory 215268 kb
Host smart-7df5858b-1b8a-4ede-89b9-f7974ffda04a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438708113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.438708113
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3090563309
Short name T1128
Test name
Test status
Simulation time 218833713 ps
CPU time 2.48 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 217532 kb
Host smart-fd2c0cac-7eae-490c-9597-8420cd1a2eed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090563309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3090563309
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.663830339
Short name T1045
Test name
Test status
Simulation time 125802393 ps
CPU time 1.44 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215284 kb
Host smart-d68acf79-4c5d-4dd6-8e7f-cc8a93006042
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663830339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.663830339
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3481963200
Short name T1039
Test name
Test status
Simulation time 133939965 ps
CPU time 0.7 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 203816 kb
Host smart-5809e156-e86e-42a7-8996-c9dbac0d2756
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481963200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3481963200
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1924854080
Short name T1017
Test name
Test status
Simulation time 60884638 ps
CPU time 3.83 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215300 kb
Host smart-c89658ea-6290-4d04-852c-de2ab71b1315
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924854080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1924854080
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3340280725
Short name T95
Test name
Test status
Simulation time 965392654 ps
CPU time 4.35 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 215464 kb
Host smart-c7e6e50d-2d29-440a-ab0b-4c26c1e895e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340280725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3340280725
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1380022799
Short name T62
Test name
Test status
Simulation time 28784913 ps
CPU time 1.87 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 216384 kb
Host smart-74c477bc-d745-41bc-93c7-048a305ced10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380022799 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1380022799
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4147258321
Short name T123
Test name
Test status
Simulation time 67569532 ps
CPU time 1.2 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215328 kb
Host smart-1aa0152d-23f5-4cd7-a7fd-2d9a483c6ebd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147258321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4147258321
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2531024887
Short name T1005
Test name
Test status
Simulation time 39751392 ps
CPU time 0.75 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 203844 kb
Host smart-b65dee94-e28c-40d4-b5a7-a119d3cc4d3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531024887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2531024887
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2003214062
Short name T148
Test name
Test status
Simulation time 136343529 ps
CPU time 3.15 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215308 kb
Host smart-e67a76a6-4f9c-48bd-9c50-5242becce7b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003214062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2003214062
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.945399321
Short name T1058
Test name
Test status
Simulation time 408442395 ps
CPU time 2.73 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 215376 kb
Host smart-81cb1541-2a6c-43bc-96e9-ec186b8fafbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945399321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.945399321
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1794282602
Short name T1076
Test name
Test status
Simulation time 114963205 ps
CPU time 2.87 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 216576 kb
Host smart-66fb585a-6d15-4fec-81f1-41bda84a0bef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794282602 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1794282602
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2483070512
Short name T120
Test name
Test status
Simulation time 119073810 ps
CPU time 2.76 seconds
Started Jul 18 06:47:29 PM PDT 24
Finished Jul 18 06:47:40 PM PDT 24
Peak memory 215296 kb
Host smart-6d412735-28d9-4f70-8a0b-893589ada3ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483070512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2483070512
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2982105566
Short name T1054
Test name
Test status
Simulation time 38440276 ps
CPU time 0.71 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 203828 kb
Host smart-9a2f51d8-57a0-4e1e-a1dd-5d574a96a76a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982105566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2982105566
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2496775312
Short name T1056
Test name
Test status
Simulation time 252239905 ps
CPU time 2.81 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 215260 kb
Host smart-635d7d92-f03f-4f82-a432-b3b43bceb580
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496775312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2496775312
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1476977260
Short name T1104
Test name
Test status
Simulation time 152198454 ps
CPU time 4.02 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:40 PM PDT 24
Peak memory 215344 kb
Host smart-fe0cd9aa-83d3-4eb5-ad4c-d08535ab21db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476977260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1476977260
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.527565400
Short name T173
Test name
Test status
Simulation time 1975855111 ps
CPU time 16.68 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 215632 kb
Host smart-6ec7c52e-0eed-4e20-9f3f-6940f907cde7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527565400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.527565400
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.84416540
Short name T1078
Test name
Test status
Simulation time 90442076 ps
CPU time 1.6 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215356 kb
Host smart-c875465c-2b1a-4553-8537-dfdbe4719884
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84416540 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.84416540
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2566220981
Short name T1053
Test name
Test status
Simulation time 537077345 ps
CPU time 1.21 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215276 kb
Host smart-497afa9c-df9e-478a-9159-0f72a3c6870d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566220981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2566220981
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.822050840
Short name T1027
Test name
Test status
Simulation time 19979774 ps
CPU time 0.78 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 203796 kb
Host smart-887f044a-3a54-49c8-b342-fbc2162cfab3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822050840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.822050840
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1555821689
Short name T1049
Test name
Test status
Simulation time 238341750 ps
CPU time 3.79 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215328 kb
Host smart-f25eb3e5-18e4-40ef-b924-3b1981bafd3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555821689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1555821689
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1776655292
Short name T1098
Test name
Test status
Simulation time 204762303 ps
CPU time 2.89 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 215508 kb
Host smart-ec0298ee-b90b-49e7-8c5a-446543d90907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776655292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1776655292
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1589593158
Short name T1079
Test name
Test status
Simulation time 405819450 ps
CPU time 13.15 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:49 PM PDT 24
Peak memory 215216 kb
Host smart-3d73a773-232e-4fd1-844a-09f739b03f20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589593158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1589593158
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2732953355
Short name T1066
Test name
Test status
Simulation time 357007877 ps
CPU time 2.62 seconds
Started Jul 18 06:47:29 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 217960 kb
Host smart-41061e82-e445-4fe1-bef7-ed1e3df6cbd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732953355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2732953355
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4132557427
Short name T127
Test name
Test status
Simulation time 37528629 ps
CPU time 2.41 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:38 PM PDT 24
Peak memory 215336 kb
Host smart-c0f7a682-77b5-424b-9052-1ba11482d533
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132557427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4132557427
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.27275064
Short name T1033
Test name
Test status
Simulation time 53578110 ps
CPU time 0.78 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 203820 kb
Host smart-f5584248-7050-4495-bc91-c9fadb37b918
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27275064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.27275064
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1732345143
Short name T1043
Test name
Test status
Simulation time 96883943 ps
CPU time 2.8 seconds
Started Jul 18 06:47:30 PM PDT 24
Finished Jul 18 06:47:40 PM PDT 24
Peak memory 214996 kb
Host smart-74487201-ae63-416a-a84a-967c0b3817e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732345143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1732345143
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.352105093
Short name T103
Test name
Test status
Simulation time 158467682 ps
CPU time 1.59 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215496 kb
Host smart-e722e6f4-f7bd-4715-a4d3-0757efeec0aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352105093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.352105093
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.322532901
Short name T108
Test name
Test status
Simulation time 901499146 ps
CPU time 14.07 seconds
Started Jul 18 06:50:58 PM PDT 24
Finished Jul 18 06:51:13 PM PDT 24
Peak memory 217752 kb
Host smart-9d34ea11-0483-4399-872c-29485bfa0f01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322532901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.322532901
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3584100438
Short name T1074
Test name
Test status
Simulation time 144047679 ps
CPU time 2.97 seconds
Started Jul 18 06:47:30 PM PDT 24
Finished Jul 18 06:47:40 PM PDT 24
Peak memory 216396 kb
Host smart-464dec3d-a585-4605-a74f-66bc4600a561
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584100438 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3584100438
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2332572624
Short name T115
Test name
Test status
Simulation time 297492188 ps
CPU time 1.4 seconds
Started Jul 18 06:47:30 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 207120 kb
Host smart-5ceb38a2-529f-4ae1-ba00-b7790ee1ceab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332572624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2332572624
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1402146704
Short name T1032
Test name
Test status
Simulation time 71645137 ps
CPU time 0.74 seconds
Started Jul 18 06:47:29 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 204156 kb
Host smart-2f2eee00-d123-4a40-99a3-08d291e4be3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402146704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1402146704
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.867339042
Short name T1127
Test name
Test status
Simulation time 178058340 ps
CPU time 3.87 seconds
Started Jul 18 06:47:29 PM PDT 24
Finished Jul 18 06:47:41 PM PDT 24
Peak memory 214112 kb
Host smart-43fb1236-9dec-4607-acb4-48af69e76f50
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867339042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.867339042
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2502797194
Short name T102
Test name
Test status
Simulation time 514322754 ps
CPU time 3.18 seconds
Started Jul 18 06:47:30 PM PDT 24
Finished Jul 18 06:47:41 PM PDT 24
Peak memory 215344 kb
Host smart-369c4dd4-2fe2-4e84-a1bc-8519e89d82f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502797194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2502797194
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.717756798
Short name T109
Test name
Test status
Simulation time 303074727 ps
CPU time 18.16 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:52 PM PDT 24
Peak memory 215224 kb
Host smart-85018d2b-3de0-4f07-9a51-450109f3df3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717756798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.717756798
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2959906086
Short name T1101
Test name
Test status
Simulation time 49055275 ps
CPU time 1.68 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 216432 kb
Host smart-4a160e65-4314-4ae3-a49c-41a5822fccd7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959906086 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2959906086
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2515556441
Short name T1111
Test name
Test status
Simulation time 38893724 ps
CPU time 1.31 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 215248 kb
Host smart-b18ae8d3-a672-41d0-911b-4a7c1e5b3855
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515556441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2515556441
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3474509235
Short name T1028
Test name
Test status
Simulation time 33125159 ps
CPU time 0.76 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 204148 kb
Host smart-439b6533-b2c6-4fe2-b6b8-4dd9a8efd3eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474509235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3474509235
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.53200304
Short name T1035
Test name
Test status
Simulation time 113126955 ps
CPU time 3.06 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 215268 kb
Host smart-049d3990-46d9-4547-95ab-16b1a9380f44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53200304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp
i_device_same_csr_outstanding.53200304
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1890531734
Short name T101
Test name
Test status
Simulation time 117221125 ps
CPU time 3.25 seconds
Started Jul 18 06:47:29 PM PDT 24
Finished Jul 18 06:47:40 PM PDT 24
Peak memory 214436 kb
Host smart-0aaa242d-78fa-4ff5-9adc-476b6781d161
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890531734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1890531734
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.339253752
Short name T96
Test name
Test status
Simulation time 1144350622 ps
CPU time 15.31 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:47 PM PDT 24
Peak memory 215472 kb
Host smart-9e40357d-741a-4214-a071-e73450150ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339253752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.339253752
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.447745120
Short name T110
Test name
Test status
Simulation time 43291675 ps
CPU time 2.64 seconds
Started Jul 18 06:47:38 PM PDT 24
Finished Jul 18 06:47:43 PM PDT 24
Peak memory 216920 kb
Host smart-5b5bdf74-a976-4241-9d33-92f8e349a4c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447745120 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.447745120
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3328567650
Short name T146
Test name
Test status
Simulation time 170030352 ps
CPU time 1.3 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 206912 kb
Host smart-1d8272c7-beb3-4b9f-bc53-8a55fa78be1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328567650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3328567650
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1214100226
Short name T1031
Test name
Test status
Simulation time 33223176 ps
CPU time 0.71 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 203828 kb
Host smart-8baa7178-3cde-4850-a04b-3ad3db6b1611
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214100226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1214100226
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.940467698
Short name T1085
Test name
Test status
Simulation time 226783694 ps
CPU time 3.73 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:50 PM PDT 24
Peak memory 215280 kb
Host smart-415e3ed0-7e39-4060-b736-3b3aa47c8686
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940467698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.940467698
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2168277542
Short name T1086
Test name
Test status
Simulation time 1553070428 ps
CPU time 2.85 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 216468 kb
Host smart-747af626-ea11-435a-926f-efd69ceb5ba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168277542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2168277542
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.338458043
Short name T169
Test name
Test status
Simulation time 848869229 ps
CPU time 22.35 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:48:03 PM PDT 24
Peak memory 215300 kb
Host smart-30346dbd-2196-41a6-ac78-2995e4f9d9db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338458043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.338458043
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4038747172
Short name T1059
Test name
Test status
Simulation time 60710592 ps
CPU time 1.81 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 216396 kb
Host smart-62b02966-c607-450d-92b8-20cbddd27fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038747172 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4038747172
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3451928063
Short name T1060
Test name
Test status
Simulation time 303641211 ps
CPU time 2.47 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 215260 kb
Host smart-ecd33b8b-0c4c-4510-973f-c11a0a0d5a87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451928063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3451928063
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.30009552
Short name T1011
Test name
Test status
Simulation time 15275472 ps
CPU time 0.76 seconds
Started Jul 18 06:47:38 PM PDT 24
Finished Jul 18 06:47:41 PM PDT 24
Peak memory 203752 kb
Host smart-04569627-6787-40ea-9025-d16c00dc6d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30009552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.30009552
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3195385059
Short name T1013
Test name
Test status
Simulation time 114366303 ps
CPU time 2.99 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:47 PM PDT 24
Peak memory 215228 kb
Host smart-1582a126-3a84-4430-a3fd-e246ec1ec74d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195385059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3195385059
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1632488398
Short name T99
Test name
Test status
Simulation time 37929546 ps
CPU time 2.68 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:49 PM PDT 24
Peak memory 216512 kb
Host smart-b57719d9-4cc4-449d-938d-3119c934b0c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632488398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1632488398
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.15368378
Short name T1116
Test name
Test status
Simulation time 600465661 ps
CPU time 1.83 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:46 PM PDT 24
Peak memory 216596 kb
Host smart-586e23cd-fe28-4cfc-8d2c-cbfb60add3a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15368378 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.15368378
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.921973125
Short name T1113
Test name
Test status
Simulation time 96857478 ps
CPU time 2.69 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 207032 kb
Host smart-de768956-60fc-4436-a2e2-00b54ee27bdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921973125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.921973125
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4178499303
Short name T1062
Test name
Test status
Simulation time 85438528 ps
CPU time 0.69 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 204128 kb
Host smart-90fed6f3-2b56-4757-91d1-e114bbaafe7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178499303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4178499303
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4067302648
Short name T1018
Test name
Test status
Simulation time 111735184 ps
CPU time 3.15 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 215312 kb
Host smart-97af0000-12c1-4eac-8462-1e01a02adc90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067302648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4067302648
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3865936913
Short name T1097
Test name
Test status
Simulation time 283619699 ps
CPU time 3.77 seconds
Started Jul 18 06:47:38 PM PDT 24
Finished Jul 18 06:47:43 PM PDT 24
Peak memory 215624 kb
Host smart-9c6d1227-c3ab-4eb3-8916-e1c95175e225
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865936913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3865936913
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2805081186
Short name T1093
Test name
Test status
Simulation time 1082442113 ps
CPU time 24.08 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:48:19 PM PDT 24
Peak memory 215316 kb
Host smart-c70953b8-21ce-4d45-99e3-d58baa6cbe20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805081186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2805081186
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.671569717
Short name T1070
Test name
Test status
Simulation time 657665990 ps
CPU time 7.19 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 215256 kb
Host smart-b6934a5c-3a7f-4999-845a-86fabcf5af31
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671569717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.671569717
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2749428730
Short name T1024
Test name
Test status
Simulation time 3362651275 ps
CPU time 14.28 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:41 PM PDT 24
Peak memory 207276 kb
Host smart-5a36b733-978e-4f05-babd-1f5650251992
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749428730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2749428730
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.4105036745
Short name T81
Test name
Test status
Simulation time 30701507 ps
CPU time 1.12 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:27 PM PDT 24
Peak memory 207040 kb
Host smart-3a6e095a-632c-43f1-9455-1e76b6e29e4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105036745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.4105036745
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3488999707
Short name T1064
Test name
Test status
Simulation time 89279333 ps
CPU time 2.63 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 217348 kb
Host smart-6af93f6e-9e6d-41b4-95e5-9d03be54e1d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488999707 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3488999707
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.463283966
Short name T1106
Test name
Test status
Simulation time 173017498 ps
CPU time 2.46 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:30 PM PDT 24
Peak memory 215276 kb
Host smart-4b66b1f9-35ab-4a8a-a6d5-b723d08e750c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463283966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.463283966
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1787299003
Short name T1046
Test name
Test status
Simulation time 28635868 ps
CPU time 0.73 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:25 PM PDT 24
Peak memory 203832 kb
Host smart-6c219490-4403-4cc0-b57c-62d042ed06d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787299003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
787299003
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2438272818
Short name T124
Test name
Test status
Simulation time 142520770 ps
CPU time 1.36 seconds
Started Jul 18 06:47:21 PM PDT 24
Finished Jul 18 06:47:24 PM PDT 24
Peak memory 215348 kb
Host smart-0db59c26-5e88-4ded-97dd-5f34be94a986
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438272818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2438272818
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3703576365
Short name T1102
Test name
Test status
Simulation time 37534979 ps
CPU time 0.66 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:32 PM PDT 24
Peak memory 203708 kb
Host smart-176357f4-c98f-4234-98ef-c71438178ab1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703576365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3703576365
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1641948285
Short name T1016
Test name
Test status
Simulation time 959890532 ps
CPU time 4.2 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215220 kb
Host smart-bd334bc7-8e16-46fa-8df6-22aac330834b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641948285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1641948285
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3721027654
Short name T1120
Test name
Test status
Simulation time 208180999 ps
CPU time 3.34 seconds
Started Jul 18 06:46:59 PM PDT 24
Finished Jul 18 06:47:04 PM PDT 24
Peak memory 215568 kb
Host smart-3851f690-c2c5-413b-abd1-ff7c65174d71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721027654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
721027654
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1344231346
Short name T1129
Test name
Test status
Simulation time 276468892 ps
CPU time 7.88 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 223504 kb
Host smart-d7d6f55a-f21f-408d-9333-0396f020a4dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344231346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1344231346
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.313949577
Short name T1057
Test name
Test status
Simulation time 65173357 ps
CPU time 0.73 seconds
Started Jul 18 06:47:37 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 203836 kb
Host smart-56a17662-98b7-4677-8bfd-311ae196428a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313949577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.313949577
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1878659191
Short name T1130
Test name
Test status
Simulation time 14353761 ps
CPU time 0.73 seconds
Started Jul 18 06:47:40 PM PDT 24
Finished Jul 18 06:47:43 PM PDT 24
Peak memory 203812 kb
Host smart-1d262d1a-d54f-416e-852f-2acc7f40553b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878659191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1878659191
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.798840921
Short name T1094
Test name
Test status
Simulation time 30198604 ps
CPU time 0.71 seconds
Started Jul 18 06:47:40 PM PDT 24
Finished Jul 18 06:47:42 PM PDT 24
Peak memory 203844 kb
Host smart-24953b40-4d06-4cf1-b546-dff9a574b10e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798840921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.798840921
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4251716884
Short name T1067
Test name
Test status
Simulation time 96207584 ps
CPU time 0.72 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:45 PM PDT 24
Peak memory 204236 kb
Host smart-60a0705b-797e-4b6e-a3e3-4ad8f0914c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251716884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4251716884
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.705032598
Short name T1009
Test name
Test status
Simulation time 73576141 ps
CPU time 0.72 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 204056 kb
Host smart-346ab75a-0a98-4626-9672-b4524572ca81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705032598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.705032598
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3274725718
Short name T1026
Test name
Test status
Simulation time 74381984 ps
CPU time 0.73 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 203788 kb
Host smart-e49bdbb4-98b0-42b7-8b32-95ce2662bbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274725718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3274725718
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2416991797
Short name T1100
Test name
Test status
Simulation time 47987248 ps
CPU time 0.76 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:46 PM PDT 24
Peak memory 203780 kb
Host smart-aff1f5f0-a09d-4e28-91d0-632b12c1d400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416991797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2416991797
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.589798856
Short name T1040
Test name
Test status
Simulation time 11957861 ps
CPU time 0.77 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:47:42 PM PDT 24
Peak memory 203928 kb
Host smart-f5055031-472f-4aff-a682-0421dec5eb35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589798856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.589798856
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.370468906
Short name T1037
Test name
Test status
Simulation time 37401714 ps
CPU time 0.74 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 204148 kb
Host smart-9d07e28c-c58b-4368-b8cd-4a47605ca951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370468906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.370468906
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.2673823846
Short name T1071
Test name
Test status
Simulation time 46503150 ps
CPU time 0.79 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:47 PM PDT 24
Peak memory 203832 kb
Host smart-226742cb-7b47-4d78-8c42-84d66be29d9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673823846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
2673823846
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3470293030
Short name T1092
Test name
Test status
Simulation time 2255590265 ps
CPU time 27.04 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:55 PM PDT 24
Peak memory 207160 kb
Host smart-a2bfab36-31e7-4210-bcb3-a91977941ada
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470293030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3470293030
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1513346030
Short name T117
Test name
Test status
Simulation time 3540035332 ps
CPU time 24.83 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:58 PM PDT 24
Peak memory 206940 kb
Host smart-353b6920-1a4e-4953-9c39-702a2e41da3a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513346030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1513346030
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1804975583
Short name T82
Test name
Test status
Simulation time 55193543 ps
CPU time 0.93 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:26 PM PDT 24
Peak memory 206820 kb
Host smart-bb19a057-dcaf-4def-bd47-137f62103dda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804975583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1804975583
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1673385880
Short name T1083
Test name
Test status
Simulation time 481325313 ps
CPU time 2.58 seconds
Started Jul 18 06:47:20 PM PDT 24
Finished Jul 18 06:47:23 PM PDT 24
Peak memory 217868 kb
Host smart-8a2f0a8b-0540-47e2-8721-8b2a6c95eb3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673385880 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.1673385880
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.281700093
Short name T1126
Test name
Test status
Simulation time 517074863 ps
CPU time 1.5 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:31 PM PDT 24
Peak memory 215220 kb
Host smart-18567b24-9084-4f16-8f09-b65dcebc7d4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281700093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.281700093
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2764066020
Short name T1023
Test name
Test status
Simulation time 22685217 ps
CPU time 0.7 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 204132 kb
Host smart-049ca186-bb5d-4003-9f52-c27319f2db6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764066020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
764066020
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1909837985
Short name T126
Test name
Test status
Simulation time 34939390 ps
CPU time 1.34 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:29 PM PDT 24
Peak memory 215440 kb
Host smart-20a6c6ed-567f-4004-8132-ab086aed973f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909837985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1909837985
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2933189881
Short name T1090
Test name
Test status
Simulation time 15190238 ps
CPU time 0.68 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 203624 kb
Host smart-3e4dbc3c-9333-4688-84f3-f1b20bccaac0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933189881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2933189881
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2921200459
Short name T1084
Test name
Test status
Simulation time 29172545 ps
CPU time 1.85 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:32 PM PDT 24
Peak memory 215844 kb
Host smart-a417066b-0d30-41a8-901b-803e9e9589c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921200459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2921200459
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1927661859
Short name T1107
Test name
Test status
Simulation time 63923086 ps
CPU time 1.93 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:38 PM PDT 24
Peak memory 215448 kb
Host smart-99161bd1-58cc-4f17-899d-f51737bbfad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927661859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
927661859
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3008753090
Short name T107
Test name
Test status
Simulation time 591615429 ps
CPU time 18.74 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:52 PM PDT 24
Peak memory 215228 kb
Host smart-a85f527c-65a5-4b5c-94bf-d2bfe474d351
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008753090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3008753090
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1972577180
Short name T1119
Test name
Test status
Simulation time 21342836 ps
CPU time 0.78 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:47:42 PM PDT 24
Peak memory 203700 kb
Host smart-38bccde3-0aca-45f5-9ead-dc3abd434bf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972577180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1972577180
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3107123868
Short name T1122
Test name
Test status
Simulation time 26552891 ps
CPU time 0.74 seconds
Started Jul 18 06:47:39 PM PDT 24
Finished Jul 18 06:47:42 PM PDT 24
Peak memory 204152 kb
Host smart-2ff94164-e52a-48b0-aa7e-15eab414f7a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107123868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3107123868
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2083299606
Short name T1029
Test name
Test status
Simulation time 21911732 ps
CPU time 0.71 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 203832 kb
Host smart-57210eaf-c223-4147-a55d-1898f06787b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083299606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2083299606
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3621436326
Short name T1025
Test name
Test status
Simulation time 18210007 ps
CPU time 0.77 seconds
Started Jul 18 06:47:48 PM PDT 24
Finished Jul 18 06:47:57 PM PDT 24
Peak memory 203824 kb
Host smart-95d78bfc-5059-4eb9-ad8c-b63321998e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621436326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3621436326
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3131070593
Short name T1030
Test name
Test status
Simulation time 12364807 ps
CPU time 0.71 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:48 PM PDT 24
Peak memory 203824 kb
Host smart-81fc58c2-d25f-4c55-9cdb-e6b1921c2c3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131070593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3131070593
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1169189160
Short name T1006
Test name
Test status
Simulation time 42897015 ps
CPU time 0.71 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:45 PM PDT 24
Peak memory 203712 kb
Host smart-9cbbe21f-df29-47f6-9a70-9273a865d0cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169189160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1169189160
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4174937332
Short name T1055
Test name
Test status
Simulation time 11338916 ps
CPU time 0.71 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:45 PM PDT 24
Peak memory 203660 kb
Host smart-e86b7311-979e-4715-b387-0abee44f057a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174937332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4174937332
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.333817879
Short name T1021
Test name
Test status
Simulation time 29645071 ps
CPU time 0.73 seconds
Started Jul 18 06:47:44 PM PDT 24
Finished Jul 18 06:47:50 PM PDT 24
Peak memory 203832 kb
Host smart-b0ce16b1-c8d2-4998-a567-cc033a136582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333817879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.333817879
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.236869162
Short name T1050
Test name
Test status
Simulation time 13129607 ps
CPU time 0.73 seconds
Started Jul 18 06:47:38 PM PDT 24
Finished Jul 18 06:47:40 PM PDT 24
Peak memory 203832 kb
Host smart-d1b12646-1f45-4f8e-ac42-45f20a177d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236869162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.236869162
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1062075658
Short name T1042
Test name
Test status
Simulation time 41069225 ps
CPU time 0.73 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 203792 kb
Host smart-5cee0f7f-9caa-4def-a08e-d5a54f6a0b11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062075658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1062075658
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.2317516693
Short name T1105
Test name
Test status
Simulation time 831858154 ps
CPU time 8.78 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 214708 kb
Host smart-53425a88-e1e0-468e-987e-536facc93be8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317516693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.2317516693
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2308043738
Short name T122
Test name
Test status
Simulation time 1847468495 ps
CPU time 27.05 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:58 PM PDT 24
Peak memory 207104 kb
Host smart-c5597360-a93b-4054-bd34-81a643977c35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308043738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2308043738
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1170596522
Short name T1118
Test name
Test status
Simulation time 86438415 ps
CPU time 1.38 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:31 PM PDT 24
Peak memory 215268 kb
Host smart-477bf2c0-04b9-450a-a04e-2527a4141546
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170596522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1170596522
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2345180539
Short name T1052
Test name
Test status
Simulation time 57067968 ps
CPU time 4.13 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 218256 kb
Host smart-683deede-bfed-4a57-833c-5ab499992c7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345180539 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2345180539
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.55197101
Short name T1108
Test name
Test status
Simulation time 95141825 ps
CPU time 2.73 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215260 kb
Host smart-b880e73f-f7f8-4ebf-9271-dede42186a2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55197101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.55197101
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.19539238
Short name T1036
Test name
Test status
Simulation time 23453892 ps
CPU time 0.69 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:27 PM PDT 24
Peak memory 203836 kb
Host smart-b0164560-f8cf-40bc-a408-c17c4289b7a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19539238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.19539238
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3919522688
Short name T125
Test name
Test status
Simulation time 30779579 ps
CPU time 1.6 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 215160 kb
Host smart-c3a317ed-fde1-4167-a10f-9441f6ecace3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919522688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3919522688
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2232606648
Short name T1034
Test name
Test status
Simulation time 30375184 ps
CPU time 0.71 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:26 PM PDT 24
Peak memory 203020 kb
Host smart-0a85e515-a293-42ac-a170-8cf62f44c309
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232606648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2232606648
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2237813933
Short name T1080
Test name
Test status
Simulation time 111795873 ps
CPU time 2.88 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:27 PM PDT 24
Peak memory 215312 kb
Host smart-537048ef-d613-4d73-8fe7-059d0f8e515a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237813933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2237813933
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3222996408
Short name T97
Test name
Test status
Simulation time 142855349 ps
CPU time 2.04 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215480 kb
Host smart-fdd2888e-67c8-4d9d-961e-b79b30d2d348
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222996408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
222996408
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4261421253
Short name T106
Test name
Test status
Simulation time 296985447 ps
CPU time 17.14 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:51 PM PDT 24
Peak memory 215576 kb
Host smart-362e2b82-35c5-4b4f-9340-8d07b979c433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261421253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4261421253
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2947861985
Short name T1091
Test name
Test status
Simulation time 34699838 ps
CPU time 0.76 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:55 PM PDT 24
Peak memory 203764 kb
Host smart-4da475b9-5c00-4720-a4f0-9a2ea0610cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947861985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2947861985
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4027755179
Short name T1072
Test name
Test status
Simulation time 111363520 ps
CPU time 0.79 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:47 PM PDT 24
Peak memory 203792 kb
Host smart-18c5ef19-b895-4507-993e-c3b2a2d67bde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027755179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4027755179
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.256078300
Short name T1008
Test name
Test status
Simulation time 38501387 ps
CPU time 0.7 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:44 PM PDT 24
Peak memory 203788 kb
Host smart-491be91c-1e2f-4598-9ed8-087d043da410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256078300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.256078300
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.996160807
Short name T1109
Test name
Test status
Simulation time 47705600 ps
CPU time 0.7 seconds
Started Jul 18 06:47:41 PM PDT 24
Finished Jul 18 06:47:43 PM PDT 24
Peak memory 203796 kb
Host smart-83b650de-c616-4723-913f-a7d23a1f60f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996160807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.996160807
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3373096408
Short name T1010
Test name
Test status
Simulation time 17369755 ps
CPU time 0.78 seconds
Started Jul 18 06:47:43 PM PDT 24
Finished Jul 18 06:47:48 PM PDT 24
Peak memory 204096 kb
Host smart-8c7a97a2-81d1-4df4-94e2-12dc76424efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373096408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3373096408
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1394268865
Short name T1007
Test name
Test status
Simulation time 33818762 ps
CPU time 0.66 seconds
Started Jul 18 06:47:46 PM PDT 24
Finished Jul 18 06:47:54 PM PDT 24
Peak memory 204064 kb
Host smart-a9597ffa-3bdf-4b3d-a533-ca1b2fa1d99a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394268865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1394268865
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3733420127
Short name T1110
Test name
Test status
Simulation time 32720310 ps
CPU time 0.74 seconds
Started Jul 18 06:47:47 PM PDT 24
Finished Jul 18 06:47:56 PM PDT 24
Peak memory 203744 kb
Host smart-1164a87a-e115-43ea-8f7f-6ede8d6253e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733420127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3733420127
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2468464675
Short name T1073
Test name
Test status
Simulation time 22992572 ps
CPU time 0.74 seconds
Started Jul 18 06:47:45 PM PDT 24
Finished Jul 18 06:47:53 PM PDT 24
Peak memory 203808 kb
Host smart-c64aa2bb-8263-42c3-aa1f-11d3b5bf11a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468464675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2468464675
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.627554039
Short name T1048
Test name
Test status
Simulation time 26090673 ps
CPU time 0.68 seconds
Started Jul 18 06:47:42 PM PDT 24
Finished Jul 18 06:47:46 PM PDT 24
Peak memory 204132 kb
Host smart-c91868fa-818f-4dca-899a-22fc9e993035
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627554039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.627554039
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2809815588
Short name T1012
Test name
Test status
Simulation time 14885918 ps
CPU time 0.73 seconds
Started Jul 18 06:47:40 PM PDT 24
Finished Jul 18 06:47:43 PM PDT 24
Peak memory 204144 kb
Host smart-cac4c8df-eb82-4f9f-8549-75745f1e80fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809815588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2809815588
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.809828550
Short name T1087
Test name
Test status
Simulation time 525407201 ps
CPU time 3.82 seconds
Started Jul 18 06:47:21 PM PDT 24
Finished Jul 18 06:47:27 PM PDT 24
Peak memory 218284 kb
Host smart-8d0167a9-a07c-49d1-9cfa-f925b8e4a5ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809828550 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.809828550
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3305987648
Short name T114
Test name
Test status
Simulation time 299362278 ps
CPU time 2.01 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:32 PM PDT 24
Peak memory 215380 kb
Host smart-fd55c2a9-3787-4a83-a922-31387912659f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305987648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
305987648
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1795500930
Short name T1096
Test name
Test status
Simulation time 11882910 ps
CPU time 0.72 seconds
Started Jul 18 06:47:22 PM PDT 24
Finished Jul 18 06:47:28 PM PDT 24
Peak memory 203820 kb
Host smart-90025bc3-707a-4f9a-ad3e-52e3698c5cd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795500930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
795500930
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.525645936
Short name T134
Test name
Test status
Simulation time 247788674 ps
CPU time 4 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215284 kb
Host smart-31461008-913e-44e8-a1ed-237b4cf00167
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525645936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.525645936
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3636159895
Short name T149
Test name
Test status
Simulation time 5217540021 ps
CPU time 7.58 seconds
Started Jul 18 06:47:21 PM PDT 24
Finished Jul 18 06:47:30 PM PDT 24
Peak memory 215888 kb
Host smart-2dcc1dd7-5941-4924-9734-316a1fb4b759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636159895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3636159895
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.4204388943
Short name T1112
Test name
Test status
Simulation time 81804940 ps
CPU time 2.5 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:32 PM PDT 24
Peak memory 216516 kb
Host smart-812b4333-5292-4f90-8eb1-3ef9853cbaab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204388943 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.4204388943
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2561177153
Short name T1121
Test name
Test status
Simulation time 45040853 ps
CPU time 1.57 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:29 PM PDT 24
Peak memory 215496 kb
Host smart-1260a6e4-6de6-4c91-b7fe-fc683c8b1c08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561177153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
561177153
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1357602029
Short name T1125
Test name
Test status
Simulation time 24151867 ps
CPU time 0.73 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:30 PM PDT 24
Peak memory 203764 kb
Host smart-8b588d51-5b00-404c-9ab7-39ab1d1d77cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357602029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
357602029
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.527576986
Short name T1022
Test name
Test status
Simulation time 452544501 ps
CPU time 3.06 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 215348 kb
Host smart-2fb6edf8-26d0-4349-8afb-592cbe2100c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527576986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.527576986
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.4208668716
Short name T1089
Test name
Test status
Simulation time 171446630 ps
CPU time 3.23 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 215532 kb
Host smart-1ce96108-794b-4aec-80e7-11baa6a74b83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208668716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.4
208668716
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3987951706
Short name T1068
Test name
Test status
Simulation time 2702057969 ps
CPU time 14.84 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:49 PM PDT 24
Peak memory 223600 kb
Host smart-4576a79e-50c0-42cc-81d4-27655d4b7ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987951706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3987951706
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3352513109
Short name T1041
Test name
Test status
Simulation time 166521785 ps
CPU time 1.65 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 215488 kb
Host smart-daf73e22-4cad-4a3d-b902-3f448a7a6d66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352513109 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3352513109
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3520249284
Short name T1014
Test name
Test status
Simulation time 72080654 ps
CPU time 2.54 seconds
Started Jul 18 06:47:21 PM PDT 24
Finished Jul 18 06:47:24 PM PDT 24
Peak memory 215308 kb
Host smart-127cbbd0-36f0-4af5-a897-a96213dca526
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520249284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
520249284
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2468750927
Short name T1019
Test name
Test status
Simulation time 19932184 ps
CPU time 0.73 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:29 PM PDT 24
Peak memory 203996 kb
Host smart-99a8dc7f-0819-4ccd-b0a4-da41c7140837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468750927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
468750927
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2987702310
Short name T1051
Test name
Test status
Simulation time 211645820 ps
CPU time 2.84 seconds
Started Jul 18 06:47:28 PM PDT 24
Finished Jul 18 06:47:39 PM PDT 24
Peak memory 215248 kb
Host smart-1cc7c31e-11b6-40cb-b5fc-62329f45dde7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987702310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2987702310
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3576516381
Short name T1124
Test name
Test status
Simulation time 2069044729 ps
CPU time 12.86 seconds
Started Jul 18 06:47:38 PM PDT 24
Finished Jul 18 06:47:52 PM PDT 24
Peak memory 215476 kb
Host smart-7c90cbef-c7b7-42e5-b0a0-f19fcb0f393f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576516381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3576516381
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3175900707
Short name T1065
Test name
Test status
Simulation time 151498335 ps
CPU time 2.41 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 215508 kb
Host smart-6b78f375-ddf6-455b-bd66-21d56244989a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175900707 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3175900707
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.921557644
Short name T1103
Test name
Test status
Simulation time 29225807 ps
CPU time 1.8 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 215252 kb
Host smart-025355ca-056a-43bc-9257-04291e05bbc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921557644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.921557644
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1073380553
Short name T1099
Test name
Test status
Simulation time 13858646 ps
CPU time 0.77 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:34 PM PDT 24
Peak memory 203836 kb
Host smart-684fb72b-16f5-48b2-9d89-160eeed51a87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073380553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
073380553
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3532123951
Short name T1015
Test name
Test status
Simulation time 116702802 ps
CPU time 3.21 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 215248 kb
Host smart-98dea073-23c2-45b1-b6d8-d71cc98a8332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532123951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3532123951
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1456319561
Short name T100
Test name
Test status
Simulation time 224011396 ps
CPU time 3.45 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 215464 kb
Host smart-711b61cb-738c-4766-8d0a-f5250d30d24b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456319561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
456319561
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1570449327
Short name T171
Test name
Test status
Simulation time 208301722 ps
CPU time 6.77 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:41 PM PDT 24
Peak memory 215232 kb
Host smart-f779f6d6-0556-4e09-8850-042a9370f89b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570449327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1570449327
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2131586479
Short name T1063
Test name
Test status
Simulation time 78277896 ps
CPU time 1.69 seconds
Started Jul 18 06:47:26 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 216368 kb
Host smart-a31791c9-40b6-40e8-8d9a-0d3b0d6ddb6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131586479 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2131586479
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2743688849
Short name T1088
Test name
Test status
Simulation time 62012193 ps
CPU time 1.96 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 215252 kb
Host smart-efe85529-1cd9-44cd-b170-3aced14029da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743688849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
743688849
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3632709854
Short name T1061
Test name
Test status
Simulation time 39847776 ps
CPU time 0.68 seconds
Started Jul 18 06:47:25 PM PDT 24
Finished Jul 18 06:47:33 PM PDT 24
Peak memory 203828 kb
Host smart-c09d33ea-b383-4103-b9c2-d431d2667771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632709854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
632709854
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3054429979
Short name T1044
Test name
Test status
Simulation time 115854254 ps
CPU time 1.72 seconds
Started Jul 18 06:47:27 PM PDT 24
Finished Jul 18 06:47:37 PM PDT 24
Peak memory 215372 kb
Host smart-484128d5-c1ec-49e7-b6f4-c997c545b34e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054429979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3054429979
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2975225841
Short name T168
Test name
Test status
Simulation time 158645382 ps
CPU time 4.48 seconds
Started Jul 18 06:47:24 PM PDT 24
Finished Jul 18 06:47:36 PM PDT 24
Peak memory 215472 kb
Host smart-ae294099-4e42-4314-83b5-07c7bfbceb73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975225841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
975225841
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1015816336
Short name T1075
Test name
Test status
Simulation time 107268545 ps
CPU time 6.77 seconds
Started Jul 18 06:47:23 PM PDT 24
Finished Jul 18 06:47:35 PM PDT 24
Peak memory 215444 kb
Host smart-56f0627d-39a1-4fe8-915d-d8aacd21c90f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015816336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1015816336
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2847570540
Short name T755
Test name
Test status
Simulation time 18249547 ps
CPU time 0.77 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:00 PM PDT 24
Peak memory 205352 kb
Host smart-272bb7e6-411e-4a73-bf48-50277626db17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847570540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
847570540
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.854340120
Short name T854
Test name
Test status
Simulation time 717086187 ps
CPU time 12.36 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:11 PM PDT 24
Peak memory 224952 kb
Host smart-f67e4e0a-0680-48c2-9728-0ef8db118cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854340120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.854340120
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2412833792
Short name T749
Test name
Test status
Simulation time 157800901 ps
CPU time 0.77 seconds
Started Jul 18 06:15:32 PM PDT 24
Finished Jul 18 06:15:35 PM PDT 24
Peak memory 206356 kb
Host smart-70bbccb0-bf52-4de4-9513-5bf50d2ef0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412833792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2412833792
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.253854970
Short name T240
Test name
Test status
Simulation time 15293197462 ps
CPU time 103.08 seconds
Started Jul 18 06:15:56 PM PDT 24
Finished Jul 18 06:17:42 PM PDT 24
Peak memory 249596 kb
Host smart-be328c29-15c8-40f4-a893-4be79c9768cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253854970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.253854970
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.1082749489
Short name T532
Test name
Test status
Simulation time 11605256345 ps
CPU time 60.82 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:17:00 PM PDT 24
Peak memory 239628 kb
Host smart-dbdef69c-c4b5-493c-b73c-d77d880c5713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082749489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1082749489
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2844238745
Short name T763
Test name
Test status
Simulation time 189250242772 ps
CPU time 108.51 seconds
Started Jul 18 06:15:55 PM PDT 24
Finished Jul 18 06:17:46 PM PDT 24
Peak memory 225044 kb
Host smart-43c4d490-fe8c-480f-a925-7ffc8dd3be42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844238745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2844238745
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2356196104
Short name T926
Test name
Test status
Simulation time 1151673684 ps
CPU time 10.82 seconds
Started Jul 18 06:15:56 PM PDT 24
Finished Jul 18 06:16:09 PM PDT 24
Peak memory 224944 kb
Host smart-0a3a8a3f-1396-49bb-8f54-a2d1cb68a7a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356196104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2356196104
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1505965232
Short name T936
Test name
Test status
Simulation time 3369710454 ps
CPU time 9.79 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:09 PM PDT 24
Peak memory 234532 kb
Host smart-6c3d7904-8316-448d-b17c-da9ebcd946de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505965232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1505965232
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1562830361
Short name T945
Test name
Test status
Simulation time 2241564979 ps
CPU time 9.44 seconds
Started Jul 18 06:15:32 PM PDT 24
Finished Jul 18 06:15:43 PM PDT 24
Peak memory 224820 kb
Host smart-58889ef5-f291-45d9-a56c-ab65ed77475b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562830361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1562830361
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.558880872
Short name T828
Test name
Test status
Simulation time 6217282069 ps
CPU time 14.54 seconds
Started Jul 18 06:15:33 PM PDT 24
Finished Jul 18 06:15:50 PM PDT 24
Peak memory 233148 kb
Host smart-11c2555e-76db-4f8b-a52f-ed2a92b5c1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558880872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.558880872
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3229007368
Short name T242
Test name
Test status
Simulation time 586054397 ps
CPU time 8.67 seconds
Started Jul 18 06:15:40 PM PDT 24
Finished Jul 18 06:15:49 PM PDT 24
Peak memory 249784 kb
Host smart-8abb5a9c-a149-4db9-9bde-11a1eea8bc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229007368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3229007368
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1738636280
Short name T567
Test name
Test status
Simulation time 310665386 ps
CPU time 2.85 seconds
Started Jul 18 06:15:35 PM PDT 24
Finished Jul 18 06:15:40 PM PDT 24
Peak memory 224992 kb
Host smart-f2902265-501c-4ca9-bb3b-6835b93253e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738636280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1738636280
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2926119602
Short name T475
Test name
Test status
Simulation time 332222770 ps
CPU time 5.28 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:04 PM PDT 24
Peak memory 220228 kb
Host smart-abba1a88-9c7c-4c09-90dd-8bca1c957aaf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2926119602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2926119602
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1195843842
Short name T753
Test name
Test status
Simulation time 79023146 ps
CPU time 1.15 seconds
Started Jul 18 06:15:55 PM PDT 24
Finished Jul 18 06:15:59 PM PDT 24
Peak memory 215540 kb
Host smart-59bac59e-18b3-4df0-8122-bdad7ac592b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195843842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1195843842
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2123954606
Short name T356
Test name
Test status
Simulation time 2319309277 ps
CPU time 23.76 seconds
Started Jul 18 06:15:31 PM PDT 24
Finished Jul 18 06:15:55 PM PDT 24
Peak memory 216772 kb
Host smart-ece64b54-7af7-4ae1-ba41-acae8a566874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123954606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2123954606
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3727937429
Short name T419
Test name
Test status
Simulation time 14879117 ps
CPU time 0.76 seconds
Started Jul 18 06:15:31 PM PDT 24
Finished Jul 18 06:15:33 PM PDT 24
Peak memory 206360 kb
Host smart-c238f2e1-6d56-4368-8433-832e11693454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727937429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3727937429
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2265503743
Short name T414
Test name
Test status
Simulation time 21311292 ps
CPU time 0.99 seconds
Started Jul 18 06:15:32 PM PDT 24
Finished Jul 18 06:15:35 PM PDT 24
Peak memory 207412 kb
Host smart-2f387f19-bab3-4a4e-ac49-da87485060ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265503743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2265503743
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3974180297
Short name T76
Test name
Test status
Simulation time 40618265 ps
CPU time 0.72 seconds
Started Jul 18 06:15:32 PM PDT 24
Finished Jul 18 06:15:34 PM PDT 24
Peak memory 206096 kb
Host smart-8b7d52bd-2951-4d93-8f40-3f9f377d7048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974180297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3974180297
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2906503601
Short name T847
Test name
Test status
Simulation time 1485489967 ps
CPU time 6.31 seconds
Started Jul 18 06:15:55 PM PDT 24
Finished Jul 18 06:16:03 PM PDT 24
Peak memory 224884 kb
Host smart-b10400a8-c3b5-4cd9-9370-8972094681e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906503601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2906503601
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1058343630
Short name T338
Test name
Test status
Simulation time 46135743 ps
CPU time 0.75 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:14 PM PDT 24
Peak memory 205972 kb
Host smart-45c34185-0c56-440e-87de-bc3cd0101284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058343630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
058343630
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.3033247399
Short name T574
Test name
Test status
Simulation time 906402712 ps
CPU time 3.65 seconds
Started Jul 18 06:16:04 PM PDT 24
Finished Jul 18 06:16:08 PM PDT 24
Peak memory 225020 kb
Host smart-283b2b6a-6085-4e24-8a3d-e204b1bc54fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033247399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.3033247399
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1785800222
Short name T493
Test name
Test status
Simulation time 178507652 ps
CPU time 0.76 seconds
Started Jul 18 06:16:03 PM PDT 24
Finished Jul 18 06:16:04 PM PDT 24
Peak memory 206184 kb
Host smart-9b60574d-63c7-4e33-a912-6e537018c6fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785800222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1785800222
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1033895083
Short name T584
Test name
Test status
Simulation time 20910392061 ps
CPU time 43.87 seconds
Started Jul 18 06:16:13 PM PDT 24
Finished Jul 18 06:16:59 PM PDT 24
Peak memory 236016 kb
Host smart-8849ea75-994a-43cb-b014-9ee684c880d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033895083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1033895083
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.493899594
Short name T73
Test name
Test status
Simulation time 12558357895 ps
CPU time 120.05 seconds
Started Jul 18 06:16:13 PM PDT 24
Finished Jul 18 06:18:15 PM PDT 24
Peak memory 240576 kb
Host smart-d8c3a94e-c6dc-4bbe-ae5a-d2c3363312e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493899594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.493899594
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2153366038
Short name T596
Test name
Test status
Simulation time 192804725843 ps
CPU time 506.06 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:24:39 PM PDT 24
Peak memory 267232 kb
Host smart-e4690573-4ebb-447e-a7b5-bfffa64c1826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153366038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2153366038
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2731345215
Short name T604
Test name
Test status
Simulation time 194635507 ps
CPU time 5.53 seconds
Started Jul 18 06:16:03 PM PDT 24
Finished Jul 18 06:16:09 PM PDT 24
Peak memory 225040 kb
Host smart-1039686f-7efb-494d-ad3c-f1c9143a62a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731345215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2731345215
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2920791108
Short name T442
Test name
Test status
Simulation time 1153767351 ps
CPU time 30.19 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:44 PM PDT 24
Peak memory 255992 kb
Host smart-63962cb5-9999-4ee0-af6f-c99887d606ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920791108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2920791108
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.90424284
Short name T37
Test name
Test status
Simulation time 28264762 ps
CPU time 2.3 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:01 PM PDT 24
Peak memory 224284 kb
Host smart-13dce393-1e96-4e5b-962b-936b1e4ee043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90424284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.90424284
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2514442562
Short name T984
Test name
Test status
Simulation time 32267884382 ps
CPU time 51.51 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:51 PM PDT 24
Peak memory 224960 kb
Host smart-1273d0a8-92ec-4f3c-ab8f-e50bed9a8f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514442562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2514442562
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1306482829
Short name T243
Test name
Test status
Simulation time 142360724519 ps
CPU time 21.31 seconds
Started Jul 18 06:15:57 PM PDT 24
Finished Jul 18 06:16:20 PM PDT 24
Peak memory 233228 kb
Host smart-fd537ffd-a105-44ad-acb3-df40e730d284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306482829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1306482829
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.698420554
Short name T236
Test name
Test status
Simulation time 21065751513 ps
CPU time 34.11 seconds
Started Jul 18 06:16:03 PM PDT 24
Finished Jul 18 06:16:38 PM PDT 24
Peak memory 233372 kb
Host smart-2e694f10-30ad-404a-8565-92bcffe6172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698420554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.698420554
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3457570365
Short name T428
Test name
Test status
Simulation time 5624387175 ps
CPU time 24.92 seconds
Started Jul 18 06:16:13 PM PDT 24
Finished Jul 18 06:16:40 PM PDT 24
Peak memory 220992 kb
Host smart-7f17ce40-37a3-4c04-86f7-29c4b9edf718
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3457570365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3457570365
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.700750257
Short name T70
Test name
Test status
Simulation time 1309042518 ps
CPU time 1.15 seconds
Started Jul 18 06:16:11 PM PDT 24
Finished Jul 18 06:16:13 PM PDT 24
Peak memory 235988 kb
Host smart-9120cbfe-0b81-4740-a8aa-325041176664
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700750257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.700750257
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4038770825
Short name T852
Test name
Test status
Simulation time 13574313300 ps
CPU time 14.08 seconds
Started Jul 18 06:16:02 PM PDT 24
Finished Jul 18 06:16:17 PM PDT 24
Peak memory 217112 kb
Host smart-b4b8a428-d0e8-482b-9bf5-d6a4c7666540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038770825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4038770825
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1346837694
Short name T902
Test name
Test status
Simulation time 1994244701 ps
CPU time 6.91 seconds
Started Jul 18 06:15:56 PM PDT 24
Finished Jul 18 06:16:05 PM PDT 24
Peak memory 216688 kb
Host smart-c8df9fb7-e119-45e3-9276-a0900f21271f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346837694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1346837694
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.202412292
Short name T330
Test name
Test status
Simulation time 101212854 ps
CPU time 1.79 seconds
Started Jul 18 06:15:56 PM PDT 24
Finished Jul 18 06:16:00 PM PDT 24
Peak memory 216644 kb
Host smart-de550d98-e10e-4d14-a556-ac8fdc2852f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202412292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.202412292
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1909798017
Short name T731
Test name
Test status
Simulation time 37168097 ps
CPU time 0.92 seconds
Started Jul 18 06:15:56 PM PDT 24
Finished Jul 18 06:15:59 PM PDT 24
Peak memory 207468 kb
Host smart-c09801dc-17fe-463d-8e74-b390d99669e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909798017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1909798017
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1635644438
Short name T458
Test name
Test status
Simulation time 17622024848 ps
CPU time 16.15 seconds
Started Jul 18 06:15:56 PM PDT 24
Finished Jul 18 06:16:14 PM PDT 24
Peak memory 241392 kb
Host smart-d395630e-c808-4b76-a5a9-3cc4f1062ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635644438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1635644438
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3955978929
Short name T384
Test name
Test status
Simulation time 14512333 ps
CPU time 0.72 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:18:26 PM PDT 24
Peak memory 205180 kb
Host smart-8daf282c-ddf5-4037-a110-9f44cfe53e49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955978929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3955978929
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2629127150
Short name T897
Test name
Test status
Simulation time 1425543068 ps
CPU time 7.35 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:18:34 PM PDT 24
Peak memory 234192 kb
Host smart-d0db373a-282a-448a-a4fe-d65b3f942507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629127150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2629127150
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.705140706
Short name T350
Test name
Test status
Simulation time 16649338 ps
CPU time 0.77 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:24 PM PDT 24
Peak memory 207336 kb
Host smart-be33272a-ce51-4b1b-9c9a-b5111c9b712a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705140706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.705140706
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.87038345
Short name T455
Test name
Test status
Simulation time 63744733799 ps
CPU time 81.42 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:19:44 PM PDT 24
Peak memory 252448 kb
Host smart-69d89bb0-abbc-42b4-8af9-1d2c9225f251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87038345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.87038345
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.4130956142
Short name T870
Test name
Test status
Simulation time 126569574517 ps
CPU time 349.5 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:24:15 PM PDT 24
Peak memory 252852 kb
Host smart-cfacff02-8477-4bf4-9351-9b272afeba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130956142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.4130956142
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4146248036
Short name T702
Test name
Test status
Simulation time 80784272 ps
CPU time 4.46 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:28 PM PDT 24
Peak memory 233068 kb
Host smart-19d61f45-05c7-49d5-bf04-10974ccd32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146248036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4146248036
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1101721226
Short name T175
Test name
Test status
Simulation time 1057360227 ps
CPU time 14.37 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:18:37 PM PDT 24
Peak memory 235044 kb
Host smart-3838cd51-7d6c-4104-8ab5-991087671edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101721226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1101721226
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2424653294
Short name T594
Test name
Test status
Simulation time 872845181 ps
CPU time 4.43 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:27 PM PDT 24
Peak memory 224888 kb
Host smart-90899ff1-b7ce-4f60-8f92-b3c7f967c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424653294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2424653294
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3311191020
Short name T689
Test name
Test status
Simulation time 3695288595 ps
CPU time 6.46 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 224868 kb
Host smart-5ea2c274-3715-4ae3-b5d5-c315ddcec175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311191020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3311191020
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2893115699
Short name T26
Test name
Test status
Simulation time 354485661 ps
CPU time 2.22 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:18:30 PM PDT 24
Peak memory 224928 kb
Host smart-badbaede-adf4-4a36-baf6-a31f63a1db00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893115699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2893115699
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1343008113
Short name T23
Test name
Test status
Simulation time 69081455 ps
CPU time 3.71 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:28 PM PDT 24
Peak memory 223336 kb
Host smart-ffb0c724-8f80-48a7-b248-cc2a3be88e08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1343008113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1343008113
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.349756371
Short name T513
Test name
Test status
Simulation time 40884963 ps
CPU time 0.95 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:18:26 PM PDT 24
Peak memory 208184 kb
Host smart-174bbfaa-655d-4230-84e5-c979e4f4dd0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349756371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.349756371
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2217843299
Short name T677
Test name
Test status
Simulation time 1703370485 ps
CPU time 9.73 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:33 PM PDT 24
Peak memory 216604 kb
Host smart-b5e5b046-17ed-46ce-bdee-551e42c859e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217843299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2217843299
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.425314641
Short name T386
Test name
Test status
Simulation time 62225010 ps
CPU time 1.39 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:18:23 PM PDT 24
Peak memory 208444 kb
Host smart-8925e976-8727-48b2-b654-82b0f52dfb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425314641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.425314641
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3317484053
Short name T446
Test name
Test status
Simulation time 20535767 ps
CPU time 0.83 seconds
Started Jul 18 06:18:24 PM PDT 24
Finished Jul 18 06:18:30 PM PDT 24
Peak memory 206468 kb
Host smart-fbe46a53-7b9b-411b-ab8a-21a98aac66bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317484053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3317484053
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2271193307
Short name T257
Test name
Test status
Simulation time 162950411 ps
CPU time 4.04 seconds
Started Jul 18 06:18:18 PM PDT 24
Finished Jul 18 06:18:25 PM PDT 24
Peak memory 224928 kb
Host smart-bb4af213-20fb-4692-8e17-97ddd3d069dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271193307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2271193307
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.855016710
Short name T498
Test name
Test status
Simulation time 16383562 ps
CPU time 0.77 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:18:26 PM PDT 24
Peak memory 205376 kb
Host smart-53676b21-f003-4bd1-99aa-c6fd44ebe690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855016710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.855016710
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1848849299
Short name T964
Test name
Test status
Simulation time 166038822 ps
CPU time 2.17 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:18:29 PM PDT 24
Peak memory 232728 kb
Host smart-c1d72432-f4c2-4426-a653-1150b77d03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848849299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1848849299
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.941395329
Short name T650
Test name
Test status
Simulation time 46755927 ps
CPU time 0.78 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:18:27 PM PDT 24
Peak memory 207076 kb
Host smart-7b5e6736-3620-43d4-bf69-47237f94009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941395329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.941395329
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3413114414
Short name T988
Test name
Test status
Simulation time 30532162343 ps
CPU time 237.12 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:22:25 PM PDT 24
Peak memory 253428 kb
Host smart-cbf78fd5-eda0-4860-8ade-f31e3c09b542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413114414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3413114414
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.4182529832
Short name T130
Test name
Test status
Simulation time 11100435827 ps
CPU time 90.01 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:19:58 PM PDT 24
Peak memory 250764 kb
Host smart-ae8f1625-a5c3-487a-8a59-95e9c9d58be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182529832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.4182529832
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3666356545
Short name T8
Test name
Test status
Simulation time 1544701989 ps
CPU time 39.27 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:19:07 PM PDT 24
Peak memory 249524 kb
Host smart-5e9d1d9e-791c-4872-910b-bcae61ef27a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666356545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3666356545
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4173393532
Short name T832
Test name
Test status
Simulation time 19765914886 ps
CPU time 34.76 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:19:03 PM PDT 24
Peak memory 232988 kb
Host smart-8e2063f0-7dbc-4bff-9ee2-2eb6265515bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173393532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4173393532
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2119390873
Short name T953
Test name
Test status
Simulation time 2633133442 ps
CPU time 43.71 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:19:12 PM PDT 24
Peak memory 252108 kb
Host smart-a3e6b94e-14ab-42c3-a23b-bc9b6bf7c3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119390873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2119390873
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.2376093416
Short name T88
Test name
Test status
Simulation time 306663189 ps
CPU time 5.07 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:28 PM PDT 24
Peak memory 224908 kb
Host smart-6a6832a7-ec3d-4ce2-ae20-896b2023bc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376093416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.2376093416
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2389299091
Short name T46
Test name
Test status
Simulation time 7819396839 ps
CPU time 61.31 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:19:30 PM PDT 24
Peak memory 250492 kb
Host smart-25051f48-615b-4a56-86a9-973cfccf3ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389299091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2389299091
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1072579043
Short name T661
Test name
Test status
Simulation time 80345471 ps
CPU time 2.73 seconds
Started Jul 18 06:18:25 PM PDT 24
Finished Jul 18 06:18:33 PM PDT 24
Peak memory 224908 kb
Host smart-3844a759-6741-43fc-9f28-98814509fae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072579043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1072579043
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3341825769
Short name T56
Test name
Test status
Simulation time 457920349 ps
CPU time 3.13 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 233036 kb
Host smart-7f167517-746d-48c7-b005-71eea79c1386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341825769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3341825769
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1442691001
Short name T773
Test name
Test status
Simulation time 808423076 ps
CPU time 8.35 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:18:30 PM PDT 24
Peak memory 223528 kb
Host smart-023bfa31-72b3-4560-8020-85d6ec7a2be2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442691001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1442691001
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.173124363
Short name T189
Test name
Test status
Simulation time 75552963653 ps
CPU time 573.07 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:28:01 PM PDT 24
Peak memory 266060 kb
Host smart-bc7c8bdb-fea7-451d-945d-fd8d3ae498e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173124363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.173124363
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2956671260
Short name T917
Test name
Test status
Simulation time 7935768579 ps
CPU time 38.34 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:19:07 PM PDT 24
Peak memory 216756 kb
Host smart-cdca9c5c-aa8a-4549-85a9-9e5276f14f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956671260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2956671260
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2217199724
Short name T396
Test name
Test status
Simulation time 1929721273 ps
CPU time 7.31 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 216440 kb
Host smart-ab49c99b-3497-49f6-91f1-0dd5b7ac4ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217199724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2217199724
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3887815707
Short name T739
Test name
Test status
Simulation time 94800013 ps
CPU time 1.62 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:18:29 PM PDT 24
Peak memory 216776 kb
Host smart-86a71e80-ddf6-40ca-814e-8776d603fba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887815707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3887815707
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.87188245
Short name T924
Test name
Test status
Simulation time 11048508 ps
CPU time 0.69 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:24 PM PDT 24
Peak memory 206068 kb
Host smart-bfed41e5-54d6-4b06-9326-902aeb2a1e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87188245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.87188245
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1692318859
Short name T670
Test name
Test status
Simulation time 8861510329 ps
CPU time 32.63 seconds
Started Jul 18 06:18:24 PM PDT 24
Finished Jul 18 06:19:02 PM PDT 24
Peak memory 234180 kb
Host smart-797dec54-b3f2-4b46-8d09-c6e00822adad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692318859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1692318859
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1705023288
Short name T718
Test name
Test status
Simulation time 18287973 ps
CPU time 0.72 seconds
Started Jul 18 06:18:35 PM PDT 24
Finished Jul 18 06:18:38 PM PDT 24
Peak memory 206276 kb
Host smart-50dbe500-40ae-4676-ab01-1de6c84310b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705023288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1705023288
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1786731234
Short name T951
Test name
Test status
Simulation time 194163087 ps
CPU time 2.43 seconds
Started Jul 18 06:18:25 PM PDT 24
Finished Jul 18 06:18:32 PM PDT 24
Peak memory 232820 kb
Host smart-e3308813-aa9d-430c-9dce-5db3563d303e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786731234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1786731234
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3030797104
Short name T463
Test name
Test status
Simulation time 16147766 ps
CPU time 0.89 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:18:30 PM PDT 24
Peak memory 206768 kb
Host smart-247aefb1-386c-4dc0-bcc5-3e4e406c9412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030797104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3030797104
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1543748256
Short name T701
Test name
Test status
Simulation time 940489858 ps
CPU time 8.68 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 233168 kb
Host smart-c3d43da4-d966-4e19-bee0-71111bee71f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543748256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1543748256
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3280041432
Short name T671
Test name
Test status
Simulation time 28175552852 ps
CPU time 282.4 seconds
Started Jul 18 06:18:26 PM PDT 24
Finished Jul 18 06:23:12 PM PDT 24
Peak memory 252740 kb
Host smart-8e5be1b9-8aec-4b1e-9a78-a3cc65c1b2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280041432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3280041432
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2617354395
Short name T710
Test name
Test status
Simulation time 3193350312 ps
CPU time 56.37 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:19:21 PM PDT 24
Peak memory 250872 kb
Host smart-080868ef-10d3-4d9a-9cae-66589c41af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617354395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2617354395
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3921977529
Short name T798
Test name
Test status
Simulation time 38010789 ps
CPU time 2.8 seconds
Started Jul 18 06:18:26 PM PDT 24
Finished Jul 18 06:18:33 PM PDT 24
Peak memory 224940 kb
Host smart-98dbb87e-6cb2-4951-975d-193f12d3e55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921977529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3921977529
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.891640115
Short name T695
Test name
Test status
Simulation time 66861996438 ps
CPU time 244.74 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:22:33 PM PDT 24
Peak memory 254864 kb
Host smart-70d3a00d-479d-43e5-bcf6-e8ece3e6603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891640115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.891640115
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1624610470
Short name T664
Test name
Test status
Simulation time 451203181 ps
CPU time 7.08 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:18:36 PM PDT 24
Peak memory 224904 kb
Host smart-249e7759-3faf-4b7b-8741-2b72348eb5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624610470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1624610470
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2982388324
Short name T817
Test name
Test status
Simulation time 102419756 ps
CPU time 2.79 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 233096 kb
Host smart-96242578-8469-4da7-ad3f-b922734538bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982388324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2982388324
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2717497092
Short name T187
Test name
Test status
Simulation time 818974196 ps
CPU time 6.83 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 224924 kb
Host smart-8c964a26-3e69-489f-8d11-72a64e62e35b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717497092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2717497092
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.115619725
Short name T933
Test name
Test status
Simulation time 2081042000 ps
CPU time 6.02 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:18:35 PM PDT 24
Peak memory 240200 kb
Host smart-fb122de8-99eb-469c-b7e1-e14c53f53adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115619725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.115619725
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1144529770
Short name T846
Test name
Test status
Simulation time 4806728256 ps
CPU time 9.49 seconds
Started Jul 18 06:18:25 PM PDT 24
Finished Jul 18 06:18:39 PM PDT 24
Peak memory 220776 kb
Host smart-b55044f1-9c0c-464d-97b4-01ef9215c43c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1144529770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1144529770
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.13396850
Short name T741
Test name
Test status
Simulation time 1214233891 ps
CPU time 9.95 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:18:39 PM PDT 24
Peak memory 219440 kb
Host smart-9973c1a9-02f7-4884-9b42-39e5f4620541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13396850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.13396850
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.2299615655
Short name T344
Test name
Test status
Simulation time 1477900832 ps
CPU time 3.33 seconds
Started Jul 18 06:18:24 PM PDT 24
Finished Jul 18 06:18:32 PM PDT 24
Peak memory 216652 kb
Host smart-39afdae4-9bae-4b80-8ee0-2b9c551e7c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299615655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.2299615655
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3978569025
Short name T597
Test name
Test status
Simulation time 502402417 ps
CPU time 1.64 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 216724 kb
Host smart-577fca90-5bdc-4a39-94e7-45c8e70e4b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978569025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3978569025
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3489701719
Short name T495
Test name
Test status
Simulation time 39413630 ps
CPU time 0.83 seconds
Started Jul 18 06:18:21 PM PDT 24
Finished Jul 18 06:18:27 PM PDT 24
Peak memory 206464 kb
Host smart-cffb70d4-e78d-4b3c-b191-69fdb201df69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489701719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3489701719
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1549479859
Short name T680
Test name
Test status
Simulation time 5401033446 ps
CPU time 4.97 seconds
Started Jul 18 06:18:22 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 224992 kb
Host smart-34b5e630-5848-4af1-ab81-57d61cd6ee22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549479859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1549479859
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.473138136
Short name T898
Test name
Test status
Simulation time 86074862 ps
CPU time 0.73 seconds
Started Jul 18 06:18:39 PM PDT 24
Finished Jul 18 06:18:42 PM PDT 24
Peak memory 205920 kb
Host smart-7aee3026-1d6b-434e-a857-3211e6ffd3ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473138136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.473138136
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.345403133
Short name T521
Test name
Test status
Simulation time 1490927964 ps
CPU time 6.33 seconds
Started Jul 18 06:18:35 PM PDT 24
Finished Jul 18 06:18:44 PM PDT 24
Peak memory 233136 kb
Host smart-93e1209e-b128-4b90-bc6f-125c5e25b9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345403133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.345403133
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1825661583
Short name T34
Test name
Test status
Simulation time 39495787 ps
CPU time 0.78 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:18:40 PM PDT 24
Peak memory 207144 kb
Host smart-007f1806-c587-42ae-830a-18c1319e5d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825661583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1825661583
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.4229441570
Short name T200
Test name
Test status
Simulation time 4232943644 ps
CPU time 55.48 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:19:34 PM PDT 24
Peak memory 249616 kb
Host smart-3fc5de38-65a4-46f6-9b84-869107ace379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229441570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.4229441570
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3129338135
Short name T591
Test name
Test status
Simulation time 1166124530 ps
CPU time 6.94 seconds
Started Jul 18 06:18:37 PM PDT 24
Finished Jul 18 06:18:47 PM PDT 24
Peak memory 217888 kb
Host smart-f7bb4d5f-00af-4d32-92d1-7362d360aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129338135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3129338135
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1751320024
Short name T341
Test name
Test status
Simulation time 165342780 ps
CPU time 3.91 seconds
Started Jul 18 06:18:38 PM PDT 24
Finished Jul 18 06:18:44 PM PDT 24
Peak memory 233168 kb
Host smart-b39b91b6-cc94-4d6e-a999-16cb225c959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751320024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1751320024
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3362671314
Short name T860
Test name
Test status
Simulation time 519887331 ps
CPU time 7.18 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:18:46 PM PDT 24
Peak memory 219228 kb
Host smart-6c7c7edc-6135-445d-8f92-ea9e81dac41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362671314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3362671314
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3013905933
Short name T729
Test name
Test status
Simulation time 6940823299 ps
CPU time 51.26 seconds
Started Jul 18 06:18:37 PM PDT 24
Finished Jul 18 06:19:31 PM PDT 24
Peak memory 240364 kb
Host smart-686f43ed-fe57-4bcf-98fa-3203eb12ce1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013905933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3013905933
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3857003176
Short name T970
Test name
Test status
Simulation time 27105359726 ps
CPU time 20.05 seconds
Started Jul 18 06:18:38 PM PDT 24
Finished Jul 18 06:19:00 PM PDT 24
Peak memory 225044 kb
Host smart-b4ecbd29-3267-4644-87a9-558018088935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857003176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3857003176
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1285480489
Short name T354
Test name
Test status
Simulation time 94148381 ps
CPU time 2.47 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:18:41 PM PDT 24
Peak memory 232832 kb
Host smart-7dd941c1-8396-4a9d-b412-37eaf0852eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285480489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1285480489
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.702924009
Short name T393
Test name
Test status
Simulation time 2259291335 ps
CPU time 10.6 seconds
Started Jul 18 06:18:40 PM PDT 24
Finished Jul 18 06:18:52 PM PDT 24
Peak memory 220496 kb
Host smart-85f6bb1f-57cf-4ff1-a0ba-cd6e2a09f647
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=702924009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.702924009
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3951167132
Short name T152
Test name
Test status
Simulation time 49454077 ps
CPU time 1.03 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:18:40 PM PDT 24
Peak memory 207256 kb
Host smart-17a2fea3-1d84-4c7d-9c44-c39e4a6696cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951167132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3951167132
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.15023460
Short name T72
Test name
Test status
Simulation time 1252757916 ps
CPU time 8.96 seconds
Started Jul 18 06:18:40 PM PDT 24
Finished Jul 18 06:18:50 PM PDT 24
Peak memory 216572 kb
Host smart-67ff6e0d-126f-489b-a953-0dbb0eddd86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15023460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.15023460
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.214224480
Short name T326
Test name
Test status
Simulation time 470413974 ps
CPU time 2.98 seconds
Started Jul 18 06:18:36 PM PDT 24
Finished Jul 18 06:18:41 PM PDT 24
Peak memory 216648 kb
Host smart-112c15da-0a28-4054-acc3-866ca32bc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214224480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.214224480
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4054892293
Short name T923
Test name
Test status
Simulation time 68538450 ps
CPU time 2.66 seconds
Started Jul 18 06:18:39 PM PDT 24
Finished Jul 18 06:18:43 PM PDT 24
Peak memory 216628 kb
Host smart-e867ea41-ce7d-4a04-974c-599833a8adc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054892293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4054892293
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.602520281
Short name T645
Test name
Test status
Simulation time 151716183 ps
CPU time 0.82 seconds
Started Jul 18 06:18:38 PM PDT 24
Finished Jul 18 06:18:41 PM PDT 24
Peak memory 206456 kb
Host smart-7d6b9c0e-121c-4cb7-ad31-e04581b5f576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602520281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.602520281
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1889625067
Short name T550
Test name
Test status
Simulation time 1278141545 ps
CPU time 11.23 seconds
Started Jul 18 06:18:38 PM PDT 24
Finished Jul 18 06:18:52 PM PDT 24
Peak memory 233116 kb
Host smart-22bd6812-7f3c-445c-a01f-3ee98ae7376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889625067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1889625067
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3334719395
Short name T395
Test name
Test status
Simulation time 2468324850 ps
CPU time 12.4 seconds
Started Jul 18 06:18:57 PM PDT 24
Finished Jul 18 06:19:10 PM PDT 24
Peak memory 225028 kb
Host smart-5bda426b-75ca-406a-a733-3cb2a3ddc914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334719395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3334719395
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.2281628762
Short name T920
Test name
Test status
Simulation time 28688707 ps
CPU time 0.79 seconds
Started Jul 18 06:18:39 PM PDT 24
Finished Jul 18 06:18:41 PM PDT 24
Peak memory 207396 kb
Host smart-c1ebe3f1-e668-4a5f-9c5c-f403f12d08d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281628762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.2281628762
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1044730584
Short name T559
Test name
Test status
Simulation time 5498681830 ps
CPU time 84.82 seconds
Started Jul 18 06:18:50 PM PDT 24
Finished Jul 18 06:20:17 PM PDT 24
Peak memory 250644 kb
Host smart-15f57f91-4ef5-4412-8b60-2e654d594129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044730584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1044730584
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2600344548
Short name T291
Test name
Test status
Simulation time 371056179 ps
CPU time 10.8 seconds
Started Jul 18 06:18:58 PM PDT 24
Finished Jul 18 06:19:10 PM PDT 24
Peak memory 237624 kb
Host smart-e3247d5c-7ba9-4aa0-b466-8f71bfa0e416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600344548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2600344548
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.3730642382
Short name T866
Test name
Test status
Simulation time 26487294054 ps
CPU time 107.12 seconds
Started Jul 18 06:18:54 PM PDT 24
Finished Jul 18 06:20:42 PM PDT 24
Peak memory 252196 kb
Host smart-b8f370a7-5623-4be8-b36b-2fc4c70d52d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730642382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.3730642382
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3992955009
Short name T973
Test name
Test status
Simulation time 4022303577 ps
CPU time 23.85 seconds
Started Jul 18 06:18:57 PM PDT 24
Finished Jul 18 06:19:22 PM PDT 24
Peak memory 224972 kb
Host smart-c7315c3b-00a5-4d82-bed0-88618a65f1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992955009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3992955009
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.766406936
Short name T217
Test name
Test status
Simulation time 30616069536 ps
CPU time 57.53 seconds
Started Jul 18 06:18:55 PM PDT 24
Finished Jul 18 06:19:54 PM PDT 24
Peak memory 240628 kb
Host smart-cc0607fe-cfc4-43fb-a627-6e3875c0ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766406936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.766406936
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.4221813171
Short name T213
Test name
Test status
Simulation time 12951382969 ps
CPU time 19.91 seconds
Started Jul 18 06:18:51 PM PDT 24
Finished Jul 18 06:19:12 PM PDT 24
Peak memory 233224 kb
Host smart-d6d69f6d-f262-4886-b297-4443ef116a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221813171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.4221813171
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2842003782
Short name T93
Test name
Test status
Simulation time 4995653228 ps
CPU time 7.78 seconds
Started Jul 18 06:18:56 PM PDT 24
Finished Jul 18 06:19:05 PM PDT 24
Peak memory 225036 kb
Host smart-de9e4a0f-3531-4c82-bdcd-9b606c88cc44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842003782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2842003782
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.591966445
Short name T969
Test name
Test status
Simulation time 178973835 ps
CPU time 4.25 seconds
Started Jul 18 06:18:52 PM PDT 24
Finished Jul 18 06:18:57 PM PDT 24
Peak memory 221080 kb
Host smart-5c9fa3de-40ee-4a5e-b129-cffdc52f4686
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=591966445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.591966445
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3011660909
Short name T425
Test name
Test status
Simulation time 1357886940 ps
CPU time 20.46 seconds
Started Jul 18 06:18:37 PM PDT 24
Finished Jul 18 06:19:00 PM PDT 24
Peak memory 216624 kb
Host smart-f1e22609-acb3-4a71-be76-bcb877dec844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011660909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3011660909
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.520130965
Short name T461
Test name
Test status
Simulation time 925984588 ps
CPU time 7.26 seconds
Started Jul 18 06:18:38 PM PDT 24
Finished Jul 18 06:18:47 PM PDT 24
Peak memory 216704 kb
Host smart-fd61f71a-f476-4bd7-ba8f-04e412f2541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520130965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.520130965
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2446714209
Short name T305
Test name
Test status
Simulation time 250125249 ps
CPU time 0.96 seconds
Started Jul 18 06:18:52 PM PDT 24
Finished Jul 18 06:18:54 PM PDT 24
Peak memory 207472 kb
Host smart-33bc95dc-5f33-4695-957a-a5db4d39e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446714209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2446714209
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2371409949
Short name T429
Test name
Test status
Simulation time 154762615 ps
CPU time 1.06 seconds
Started Jul 18 06:18:55 PM PDT 24
Finished Jul 18 06:18:56 PM PDT 24
Peak memory 207480 kb
Host smart-23b8662f-1ad8-46e3-9278-b5d61c85a8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371409949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2371409949
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3515302877
Short name T28
Test name
Test status
Simulation time 500739962 ps
CPU time 4.02 seconds
Started Jul 18 06:18:57 PM PDT 24
Finished Jul 18 06:19:02 PM PDT 24
Peak memory 224892 kb
Host smart-13dfd228-17f4-4e06-b745-4e4f76abbef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515302877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3515302877
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2210925939
Short name T918
Test name
Test status
Simulation time 11466007 ps
CPU time 0.73 seconds
Started Jul 18 06:19:10 PM PDT 24
Finished Jul 18 06:19:11 PM PDT 24
Peak memory 205356 kb
Host smart-ec7bab74-01fe-4231-98d8-1d2b3cccef4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210925939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2210925939
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.490483872
Short name T806
Test name
Test status
Simulation time 46831028 ps
CPU time 2.29 seconds
Started Jul 18 06:19:10 PM PDT 24
Finished Jul 18 06:19:13 PM PDT 24
Peak memory 224512 kb
Host smart-d78eb304-1fbc-470d-952a-8b2f3abfc74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490483872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.490483872
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.167356997
Short name T534
Test name
Test status
Simulation time 15064136 ps
CPU time 0.82 seconds
Started Jul 18 06:18:54 PM PDT 24
Finished Jul 18 06:18:56 PM PDT 24
Peak memory 207084 kb
Host smart-66368010-b693-46f6-8c9f-f7a40ff28d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167356997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.167356997
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.995808871
Short name T672
Test name
Test status
Simulation time 525453657 ps
CPU time 3.02 seconds
Started Jul 18 06:19:13 PM PDT 24
Finished Jul 18 06:19:17 PM PDT 24
Peak memory 217796 kb
Host smart-6075d088-3fc6-44b6-aa26-6eecdaa5f788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995808871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.995808871
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4203000022
Short name T301
Test name
Test status
Simulation time 4120132749 ps
CPU time 25.68 seconds
Started Jul 18 06:19:13 PM PDT 24
Finished Jul 18 06:19:40 PM PDT 24
Peak memory 218108 kb
Host smart-96a0ea4f-53c4-4a65-a3f6-20f5305bad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203000022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4203000022
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.700406270
Short name T499
Test name
Test status
Simulation time 963271871 ps
CPU time 5.04 seconds
Started Jul 18 06:19:14 PM PDT 24
Finished Jul 18 06:19:20 PM PDT 24
Peak memory 233136 kb
Host smart-7bffbc54-dda6-4710-a39a-b23beac4e4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700406270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.700406270
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.894022753
Short name T363
Test name
Test status
Simulation time 353387048 ps
CPU time 5.15 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:18 PM PDT 24
Peak memory 224944 kb
Host smart-775e20cd-7a28-4bdf-9799-dbba7f693d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894022753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds
.894022753
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2809488312
Short name T646
Test name
Test status
Simulation time 286945988 ps
CPU time 5.16 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:17 PM PDT 24
Peak memory 233120 kb
Host smart-aee1fad4-503f-45af-ba5e-48b65efc5609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809488312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2809488312
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2003066144
Short name T565
Test name
Test status
Simulation time 18930071215 ps
CPU time 87.23 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:20:40 PM PDT 24
Peak memory 233416 kb
Host smart-3e2cd3fd-f62f-4cf4-a4ed-60b112c30153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003066144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2003066144
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2957007904
Short name T562
Test name
Test status
Simulation time 440713434 ps
CPU time 3.61 seconds
Started Jul 18 06:18:53 PM PDT 24
Finished Jul 18 06:18:57 PM PDT 24
Peak memory 224860 kb
Host smart-0ba23927-abf8-43bd-9917-8beb8d038894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957007904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2957007904
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2817224154
Short name T164
Test name
Test status
Simulation time 17553927065 ps
CPU time 12.58 seconds
Started Jul 18 06:18:58 PM PDT 24
Finished Jul 18 06:19:11 PM PDT 24
Peak memory 233132 kb
Host smart-3b84f2f1-52cb-4c31-8a0b-6e894ea36b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817224154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2817224154
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3996671134
Short name T649
Test name
Test status
Simulation time 297170688 ps
CPU time 3.66 seconds
Started Jul 18 06:19:10 PM PDT 24
Finished Jul 18 06:19:15 PM PDT 24
Peak memory 219636 kb
Host smart-a2fa2278-c4fd-4dbd-bd9c-003465ece96d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996671134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3996671134
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3163874282
Short name T382
Test name
Test status
Simulation time 16561387 ps
CPU time 0.76 seconds
Started Jul 18 06:18:54 PM PDT 24
Finished Jul 18 06:18:56 PM PDT 24
Peak memory 206196 kb
Host smart-8e5c4957-782f-493b-abf1-b04b56cca717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163874282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3163874282
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1218777251
Short name T786
Test name
Test status
Simulation time 30001458 ps
CPU time 1.78 seconds
Started Jul 18 06:18:57 PM PDT 24
Finished Jul 18 06:19:00 PM PDT 24
Peak memory 216660 kb
Host smart-d76de90a-5d79-41b3-9e25-d03c3077248d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218777251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1218777251
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.363704055
Short name T669
Test name
Test status
Simulation time 162346478 ps
CPU time 0.87 seconds
Started Jul 18 06:18:54 PM PDT 24
Finished Jul 18 06:18:56 PM PDT 24
Peak memory 206448 kb
Host smart-5020867c-56c4-45a7-993e-92979aaa20d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363704055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.363704055
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.3372889509
Short name T907
Test name
Test status
Simulation time 200395698 ps
CPU time 4.16 seconds
Started Jul 18 06:19:10 PM PDT 24
Finished Jul 18 06:19:16 PM PDT 24
Peak memory 224884 kb
Host smart-30c7ff09-602f-419d-9f3b-902b3207d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372889509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3372889509
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1317694501
Short name T537
Test name
Test status
Simulation time 15877145 ps
CPU time 0.73 seconds
Started Jul 18 06:19:37 PM PDT 24
Finished Jul 18 06:19:39 PM PDT 24
Peak memory 205376 kb
Host smart-feea3438-7350-460c-b7a4-d7508135ffb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317694501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1317694501
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2937021022
Short name T769
Test name
Test status
Simulation time 164148761 ps
CPU time 5.41 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:49 PM PDT 24
Peak memory 224928 kb
Host smart-1ebfa4f8-72b9-455b-9f4c-0a93bff68661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937021022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2937021022
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.368752764
Short name T517
Test name
Test status
Simulation time 18743439 ps
CPU time 0.77 seconds
Started Jul 18 06:19:09 PM PDT 24
Finished Jul 18 06:19:10 PM PDT 24
Peak memory 206048 kb
Host smart-d3fdb6f9-19f7-4c19-89c3-91c8b9bd53c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368752764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.368752764
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1213258320
Short name T390
Test name
Test status
Simulation time 2878453198 ps
CPU time 57.6 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:20:39 PM PDT 24
Peak memory 254632 kb
Host smart-6a61607d-6766-4c10-983a-8c9cb11ec775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213258320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1213258320
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.536668903
Short name T181
Test name
Test status
Simulation time 42724285809 ps
CPU time 247.65 seconds
Started Jul 18 06:19:47 PM PDT 24
Finished Jul 18 06:23:57 PM PDT 24
Peak memory 265860 kb
Host smart-421a6db8-5e6e-4570-8c3d-5e69c1c06940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536668903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.536668903
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2524600902
Short name T1
Test name
Test status
Simulation time 8116955808 ps
CPU time 40.43 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:20:20 PM PDT 24
Peak memory 250688 kb
Host smart-2093b9c0-9e40-4297-a239-31c4e1c0dd09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524600902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2524600902
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1910916526
Short name T658
Test name
Test status
Simulation time 572853562 ps
CPU time 5.63 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:19:45 PM PDT 24
Peak memory 224880 kb
Host smart-292e7268-3e82-44d5-87f5-282ec247b964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910916526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1910916526
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.382369010
Short name T268
Test name
Test status
Simulation time 37665084147 ps
CPU time 140.9 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:22:06 PM PDT 24
Peak memory 250872 kb
Host smart-548d0b7d-2cff-47a8-97cc-d26e9e4ad7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382369010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds
.382369010
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4228343104
Short name T810
Test name
Test status
Simulation time 782516672 ps
CPU time 9.69 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:54 PM PDT 24
Peak memory 224936 kb
Host smart-2729c6c1-7a20-4f4a-8cd5-fa5ecf3725ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228343104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4228343104
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.747584526
Short name T448
Test name
Test status
Simulation time 897014741 ps
CPU time 21.69 seconds
Started Jul 18 06:19:45 PM PDT 24
Finished Jul 18 06:20:10 PM PDT 24
Peak memory 241108 kb
Host smart-c3770aea-781c-473b-88a3-7640a23da0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747584526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.747584526
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3322394741
Short name T221
Test name
Test status
Simulation time 1612384689 ps
CPU time 10.16 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:19:50 PM PDT 24
Peak memory 240888 kb
Host smart-8e8e2021-c668-4a1c-9a9e-d009596170e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322394741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3322394741
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.4076450861
Short name T163
Test name
Test status
Simulation time 8044959880 ps
CPU time 7.28 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:20 PM PDT 24
Peak memory 225056 kb
Host smart-6027ecd1-9e85-432c-95be-a2a72e2e4a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076450861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.4076450861
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3748009984
Short name T523
Test name
Test status
Simulation time 121090629 ps
CPU time 3.65 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:48 PM PDT 24
Peak memory 222888 kb
Host smart-df3b833b-278f-447e-8420-e964547b7559
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3748009984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3748009984
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3524750991
Short name T153
Test name
Test status
Simulation time 220649569 ps
CPU time 1.06 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:19:43 PM PDT 24
Peak memory 215656 kb
Host smart-aabf0318-ba67-49e2-ae33-39c4184da6a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524750991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3524750991
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4064611965
Short name T352
Test name
Test status
Simulation time 32338797 ps
CPU time 0.74 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:14 PM PDT 24
Peak memory 206516 kb
Host smart-014efd84-7954-4f93-8b2a-64d63fce0164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064611965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4064611965
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1883524756
Short name T413
Test name
Test status
Simulation time 6676050216 ps
CPU time 16.82 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:29 PM PDT 24
Peak memory 216732 kb
Host smart-b990d852-1b43-4f54-8df2-080e86b34eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883524756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1883524756
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3965266000
Short name T544
Test name
Test status
Simulation time 311439612 ps
CPU time 1.61 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:14 PM PDT 24
Peak memory 216832 kb
Host smart-967fe271-6ea6-48a7-b257-4bd6fee34cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965266000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3965266000
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2999267199
Short name T408
Test name
Test status
Simulation time 118639690 ps
CPU time 0.86 seconds
Started Jul 18 06:19:11 PM PDT 24
Finished Jul 18 06:19:14 PM PDT 24
Peak memory 206428 kb
Host smart-78d52ac4-1205-4c8b-a7fb-3bc45144bce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999267199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2999267199
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2314881603
Short name T510
Test name
Test status
Simulation time 2757203913 ps
CPU time 15.36 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:19:58 PM PDT 24
Peak memory 233024 kb
Host smart-d5d9e965-29e1-428b-b22e-f0d1de8304fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314881603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2314881603
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.228399649
Short name T967
Test name
Test status
Simulation time 33208360 ps
CPU time 0.72 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:19:40 PM PDT 24
Peak memory 206300 kb
Host smart-b6e0b695-ee09-448b-a21d-ddeb5b5ff0a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228399649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.228399649
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.181203191
Short name T745
Test name
Test status
Simulation time 431276966 ps
CPU time 4.21 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:19:50 PM PDT 24
Peak memory 224896 kb
Host smart-259c05e0-1fbf-42e2-9255-490502186f3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181203191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.181203191
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.4287757339
Short name T582
Test name
Test status
Simulation time 58038935 ps
CPU time 0.79 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:19:48 PM PDT 24
Peak memory 207072 kb
Host smart-20617147-ead4-471a-964b-23f4e8799628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287757339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.4287757339
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1936404605
Short name T968
Test name
Test status
Simulation time 13413306487 ps
CPU time 106.99 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:21:34 PM PDT 24
Peak memory 241236 kb
Host smart-195cba7e-5ca5-47d2-b943-c8c48adc9c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936404605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1936404605
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3338802165
Short name T41
Test name
Test status
Simulation time 66528941032 ps
CPU time 192.21 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:22:55 PM PDT 24
Peak memory 249836 kb
Host smart-5f072c20-a449-4242-9414-b53d04620f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338802165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3338802165
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.1791206033
Short name T807
Test name
Test status
Simulation time 3564139076 ps
CPU time 27.62 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:20:13 PM PDT 24
Peak memory 225052 kb
Host smart-98a8913e-8e60-45bf-9497-2f2e336793af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791206033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.1791206033
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1224556741
Short name T158
Test name
Test status
Simulation time 1735184526 ps
CPU time 21.63 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:20:07 PM PDT 24
Peak memory 249548 kb
Host smart-4b7c1887-1723-489d-97d3-1496c8479116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224556741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1224556741
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.3926166432
Short name T3
Test name
Test status
Simulation time 40277603147 ps
CPU time 95.09 seconds
Started Jul 18 06:19:37 PM PDT 24
Finished Jul 18 06:21:13 PM PDT 24
Peak memory 255516 kb
Host smart-443e59e6-c034-4e2e-aa8a-bef2a7ca0453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926166432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.3926166432
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.967142865
Short name T466
Test name
Test status
Simulation time 348592878 ps
CPU time 7.18 seconds
Started Jul 18 06:19:43 PM PDT 24
Finished Jul 18 06:19:54 PM PDT 24
Peak memory 224868 kb
Host smart-1e5f9fcf-28bf-4b67-9262-74edddfa0345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967142865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.967142865
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.161651981
Short name T642
Test name
Test status
Simulation time 319935731 ps
CPU time 6.63 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:50 PM PDT 24
Peak memory 224888 kb
Host smart-0842ba11-6b5d-483f-8048-6665a58122ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161651981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.161651981
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3544914105
Short name T247
Test name
Test status
Simulation time 4588325726 ps
CPU time 10.38 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:19:50 PM PDT 24
Peak memory 233148 kb
Host smart-c2f1a4c8-df3a-4f91-8c70-72cfc491c035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544914105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3544914105
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.832269147
Short name T462
Test name
Test status
Simulation time 7316274548 ps
CPU time 16.52 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:19:58 PM PDT 24
Peak memory 225044 kb
Host smart-e9e3b9f8-1a2c-48cd-b64c-4cbd8e1c9fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832269147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.832269147
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3560416911
Short name T496
Test name
Test status
Simulation time 1613982230 ps
CPU time 16.94 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 223080 kb
Host smart-c322abb8-fbf4-4291-8a3c-fdbe8378620a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3560416911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3560416911
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1873225152
Short name T381
Test name
Test status
Simulation time 552283970 ps
CPU time 0.96 seconds
Started Jul 18 06:19:45 PM PDT 24
Finished Jul 18 06:19:49 PM PDT 24
Peak memory 207076 kb
Host smart-ec52f53a-0a8a-4c22-8019-aeb8a68b06a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873225152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1873225152
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.4226295030
Short name T318
Test name
Test status
Simulation time 796422866 ps
CPU time 3.11 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:19:44 PM PDT 24
Peak memory 216740 kb
Host smart-5428975b-c4bc-49b0-9462-a3a1b168c4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226295030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.4226295030
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2920379278
Short name T734
Test name
Test status
Simulation time 17921761 ps
CPU time 0.74 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:46 PM PDT 24
Peak memory 206160 kb
Host smart-1a427b5b-515e-4267-af1b-8835e7bbe132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920379278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2920379278
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.1617012201
Short name T766
Test name
Test status
Simulation time 87082100 ps
CPU time 1.29 seconds
Started Jul 18 06:19:44 PM PDT 24
Finished Jul 18 06:19:49 PM PDT 24
Peak memory 216636 kb
Host smart-67543b64-76d8-4cbb-8293-8bbe21e9bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617012201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1617012201
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2279760372
Short name T840
Test name
Test status
Simulation time 264025840 ps
CPU time 0.93 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:19:46 PM PDT 24
Peak memory 206444 kb
Host smart-89cb9563-2801-4b54-ac5b-b77430f6a985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279760372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2279760372
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3411733819
Short name T540
Test name
Test status
Simulation time 15454744192 ps
CPU time 13.11 seconds
Started Jul 18 06:19:47 PM PDT 24
Finished Jul 18 06:20:02 PM PDT 24
Peak memory 233184 kb
Host smart-42b1e006-18a9-4c47-a27d-30720f32d887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411733819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3411733819
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3375673812
Short name T552
Test name
Test status
Simulation time 66047925 ps
CPU time 0.74 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:19:43 PM PDT 24
Peak memory 205808 kb
Host smart-e6c865ab-4729-4989-af96-9980d5c92f6d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375673812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3375673812
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3543114021
Short name T529
Test name
Test status
Simulation time 477197594 ps
CPU time 6.17 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:51 PM PDT 24
Peak memory 224768 kb
Host smart-20033dd6-af0a-48f2-b2d0-460f662ee4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543114021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3543114021
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.713573351
Short name T306
Test name
Test status
Simulation time 68934525 ps
CPU time 0.81 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:19:47 PM PDT 24
Peak memory 207076 kb
Host smart-a6169a1b-711b-4f31-a4af-5741024a32cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713573351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.713573351
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1311930747
Short name T509
Test name
Test status
Simulation time 24516426920 ps
CPU time 76.54 seconds
Started Jul 18 06:19:43 PM PDT 24
Finished Jul 18 06:21:04 PM PDT 24
Peak memory 241416 kb
Host smart-30a270f7-3231-40b1-a410-206553083fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311930747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1311930747
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1718608315
Short name T165
Test name
Test status
Simulation time 3705566011 ps
CPU time 77.54 seconds
Started Jul 18 06:19:43 PM PDT 24
Finished Jul 18 06:21:05 PM PDT 24
Peak memory 255812 kb
Host smart-e1ce33fc-4ffb-4352-9713-59fdf605c63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718608315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1718608315
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1378557116
Short name T371
Test name
Test status
Simulation time 250972786 ps
CPU time 6.18 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:19:52 PM PDT 24
Peak memory 233156 kb
Host smart-fb41c40f-e03c-4a49-b3d2-167b59a51d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378557116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1378557116
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3472912707
Short name T391
Test name
Test status
Simulation time 10673046071 ps
CPU time 101.22 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:21:23 PM PDT 24
Peak memory 252528 kb
Host smart-f1032be8-4f42-4818-bc11-dc29830cb00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472912707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3472912707
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.159697342
Short name T410
Test name
Test status
Simulation time 13032656714 ps
CPU time 15.31 seconds
Started Jul 18 06:19:45 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 233152 kb
Host smart-f0628e58-f759-4191-b58a-0c18f1101fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159697342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.159697342
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1459566254
Short name T500
Test name
Test status
Simulation time 132472860 ps
CPU time 2.61 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:19:48 PM PDT 24
Peak memory 232832 kb
Host smart-6b010c42-b3be-4dff-b6e2-21d40b45da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459566254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1459566254
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2448320028
Short name T484
Test name
Test status
Simulation time 2689590484 ps
CPU time 8.15 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:53 PM PDT 24
Peak memory 241284 kb
Host smart-09373214-c301-49a2-873b-22b8fcb67ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448320028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2448320028
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2274171766
Short name T441
Test name
Test status
Simulation time 627699457 ps
CPU time 3.8 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:19:49 PM PDT 24
Peak memory 233120 kb
Host smart-30222260-5386-419d-9cf3-053c1311fad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274171766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2274171766
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3151496641
Short name T576
Test name
Test status
Simulation time 699604795 ps
CPU time 10.2 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:53 PM PDT 24
Peak memory 223440 kb
Host smart-575d2506-d6f5-45aa-b78d-5daf44f0589f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3151496641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3151496641
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.555293359
Short name T667
Test name
Test status
Simulation time 18453885 ps
CPU time 0.73 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:19:40 PM PDT 24
Peak memory 206148 kb
Host smart-461a04e8-c637-479f-b108-b3468d90b66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555293359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.555293359
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2418443144
Short name T325
Test name
Test status
Simulation time 956538072 ps
CPU time 7.07 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:19:54 PM PDT 24
Peak memory 216688 kb
Host smart-fb0ba370-4729-4e71-9f88-a1ff1edf8bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418443144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2418443144
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.4006691672
Short name T835
Test name
Test status
Simulation time 3302315526 ps
CPU time 3.12 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:47 PM PDT 24
Peak memory 216732 kb
Host smart-37b9baf3-9dd4-4697-bbb4-42dd90ef56c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006691672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.4006691672
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.679567182
Short name T785
Test name
Test status
Simulation time 67493887 ps
CPU time 0.82 seconds
Started Jul 18 06:19:38 PM PDT 24
Finished Jul 18 06:19:40 PM PDT 24
Peak memory 206416 kb
Host smart-cac1e7a2-1747-48c3-8aef-a4ba01536cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679567182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.679567182
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3196251728
Short name T694
Test name
Test status
Simulation time 129986168 ps
CPU time 3.88 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:19:51 PM PDT 24
Peak memory 233108 kb
Host smart-f3773bfd-15c9-46d2-8b52-e12ec95a3d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196251728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3196251728
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3353338527
Short name T754
Test name
Test status
Simulation time 12862794 ps
CPU time 0.75 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:00 PM PDT 24
Peak memory 205956 kb
Host smart-85961076-81e5-490b-90f3-8f4bfade4bd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353338527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3353338527
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.34994051
Short name T489
Test name
Test status
Simulation time 193702972 ps
CPU time 4.69 seconds
Started Jul 18 06:19:43 PM PDT 24
Finished Jul 18 06:19:52 PM PDT 24
Peak memory 233156 kb
Host smart-7fb25d6d-5d7c-4678-96f2-409fb332cf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34994051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.34994051
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4058061695
Short name T762
Test name
Test status
Simulation time 14666154 ps
CPU time 0.79 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:45 PM PDT 24
Peak memory 207020 kb
Host smart-2d225420-fc09-4240-b832-57a1dacf7e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058061695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4058061695
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2105271007
Short name T465
Test name
Test status
Simulation time 17282388095 ps
CPU time 72.97 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:20:57 PM PDT 24
Peak memory 249588 kb
Host smart-4cafb1a1-bf65-4622-8734-f9658da2376a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105271007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2105271007
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4175617256
Short name T928
Test name
Test status
Simulation time 222876640897 ps
CPU time 239.2 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 257536 kb
Host smart-3e55f3e2-4032-488c-a9f3-797fdcccf054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175617256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4175617256
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4214729852
Short name T684
Test name
Test status
Simulation time 2302459928 ps
CPU time 46.13 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:20:32 PM PDT 24
Peak memory 249152 kb
Host smart-240cc305-bd97-42c0-9e37-4397ce3feb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214729852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4214729852
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1237509050
Short name T730
Test name
Test status
Simulation time 493061244 ps
CPU time 8.02 seconds
Started Jul 18 06:19:45 PM PDT 24
Finished Jul 18 06:19:56 PM PDT 24
Peak memory 233172 kb
Host smart-288e36b3-9502-4ef1-99ef-4ac4d2d41ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237509050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1237509050
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1044212798
Short name T934
Test name
Test status
Simulation time 356119072435 ps
CPU time 524.33 seconds
Started Jul 18 06:19:44 PM PDT 24
Finished Jul 18 06:28:32 PM PDT 24
Peak memory 255376 kb
Host smart-2d6b2550-4b10-4016-8f50-46c9323faac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044212798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1044212798
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1301964368
Short name T818
Test name
Test status
Simulation time 70798544 ps
CPU time 2.78 seconds
Started Jul 18 06:19:39 PM PDT 24
Finished Jul 18 06:19:45 PM PDT 24
Peak memory 233192 kb
Host smart-da8c6515-b4f8-4359-bb46-095f46f28049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301964368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1301964368
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.657398939
Short name T892
Test name
Test status
Simulation time 6139983494 ps
CPU time 22.24 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:20:09 PM PDT 24
Peak memory 233164 kb
Host smart-d2dd050f-26ae-4864-afee-4d0a7ea1f867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657398939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.657398939
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1253895828
Short name T838
Test name
Test status
Simulation time 951084123 ps
CPU time 7.29 seconds
Started Jul 18 06:19:41 PM PDT 24
Finished Jul 18 06:19:52 PM PDT 24
Peak memory 238112 kb
Host smart-4e9d4384-88ef-4259-9ed0-5671c3a145e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253895828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1253895828
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2859363752
Short name T457
Test name
Test status
Simulation time 274899654 ps
CPU time 2.66 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:47 PM PDT 24
Peak memory 233172 kb
Host smart-604d6063-f461-47a7-ac48-62f51d755c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859363752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2859363752
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1338641533
Short name T135
Test name
Test status
Simulation time 4190107506 ps
CPU time 14.26 seconds
Started Jul 18 06:19:43 PM PDT 24
Finished Jul 18 06:20:01 PM PDT 24
Peak memory 222676 kb
Host smart-24d5842e-9f2c-4e71-a9d0-53f22f6eb7b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1338641533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1338641533
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3081157486
Short name T50
Test name
Test status
Simulation time 41033937159 ps
CPU time 474.63 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:28:00 PM PDT 24
Peak memory 273144 kb
Host smart-f9778c8b-4f9b-44f8-a5dd-c0c1bcf38f5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081157486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3081157486
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3824306378
Short name T714
Test name
Test status
Simulation time 2177711805 ps
CPU time 5.9 seconds
Started Jul 18 06:19:45 PM PDT 24
Finished Jul 18 06:19:54 PM PDT 24
Peak memory 216704 kb
Host smart-10a3ac2e-a11c-45c2-a9a0-d91ea2a65722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824306378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3824306378
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.875116448
Short name T506
Test name
Test status
Simulation time 11260908015 ps
CPU time 6.93 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:51 PM PDT 24
Peak memory 217512 kb
Host smart-8791a997-a9fb-4e4e-a696-dd6d99fc4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875116448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.875116448
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3579144895
Short name T819
Test name
Test status
Simulation time 71753315 ps
CPU time 1.18 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:19:45 PM PDT 24
Peak memory 207596 kb
Host smart-610e136e-5f5e-4a96-95d0-8c90bcba82d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579144895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3579144895
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2987865898
Short name T453
Test name
Test status
Simulation time 19210394 ps
CPU time 0.71 seconds
Started Jul 18 06:19:42 PM PDT 24
Finished Jul 18 06:19:47 PM PDT 24
Peak memory 206100 kb
Host smart-4ff21eb8-76b5-4df1-a2fa-7cfe64971680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987865898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2987865898
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2555093055
Short name T578
Test name
Test status
Simulation time 22171753788 ps
CPU time 19.17 seconds
Started Jul 18 06:19:40 PM PDT 24
Finished Jul 18 06:20:04 PM PDT 24
Peak memory 233188 kb
Host smart-f4863a0b-dd58-41a2-acf1-6be786cab65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555093055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2555093055
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4205791167
Short name T337
Test name
Test status
Simulation time 12554891 ps
CPU time 0.75 seconds
Started Jul 18 06:16:32 PM PDT 24
Finished Jul 18 06:16:35 PM PDT 24
Peak memory 206260 kb
Host smart-b7cd1b83-fdc9-46eb-b2b7-431b5ceecbad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205791167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
205791167
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1474404771
Short name T916
Test name
Test status
Simulation time 59850192 ps
CPU time 2.15 seconds
Started Jul 18 06:16:15 PM PDT 24
Finished Jul 18 06:16:18 PM PDT 24
Peak memory 224944 kb
Host smart-93bec673-c731-45ed-adf5-238c13b46702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474404771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1474404771
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1970512490
Short name T878
Test name
Test status
Simulation time 20667359 ps
CPU time 0.8 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:15 PM PDT 24
Peak memory 207052 kb
Host smart-cd253f3d-0b93-4140-bb57-e32e9b216ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970512490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1970512490
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1913763215
Short name T602
Test name
Test status
Simulation time 6333507530 ps
CPU time 23.1 seconds
Started Jul 18 06:16:31 PM PDT 24
Finished Jul 18 06:16:55 PM PDT 24
Peak memory 241348 kb
Host smart-60ae8b95-762d-4ae5-a3df-1c5874104d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913763215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1913763215
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.20881031
Short name T768
Test name
Test status
Simulation time 7490174618 ps
CPU time 88.41 seconds
Started Jul 18 06:16:55 PM PDT 24
Finished Jul 18 06:18:25 PM PDT 24
Peak memory 254832 kb
Host smart-6c86452b-2445-4b27-a336-2d53049bc851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20881031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.20881031
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.3531464531
Short name T757
Test name
Test status
Simulation time 28094949181 ps
CPU time 100.39 seconds
Started Jul 18 06:16:32 PM PDT 24
Finished Jul 18 06:18:13 PM PDT 24
Peak memory 238008 kb
Host smart-c6cc8119-acbf-4412-88a5-e0b17f7dc34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531464531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.3531464531
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3372302302
Short name T290
Test name
Test status
Simulation time 764304884 ps
CPU time 6.28 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:20 PM PDT 24
Peak memory 224888 kb
Host smart-f18cc610-f42d-424b-b2e8-adea0d1b2cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372302302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3372302302
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1346274773
Short name T824
Test name
Test status
Simulation time 206820090736 ps
CPU time 530.35 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:25:03 PM PDT 24
Peak memory 265996 kb
Host smart-601df19c-f61a-4bae-b93e-092b718be6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346274773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1346274773
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.1528568152
Short name T742
Test name
Test status
Simulation time 2658983567 ps
CPU time 12.86 seconds
Started Jul 18 06:16:17 PM PDT 24
Finished Jul 18 06:16:30 PM PDT 24
Peak memory 225092 kb
Host smart-04b32673-218c-483d-b87e-be0c874e364b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528568152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.1528568152
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.463893637
Short name T490
Test name
Test status
Simulation time 2848459342 ps
CPU time 8.86 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:23 PM PDT 24
Peak memory 238972 kb
Host smart-6bd87479-0532-4a1e-a429-b5088eac9e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463893637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.463893637
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1913830149
Short name T778
Test name
Test status
Simulation time 788525660 ps
CPU time 4.37 seconds
Started Jul 18 06:16:13 PM PDT 24
Finished Jul 18 06:16:19 PM PDT 24
Peak memory 224816 kb
Host smart-966ada94-9fa3-43ca-a003-05345ff92b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913830149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1913830149
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.3133152350
Short name T872
Test name
Test status
Simulation time 41755081958 ps
CPU time 21.42 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:34 PM PDT 24
Peak memory 241260 kb
Host smart-2ca9bfb3-029a-4c85-86b3-53c0d1ead8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133152350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3133152350
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1115833262
Short name T71
Test name
Test status
Simulation time 1466330026 ps
CPU time 4.05 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:18 PM PDT 24
Peak memory 221268 kb
Host smart-6ee7cd9c-7996-47a5-9c41-ce89425b8daf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1115833262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1115833262
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3126569421
Short name T69
Test name
Test status
Simulation time 560786361 ps
CPU time 1.06 seconds
Started Jul 18 06:16:31 PM PDT 24
Finished Jul 18 06:16:33 PM PDT 24
Peak memory 235552 kb
Host smart-30de2afc-09bd-4e94-a813-36b0c273088d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126569421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3126569421
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1969830162
Short name T698
Test name
Test status
Simulation time 188824672 ps
CPU time 0.98 seconds
Started Jul 18 06:16:31 PM PDT 24
Finished Jul 18 06:16:33 PM PDT 24
Peak memory 207096 kb
Host smart-fb043e43-674f-4a96-b8fb-f3045e7a57fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969830162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1969830162
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2581274741
Short name T825
Test name
Test status
Simulation time 5789482363 ps
CPU time 6.69 seconds
Started Jul 18 06:16:13 PM PDT 24
Finished Jul 18 06:16:21 PM PDT 24
Peak memory 217036 kb
Host smart-206a9d6a-46b2-48c5-b687-dfdf012ad830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581274741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2581274741
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2248408041
Short name T543
Test name
Test status
Simulation time 1698174339 ps
CPU time 6.75 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:20 PM PDT 24
Peak memory 216720 kb
Host smart-a18c9bc8-a103-456c-b946-3fdad21e0777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248408041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2248408041
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.4164101646
Short name T307
Test name
Test status
Simulation time 26950522 ps
CPU time 1.21 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:14 PM PDT 24
Peak memory 208308 kb
Host smart-719994af-c5c6-4f0b-9457-19dc43e50808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164101646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.4164101646
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1130212301
Short name T662
Test name
Test status
Simulation time 241373105 ps
CPU time 0.9 seconds
Started Jul 18 06:16:10 PM PDT 24
Finished Jul 18 06:16:12 PM PDT 24
Peak memory 206452 kb
Host smart-78f54e67-138b-4e85-83a2-a782b26bf804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130212301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1130212301
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2689618283
Short name T961
Test name
Test status
Simulation time 2858344216 ps
CPU time 3.62 seconds
Started Jul 18 06:16:12 PM PDT 24
Finished Jul 18 06:16:18 PM PDT 24
Peak memory 225020 kb
Host smart-7d278f86-165d-47de-bb06-45f70d6cff4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689618283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2689618283
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3809694024
Short name T666
Test name
Test status
Simulation time 14646434 ps
CPU time 0.76 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:00 PM PDT 24
Peak memory 205944 kb
Host smart-225b9dbc-9114-4f83-9b8d-52442e2c8322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809694024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3809694024
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2290794642
Short name T364
Test name
Test status
Simulation time 206764646 ps
CPU time 4.01 seconds
Started Jul 18 06:19:56 PM PDT 24
Finished Jul 18 06:20:01 PM PDT 24
Peak memory 224916 kb
Host smart-e327fcc1-2163-4f76-92f3-5fb3209866a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290794642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2290794642
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.169033917
Short name T803
Test name
Test status
Simulation time 47561849 ps
CPU time 0.83 seconds
Started Jul 18 06:20:01 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 207044 kb
Host smart-c8d08d56-0f03-4e06-93bf-39b66b5bf201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169033917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.169033917
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.878021885
Short name T252
Test name
Test status
Simulation time 131185514170 ps
CPU time 141.82 seconds
Started Jul 18 06:20:01 PM PDT 24
Finished Jul 18 06:22:25 PM PDT 24
Peak memory 255592 kb
Host smart-28cc3203-8eed-4fcd-a281-072f3d2dbe67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878021885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.878021885
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1280888820
Short name T58
Test name
Test status
Simulation time 165742348097 ps
CPU time 131.43 seconds
Started Jul 18 06:19:59 PM PDT 24
Finished Jul 18 06:22:13 PM PDT 24
Peak memory 250584 kb
Host smart-5518b7cc-4ec0-4c3b-a6dc-f157293f03df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280888820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1280888820
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3197565086
Short name T491
Test name
Test status
Simulation time 72822073439 ps
CPU time 178.45 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:22:58 PM PDT 24
Peak memory 257904 kb
Host smart-7462bb57-ab6f-4179-b871-c037d569e2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197565086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3197565086
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.156293195
Short name T687
Test name
Test status
Simulation time 1747107057 ps
CPU time 13.47 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:13 PM PDT 24
Peak memory 225068 kb
Host smart-a625bd07-cad0-4cc1-a8b3-99a558c96a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156293195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.156293195
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1214854381
Short name T858
Test name
Test status
Simulation time 6710506968 ps
CPU time 14.82 seconds
Started Jul 18 06:20:01 PM PDT 24
Finished Jul 18 06:20:18 PM PDT 24
Peak memory 224988 kb
Host smart-8fbc6f40-bf03-45de-a967-8323550dd6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214854381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1214854381
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3562389513
Short name T932
Test name
Test status
Simulation time 68900440 ps
CPU time 2.7 seconds
Started Jul 18 06:19:59 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 233060 kb
Host smart-2b6f2228-8fb4-4f72-92f7-e8039d8febbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562389513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3562389513
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3942378021
Short name T600
Test name
Test status
Simulation time 654570566 ps
CPU time 13.86 seconds
Started Jul 18 06:19:57 PM PDT 24
Finished Jul 18 06:20:13 PM PDT 24
Peak memory 241332 kb
Host smart-c5b62884-1f4c-4423-9957-b1462e2d6d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942378021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3942378021
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1618271632
Short name T525
Test name
Test status
Simulation time 144275058 ps
CPU time 2.39 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:20:07 PM PDT 24
Peak memory 224228 kb
Host smart-c9a51da5-2301-4122-b548-d247f446876d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618271632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1618271632
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3754603602
Short name T690
Test name
Test status
Simulation time 202045666 ps
CPU time 3.56 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 233180 kb
Host smart-42dd2470-0a09-4913-b772-4ff0a08daa04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754603602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3754603602
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.1883058125
Short name T472
Test name
Test status
Simulation time 294196313 ps
CPU time 5.74 seconds
Started Jul 18 06:19:59 PM PDT 24
Finished Jul 18 06:20:07 PM PDT 24
Peak memory 221004 kb
Host smart-8a72af58-4aea-47bd-9a27-d51d773cb8ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1883058125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.1883058125
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3026913790
Short name T296
Test name
Test status
Simulation time 3801502478 ps
CPU time 20.53 seconds
Started Jul 18 06:20:00 PM PDT 24
Finished Jul 18 06:20:23 PM PDT 24
Peak memory 216772 kb
Host smart-230bf5ed-50ff-47a4-86f8-b95fe21fb9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026913790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3026913790
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2802335587
Short name T35
Test name
Test status
Simulation time 1407469370 ps
CPU time 3.41 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 216704 kb
Host smart-65d2fc6d-23c7-4652-98e8-70bedbf3dda2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802335587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2802335587
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2734664587
Short name T323
Test name
Test status
Simulation time 176580296 ps
CPU time 4.21 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:04 PM PDT 24
Peak memory 216720 kb
Host smart-832b6727-daeb-4b88-b285-308d41f138e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734664587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2734664587
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1670921109
Short name T727
Test name
Test status
Simulation time 131260836 ps
CPU time 0.83 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:00 PM PDT 24
Peak memory 206448 kb
Host smart-fc1b4123-9e7e-4a85-9992-16ab49d967f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670921109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1670921109
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.4121702016
Short name T336
Test name
Test status
Simulation time 365260336 ps
CPU time 3.42 seconds
Started Jul 18 06:20:05 PM PDT 24
Finished Jul 18 06:20:10 PM PDT 24
Peak memory 224976 kb
Host smart-3b12ad44-8078-4d92-b4d2-9d378ca66e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121702016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.4121702016
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3759229044
Short name T660
Test name
Test status
Simulation time 12431819 ps
CPU time 0.75 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:20 PM PDT 24
Peak memory 205948 kb
Host smart-28fedcdb-1aeb-4e63-a54b-2c02e79c3e5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759229044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3759229044
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1020197627
Short name T883
Test name
Test status
Simulation time 46246541 ps
CPU time 2.78 seconds
Started Jul 18 06:20:01 PM PDT 24
Finished Jul 18 06:20:06 PM PDT 24
Peak memory 233024 kb
Host smart-d59ebeb8-f4b9-4786-9bd1-0e17d487ecd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020197627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1020197627
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2019552625
Short name T546
Test name
Test status
Simulation time 49210111 ps
CPU time 0.73 seconds
Started Jul 18 06:19:57 PM PDT 24
Finished Jul 18 06:19:59 PM PDT 24
Peak memory 206372 kb
Host smart-826cee01-1cd1-4591-8e04-ebaa0085efe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019552625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2019552625
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3892301270
Short name T40
Test name
Test status
Simulation time 210355916068 ps
CPU time 330.23 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:25:35 PM PDT 24
Peak memory 257028 kb
Host smart-d7f6496b-2cc8-4205-976a-1332ca6a9c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892301270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3892301270
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2278919820
Short name T267
Test name
Test status
Simulation time 1659282610 ps
CPU time 22.49 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:20:28 PM PDT 24
Peak memory 223788 kb
Host smart-b1e53adf-7e62-4576-a752-c0f9f85397e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278919820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2278919820
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3228518366
Short name T693
Test name
Test status
Simulation time 3071738935 ps
CPU time 28.4 seconds
Started Jul 18 06:20:02 PM PDT 24
Finished Jul 18 06:20:32 PM PDT 24
Peak memory 239488 kb
Host smart-23c29fdf-81b4-4d50-961f-c3bbc0027e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228518366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3228518366
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3879155831
Short name T607
Test name
Test status
Simulation time 20803439587 ps
CPU time 70.87 seconds
Started Jul 18 06:19:57 PM PDT 24
Finished Jul 18 06:21:08 PM PDT 24
Peak memory 251748 kb
Host smart-e4878bef-33b4-4afc-a23a-cd379982a227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879155831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3879155831
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.1470891036
Short name T941
Test name
Test status
Simulation time 140454434091 ps
CPU time 499.87 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:28:25 PM PDT 24
Peak memory 264004 kb
Host smart-3f9ef214-289a-42d6-b5af-83cebde752f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470891036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.1470891036
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3851871229
Short name T197
Test name
Test status
Simulation time 4775547259 ps
CPU time 20.31 seconds
Started Jul 18 06:19:59 PM PDT 24
Finished Jul 18 06:20:21 PM PDT 24
Peak memory 233172 kb
Host smart-e5388bac-3593-4d97-8eed-aaf86d22b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851871229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3851871229
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3056289159
Short name T862
Test name
Test status
Simulation time 1551708935 ps
CPU time 8.43 seconds
Started Jul 18 06:20:00 PM PDT 24
Finished Jul 18 06:20:11 PM PDT 24
Peak memory 224788 kb
Host smart-b5341527-7950-4006-b144-9d9aac889f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056289159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3056289159
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.969533055
Short name T628
Test name
Test status
Simulation time 8060908141 ps
CPU time 23.97 seconds
Started Jul 18 06:19:57 PM PDT 24
Finished Jul 18 06:20:21 PM PDT 24
Peak memory 233244 kb
Host smart-0036fc40-a800-4241-b789-df93cbf9d0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969533055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.969533055
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2660997846
Short name T144
Test name
Test status
Simulation time 12046547170 ps
CPU time 26.88 seconds
Started Jul 18 06:19:59 PM PDT 24
Finished Jul 18 06:20:28 PM PDT 24
Peak memory 225036 kb
Host smart-0aae3dc2-6a0f-48fd-b283-54c7e4db0534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660997846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2660997846
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.126729486
Short name T886
Test name
Test status
Simulation time 784829717 ps
CPU time 5.25 seconds
Started Jul 18 06:20:00 PM PDT 24
Finished Jul 18 06:20:08 PM PDT 24
Peak memory 222808 kb
Host smart-2498d2a6-9d5e-430d-8570-3c9d6cba8c72
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=126729486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.126729486
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2455240296
Short name T49
Test name
Test status
Simulation time 223534169409 ps
CPU time 921.77 seconds
Started Jul 18 06:20:05 PM PDT 24
Finished Jul 18 06:35:28 PM PDT 24
Peak memory 284552 kb
Host smart-ebb6ec02-c317-493d-bbcc-d4c2c3035614
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455240296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2455240296
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2772460182
Short name T728
Test name
Test status
Simulation time 1469871225 ps
CPU time 20.03 seconds
Started Jul 18 06:19:58 PM PDT 24
Finished Jul 18 06:20:19 PM PDT 24
Peak memory 217056 kb
Host smart-1991ed85-5d9c-458b-86f0-b1a0a3a137c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772460182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2772460182
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1061804704
Short name T482
Test name
Test status
Simulation time 16380223398 ps
CPU time 26.92 seconds
Started Jul 18 06:20:05 PM PDT 24
Finished Jul 18 06:20:33 PM PDT 24
Peak memory 216804 kb
Host smart-0bea1b69-e8d0-4b89-8804-76bfd30062d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061804704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1061804704
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3666974564
Short name T365
Test name
Test status
Simulation time 46055452 ps
CPU time 1.38 seconds
Started Jul 18 06:20:03 PM PDT 24
Finished Jul 18 06:20:06 PM PDT 24
Peak memory 216744 kb
Host smart-78493eb9-5c0b-4bf2-86b8-91d7afcec4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666974564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3666974564
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2990072241
Short name T652
Test name
Test status
Simulation time 141434785 ps
CPU time 0.92 seconds
Started Jul 18 06:20:00 PM PDT 24
Finished Jul 18 06:20:03 PM PDT 24
Peak memory 206448 kb
Host smart-63ed9b52-2a9d-4a50-8cfa-c9c111e997e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990072241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2990072241
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.611720868
Short name T598
Test name
Test status
Simulation time 945776687 ps
CPU time 3.09 seconds
Started Jul 18 06:20:01 PM PDT 24
Finished Jul 18 06:20:06 PM PDT 24
Peak memory 224908 kb
Host smart-aee3120f-7a15-4f90-ad66-e3047179ff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611720868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.611720868
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3434833778
Short name T944
Test name
Test status
Simulation time 38533955 ps
CPU time 0.72 seconds
Started Jul 18 06:20:16 PM PDT 24
Finished Jul 18 06:20:17 PM PDT 24
Peak memory 205936 kb
Host smart-f5d10955-cde4-4596-abc3-b509daea47cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434833778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3434833778
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3129231460
Short name T398
Test name
Test status
Simulation time 1735767013 ps
CPU time 6.84 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:27 PM PDT 24
Peak memory 233208 kb
Host smart-8e77560e-c86f-4ed1-9682-38c6133f15fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129231460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3129231460
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.4230562415
Short name T518
Test name
Test status
Simulation time 31836993 ps
CPU time 0.8 seconds
Started Jul 18 06:20:16 PM PDT 24
Finished Jul 18 06:20:18 PM PDT 24
Peak memory 207144 kb
Host smart-15ae373a-0652-4e2f-8ea3-d6875a3c059f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230562415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.4230562415
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.95980533
Short name T605
Test name
Test status
Simulation time 2461420541 ps
CPU time 5.86 seconds
Started Jul 18 06:20:19 PM PDT 24
Finished Jul 18 06:20:26 PM PDT 24
Peak memory 235020 kb
Host smart-032af5d7-8d3b-4a41-8bfd-cc87991a608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95980533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.95980533
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2159150248
Short name T80
Test name
Test status
Simulation time 151588410467 ps
CPU time 406.66 seconds
Started Jul 18 06:20:22 PM PDT 24
Finished Jul 18 06:27:10 PM PDT 24
Peak memory 266060 kb
Host smart-439881fa-dfe5-4cc7-a537-2b8a63dae3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159150248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2159150248
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.545686281
Short name T813
Test name
Test status
Simulation time 600522912 ps
CPU time 9.34 seconds
Started Jul 18 06:20:25 PM PDT 24
Finished Jul 18 06:20:35 PM PDT 24
Peak memory 238612 kb
Host smart-b84c4e4e-d75f-4e54-8777-a9dd6311f28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545686281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.545686281
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2184392644
Short name T443
Test name
Test status
Simulation time 184015277591 ps
CPU time 309.01 seconds
Started Jul 18 06:20:25 PM PDT 24
Finished Jul 18 06:25:35 PM PDT 24
Peak memory 249616 kb
Host smart-e60834c7-01d5-43b2-8ae9-4d6a5c637dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184392644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2184392644
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3584104688
Short name T960
Test name
Test status
Simulation time 3501037219 ps
CPU time 9.56 seconds
Started Jul 18 06:20:16 PM PDT 24
Finished Jul 18 06:20:26 PM PDT 24
Peak memory 233180 kb
Host smart-89dc0d8c-ce03-4364-ad65-0ca828429c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584104688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3584104688
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3527399432
Short name T963
Test name
Test status
Simulation time 9861376469 ps
CPU time 100.79 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:21:59 PM PDT 24
Peak memory 233236 kb
Host smart-643fa76b-d1d1-444e-b339-2a300656bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527399432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3527399432
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3508268799
Short name T251
Test name
Test status
Simulation time 3731862907 ps
CPU time 9.38 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:20:28 PM PDT 24
Peak memory 233140 kb
Host smart-dc0fbf56-a1bf-4e3c-96c7-32fd9aee75f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508268799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3508268799
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.336066634
Short name T524
Test name
Test status
Simulation time 36611414 ps
CPU time 1.99 seconds
Started Jul 18 06:20:19 PM PDT 24
Finished Jul 18 06:20:23 PM PDT 24
Peak memory 224916 kb
Host smart-c34cb17a-af8a-440d-8615-ebe6deacc587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336066634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.336066634
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.503347348
Short name T647
Test name
Test status
Simulation time 4974705762 ps
CPU time 6.33 seconds
Started Jul 18 06:20:19 PM PDT 24
Finished Jul 18 06:20:27 PM PDT 24
Peak memory 220452 kb
Host smart-2bbad7da-e684-46a6-8c32-a0606ff55236
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=503347348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.503347348
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.942777149
Short name T483
Test name
Test status
Simulation time 162286169712 ps
CPU time 478.79 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:28:19 PM PDT 24
Peak memory 270124 kb
Host smart-2b1c4988-592c-4791-ba01-b14bd6999c7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942777149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.942777149
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4029436685
Short name T403
Test name
Test status
Simulation time 2540620537 ps
CPU time 24.38 seconds
Started Jul 18 06:20:25 PM PDT 24
Finished Jul 18 06:20:50 PM PDT 24
Peak memory 217044 kb
Host smart-b25765f5-e889-4bc4-beba-b1f6b37246f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029436685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4029436685
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2074439694
Short name T900
Test name
Test status
Simulation time 3807771100 ps
CPU time 7.08 seconds
Started Jul 18 06:20:25 PM PDT 24
Finished Jul 18 06:20:33 PM PDT 24
Peak memory 216792 kb
Host smart-ab29b39a-2a6b-451e-8677-23f3614ac3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074439694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2074439694
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1804370453
Short name T347
Test name
Test status
Simulation time 28469897 ps
CPU time 1.13 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:21 PM PDT 24
Peak memory 207900 kb
Host smart-73022828-8202-413b-9117-29713d3e8974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804370453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1804370453
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1045096996
Short name T501
Test name
Test status
Simulation time 18551589 ps
CPU time 0.76 seconds
Started Jul 18 06:20:22 PM PDT 24
Finished Jul 18 06:20:24 PM PDT 24
Peak memory 206456 kb
Host smart-e52f4956-9e13-4754-bfff-406217e16665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045096996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1045096996
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2827644535
Short name T235
Test name
Test status
Simulation time 12867839266 ps
CPU time 10.06 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:20:29 PM PDT 24
Peak memory 224960 kb
Host smart-ce861256-2700-48e8-8347-d8fa271433e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827644535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2827644535
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2809518028
Short name T535
Test name
Test status
Simulation time 57527204 ps
CPU time 0.71 seconds
Started Jul 18 06:20:36 PM PDT 24
Finished Jul 18 06:20:39 PM PDT 24
Peak memory 205932 kb
Host smart-bd03ef2c-4b64-443e-9844-0573dadee6f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809518028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2809518028
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2140451975
Short name T697
Test name
Test status
Simulation time 1003658165 ps
CPU time 9.34 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:29 PM PDT 24
Peak memory 224884 kb
Host smart-5a4e067b-78ef-4438-96a2-3d55bfb54840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140451975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2140451975
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2986588758
Short name T560
Test name
Test status
Simulation time 53494287 ps
CPU time 0.76 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:20:19 PM PDT 24
Peak memory 207036 kb
Host smart-c3a82113-760b-49a0-888c-897f5c793fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986588758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2986588758
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3624159650
Short name T277
Test name
Test status
Simulation time 712659787737 ps
CPU time 291.13 seconds
Started Jul 18 06:20:32 PM PDT 24
Finished Jul 18 06:25:24 PM PDT 24
Peak memory 274104 kb
Host smart-83c1d9bf-58b4-435f-ba7c-58cb7d2b23f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624159650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3624159650
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2143699724
Short name T816
Test name
Test status
Simulation time 28238102924 ps
CPU time 289.64 seconds
Started Jul 18 06:20:32 PM PDT 24
Finished Jul 18 06:25:23 PM PDT 24
Peak memory 250688 kb
Host smart-88f050fc-0025-49b0-b419-9bbff42b0667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143699724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2143699724
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3021495978
Short name T216
Test name
Test status
Simulation time 12741728639 ps
CPU time 116.71 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:22:32 PM PDT 24
Peak memory 269004 kb
Host smart-8f02213c-2218-42ee-8bca-0ef36d409cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021495978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3021495978
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1183228154
Short name T868
Test name
Test status
Simulation time 1595820752 ps
CPU time 6.33 seconds
Started Jul 18 06:20:24 PM PDT 24
Finished Jul 18 06:20:32 PM PDT 24
Peak memory 241292 kb
Host smart-2082125d-0e51-4362-aa7d-d80ff0254838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183228154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1183228154
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3710012461
Short name T92
Test name
Test status
Simulation time 935504634 ps
CPU time 10.61 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:20:29 PM PDT 24
Peak memory 224932 kb
Host smart-90da1000-0c33-45a8-9601-580d97cd97bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710012461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3710012461
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4167749033
Short name T738
Test name
Test status
Simulation time 3166247268 ps
CPU time 8.65 seconds
Started Jul 18 06:20:22 PM PDT 24
Finished Jul 18 06:20:32 PM PDT 24
Peak memory 233188 kb
Host smart-2cca6ef5-acc2-47cb-bd3f-38b61ff5aa89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167749033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4167749033
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.4131219294
Short name T977
Test name
Test status
Simulation time 48159352639 ps
CPU time 12.79 seconds
Started Jul 18 06:20:12 PM PDT 24
Finished Jul 18 06:20:27 PM PDT 24
Peak memory 233156 kb
Host smart-082f20f7-d505-4d3a-9618-a35f0eafb1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131219294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.4131219294
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1420862359
Short name T688
Test name
Test status
Simulation time 11798663583 ps
CPU time 10.33 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:30 PM PDT 24
Peak memory 225044 kb
Host smart-377ce9ce-7003-40b5-b04c-cd3c75d4f662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420862359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1420862359
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3912724264
Short name T397
Test name
Test status
Simulation time 1987664448 ps
CPU time 7.45 seconds
Started Jul 18 06:20:36 PM PDT 24
Finished Jul 18 06:20:45 PM PDT 24
Peak memory 221848 kb
Host smart-2750024e-b02c-4325-9cf9-4291343889af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3912724264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3912724264
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.629367039
Short name T132
Test name
Test status
Simulation time 21630265871 ps
CPU time 229.95 seconds
Started Jul 18 06:20:32 PM PDT 24
Finished Jul 18 06:24:23 PM PDT 24
Peak memory 282480 kb
Host smart-ef6b4749-8f35-40bd-b61f-5f5c8962e392
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629367039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.629367039
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2068498714
Short name T435
Test name
Test status
Simulation time 19093441179 ps
CPU time 24.68 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:20:43 PM PDT 24
Peak memory 216976 kb
Host smart-59fc89ab-18dc-4285-95a7-3048575c91cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068498714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2068498714
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1784039825
Short name T378
Test name
Test status
Simulation time 1010563780 ps
CPU time 4.31 seconds
Started Jul 18 06:20:17 PM PDT 24
Finished Jul 18 06:20:22 PM PDT 24
Peak memory 216828 kb
Host smart-3e2acc34-1b13-4c1e-98c6-58deaa7acd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784039825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1784039825
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2209663820
Short name T640
Test name
Test status
Simulation time 98646439 ps
CPU time 1.61 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:21 PM PDT 24
Peak memory 216708 kb
Host smart-83f56f9f-dae9-421a-a375-34c83523d576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209663820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2209663820
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.159230054
Short name T839
Test name
Test status
Simulation time 74696754 ps
CPU time 0.75 seconds
Started Jul 18 06:20:25 PM PDT 24
Finished Jul 18 06:20:26 PM PDT 24
Peak memory 206448 kb
Host smart-c25cfffd-1ee0-4438-9c2f-46215078d001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159230054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.159230054
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1789721556
Short name T387
Test name
Test status
Simulation time 618465147 ps
CPU time 6.56 seconds
Started Jul 18 06:20:18 PM PDT 24
Finished Jul 18 06:20:27 PM PDT 24
Peak memory 236084 kb
Host smart-9a211d20-8617-4a38-8416-db5edbe57455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789721556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1789721556
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2505673623
Short name T61
Test name
Test status
Simulation time 15335331 ps
CPU time 0.73 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:36 PM PDT 24
Peak memory 205368 kb
Host smart-4cfd9cde-53b2-4acf-92e4-b5e1bf7e8c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505673623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2505673623
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2409096947
Short name T829
Test name
Test status
Simulation time 1261011582 ps
CPU time 6.51 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:42 PM PDT 24
Peak memory 233156 kb
Host smart-7f4ed468-3b30-4d32-8855-778f599458ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409096947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2409096947
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.891047951
Short name T799
Test name
Test status
Simulation time 43807051 ps
CPU time 0.83 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:37 PM PDT 24
Peak memory 207064 kb
Host smart-eb0948be-c689-4180-a897-cdd1c5f56a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891047951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.891047951
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2121829978
Short name T281
Test name
Test status
Simulation time 235570892444 ps
CPU time 302.32 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 254240 kb
Host smart-691a0eeb-8204-4881-b2fb-7ded06dfbb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121829978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2121829978
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1368322503
Short name T571
Test name
Test status
Simulation time 4951694121 ps
CPU time 27.8 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:21:04 PM PDT 24
Peak memory 224964 kb
Host smart-5fb5d7d1-3ec2-4ce3-b829-98450e2a1a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368322503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1368322503
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2006858411
Short name T166
Test name
Test status
Simulation time 17886525185 ps
CPU time 23.46 seconds
Started Jul 18 06:20:33 PM PDT 24
Finished Jul 18 06:20:58 PM PDT 24
Peak memory 241408 kb
Host smart-3c15185c-de7e-476a-b653-18618d77a47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006858411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2006858411
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1051110568
Short name T285
Test name
Test status
Simulation time 12262730843 ps
CPU time 93.33 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 241380 kb
Host smart-bfc08bb6-eec6-490e-a488-db1697ba876a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051110568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1051110568
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.238196712
Short name T269
Test name
Test status
Simulation time 269537248186 ps
CPU time 136.79 seconds
Started Jul 18 06:20:33 PM PDT 24
Finished Jul 18 06:22:51 PM PDT 24
Peak memory 236616 kb
Host smart-20933fdc-b80a-4def-9556-22936c5efda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238196712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.238196712
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3473245517
Short name T572
Test name
Test status
Simulation time 3021038727 ps
CPU time 32.96 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:21:10 PM PDT 24
Peak memory 225032 kb
Host smart-72b738e1-eeb9-4ea4-8993-e50e1fd58088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473245517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3473245517
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2212650871
Short name T328
Test name
Test status
Simulation time 182935715 ps
CPU time 5.15 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:41 PM PDT 24
Peak memory 233044 kb
Host smart-de7de09f-40fe-431a-9294-41d7a19a67be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212650871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2212650871
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.398875438
Short name T276
Test name
Test status
Simulation time 1954036197 ps
CPU time 4.58 seconds
Started Jul 18 06:20:37 PM PDT 24
Finished Jul 18 06:20:43 PM PDT 24
Peak memory 233092 kb
Host smart-c68e6f8a-d34d-4942-a956-b0b31a0c197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398875438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.398875438
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.220499614
Short name T930
Test name
Test status
Simulation time 3169447092 ps
CPU time 3.63 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:41 PM PDT 24
Peak memory 224972 kb
Host smart-523bd169-070f-4100-8e2d-172153b3cfec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220499614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.220499614
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.613404596
Short name T142
Test name
Test status
Simulation time 5347561707 ps
CPU time 7.78 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:44 PM PDT 24
Peak memory 219644 kb
Host smart-ef05bba3-6cbe-4e6b-87c0-d21aa9fbad89
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=613404596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.613404596
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1359662581
Short name T51
Test name
Test status
Simulation time 3181544817 ps
CPU time 78.8 seconds
Started Jul 18 06:20:36 PM PDT 24
Finished Jul 18 06:21:57 PM PDT 24
Peak memory 253488 kb
Host smart-8a1baa91-67f2-45a5-94a2-c176210f4636
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359662581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1359662581
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.148268566
Short name T519
Test name
Test status
Simulation time 2094596810 ps
CPU time 11.7 seconds
Started Jul 18 06:20:36 PM PDT 24
Finished Jul 18 06:20:50 PM PDT 24
Peak memory 216456 kb
Host smart-6187d525-0bc0-4079-a3d6-f17ec9d789a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148268566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.148268566
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.667150454
Short name T310
Test name
Test status
Simulation time 3061208261 ps
CPU time 9.47 seconds
Started Jul 18 06:20:39 PM PDT 24
Finished Jul 18 06:20:50 PM PDT 24
Peak memory 216704 kb
Host smart-3e523dd0-99cb-4134-bfb8-948a2f124334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667150454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.667150454
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1388968484
Short name T579
Test name
Test status
Simulation time 105283901 ps
CPU time 1.62 seconds
Started Jul 18 06:20:32 PM PDT 24
Finished Jul 18 06:20:35 PM PDT 24
Peak memory 216664 kb
Host smart-ee79e676-7ba2-476a-81a0-20f76b91ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388968484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1388968484
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.2194222527
Short name T758
Test name
Test status
Simulation time 32346679 ps
CPU time 0.87 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:39 PM PDT 24
Peak memory 206444 kb
Host smart-a9c3b927-7788-499a-98bb-92502eefc1a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194222527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.2194222527
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.4023352245
Short name T720
Test name
Test status
Simulation time 10493854964 ps
CPU time 12.18 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:49 PM PDT 24
Peak memory 240668 kb
Host smart-e08c5e98-736d-4c81-9b2b-8ca9f6e85641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023352245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4023352245
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1495658797
Short name T6
Test name
Test status
Simulation time 14292193 ps
CPU time 0.74 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:20:55 PM PDT 24
Peak memory 206284 kb
Host smart-4dcd2c6d-58b5-4c46-b688-ac5a96252509
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495658797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1495658797
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.883132210
Short name T473
Test name
Test status
Simulation time 613858538 ps
CPU time 3.26 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:40 PM PDT 24
Peak memory 224976 kb
Host smart-75289043-5797-4cf1-8dc4-19bbfbcc49ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883132210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.883132210
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2374865071
Short name T470
Test name
Test status
Simulation time 13526232 ps
CPU time 0.75 seconds
Started Jul 18 06:20:36 PM PDT 24
Finished Jul 18 06:20:39 PM PDT 24
Peak memory 206020 kb
Host smart-be845d5b-966e-4936-a3d6-7c4979dcbfd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374865071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2374865071
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1775945023
Short name T191
Test name
Test status
Simulation time 48072864770 ps
CPU time 366.55 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:27:04 PM PDT 24
Peak memory 274060 kb
Host smart-375d3e27-73ae-41c1-b9c7-a92094c11c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775945023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1775945023
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1851379379
Short name T199
Test name
Test status
Simulation time 21709888701 ps
CPU time 201.1 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:24:20 PM PDT 24
Peak memory 257876 kb
Host smart-addfac6a-87ee-47cd-862d-48c0e4cb99ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851379379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1851379379
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2943569296
Short name T274
Test name
Test status
Simulation time 3135021124 ps
CPU time 67.82 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:22:07 PM PDT 24
Peak memory 257820 kb
Host smart-edc5c30a-51c9-410b-a945-b78e0a4e08bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943569296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2943569296
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1771552514
Short name T724
Test name
Test status
Simulation time 782435595 ps
CPU time 7.73 seconds
Started Jul 18 06:20:37 PM PDT 24
Finished Jul 18 06:20:47 PM PDT 24
Peak memory 249532 kb
Host smart-24fb825c-bcc5-44e4-baeb-51fc9e42abb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771552514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1771552514
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2905177695
Short name T270
Test name
Test status
Simulation time 214459989420 ps
CPU time 251.87 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:24:48 PM PDT 24
Peak memory 264380 kb
Host smart-f8551e37-8191-4205-9d74-30b6b0e1ee4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905177695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2905177695
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1440896811
Short name T585
Test name
Test status
Simulation time 235996959 ps
CPU time 4.78 seconds
Started Jul 18 06:20:36 PM PDT 24
Finished Jul 18 06:20:43 PM PDT 24
Peak memory 233156 kb
Host smart-9be53df9-4423-47c7-b742-6bef0d6514c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440896811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1440896811
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1592605125
Short name T971
Test name
Test status
Simulation time 566397726 ps
CPU time 4.95 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:42 PM PDT 24
Peak memory 233236 kb
Host smart-62020e0b-e196-474c-94fc-3edca1c6e44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592605125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1592605125
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3583421810
Short name T249
Test name
Test status
Simulation time 463867838 ps
CPU time 7.66 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:44 PM PDT 24
Peak memory 241156 kb
Host smart-9c54466e-ab5e-4aa3-a6f5-72ad5825c842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583421810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3583421810
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2611839758
Short name T857
Test name
Test status
Simulation time 4501750581 ps
CPU time 15.47 seconds
Started Jul 18 06:20:34 PM PDT 24
Finished Jul 18 06:20:52 PM PDT 24
Peak memory 233180 kb
Host smart-29e6e798-28b3-41a9-91d8-59b6fbd6969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611839758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2611839758
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.364264649
Short name T896
Test name
Test status
Simulation time 543899244 ps
CPU time 7.15 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:45 PM PDT 24
Peak memory 222824 kb
Host smart-0ead1054-4f8f-4e32-9536-06482d46cec8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=364264649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.364264649
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1691668215
Short name T22
Test name
Test status
Simulation time 64034847 ps
CPU time 1.03 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:01 PM PDT 24
Peak memory 208032 kb
Host smart-10ee7035-e98e-4b69-a474-70438c75a010
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691668215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1691668215
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2105878987
Short name T752
Test name
Test status
Simulation time 1635601393 ps
CPU time 9.21 seconds
Started Jul 18 06:20:37 PM PDT 24
Finished Jul 18 06:20:48 PM PDT 24
Peak memory 216628 kb
Host smart-f902477b-4952-4311-a5b1-d66ad74e3100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105878987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2105878987
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1552205550
Short name T433
Test name
Test status
Simulation time 3893465479 ps
CPU time 5.23 seconds
Started Jul 18 06:20:33 PM PDT 24
Finished Jul 18 06:20:39 PM PDT 24
Peak memory 216788 kb
Host smart-765b98c2-a57e-4f71-9176-d22057ab15ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552205550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1552205550
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1411008955
Short name T717
Test name
Test status
Simulation time 396008316 ps
CPU time 2.53 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:40 PM PDT 24
Peak memory 217824 kb
Host smart-8d8730e0-9cd8-4dcd-883f-a567c37ebad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411008955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1411008955
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3174978610
Short name T74
Test name
Test status
Simulation time 1764228721 ps
CPU time 0.99 seconds
Started Jul 18 06:20:32 PM PDT 24
Finished Jul 18 06:20:34 PM PDT 24
Peak memory 207472 kb
Host smart-e17e7340-52a5-474c-bf8b-9f8b2cc8a475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174978610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3174978610
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1499440173
Short name T558
Test name
Test status
Simulation time 2373890382 ps
CPU time 10.03 seconds
Started Jul 18 06:20:35 PM PDT 24
Finished Jul 18 06:20:47 PM PDT 24
Peak memory 224960 kb
Host smart-bb4e855e-2eeb-4c21-aaec-784e9fb2d29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499440173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1499440173
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3571891611
Short name T426
Test name
Test status
Simulation time 27887680 ps
CPU time 0.69 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:20:57 PM PDT 24
Peak memory 205384 kb
Host smart-18eb5645-fdf9-4d58-bfa5-e99dc231cba0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571891611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3571891611
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2959926751
Short name T704
Test name
Test status
Simulation time 661617357 ps
CPU time 9.19 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:21:08 PM PDT 24
Peak memory 224972 kb
Host smart-97089d4f-eaf4-4768-9a23-761893d37584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959926751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2959926751
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3419659139
Short name T716
Test name
Test status
Simulation time 27018632 ps
CPU time 0.8 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:20:57 PM PDT 24
Peak memory 207068 kb
Host smart-b0be7cb5-531d-4a39-b03c-58e8229a3e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419659139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3419659139
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2415458544
Short name T715
Test name
Test status
Simulation time 11399559616 ps
CPU time 43.27 seconds
Started Jul 18 06:20:58 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 249600 kb
Host smart-0db2faf1-0d8a-4d87-8b3f-bc745fc3656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415458544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2415458544
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1036507105
Short name T905
Test name
Test status
Simulation time 5948832491 ps
CPU time 50.78 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:21:46 PM PDT 24
Peak memory 250964 kb
Host smart-fb58236d-0570-45bd-885a-30888fab7e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036507105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1036507105
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.4039364194
Short name T706
Test name
Test status
Simulation time 151976398 ps
CPU time 3.7 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:02 PM PDT 24
Peak memory 233012 kb
Host smart-28663ad1-f3c2-43d1-8d04-6d03d3b94e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039364194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.4039364194
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1812603848
Short name T239
Test name
Test status
Simulation time 101725256669 ps
CPU time 360.31 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:26:59 PM PDT 24
Peak memory 254196 kb
Host smart-8d2c7719-a0f2-4617-84c0-1b3a677e834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812603848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1812603848
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1919235779
Short name T681
Test name
Test status
Simulation time 2401669117 ps
CPU time 10.05 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:21:05 PM PDT 24
Peak memory 225032 kb
Host smart-59a88445-4c56-4a04-8bfc-1e38831edfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919235779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1919235779
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1590424670
Short name T196
Test name
Test status
Simulation time 8083430300 ps
CPU time 75.55 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:22:15 PM PDT 24
Peak memory 224948 kb
Host smart-365726c9-8fd6-41c6-b986-8a525a1b9015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590424670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1590424670
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2067806990
Short name T570
Test name
Test status
Simulation time 11065822963 ps
CPU time 19.13 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:21:12 PM PDT 24
Peak memory 233232 kb
Host smart-55e1b5cd-cb35-42ee-b567-7a0f2563ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067806990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2067806990
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2707450949
Short name T392
Test name
Test status
Simulation time 7468358485 ps
CPU time 19.04 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:21:17 PM PDT 24
Peak memory 233180 kb
Host smart-913644d1-1eaf-4ca7-a1f7-4f28ec082922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707450949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2707450949
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3243891809
Short name T962
Test name
Test status
Simulation time 6661637434 ps
CPU time 11.9 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:21:09 PM PDT 24
Peak memory 223236 kb
Host smart-a243fd63-7d73-4463-9079-8bd7798c872e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3243891809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3243891809
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4232977988
Short name T19
Test name
Test status
Simulation time 56579066 ps
CPU time 0.97 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:20:59 PM PDT 24
Peak memory 207412 kb
Host smart-e9c6736e-3b40-44a4-92eb-94d97c31ed19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232977988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4232977988
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1501437021
Short name T143
Test name
Test status
Simulation time 15030951 ps
CPU time 0.73 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:20:56 PM PDT 24
Peak memory 206236 kb
Host smart-bb968baa-6d13-4c41-affe-89d963b3d1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501437021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1501437021
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3985104067
Short name T890
Test name
Test status
Simulation time 1313512092 ps
CPU time 2.48 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:21:00 PM PDT 24
Peak memory 216644 kb
Host smart-ac1b7af3-3942-4060-805d-4ede1fbc605c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985104067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3985104067
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1401676492
Short name T308
Test name
Test status
Simulation time 106455835 ps
CPU time 1.88 seconds
Started Jul 18 06:20:44 PM PDT 24
Finished Jul 18 06:20:47 PM PDT 24
Peak memory 216648 kb
Host smart-95ea9e41-2f25-4137-b8ae-627e7e2e2088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401676492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1401676492
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3785815891
Short name T804
Test name
Test status
Simulation time 38991472 ps
CPU time 0.85 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:20:56 PM PDT 24
Peak memory 206440 kb
Host smart-1f9429ec-f9bb-4cc5-97df-d61f495570a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785815891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3785815891
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2667436828
Short name T888
Test name
Test status
Simulation time 436622833 ps
CPU time 3.87 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:20:59 PM PDT 24
Peak memory 233132 kb
Host smart-4fddf430-ea35-4061-a144-ea1de6a69405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667436828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2667436828
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2878401731
Short name T797
Test name
Test status
Simulation time 19387236 ps
CPU time 0.73 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:20:54 PM PDT 24
Peak memory 205932 kb
Host smart-ce7441a2-57bb-4aa5-954a-5dba6e5f2be9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878401731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2878401731
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.793803369
Short name T343
Test name
Test status
Simulation time 578474060 ps
CPU time 6.29 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:21:01 PM PDT 24
Peak memory 233116 kb
Host smart-b0ac3f49-8711-4470-b9af-85abef0ea80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793803369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.793803369
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1631844884
Short name T362
Test name
Test status
Simulation time 29629348 ps
CPU time 0.8 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:20:56 PM PDT 24
Peak memory 206040 kb
Host smart-104b4f81-115f-46da-a73c-22d3150314c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631844884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1631844884
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1394321763
Short name T52
Test name
Test status
Simulation time 128882590912 ps
CPU time 224.15 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:24:43 PM PDT 24
Peak memory 254284 kb
Host smart-51150a02-3454-400e-86fd-68646b004661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394321763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1394321763
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2608066440
Short name T536
Test name
Test status
Simulation time 55896590546 ps
CPU time 285.37 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:25:41 PM PDT 24
Peak memory 266060 kb
Host smart-5b7af77c-3f85-450a-b27c-df86df94e0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608066440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2608066440
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2784972380
Short name T232
Test name
Test status
Simulation time 4611681862 ps
CPU time 39.29 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:21:38 PM PDT 24
Peak memory 241464 kb
Host smart-b3dd6a62-67bc-4140-911f-7a7d8f7f8422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784972380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2784972380
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1908699084
Short name T289
Test name
Test status
Simulation time 4396064750 ps
CPU time 19.07 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:19 PM PDT 24
Peak memory 224928 kb
Host smart-29ee1b9a-408b-4d03-8340-7eb2e25f7e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908699084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1908699084
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.776952253
Short name T260
Test name
Test status
Simulation time 374395695 ps
CPU time 6.96 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:21:04 PM PDT 24
Peak memory 236244 kb
Host smart-ebb4bff7-7a13-4385-8e1b-dd11d570b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776952253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.776952253
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1101974703
Short name T237
Test name
Test status
Simulation time 403456845 ps
CPU time 2.82 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:02 PM PDT 24
Peak memory 224912 kb
Host smart-daeec0aa-510d-482c-b78c-e25965e5e32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101974703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1101974703
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1119518982
Short name T214
Test name
Test status
Simulation time 643823131 ps
CPU time 16.65 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:16 PM PDT 24
Peak memory 249368 kb
Host smart-da237d64-1d36-4e60-b83c-94d9c6e9ee6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119518982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1119518982
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2184189984
Short name T246
Test name
Test status
Simulation time 803389313 ps
CPU time 3.36 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:21:02 PM PDT 24
Peak memory 224872 kb
Host smart-f9322400-b1ba-40a7-be83-4beafcc3ac86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184189984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2184189984
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.523819014
Short name T776
Test name
Test status
Simulation time 76005199 ps
CPU time 2.44 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:20:57 PM PDT 24
Peak memory 224584 kb
Host smart-8ab9c55a-a0c7-4872-83ed-2a6bf78ec65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523819014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.523819014
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2396179281
Short name T959
Test name
Test status
Simulation time 170398049 ps
CPU time 4.77 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:21:00 PM PDT 24
Peak memory 223088 kb
Host smart-ef83bbac-9c82-450f-afb3-205af535777a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2396179281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2396179281
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.564930103
Short name T982
Test name
Test status
Simulation time 163832150 ps
CPU time 0.9 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:00 PM PDT 24
Peak memory 206144 kb
Host smart-08d1d0c0-f661-46b6-aca7-37ea3def9eeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564930103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.564930103
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2921459800
Short name T823
Test name
Test status
Simulation time 1579314255 ps
CPU time 20.4 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:21:18 PM PDT 24
Peak memory 216716 kb
Host smart-0d88c18e-edef-4d36-8ca1-3a1bc18413cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921459800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2921459800
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3164286758
Short name T654
Test name
Test status
Simulation time 16923781479 ps
CPU time 14.14 seconds
Started Jul 18 06:20:56 PM PDT 24
Finished Jul 18 06:21:12 PM PDT 24
Peak memory 216836 kb
Host smart-adaf66fd-dfad-4f05-95e6-be65164815c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164286758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3164286758
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2570887294
Short name T59
Test name
Test status
Simulation time 64999804 ps
CPU time 1.36 seconds
Started Jul 18 06:20:53 PM PDT 24
Finished Jul 18 06:20:55 PM PDT 24
Peak memory 208624 kb
Host smart-e7957a6d-0a3b-43f5-a7ee-cd8957ba153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570887294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2570887294
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2071353971
Short name T927
Test name
Test status
Simulation time 33649179 ps
CPU time 0.82 seconds
Started Jul 18 06:20:54 PM PDT 24
Finished Jul 18 06:20:56 PM PDT 24
Peak memory 206428 kb
Host smart-0705d9d1-6795-43f3-b32b-3e168db59a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071353971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2071353971
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1933206520
Short name T954
Test name
Test status
Simulation time 418912909 ps
CPU time 7.53 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:21:05 PM PDT 24
Peak memory 233084 kb
Host smart-fab934c2-f12d-476c-ac99-73fec9ac90fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933206520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1933206520
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.4168703083
Short name T57
Test name
Test status
Simulation time 35915653 ps
CPU time 0.76 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:18 PM PDT 24
Peak memory 205880 kb
Host smart-efc98cdc-349a-45e9-acde-e1a50c268aa5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168703083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
4168703083
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1049321096
Short name T224
Test name
Test status
Simulation time 119864090 ps
CPU time 2.23 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:19 PM PDT 24
Peak memory 224964 kb
Host smart-c6234a71-112f-488c-98e7-c7015a3c72c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049321096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1049321096
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3605908805
Short name T915
Test name
Test status
Simulation time 40828137 ps
CPU time 0.75 seconds
Started Jul 18 06:20:55 PM PDT 24
Finished Jul 18 06:20:58 PM PDT 24
Peak memory 207384 kb
Host smart-f734c42e-6357-477a-9aaf-32ac36c6e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605908805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3605908805
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3377633758
Short name T587
Test name
Test status
Simulation time 4354203447 ps
CPU time 17.98 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:35 PM PDT 24
Peak memory 237168 kb
Host smart-31de4bc1-e72e-4577-a4c6-fd8e8e3aafeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377633758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3377633758
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3172715520
Short name T271
Test name
Test status
Simulation time 76780817787 ps
CPU time 202.2 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:24:40 PM PDT 24
Peak memory 264988 kb
Host smart-1dfcb99e-2dab-433d-9ab7-ecf85fa0d9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172715520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3172715520
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.2332234140
Short name T747
Test name
Test status
Simulation time 13839232533 ps
CPU time 125.07 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:23:22 PM PDT 24
Peak memory 250680 kb
Host smart-a8a1949f-c2ca-4701-8df3-bf47af43f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332234140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.2332234140
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1062174094
Short name T922
Test name
Test status
Simulation time 5333567123 ps
CPU time 50.21 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:22:05 PM PDT 24
Peak memory 241636 kb
Host smart-09c38631-04f5-4b23-9eb4-12e7c0fa3fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062174094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1062174094
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.221504895
Short name T422
Test name
Test status
Simulation time 89854962 ps
CPU time 3.67 seconds
Started Jul 18 06:21:17 PM PDT 24
Finished Jul 18 06:21:23 PM PDT 24
Peak memory 219348 kb
Host smart-43128ab7-dd6b-4b51-acc9-f649913b43e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221504895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.221504895
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1273871218
Short name T625
Test name
Test status
Simulation time 9051752343 ps
CPU time 15.5 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:31 PM PDT 24
Peak memory 240132 kb
Host smart-88c17e15-b801-4470-bfb5-0ff918464a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273871218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1273871218
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.586549797
Short name T746
Test name
Test status
Simulation time 11070352876 ps
CPU time 10.64 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:26 PM PDT 24
Peak memory 233152 kb
Host smart-dd3f776e-b1bb-4579-9c54-f018daee3827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586549797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.586549797
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1839620176
Short name T950
Test name
Test status
Simulation time 623715299 ps
CPU time 5.62 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:22 PM PDT 24
Peak memory 240136 kb
Host smart-e1ee1215-a6f2-411c-82ab-46a87dac3e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839620176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1839620176
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.4046881419
Short name T996
Test name
Test status
Simulation time 1421907306 ps
CPU time 22.4 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:40 PM PDT 24
Peak memory 221180 kb
Host smart-a0b17924-6e26-4ac8-b186-c013c35819bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4046881419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.4046881419
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3218892799
Short name T919
Test name
Test status
Simulation time 6671710846 ps
CPU time 24.9 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 225032 kb
Host smart-20562072-e54f-4e9f-b178-bdca608932ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218892799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3218892799
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.410140173
Short name T302
Test name
Test status
Simulation time 1626494950 ps
CPU time 17.8 seconds
Started Jul 18 06:21:13 PM PDT 24
Finished Jul 18 06:21:32 PM PDT 24
Peak memory 219968 kb
Host smart-68a15609-20ad-4e91-8665-e310d8e9dffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410140173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.410140173
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2774691902
Short name T33
Test name
Test status
Simulation time 9776539411 ps
CPU time 15.71 seconds
Started Jul 18 06:20:57 PM PDT 24
Finished Jul 18 06:21:15 PM PDT 24
Peak memory 216688 kb
Host smart-a1880f64-c6b9-4887-b551-30f076efc732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774691902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2774691902
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2275238229
Short name T376
Test name
Test status
Simulation time 15628933 ps
CPU time 0.98 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:19 PM PDT 24
Peak memory 207808 kb
Host smart-7bfb5045-9c27-4194-9fae-2656d3fe06dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275238229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2275238229
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2899502230
Short name T316
Test name
Test status
Simulation time 19122167 ps
CPU time 0.72 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:19 PM PDT 24
Peak memory 206116 kb
Host smart-a37f5210-df4b-40c7-a1c3-7c1b52cb8827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899502230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2899502230
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2400781662
Short name T759
Test name
Test status
Simulation time 56520325912 ps
CPU time 43.92 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:22:01 PM PDT 24
Peak memory 237296 kb
Host smart-0bf3cbaa-4b8d-4e96-a7fd-d5e661f88cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400781662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2400781662
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2695338390
Short name T319
Test name
Test status
Simulation time 37722476 ps
CPU time 0.73 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:19 PM PDT 24
Peak memory 206300 kb
Host smart-f7a49a59-6454-484b-af36-91aa0296a5b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695338390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2695338390
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1872870712
Short name T226
Test name
Test status
Simulation time 2932188621 ps
CPU time 8.59 seconds
Started Jul 18 06:21:17 PM PDT 24
Finished Jul 18 06:21:27 PM PDT 24
Peak memory 233212 kb
Host smart-f232e906-98ac-4259-ae85-ac6f421c7209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872870712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1872870712
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1148039089
Short name T503
Test name
Test status
Simulation time 16391445 ps
CPU time 0.79 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:17 PM PDT 24
Peak memory 206048 kb
Host smart-fd35622e-e249-49cd-808f-de14074bafb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148039089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1148039089
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3545063332
Short name T183
Test name
Test status
Simulation time 8140298472 ps
CPU time 29.16 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:48 PM PDT 24
Peak memory 233192 kb
Host smart-60cd92fa-2bc1-464e-bb66-88da6388cc2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545063332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3545063332
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3234538249
Short name T853
Test name
Test status
Simulation time 69683077278 ps
CPU time 199.85 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:24:35 PM PDT 24
Peak memory 249664 kb
Host smart-b6876a06-bcb6-4ee0-b92c-3d0958af9a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234538249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3234538249
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2745851651
Short name T292
Test name
Test status
Simulation time 468713077 ps
CPU time 8.45 seconds
Started Jul 18 06:21:13 PM PDT 24
Finished Jul 18 06:21:22 PM PDT 24
Peak memory 240508 kb
Host smart-0bde7199-03e9-488c-ad07-f58652e04c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745851651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2745851651
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.730925126
Short name T480
Test name
Test status
Simulation time 5438846342 ps
CPU time 11.15 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:27 PM PDT 24
Peak memory 233164 kb
Host smart-05bda0cd-ea8b-4797-8319-bd2efef815ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730925126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.730925126
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2253798511
Short name T668
Test name
Test status
Simulation time 1277108450 ps
CPU time 15.36 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:33 PM PDT 24
Peak memory 233088 kb
Host smart-3a79ac0a-c13e-47da-b4e7-5ad1041afff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253798511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2253798511
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2132838314
Short name T775
Test name
Test status
Simulation time 3495272208 ps
CPU time 12.84 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:28 PM PDT 24
Peak memory 219240 kb
Host smart-67aed0a7-7457-41c0-b8a2-7802109bb28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132838314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2132838314
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1397226079
Short name T360
Test name
Test status
Simulation time 101966962 ps
CPU time 2.52 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:20 PM PDT 24
Peak memory 224728 kb
Host smart-752c670f-6296-4f39-9f1a-d63d444e174d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397226079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1397226079
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.247214278
Short name T643
Test name
Test status
Simulation time 4843817038 ps
CPU time 11.24 seconds
Started Jul 18 06:21:17 PM PDT 24
Finished Jul 18 06:21:30 PM PDT 24
Peak memory 221072 kb
Host smart-1d3ffd2b-aa18-4441-b2f4-8e76e115eedf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=247214278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.247214278
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1645570799
Short name T16
Test name
Test status
Simulation time 276301157 ps
CPU time 1.28 seconds
Started Jul 18 06:21:15 PM PDT 24
Finished Jul 18 06:21:19 PM PDT 24
Peak memory 207540 kb
Host smart-2f858322-ec0b-4ad3-b731-ee0c5e694f49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645570799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1645570799
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3987630723
Short name T505
Test name
Test status
Simulation time 3008874613 ps
CPU time 10.25 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:29 PM PDT 24
Peak memory 216788 kb
Host smart-ebc0bfa6-c3ce-401d-be91-b06ebfe3cb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987630723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3987630723
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.292861238
Short name T303
Test name
Test status
Simulation time 30456353 ps
CPU time 0.73 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:17 PM PDT 24
Peak memory 206172 kb
Host smart-07e6e89a-224b-497c-a26b-d44921813a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292861238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.292861238
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2395877624
Short name T418
Test name
Test status
Simulation time 226014908 ps
CPU time 2.82 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:21 PM PDT 24
Peak memory 216712 kb
Host smart-ea96b657-0fb3-4d71-8f15-e0fab5659f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395877624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2395877624
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2546174067
Short name T449
Test name
Test status
Simulation time 49886520 ps
CPU time 0.73 seconds
Started Jul 18 06:21:14 PM PDT 24
Finished Jul 18 06:21:17 PM PDT 24
Peak memory 206512 kb
Host smart-fd14c85d-baad-4704-9b42-3a5a92bb925f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546174067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2546174067
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.176937424
Short name T653
Test name
Test status
Simulation time 3026976724 ps
CPU time 11.64 seconds
Started Jul 18 06:21:16 PM PDT 24
Finished Jul 18 06:21:30 PM PDT 24
Peak memory 233232 kb
Host smart-f0adc0ca-7d8a-46ac-8115-f1867ddff0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176937424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.176937424
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1845961576
Short name T332
Test name
Test status
Simulation time 35871756 ps
CPU time 0.77 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:16:52 PM PDT 24
Peak memory 206260 kb
Host smart-00e2195d-3bd5-454a-b8c4-ebf46363c21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845961576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
845961576
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1757965445
Short name T827
Test name
Test status
Simulation time 15807122679 ps
CPU time 9.57 seconds
Started Jul 18 06:16:53 PM PDT 24
Finished Jul 18 06:17:04 PM PDT 24
Peak memory 233144 kb
Host smart-f042ffd2-fdd3-44f8-a1f2-f97068651cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757965445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1757965445
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4208933079
Short name T311
Test name
Test status
Simulation time 73491371 ps
CPU time 0.77 seconds
Started Jul 18 06:16:31 PM PDT 24
Finished Jul 18 06:16:33 PM PDT 24
Peak memory 206056 kb
Host smart-c83a965c-2d64-40b1-b896-88b6cd7847c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208933079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4208933079
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.2135318068
Short name T394
Test name
Test status
Simulation time 4440376025 ps
CPU time 37.79 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:17:31 PM PDT 24
Peak memory 239440 kb
Host smart-5038ed27-b9d8-44b5-a4ee-61a86dfa4926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135318068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.2135318068
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2482392551
Short name T856
Test name
Test status
Simulation time 21280361612 ps
CPU time 113.42 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:18:42 PM PDT 24
Peak memory 250368 kb
Host smart-b2a216ab-6567-434b-898f-60afbc5dad34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482392551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2482392551
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1712862161
Short name T663
Test name
Test status
Simulation time 50081908559 ps
CPU time 112.99 seconds
Started Jul 18 06:16:52 PM PDT 24
Finished Jul 18 06:18:47 PM PDT 24
Peak memory 255652 kb
Host smart-94b58691-2faf-4613-9b74-55f9d6ef3722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712862161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1712862161
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1088399905
Short name T287
Test name
Test status
Simulation time 963038950 ps
CPU time 18.32 seconds
Started Jul 18 06:16:46 PM PDT 24
Finished Jul 18 06:17:05 PM PDT 24
Peak memory 234176 kb
Host smart-dc1dcc49-f747-471c-976b-4611012958b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088399905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1088399905
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3233855976
Short name T722
Test name
Test status
Simulation time 15761037 ps
CPU time 0.77 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:16:53 PM PDT 24
Peak memory 216208 kb
Host smart-01852020-2f8e-496d-9947-8834c771f33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233855976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3233855976
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1947010850
Short name T206
Test name
Test status
Simulation time 778977610 ps
CPU time 6.86 seconds
Started Jul 18 06:16:46 PM PDT 24
Finished Jul 18 06:16:54 PM PDT 24
Peak memory 233084 kb
Host smart-a5119fbc-f181-4976-a1dd-f44878042d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947010850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1947010850
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1428466251
Short name T978
Test name
Test status
Simulation time 70063635490 ps
CPU time 40.15 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:17:32 PM PDT 24
Peak memory 238064 kb
Host smart-b8b8a687-9c86-44c5-aa33-a8ac12e50131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428466251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1428466251
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3153828368
Short name T877
Test name
Test status
Simulation time 570530350 ps
CPU time 5.27 seconds
Started Jul 18 06:16:53 PM PDT 24
Finished Jul 18 06:17:00 PM PDT 24
Peak memory 224916 kb
Host smart-386a2d9a-210f-477b-ac75-008c9f3d8897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153828368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3153828368
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3449077287
Short name T409
Test name
Test status
Simulation time 1527391257 ps
CPU time 7.88 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:17:00 PM PDT 24
Peak memory 224956 kb
Host smart-9c4c3439-8cdc-4d15-a718-702b9c39547d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449077287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3449077287
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.357451944
Short name T848
Test name
Test status
Simulation time 1233572596 ps
CPU time 13.93 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:17:07 PM PDT 24
Peak memory 219744 kb
Host smart-f32f29bd-938a-4b9d-94bd-e2f7c77c607f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=357451944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direc
t.357451944
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3633323737
Short name T68
Test name
Test status
Simulation time 391755437 ps
CPU time 1.09 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:16:51 PM PDT 24
Peak memory 235920 kb
Host smart-6f4384a2-d218-4ec7-a989-b19587138d67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633323737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3633323737
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3945933397
Short name T154
Test name
Test status
Simulation time 11873855569 ps
CPU time 145.26 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:19:13 PM PDT 24
Peak memory 256416 kb
Host smart-04c20c67-bfe5-40fc-8a71-72b78a851d1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945933397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3945933397
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.86212343
Short name T373
Test name
Test status
Simulation time 4461489468 ps
CPU time 18.4 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:17:10 PM PDT 24
Peak memory 217128 kb
Host smart-eee35adb-bfc9-463e-8579-ec57f585a877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86212343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.86212343
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4078730544
Short name T616
Test name
Test status
Simulation time 17565285804 ps
CPU time 17.05 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:17:08 PM PDT 24
Peak memory 216508 kb
Host smart-e410a5ff-f4fa-4f33-8e74-1f7e690b2e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078730544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4078730544
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3943790365
Short name T314
Test name
Test status
Simulation time 92122050 ps
CPU time 1.39 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:16:54 PM PDT 24
Peak memory 208340 kb
Host smart-048e148a-1b86-473c-ad85-eedb58f48c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943790365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3943790365
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1874316995
Short name T620
Test name
Test status
Simulation time 73006685 ps
CPU time 0.89 seconds
Started Jul 18 06:16:46 PM PDT 24
Finished Jul 18 06:16:48 PM PDT 24
Peak memory 206448 kb
Host smart-641019e5-c053-47fe-826b-e1a542c992bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874316995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1874316995
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.670688976
Short name T527
Test name
Test status
Simulation time 10753368533 ps
CPU time 7.61 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:16:56 PM PDT 24
Peak memory 233144 kb
Host smart-51d0d909-8a11-45c1-bd1a-4bf62e4111a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670688976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.670688976
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.707024776
Short name T415
Test name
Test status
Simulation time 27106443 ps
CPU time 0.8 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:21:47 PM PDT 24
Peak memory 205368 kb
Host smart-c64d0977-fb3d-46e2-8356-20e4ce9afebd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707024776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.707024776
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.4102543111
Short name T636
Test name
Test status
Simulation time 129174517 ps
CPU time 2.91 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:47 PM PDT 24
Peak memory 224856 kb
Host smart-0c6214cb-39d4-4bcf-9c03-0cabeb6affc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102543111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.4102543111
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3106002921
Short name T515
Test name
Test status
Simulation time 17793294 ps
CPU time 0.78 seconds
Started Jul 18 06:21:45 PM PDT 24
Finished Jul 18 06:21:48 PM PDT 24
Peak memory 207100 kb
Host smart-431636df-fdb0-46ce-b183-ab59b5a10b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106002921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3106002921
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1107908961
Short name T910
Test name
Test status
Simulation time 15004613 ps
CPU time 0.77 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:21:44 PM PDT 24
Peak memory 216252 kb
Host smart-3527c3c3-3d5a-4f70-9e53-b92201fe1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107908961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1107908961
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2934579866
Short name T195
Test name
Test status
Simulation time 608502817920 ps
CPU time 357.88 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:27:42 PM PDT 24
Peak memory 266000 kb
Host smart-f02baafe-6e11-43f3-baee-e745903f0b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934579866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2934579866
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2128451111
Short name T280
Test name
Test status
Simulation time 334002103651 ps
CPU time 678 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:33:00 PM PDT 24
Peak memory 268296 kb
Host smart-35ba4210-3507-45b0-b368-9571207d4562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128451111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2128451111
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1331886842
Short name T380
Test name
Test status
Simulation time 677242085 ps
CPU time 14.23 seconds
Started Jul 18 06:21:38 PM PDT 24
Finished Jul 18 06:21:54 PM PDT 24
Peak memory 239712 kb
Host smart-24b83579-1ae8-42e4-a36d-92653411d3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331886842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1331886842
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.427642357
Short name T906
Test name
Test status
Simulation time 37276333531 ps
CPU time 64.98 seconds
Started Jul 18 06:21:45 PM PDT 24
Finished Jul 18 06:22:52 PM PDT 24
Peak memory 241428 kb
Host smart-411fa5f2-3e4d-416f-8f0a-5e1ec892b814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427642357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.427642357
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2491116949
Short name T77
Test name
Test status
Simulation time 439745269 ps
CPU time 6.24 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:21:47 PM PDT 24
Peak memory 224908 kb
Host smart-192ac4cb-2dbc-4146-a1c4-c6a343687313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491116949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2491116949
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.573297816
Short name T595
Test name
Test status
Simulation time 4398398890 ps
CPU time 22.65 seconds
Started Jul 18 06:21:39 PM PDT 24
Finished Jul 18 06:22:03 PM PDT 24
Peak memory 233216 kb
Host smart-518d62e9-c8a2-4a92-bb3e-c66f0828f0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573297816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.573297816
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2449794840
Short name T947
Test name
Test status
Simulation time 4513974302 ps
CPU time 7.05 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:52 PM PDT 24
Peak memory 236956 kb
Host smart-e018d3b3-30bb-4aa6-8862-70c7b6fcce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449794840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2449794840
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.531127031
Short name T372
Test name
Test status
Simulation time 11399328453 ps
CPU time 28.4 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:22:14 PM PDT 24
Peak memory 233212 kb
Host smart-20c04296-4a81-42ad-8074-f55a17e6dee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531127031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.531127031
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3323518173
Short name T530
Test name
Test status
Simulation time 23329372995 ps
CPU time 16.37 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:21:58 PM PDT 24
Peak memory 222620 kb
Host smart-1e7a0e17-a491-4716-88be-4a555c097865
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3323518173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3323518173
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1185987180
Short name T981
Test name
Test status
Simulation time 35915686124 ps
CPU time 362.07 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:27:45 PM PDT 24
Peak memory 265944 kb
Host smart-69d5b74c-802e-4466-8089-43ccf3ef2da3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185987180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1185987180
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1813716062
Short name T295
Test name
Test status
Simulation time 4261944392 ps
CPU time 24.08 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 216708 kb
Host smart-202f5d64-7547-4f54-b2d2-2f74afa6881d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813716062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1813716062
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1964209979
Short name T976
Test name
Test status
Simulation time 1570672015 ps
CPU time 3.05 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:21:47 PM PDT 24
Peak memory 216716 kb
Host smart-4ab64d4f-1ab6-46c7-8c2d-71f4ba70e842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964209979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1964209979
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2121975297
Short name T300
Test name
Test status
Simulation time 24430321 ps
CPU time 0.92 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:21:46 PM PDT 24
Peak memory 207112 kb
Host smart-ccd13f58-3170-4feb-a180-a9f44d06c71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121975297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2121975297
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2033715269
Short name T36
Test name
Test status
Simulation time 333557471 ps
CPU time 1 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:46 PM PDT 24
Peak memory 207044 kb
Host smart-dea024e5-8cdc-4862-90ec-73a4e50eb102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033715269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2033715269
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3606573002
Short name T610
Test name
Test status
Simulation time 774782764 ps
CPU time 4.54 seconds
Started Jul 18 06:21:39 PM PDT 24
Finished Jul 18 06:21:45 PM PDT 24
Peak memory 233120 kb
Host smart-d7791483-6cd8-4c21-8f31-ca6c8ab1efca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606573002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3606573002
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2111736287
Short name T416
Test name
Test status
Simulation time 43638714 ps
CPU time 0.75 seconds
Started Jul 18 06:21:39 PM PDT 24
Finished Jul 18 06:21:41 PM PDT 24
Peak memory 205400 kb
Host smart-e628b79c-6413-4e55-b898-410855c5e427
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111736287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2111736287
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1288930181
Short name T589
Test name
Test status
Simulation time 32559265 ps
CPU time 2.39 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:21:46 PM PDT 24
Peak memory 232828 kb
Host smart-e2021fe3-9000-49f5-ba56-674c97caa0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288930181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1288930181
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.852032889
Short name T436
Test name
Test status
Simulation time 71518652 ps
CPU time 0.8 seconds
Started Jul 18 06:21:39 PM PDT 24
Finished Jul 18 06:21:41 PM PDT 24
Peak memory 207244 kb
Host smart-27a70ad2-f499-43bb-932a-a3779a0dffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852032889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.852032889
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2977471675
Short name T876
Test name
Test status
Simulation time 9857309537 ps
CPU time 70.7 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:22:57 PM PDT 24
Peak memory 249716 kb
Host smart-fbe03f93-aa7a-4f0c-81bb-829269b2d847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977471675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2977471675
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2765759875
Short name T837
Test name
Test status
Simulation time 21133437358 ps
CPU time 95.39 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:23:18 PM PDT 24
Peak memory 254708 kb
Host smart-1d7e955e-168c-45c3-ac84-a53b639b18f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765759875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2765759875
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1801559403
Short name T904
Test name
Test status
Simulation time 37384933415 ps
CPU time 250.5 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:25:53 PM PDT 24
Peak memory 250088 kb
Host smart-3589a303-f468-418e-8566-f186ee573351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801559403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1801559403
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2319686960
Short name T180
Test name
Test status
Simulation time 880991250 ps
CPU time 5.29 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:51 PM PDT 24
Peak memory 224896 kb
Host smart-8a0adb52-82da-4357-9c36-7f12f066155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319686960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2319686960
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4169162582
Short name T952
Test name
Test status
Simulation time 26983150071 ps
CPU time 32.64 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:22:17 PM PDT 24
Peak memory 235412 kb
Host smart-7c52ae12-f05b-45f9-92e9-f7657fffd63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169162582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4169162582
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3639498435
Short name T219
Test name
Test status
Simulation time 4255789776 ps
CPU time 16.4 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:22:01 PM PDT 24
Peak memory 239336 kb
Host smart-1be53a36-4da8-43f0-a42d-5d1a02b37542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639498435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3639498435
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3020327195
Short name T903
Test name
Test status
Simulation time 8387239036 ps
CPU time 9.93 seconds
Started Jul 18 06:21:38 PM PDT 24
Finished Jul 18 06:21:49 PM PDT 24
Peak memory 241192 kb
Host smart-a36bd2c0-761d-4205-a10b-5c87f791a830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020327195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3020327195
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2215704090
Short name T993
Test name
Test status
Simulation time 1076118847 ps
CPU time 9.89 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:21:52 PM PDT 24
Peak memory 220640 kb
Host smart-4224034d-c9fe-4786-9ed3-01629ef357e4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2215704090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2215704090
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2014455700
Short name T278
Test name
Test status
Simulation time 58392731709 ps
CPU time 220.28 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:25:22 PM PDT 24
Peak memory 257468 kb
Host smart-ff22a010-9983-464a-ab1e-0e75fc045230
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014455700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2014455700
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3502016715
Short name T735
Test name
Test status
Simulation time 4925643360 ps
CPU time 13.94 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:58 PM PDT 24
Peak memory 216496 kb
Host smart-71ecc238-d52f-4b80-83c1-c6145c2180c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502016715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3502016715
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3023559385
Short name T615
Test name
Test status
Simulation time 2013375031 ps
CPU time 4.79 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:21:51 PM PDT 24
Peak memory 216640 kb
Host smart-7261cc33-60f2-4bf7-8657-68e177666ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023559385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3023559385
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1228851991
Short name T545
Test name
Test status
Simulation time 88748559 ps
CPU time 1.09 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 208296 kb
Host smart-86348cef-0b17-462e-a728-405392d353de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228851991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1228851991
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1673652241
Short name T31
Test name
Test status
Simulation time 20612276 ps
CPU time 0.78 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:45 PM PDT 24
Peak memory 206632 kb
Host smart-550318b8-7cb1-4d2f-8c60-601ce1d3bf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673652241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1673652241
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.845734399
Short name T575
Test name
Test status
Simulation time 145083895 ps
CPU time 2.78 seconds
Started Jul 18 06:21:39 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 224880 kb
Host smart-02337ef5-9915-43f2-bc64-74255c0f4a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845734399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.845734399
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.50606244
Short name T375
Test name
Test status
Simulation time 12295770 ps
CPU time 0.75 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:06 PM PDT 24
Peak memory 205992 kb
Host smart-b9cf3076-92de-4228-a005-cffef2f00b06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50606244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.50606244
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3749203301
Short name T985
Test name
Test status
Simulation time 969026492 ps
CPU time 3.35 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:48 PM PDT 24
Peak memory 224892 kb
Host smart-e9de0f76-99b6-4eae-8ab4-57873f6fd079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749203301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3749203301
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3493190748
Short name T792
Test name
Test status
Simulation time 51009682 ps
CPU time 0.8 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 207396 kb
Host smart-3c6ce92b-200d-4d17-b295-3a0f9b6b920d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493190748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3493190748
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.953223315
Short name T222
Test name
Test status
Simulation time 21564648232 ps
CPU time 168.45 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:24:50 PM PDT 24
Peak memory 257808 kb
Host smart-2a751edd-c833-4bee-b26a-be24b658e21d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953223315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.953223315
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2632314974
Short name T78
Test name
Test status
Simulation time 21087547692 ps
CPU time 157.26 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:24:40 PM PDT 24
Peak memory 249672 kb
Host smart-c1734103-4239-482b-96ea-6070484eead4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632314974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2632314974
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1221023621
Short name T178
Test name
Test status
Simulation time 31720814133 ps
CPU time 320.98 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:27:28 PM PDT 24
Peak memory 253100 kb
Host smart-5ae9156c-8d26-4ef2-8a09-6b40a3b308bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221023621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1221023621
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2009654463
Short name T459
Test name
Test status
Simulation time 1075090843 ps
CPU time 10.19 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:21:56 PM PDT 24
Peak memory 239368 kb
Host smart-d16e45ff-f6e4-4953-8b11-6a3404cdd340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009654463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2009654463
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2907720507
Short name T400
Test name
Test status
Simulation time 569210923 ps
CPU time 4.91 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:50 PM PDT 24
Peak memory 233104 kb
Host smart-ea903d68-4288-42c4-87e0-58ec35402cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907720507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2907720507
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3744844937
Short name T850
Test name
Test status
Simulation time 280981680 ps
CPU time 2.31 seconds
Started Jul 18 06:21:40 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 223412 kb
Host smart-6041b730-e0cd-42d5-8ba1-c69d0d3efba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744844937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3744844937
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.551075073
Short name T29
Test name
Test status
Simulation time 712142531 ps
CPU time 4.37 seconds
Started Jul 18 06:21:42 PM PDT 24
Finished Jul 18 06:21:49 PM PDT 24
Peak memory 238300 kb
Host smart-21884a18-d6f9-4b45-95cf-f3c2acf76392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551075073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.551075073
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4260755215
Short name T648
Test name
Test status
Simulation time 7954005380 ps
CPU time 9.68 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:21:53 PM PDT 24
Peak memory 233184 kb
Host smart-f184c209-9ff0-4e43-a701-ca7bec1b8346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260755215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4260755215
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2880147742
Short name T899
Test name
Test status
Simulation time 748094786 ps
CPU time 6.77 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:13 PM PDT 24
Peak memory 222528 kb
Host smart-6ca095fb-21bf-46c4-abb7-080e614e5e43
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2880147742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2880147742
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.692644027
Short name T987
Test name
Test status
Simulation time 14812181598 ps
CPU time 22.75 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 216980 kb
Host smart-31e38ffc-5ebc-4091-b55b-ff7423943ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692644027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.692644027
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.233953098
Short name T983
Test name
Test status
Simulation time 34236779146 ps
CPU time 20.2 seconds
Started Jul 18 06:21:41 PM PDT 24
Finished Jul 18 06:22:04 PM PDT 24
Peak memory 216708 kb
Host smart-9c5e4e54-f9e7-45c7-a2b0-5b50a1937765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233953098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.233953098
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.598520171
Short name T914
Test name
Test status
Simulation time 595069245 ps
CPU time 2.53 seconds
Started Jul 18 06:21:39 PM PDT 24
Finished Jul 18 06:21:43 PM PDT 24
Peak memory 216524 kb
Host smart-5e099169-9c31-415d-b7b5-8d84dcf76f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598520171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.598520171
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1893352801
Short name T389
Test name
Test status
Simulation time 54113073 ps
CPU time 0.77 seconds
Started Jul 18 06:21:43 PM PDT 24
Finished Jul 18 06:21:46 PM PDT 24
Peak memory 206448 kb
Host smart-d77cf603-42a3-4d93-9141-5d4a51d52fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893352801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1893352801
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1546013479
Short name T234
Test name
Test status
Simulation time 383468871 ps
CPU time 5.67 seconds
Started Jul 18 06:21:44 PM PDT 24
Finished Jul 18 06:21:52 PM PDT 24
Peak memory 233108 kb
Host smart-f20a1cae-debe-4eed-956d-1cd1e4a5faa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546013479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1546013479
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2215007423
Short name T891
Test name
Test status
Simulation time 15377581 ps
CPU time 0.81 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:07 PM PDT 24
Peak memory 206024 kb
Host smart-49294bfc-75b1-4f63-b17c-28cea1286ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215007423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2215007423
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.411692075
Short name T889
Test name
Test status
Simulation time 292003493 ps
CPU time 2.3 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:22:05 PM PDT 24
Peak memory 224900 kb
Host smart-62349277-fda0-4fa2-9ac1-f5f148d55f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411692075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.411692075
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1246953371
Short name T865
Test name
Test status
Simulation time 44116668 ps
CPU time 0.74 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 206084 kb
Host smart-cafb6407-aa13-4812-8a65-ba0ea346cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246953371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1246953371
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2871537569
Short name T912
Test name
Test status
Simulation time 171668309335 ps
CPU time 205.97 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:25:33 PM PDT 24
Peak memory 256740 kb
Host smart-5c666752-a529-4d5f-8163-a56cd6ca5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871537569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2871537569
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1300678488
Short name T1001
Test name
Test status
Simulation time 4367270791 ps
CPU time 116.93 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:24:03 PM PDT 24
Peak memory 272048 kb
Host smart-b0726efc-81ec-475b-bec6-f935553c6b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300678488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1300678488
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3045908295
Short name T129
Test name
Test status
Simulation time 46031191675 ps
CPU time 247.43 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:26:09 PM PDT 24
Peak memory 267632 kb
Host smart-273a051e-75d7-45be-b694-4fa6657dedd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045908295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3045908295
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3829576771
Short name T450
Test name
Test status
Simulation time 200819482 ps
CPU time 6.03 seconds
Started Jul 18 06:22:05 PM PDT 24
Finished Jul 18 06:22:14 PM PDT 24
Peak memory 233084 kb
Host smart-a48e153d-65c3-47e4-89fe-3d5f8952e0f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829576771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3829576771
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1307947999
Short name T737
Test name
Test status
Simulation time 2461669072 ps
CPU time 8.6 seconds
Started Jul 18 06:22:01 PM PDT 24
Finished Jul 18 06:22:12 PM PDT 24
Peak memory 224948 kb
Host smart-76ebf5d5-8667-46bd-a26a-7d14e8d5461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307947999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1307947999
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2261759126
Short name T788
Test name
Test status
Simulation time 138733157 ps
CPU time 5.02 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:12 PM PDT 24
Peak memory 233156 kb
Host smart-796b4ba7-57a0-47f2-96a6-51553c7ddb59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261759126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2261759126
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1681050782
Short name T253
Test name
Test status
Simulation time 238010574 ps
CPU time 7.01 seconds
Started Jul 18 06:21:58 PM PDT 24
Finished Jul 18 06:22:07 PM PDT 24
Peak memory 224860 kb
Host smart-501785a8-3076-4be6-bd05-1f9818dd7586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681050782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1681050782
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2502937465
Short name T843
Test name
Test status
Simulation time 1212938167 ps
CPU time 3.42 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:22:05 PM PDT 24
Peak memory 233096 kb
Host smart-5e2a5c41-099f-4117-98f3-27d8b16d8064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502937465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2502937465
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3539613425
Short name T229
Test name
Test status
Simulation time 30864391729 ps
CPU time 18.69 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:22:26 PM PDT 24
Peak memory 225052 kb
Host smart-dd518ddf-5df1-4fa0-9f4b-e68e12eae865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539613425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3539613425
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3534685423
Short name T644
Test name
Test status
Simulation time 729246347 ps
CPU time 8.68 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:15 PM PDT 24
Peak memory 223076 kb
Host smart-3d81751d-5360-4b53-9bc2-63d94ef34210
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3534685423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3534685423
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1211730068
Short name T188
Test name
Test status
Simulation time 63701051037 ps
CPU time 210.7 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:25:38 PM PDT 24
Peak memory 247564 kb
Host smart-442c7db3-12e4-4d5e-806e-620f5d2481e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211730068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1211730068
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2689101574
Short name T359
Test name
Test status
Simulation time 2964874385 ps
CPU time 19.9 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:25 PM PDT 24
Peak memory 216776 kb
Host smart-80519faf-c32c-4236-8452-719d7b8b6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689101574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2689101574
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1267321537
Short name T161
Test name
Test status
Simulation time 3210227278 ps
CPU time 11.28 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:22:19 PM PDT 24
Peak memory 216724 kb
Host smart-b3cbaf1b-b8c9-4097-bf83-71e33c1d6b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267321537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1267321537
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3680662242
Short name T692
Test name
Test status
Simulation time 52384981 ps
CPU time 0.94 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:05 PM PDT 24
Peak memory 207312 kb
Host smart-0259851e-6f93-4f9d-b197-60c57c5f1739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680662242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3680662242
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2112603581
Short name T358
Test name
Test status
Simulation time 126799739 ps
CPU time 0.87 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:07 PM PDT 24
Peak memory 206444 kb
Host smart-6fe141a7-409c-4eaa-baef-58a7f28fa029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112603581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2112603581
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2160906588
Short name T931
Test name
Test status
Simulation time 62111447990 ps
CPU time 24.84 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:30 PM PDT 24
Peak memory 241328 kb
Host smart-9268d979-cdd3-4ecf-a44d-266daa70f984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160906588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2160906588
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4090946706
Short name T780
Test name
Test status
Simulation time 50061519 ps
CPU time 0.74 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:06 PM PDT 24
Peak memory 205920 kb
Host smart-beb5e97c-d7b9-4d88-90ad-187f006680d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090946706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4090946706
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.2431346498
Short name T929
Test name
Test status
Simulation time 374502505 ps
CPU time 4.55 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:22:06 PM PDT 24
Peak memory 233088 kb
Host smart-0cb40728-6f74-49fa-8420-cd71b98a9968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431346498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2431346498
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.2798714463
Short name T488
Test name
Test status
Simulation time 115638358 ps
CPU time 0.79 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:06 PM PDT 24
Peak memory 207084 kb
Host smart-908b941b-e2b7-4da7-9964-b971013eb2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798714463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2798714463
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1293779282
Short name T635
Test name
Test status
Simulation time 2488697245 ps
CPU time 24.64 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:31 PM PDT 24
Peak memory 249776 kb
Host smart-fd592a93-08d8-45ec-a7ce-d01036e4b3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293779282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1293779282
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1419430078
Short name T502
Test name
Test status
Simulation time 8938695194 ps
CPU time 93.78 seconds
Started Jul 18 06:21:59 PM PDT 24
Finished Jul 18 06:23:34 PM PDT 24
Peak memory 250424 kb
Host smart-ee16226b-ab70-43a1-b29e-2f100029a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419430078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1419430078
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4082451509
Short name T531
Test name
Test status
Simulation time 1914931401 ps
CPU time 8.97 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:22:12 PM PDT 24
Peak memory 234196 kb
Host smart-19589111-47ce-4618-b058-5b663e8de655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082451509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4082451509
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2587964690
Short name T955
Test name
Test status
Simulation time 39986196 ps
CPU time 2.48 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 233144 kb
Host smart-c58f4678-2b01-43d8-84a7-70d7269be3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587964690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2587964690
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.1457354318
Short name T261
Test name
Test status
Simulation time 582191455091 ps
CPU time 311.06 seconds
Started Jul 18 06:22:05 PM PDT 24
Finished Jul 18 06:27:20 PM PDT 24
Peak memory 254716 kb
Host smart-f2a20f23-8b24-46e2-abd5-05e49d48fc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457354318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.1457354318
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.17694153
Short name T793
Test name
Test status
Simulation time 10118566629 ps
CPU time 32.89 seconds
Started Jul 18 06:22:01 PM PDT 24
Finished Jul 18 06:22:36 PM PDT 24
Peak memory 225000 kb
Host smart-99b266d0-0cb5-4dc1-b8e8-82e0b1c02727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17694153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.17694153
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1928587797
Short name T772
Test name
Test status
Simulation time 102281320 ps
CPU time 2.67 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:07 PM PDT 24
Peak memory 232780 kb
Host smart-16327822-23af-4f4f-ae74-57c09bfa29ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928587797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1928587797
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2406961345
Short name T875
Test name
Test status
Simulation time 1150501449 ps
CPU time 5.49 seconds
Started Jul 18 06:22:00 PM PDT 24
Finished Jul 18 06:22:07 PM PDT 24
Peak memory 224912 kb
Host smart-38aca208-fe70-410d-b2b6-64b3a9ce641d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406961345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2406961345
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.4009248243
Short name T348
Test name
Test status
Simulation time 62613118349 ps
CPU time 18.48 seconds
Started Jul 18 06:21:59 PM PDT 24
Finished Jul 18 06:22:20 PM PDT 24
Peak memory 233176 kb
Host smart-5a949bf0-c6c1-4535-b1c1-df60a52ec866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009248243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4009248243
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1293824478
Short name T137
Test name
Test status
Simulation time 1398231961 ps
CPU time 5.93 seconds
Started Jul 18 06:22:01 PM PDT 24
Finished Jul 18 06:22:09 PM PDT 24
Peak memory 219540 kb
Host smart-b0b217d8-d788-4664-a2d8-868861bc71c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1293824478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1293824478
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.108266506
Short name T17
Test name
Test status
Simulation time 32621214442 ps
CPU time 72.24 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:23:16 PM PDT 24
Peak memory 249488 kb
Host smart-9a6b43f5-8135-46fa-b3d6-66f49a109ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108266506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.108266506
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1225102824
Short name T539
Test name
Test status
Simulation time 20938055567 ps
CPU time 16.34 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:23 PM PDT 24
Peak memory 216724 kb
Host smart-89530c94-f4b8-47f4-8e1a-6fa8568e5f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225102824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1225102824
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4266834314
Short name T334
Test name
Test status
Simulation time 2192904599 ps
CPU time 5.77 seconds
Started Jul 18 06:22:01 PM PDT 24
Finished Jul 18 06:22:09 PM PDT 24
Peak memory 216708 kb
Host smart-9af2a43c-9791-426d-9cb4-fb4672c16b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266834314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4266834314
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1273512830
Short name T479
Test name
Test status
Simulation time 51877810 ps
CPU time 1.2 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:22:09 PM PDT 24
Peak memory 208368 kb
Host smart-bd922dcf-d179-4c3b-add4-941daa3f04d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273512830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1273512830
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3201171301
Short name T355
Test name
Test status
Simulation time 20844822 ps
CPU time 0.79 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 206432 kb
Host smart-e3201c77-4242-4eae-b835-5bac9a1ccba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201171301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3201171301
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2209469108
Short name T811
Test name
Test status
Simulation time 5063477494 ps
CPU time 4.17 seconds
Started Jul 18 06:22:02 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 233176 kb
Host smart-8c169993-1a62-48fe-b3f5-ac9c7e31eef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209469108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2209469108
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3312182622
Short name T783
Test name
Test status
Simulation time 12744245 ps
CPU time 0.76 seconds
Started Jul 18 06:22:20 PM PDT 24
Finished Jul 18 06:22:23 PM PDT 24
Peak memory 206280 kb
Host smart-9fd409dc-2846-4d64-b1bc-f921d5cf5c54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312182622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3312182622
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1431250366
Short name T760
Test name
Test status
Simulation time 987056598 ps
CPU time 3.58 seconds
Started Jul 18 06:22:21 PM PDT 24
Finished Jul 18 06:22:26 PM PDT 24
Peak memory 224964 kb
Host smart-eaa153a9-2a70-4c0b-9616-24a3b5ab9a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431250366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1431250366
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.290266940
Short name T622
Test name
Test status
Simulation time 15413614 ps
CPU time 0.82 seconds
Started Jul 18 06:22:04 PM PDT 24
Finished Jul 18 06:22:09 PM PDT 24
Peak memory 207076 kb
Host smart-43555405-a244-4ce8-abf8-1cb782ac7c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290266940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.290266940
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1460273779
Short name T202
Test name
Test status
Simulation time 85214436566 ps
CPU time 484.57 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:30:22 PM PDT 24
Peak memory 257788 kb
Host smart-8d92d936-e78c-4fbd-9eb2-2b74783b9d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460273779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1460273779
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.162003218
Short name T128
Test name
Test status
Simulation time 43922485319 ps
CPU time 87.38 seconds
Started Jul 18 06:22:21 PM PDT 24
Finished Jul 18 06:23:50 PM PDT 24
Peak memory 251920 kb
Host smart-e6e66423-b7cf-4abb-985c-5f0c773e38ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162003218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.162003218
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3855063805
Short name T979
Test name
Test status
Simulation time 77998114403 ps
CPU time 302.91 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:27:20 PM PDT 24
Peak memory 273336 kb
Host smart-5d6a7691-62bd-4096-af14-3c4676e7166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855063805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3855063805
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3900563556
Short name T726
Test name
Test status
Simulation time 2073013705 ps
CPU time 13.59 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:22:31 PM PDT 24
Peak memory 249560 kb
Host smart-dd28c156-6320-48f1-b0b7-763f47957573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900563556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3900563556
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1671795147
Short name T736
Test name
Test status
Simulation time 10308022378 ps
CPU time 56.51 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:23:13 PM PDT 24
Peak memory 255856 kb
Host smart-b79562d6-a9a8-41e9-81bc-ddec29ff2c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671795147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1671795147
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4226698326
Short name T255
Test name
Test status
Simulation time 2022274647 ps
CPU time 6.59 seconds
Started Jul 18 06:22:19 PM PDT 24
Finished Jul 18 06:22:27 PM PDT 24
Peak memory 224888 kb
Host smart-0d838cb4-1ab4-4bcb-b4c7-22ac5da9431c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226698326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4226698326
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2016738653
Short name T629
Test name
Test status
Simulation time 8889506750 ps
CPU time 34.22 seconds
Started Jul 18 06:22:17 PM PDT 24
Finished Jul 18 06:22:53 PM PDT 24
Peak memory 249844 kb
Host smart-27f648de-9b60-4014-825e-7255ac7c12e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016738653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2016738653
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.93303880
Short name T805
Test name
Test status
Simulation time 26593076961 ps
CPU time 16.09 seconds
Started Jul 18 06:22:19 PM PDT 24
Finished Jul 18 06:22:37 PM PDT 24
Peak memory 225012 kb
Host smart-7fa1b300-d75d-44ff-9239-5d57a53355f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93303880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.93303880
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2926432514
Short name T211
Test name
Test status
Simulation time 4181297338 ps
CPU time 4.59 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:22:20 PM PDT 24
Peak memory 233176 kb
Host smart-fab2af67-3484-48e6-be38-6cb28515f5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926432514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2926432514
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3813002910
Short name T140
Test name
Test status
Simulation time 417339750 ps
CPU time 3.95 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:22:21 PM PDT 24
Peak memory 223060 kb
Host smart-07b28fa2-c9f6-4bc1-a664-1e1db5b22483
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3813002910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3813002910
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2825697455
Short name T590
Test name
Test status
Simulation time 21200765335 ps
CPU time 250.94 seconds
Started Jul 18 06:22:18 PM PDT 24
Finished Jul 18 06:26:31 PM PDT 24
Peak memory 251072 kb
Host smart-2602779d-0898-4a0a-b634-75be55e8adc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825697455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2825697455
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1225223468
Short name T795
Test name
Test status
Simulation time 21357521838 ps
CPU time 31.12 seconds
Started Jul 18 06:22:14 PM PDT 24
Finished Jul 18 06:22:46 PM PDT 24
Peak memory 217124 kb
Host smart-7e198a87-46c6-457e-b5d1-80d418e2b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225223468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1225223468
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2501124043
Short name T468
Test name
Test status
Simulation time 602143436 ps
CPU time 2.25 seconds
Started Jul 18 06:22:03 PM PDT 24
Finished Jul 18 06:22:08 PM PDT 24
Peak memory 216728 kb
Host smart-fdc794fa-f37d-492e-9358-15eb94a5fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501124043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2501124043
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.169794113
Short name T10
Test name
Test status
Simulation time 19950166 ps
CPU time 0.95 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:22:17 PM PDT 24
Peak memory 207064 kb
Host smart-ab35ffeb-cc52-4699-8b0b-2cc55633aff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169794113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.169794113
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.895733338
Short name T516
Test name
Test status
Simulation time 49661422 ps
CPU time 0.81 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:22:17 PM PDT 24
Peak memory 206464 kb
Host smart-6110621d-5fcc-496d-bbc6-c3e8a42c4edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895733338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.895733338
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.966488929
Short name T427
Test name
Test status
Simulation time 3534392996 ps
CPU time 8.81 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:22:25 PM PDT 24
Peak memory 225012 kb
Host smart-78bfbecd-7b99-4ffd-80af-d62d69ca1f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966488929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.966488929
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2700959123
Short name T60
Test name
Test status
Simulation time 42901061 ps
CPU time 0.76 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:33 PM PDT 24
Peak memory 205380 kb
Host smart-b5b64a63-0706-41c5-9e89-39c6baede83b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700959123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2700959123
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1578684112
Short name T541
Test name
Test status
Simulation time 468604281 ps
CPU time 2.76 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:22:21 PM PDT 24
Peak memory 224196 kb
Host smart-040b089b-435a-409c-95f2-ea58eec85f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578684112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1578684112
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.93085748
Short name T379
Test name
Test status
Simulation time 74359998 ps
CPU time 0.84 seconds
Started Jul 18 06:22:20 PM PDT 24
Finished Jul 18 06:22:22 PM PDT 24
Peak memory 207080 kb
Host smart-397d4301-0372-4d6e-b31a-93f0bc26bad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93085748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.93085748
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1109373285
Short name T471
Test name
Test status
Simulation time 627208182 ps
CPU time 9.24 seconds
Started Jul 18 06:22:19 PM PDT 24
Finished Jul 18 06:22:30 PM PDT 24
Peak memory 235036 kb
Host smart-19e42eb4-a5ea-4bde-9cc0-ef18a448c3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109373285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1109373285
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.359726905
Short name T176
Test name
Test status
Simulation time 17546121104 ps
CPU time 160.79 seconds
Started Jul 18 06:22:17 PM PDT 24
Finished Jul 18 06:25:00 PM PDT 24
Peak memory 238800 kb
Host smart-b7321f6d-3810-472c-8355-d0a249eb73e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359726905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.359726905
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1092967315
Short name T42
Test name
Test status
Simulation time 10922712816 ps
CPU time 117 seconds
Started Jul 18 06:22:22 PM PDT 24
Finished Jul 18 06:24:21 PM PDT 24
Peak memory 237764 kb
Host smart-145d749f-4770-42a0-9885-e4c85f02cc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092967315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1092967315
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2857059595
Short name T784
Test name
Test status
Simulation time 753004566 ps
CPU time 11.01 seconds
Started Jul 18 06:22:18 PM PDT 24
Finished Jul 18 06:22:30 PM PDT 24
Peak memory 235124 kb
Host smart-445e4947-2c38-4a89-8933-a0f8a9e7c910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857059595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2857059595
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3771674818
Short name T91
Test name
Test status
Simulation time 12837732255 ps
CPU time 105.56 seconds
Started Jul 18 06:22:18 PM PDT 24
Finished Jul 18 06:24:06 PM PDT 24
Peak memory 249612 kb
Host smart-79b19226-38c1-4eca-9fa7-0542e539d270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771674818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3771674818
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.4271012214
Short name T791
Test name
Test status
Simulation time 2938124808 ps
CPU time 5.36 seconds
Started Jul 18 06:22:17 PM PDT 24
Finished Jul 18 06:22:24 PM PDT 24
Peak memory 224944 kb
Host smart-d732713c-d22c-4cf4-b25b-2976b7da4984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271012214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.4271012214
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.264553025
Short name T836
Test name
Test status
Simulation time 17119709773 ps
CPU time 100.15 seconds
Started Jul 18 06:22:18 PM PDT 24
Finished Jul 18 06:24:00 PM PDT 24
Peak memory 240952 kb
Host smart-8f521899-a9d6-4299-92f7-13ff0255e7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264553025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.264553025
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.442748505
Short name T342
Test name
Test status
Simulation time 1187940183 ps
CPU time 5.31 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:22:22 PM PDT 24
Peak memory 233084 kb
Host smart-8d2a3f3d-7242-4fd0-9c0e-eabcef14c175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442748505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.442748505
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3550849330
Short name T765
Test name
Test status
Simulation time 63000182990 ps
CPU time 43.81 seconds
Started Jul 18 06:22:19 PM PDT 24
Finished Jul 18 06:23:05 PM PDT 24
Peak memory 233172 kb
Host smart-302581c6-ef47-4ad5-bb46-28e3511ea9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550849330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3550849330
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3177118226
Short name T675
Test name
Test status
Simulation time 3224302110 ps
CPU time 17.19 seconds
Started Jul 18 06:22:18 PM PDT 24
Finished Jul 18 06:22:37 PM PDT 24
Peak memory 223500 kb
Host smart-3b89eab3-2cf0-4b50-98bf-80795ed4a5ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3177118226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3177118226
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2257199935
Short name T14
Test name
Test status
Simulation time 17918549392 ps
CPU time 28.46 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:22:47 PM PDT 24
Peak memory 223960 kb
Host smart-341c13fa-8cb3-4191-8685-2689717629a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257199935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2257199935
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3254106635
Short name T800
Test name
Test status
Simulation time 16013889224 ps
CPU time 20.57 seconds
Started Jul 18 06:22:15 PM PDT 24
Finished Jul 18 06:22:37 PM PDT 24
Peak memory 216736 kb
Host smart-082d0a73-3725-4431-8f24-81fd387fd37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254106635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3254106635
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2992488698
Short name T972
Test name
Test status
Simulation time 4355118910 ps
CPU time 14.67 seconds
Started Jul 18 06:22:22 PM PDT 24
Finished Jul 18 06:22:38 PM PDT 24
Peak memory 216788 kb
Host smart-868277b2-205e-43ae-af7b-46bc5f19d1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992488698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2992488698
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3755755066
Short name T725
Test name
Test status
Simulation time 86470555 ps
CPU time 1.69 seconds
Started Jul 18 06:22:20 PM PDT 24
Finished Jul 18 06:22:23 PM PDT 24
Peak memory 216724 kb
Host smart-b59ae0fc-ff1f-480e-98e7-f203d60a041d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755755066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3755755066
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.168320124
Short name T160
Test name
Test status
Simulation time 119572870 ps
CPU time 0.87 seconds
Started Jul 18 06:22:16 PM PDT 24
Finished Jul 18 06:22:18 PM PDT 24
Peak memory 206464 kb
Host smart-58306a50-85b9-4c8a-bf06-01c295c14604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168320124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.168320124
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.4014448662
Short name T238
Test name
Test status
Simulation time 8349981538 ps
CPU time 8.66 seconds
Started Jul 18 06:22:21 PM PDT 24
Finished Jul 18 06:22:31 PM PDT 24
Peak memory 233192 kb
Host smart-ecfe72c2-4cf7-4f16-95ab-aa98b0864992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014448662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.4014448662
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1275255982
Short name T942
Test name
Test status
Simulation time 16356155 ps
CPU time 0.73 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:33 PM PDT 24
Peak memory 205972 kb
Host smart-349cad19-abb3-43d8-88d5-f9d3162d2db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275255982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1275255982
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3794813489
Short name T87
Test name
Test status
Simulation time 311456028 ps
CPU time 5.59 seconds
Started Jul 18 06:22:29 PM PDT 24
Finished Jul 18 06:22:36 PM PDT 24
Peak memory 233156 kb
Host smart-c9dc945d-9342-45b4-b398-94ad0f9cb13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794813489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3794813489
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.1006144533
Short name T407
Test name
Test status
Simulation time 42970384 ps
CPU time 0.75 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:34 PM PDT 24
Peak memory 206012 kb
Host smart-ee70cde7-a99a-45df-91f9-9bf7f674d291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006144533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1006144533
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1904114820
Short name T368
Test name
Test status
Simulation time 56661166 ps
CPU time 0.81 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:35 PM PDT 24
Peak memory 215044 kb
Host smart-34f5a7d2-15b1-42b3-a5d5-f06f31063bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904114820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1904114820
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.4068283211
Short name T713
Test name
Test status
Simulation time 16905992329 ps
CPU time 106.88 seconds
Started Jul 18 06:22:32 PM PDT 24
Finished Jul 18 06:24:21 PM PDT 24
Peak memory 264956 kb
Host smart-7311c3dd-70f3-49cf-b07b-ce86ea36327a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068283211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.4068283211
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3278703458
Short name T514
Test name
Test status
Simulation time 3564061332 ps
CPU time 19.87 seconds
Started Jul 18 06:22:29 PM PDT 24
Finished Jul 18 06:22:51 PM PDT 24
Peak memory 238352 kb
Host smart-c7918dd5-cf1e-4be9-8fd2-352ab79a5084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278703458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3278703458
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.31169166
Short name T801
Test name
Test status
Simulation time 3391611385 ps
CPU time 21.56 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:55 PM PDT 24
Peak memory 224988 kb
Host smart-5cfecb56-1b48-4231-aedb-7f4b141a0257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31169166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.31169166
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2265240942
Short name T283
Test name
Test status
Simulation time 7082521011 ps
CPU time 80.31 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:23:53 PM PDT 24
Peak memory 251748 kb
Host smart-dec2c624-eb23-4498-a998-eb99a9a0da2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265240942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2265240942
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1937801581
Short name T974
Test name
Test status
Simulation time 1348870749 ps
CPU time 19.11 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:51 PM PDT 24
Peak memory 224904 kb
Host smart-a4e91f0a-aa38-4178-9c37-151fbbd8b949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937801581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1937801581
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4217217337
Short name T481
Test name
Test status
Simulation time 2274306628 ps
CPU time 23.28 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:57 PM PDT 24
Peak memory 233164 kb
Host smart-261667ee-f277-4e2d-9441-937cf33343af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217217337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4217217337
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1140731442
Short name T533
Test name
Test status
Simulation time 2759336849 ps
CPU time 3.88 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:38 PM PDT 24
Peak memory 224968 kb
Host smart-c1fcb23f-228c-457e-834a-e938d0dba77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140731442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1140731442
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2027464547
Short name T994
Test name
Test status
Simulation time 1939987527 ps
CPU time 8.3 seconds
Started Jul 18 06:22:32 PM PDT 24
Finished Jul 18 06:22:43 PM PDT 24
Peak memory 233208 kb
Host smart-afda682a-5163-44d4-9ad7-a4c80b066ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027464547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2027464547
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3759433649
Short name T351
Test name
Test status
Simulation time 2904101555 ps
CPU time 7.7 seconds
Started Jul 18 06:22:29 PM PDT 24
Finished Jul 18 06:22:39 PM PDT 24
Peak memory 223668 kb
Host smart-f2a7d5f3-a224-47cb-b0a9-8f2c9de46a21
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3759433649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3759433649
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3947114232
Short name T297
Test name
Test status
Simulation time 3812162741 ps
CPU time 31.94 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:23:06 PM PDT 24
Peak memory 217100 kb
Host smart-066bfae1-e037-406f-98b0-428e0fcad5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947114232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3947114232
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2220193117
Short name T696
Test name
Test status
Simulation time 7694103064 ps
CPU time 6.88 seconds
Started Jul 18 06:22:28 PM PDT 24
Finished Jul 18 06:22:36 PM PDT 24
Peak memory 216772 kb
Host smart-53eca5e3-0fc6-43bb-ac90-00cb491b912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220193117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2220193117
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3999258109
Short name T460
Test name
Test status
Simulation time 23244975 ps
CPU time 0.7 seconds
Started Jul 18 06:22:33 PM PDT 24
Finished Jul 18 06:22:36 PM PDT 24
Peak memory 206136 kb
Host smart-931e6d4b-4416-4ae0-999c-b3ff0ff18293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999258109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3999258109
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1338739394
Short name T834
Test name
Test status
Simulation time 131029170 ps
CPU time 1.08 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:34 PM PDT 24
Peak memory 207540 kb
Host smart-94221a88-ab67-4f1d-bd60-4a887660cd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338739394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1338739394
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2909239579
Short name T864
Test name
Test status
Simulation time 415997050 ps
CPU time 5.98 seconds
Started Jul 18 06:22:32 PM PDT 24
Finished Jul 18 06:22:40 PM PDT 24
Peak memory 240692 kb
Host smart-40bfc849-0448-47b6-bc39-47605e4cdce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909239579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2909239579
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2017038645
Short name T411
Test name
Test status
Simulation time 36480765 ps
CPU time 0.71 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:22:49 PM PDT 24
Peak memory 206264 kb
Host smart-ed29e6d0-1c47-4e29-b634-c3e287a0ce42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017038645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2017038645
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3854790525
Short name T921
Test name
Test status
Simulation time 125718049 ps
CPU time 4.46 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:38 PM PDT 24
Peak memory 233140 kb
Host smart-0e8f9c03-8503-4f71-98e1-41f483228fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854790525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3854790525
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.93988059
Short name T568
Test name
Test status
Simulation time 14395723 ps
CPU time 0.81 seconds
Started Jul 18 06:22:34 PM PDT 24
Finished Jul 18 06:22:36 PM PDT 24
Peak memory 207080 kb
Host smart-a0602354-c018-4bad-a134-e48fdb882921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93988059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.93988059
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.935401602
Short name T185
Test name
Test status
Simulation time 36312563219 ps
CPU time 280.36 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:27:27 PM PDT 24
Peak memory 257020 kb
Host smart-1d3e13dd-3d00-4e43-8891-3c0ee36f24f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935401602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.935401602
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.505558886
Short name T284
Test name
Test status
Simulation time 37411329226 ps
CPU time 133.43 seconds
Started Jul 18 06:22:48 PM PDT 24
Finished Jul 18 06:25:04 PM PDT 24
Peak memory 257248 kb
Host smart-f032a625-656b-4329-a095-97fe26cc18a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505558886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.505558886
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1954715184
Short name T298
Test name
Test status
Simulation time 11981318493 ps
CPU time 55.16 seconds
Started Jul 18 06:22:48 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 233076 kb
Host smart-03032c66-6a44-4366-8f5c-b38a821ed689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954715184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1954715184
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3208533752
Short name T327
Test name
Test status
Simulation time 83088086 ps
CPU time 3.87 seconds
Started Jul 18 06:22:44 PM PDT 24
Finished Jul 18 06:22:49 PM PDT 24
Peak memory 233108 kb
Host smart-7ef227cc-e17d-43a9-8810-90f396f7e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208533752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3208533752
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3912928742
Short name T958
Test name
Test status
Simulation time 47233201739 ps
CPU time 169.65 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:25:39 PM PDT 24
Peak memory 249588 kb
Host smart-e4bd1bf7-f691-4c42-bcf4-788b8ff1839f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912928742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3912928742
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3684920660
Short name T182
Test name
Test status
Simulation time 182656836 ps
CPU time 2.93 seconds
Started Jul 18 06:22:29 PM PDT 24
Finished Jul 18 06:22:34 PM PDT 24
Peak memory 224884 kb
Host smart-70d61209-d937-4f77-b99f-94e75389e16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684920660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3684920660
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2765662294
Short name T986
Test name
Test status
Simulation time 24009877202 ps
CPU time 50.15 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:23:22 PM PDT 24
Peak memory 234148 kb
Host smart-112b067c-c186-4d02-b705-27aa97b29363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765662294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2765662294
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3915890422
Short name T634
Test name
Test status
Simulation time 64948314369 ps
CPU time 13.96 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:48 PM PDT 24
Peak memory 231852 kb
Host smart-cbda8aca-d6a3-4103-af79-dd16547f1d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915890422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3915890422
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2013980016
Short name T893
Test name
Test status
Simulation time 5662299649 ps
CPU time 9.31 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:41 PM PDT 24
Peak memory 240160 kb
Host smart-84444ff0-c7cc-457a-9079-d8605641ee81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013980016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2013980016
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.541091187
Short name T867
Test name
Test status
Simulation time 149570397 ps
CPU time 4.17 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:22:50 PM PDT 24
Peak memory 220700 kb
Host smart-eb9bdd24-9794-44c4-8f65-15cca5f4a02f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=541091187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.541091187
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.954689768
Short name T612
Test name
Test status
Simulation time 77518375 ps
CPU time 1.24 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:22:50 PM PDT 24
Peak memory 207548 kb
Host smart-b805513f-91c6-4817-b6d8-10de71466bf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954689768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.954689768
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3031260263
Short name T844
Test name
Test status
Simulation time 17021547 ps
CPU time 0.73 seconds
Started Jul 18 06:22:33 PM PDT 24
Finished Jul 18 06:22:36 PM PDT 24
Peak memory 206500 kb
Host smart-c902396a-441a-4c9a-a0ae-f0a180e72d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031260263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3031260263
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.371097856
Short name T707
Test name
Test status
Simulation time 5485595519 ps
CPU time 13.3 seconds
Started Jul 18 06:22:30 PM PDT 24
Finished Jul 18 06:22:45 PM PDT 24
Peak memory 216708 kb
Host smart-e1458b24-0b02-44ba-8d8d-f26e83269e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371097856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.371097856
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2638270929
Short name T412
Test name
Test status
Simulation time 151070492 ps
CPU time 0.81 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:34 PM PDT 24
Peak memory 206464 kb
Host smart-03dc5966-4ae8-45a6-9865-62547a03c86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638270929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2638270929
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2553779623
Short name T901
Test name
Test status
Simulation time 37491770 ps
CPU time 0.78 seconds
Started Jul 18 06:22:31 PM PDT 24
Finished Jul 18 06:22:35 PM PDT 24
Peak memory 206628 kb
Host smart-16a3e1a4-3add-4204-b7b7-53c87a1e8232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553779623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2553779623
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2834037781
Short name T4
Test name
Test status
Simulation time 5808584484 ps
CPU time 12.51 seconds
Started Jul 18 06:22:32 PM PDT 24
Finished Jul 18 06:22:47 PM PDT 24
Peak memory 233152 kb
Host smart-7da592d8-a223-472a-8769-e61e63877c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834037781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2834037781
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1534721673
Short name T399
Test name
Test status
Simulation time 17224949 ps
CPU time 0.74 seconds
Started Jul 18 06:22:46 PM PDT 24
Finished Jul 18 06:22:49 PM PDT 24
Peak memory 205284 kb
Host smart-b757f1bc-257b-4f7b-9349-8ad95820e7f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534721673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1534721673
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1343909126
Short name T370
Test name
Test status
Simulation time 279216977 ps
CPU time 2.32 seconds
Started Jul 18 06:22:49 PM PDT 24
Finished Jul 18 06:22:54 PM PDT 24
Peak memory 224556 kb
Host smart-a63f6139-aaf6-49bf-ba86-a639a4aa59c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343909126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1343909126
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1069111327
Short name T617
Test name
Test status
Simulation time 53452438 ps
CPU time 0.79 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:22:47 PM PDT 24
Peak memory 207144 kb
Host smart-9e3c26fc-f551-4379-9013-23a66199305c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069111327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1069111327
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1766448248
Short name T580
Test name
Test status
Simulation time 1937736875 ps
CPU time 25.11 seconds
Started Jul 18 06:22:46 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 249548 kb
Host smart-3ac00c90-9e1d-4464-8deb-37718394ddac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766448248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1766448248
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1794408465
Short name T564
Test name
Test status
Simulation time 65000521655 ps
CPU time 80.84 seconds
Started Jul 18 06:22:49 PM PDT 24
Finished Jul 18 06:24:12 PM PDT 24
Peak memory 252500 kb
Host smart-59c04910-4d48-4f8c-a538-d258db7dbe88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794408465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1794408465
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.964933915
Short name T263
Test name
Test status
Simulation time 7097624044 ps
CPU time 87.59 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:24:15 PM PDT 24
Peak memory 255724 kb
Host smart-fa3fa880-c8b3-4ba5-8ceb-03af9fdc130a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964933915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.964933915
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.713386067
Short name T288
Test name
Test status
Simulation time 18659166336 ps
CPU time 68.74 seconds
Started Jul 18 06:22:46 PM PDT 24
Finished Jul 18 06:23:58 PM PDT 24
Peak memory 252968 kb
Host smart-6df59b98-dfc5-45af-a2fd-cfb2bfc9c73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713386067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.713386067
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.322895165
Short name T991
Test name
Test status
Simulation time 28374281995 ps
CPU time 205.31 seconds
Started Jul 18 06:22:46 PM PDT 24
Finished Jul 18 06:26:14 PM PDT 24
Peak memory 255056 kb
Host smart-cadb0159-31ad-49e5-9b41-ffe18f93515a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322895165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.322895165
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2222314799
Short name T682
Test name
Test status
Simulation time 8656205008 ps
CPU time 16.81 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:23:05 PM PDT 24
Peak memory 224956 kb
Host smart-a2e13a99-fb4e-4244-a4f6-24d92ad6d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222314799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2222314799
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.484769215
Short name T911
Test name
Test status
Simulation time 29220015302 ps
CPU time 163.24 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:25:31 PM PDT 24
Peak memory 234236 kb
Host smart-e3a298c4-f65f-419d-b275-8e4a914f238d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484769215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.484769215
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.351959658
Short name T956
Test name
Test status
Simulation time 267060422 ps
CPU time 2.97 seconds
Started Jul 18 06:22:49 PM PDT 24
Finished Jul 18 06:22:54 PM PDT 24
Peak memory 233156 kb
Host smart-4377b268-daf6-491b-bd65-c63c0c6ff538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351959658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.351959658
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.497482541
Short name T999
Test name
Test status
Simulation time 1700907784 ps
CPU time 3.4 seconds
Started Jul 18 06:22:48 PM PDT 24
Finished Jul 18 06:22:55 PM PDT 24
Peak memory 224736 kb
Host smart-1ce89fb7-7000-44ce-89e2-6955270e04b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497482541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.497482541
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2064937022
Short name T1004
Test name
Test status
Simulation time 1011864657 ps
CPU time 11.27 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:22:58 PM PDT 24
Peak memory 220828 kb
Host smart-f7934756-ca6b-4e0b-8e98-3a030905a67d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2064937022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2064937022
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1644804811
Short name T492
Test name
Test status
Simulation time 11881749677 ps
CPU time 17.88 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:23:07 PM PDT 24
Peak memory 224896 kb
Host smart-cb3678d7-1829-48b7-9e67-c3c15b693abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644804811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1644804811
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.760753610
Short name T609
Test name
Test status
Simulation time 1876059779 ps
CPU time 10.73 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:23:00 PM PDT 24
Peak memory 216652 kb
Host smart-e0d89565-35ee-4228-8e17-b630efc85b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760753610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.760753610
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2494064821
Short name T159
Test name
Test status
Simulation time 4153125188 ps
CPU time 6.92 seconds
Started Jul 18 06:22:45 PM PDT 24
Finished Jul 18 06:22:54 PM PDT 24
Peak memory 216740 kb
Host smart-722d2c0e-f9c9-43e5-b7c5-3bc3d6c5a502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494064821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2494064821
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.1789934792
Short name T511
Test name
Test status
Simulation time 24093274 ps
CPU time 0.9 seconds
Started Jul 18 06:22:48 PM PDT 24
Finished Jul 18 06:22:51 PM PDT 24
Peak memory 207224 kb
Host smart-bd6e3ab4-084f-4ac6-9dec-e2f18831ab54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789934792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1789934792
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.2880120468
Short name T401
Test name
Test status
Simulation time 77910168 ps
CPU time 0.85 seconds
Started Jul 18 06:22:50 PM PDT 24
Finished Jul 18 06:22:53 PM PDT 24
Peak memory 206436 kb
Host smart-21536407-f1c8-4518-8456-75be34845f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880120468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.2880120468
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4030328704
Short name T849
Test name
Test status
Simulation time 114297305 ps
CPU time 2.07 seconds
Started Jul 18 06:22:46 PM PDT 24
Finished Jul 18 06:22:50 PM PDT 24
Peak memory 224880 kb
Host smart-458682af-5b6e-477d-afca-583138be08f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030328704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4030328704
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2712888875
Short name T611
Test name
Test status
Simulation time 13423142 ps
CPU time 0.76 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:16:54 PM PDT 24
Peak memory 206248 kb
Host smart-723dfa90-dfce-4a70-a344-f9093214c2c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712888875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
712888875
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.617384306
Short name T624
Test name
Test status
Simulation time 41726247 ps
CPU time 2.76 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:16:53 PM PDT 24
Peak memory 233156 kb
Host smart-42448982-d08c-44c7-8ee3-e30d111bda24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617384306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.617384306
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3029213102
Short name T309
Test name
Test status
Simulation time 16060983 ps
CPU time 0.74 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:16:53 PM PDT 24
Peak memory 207380 kb
Host smart-c0485cdc-a58a-4839-9cea-cc4e8ff72575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029213102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3029213102
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2926688019
Short name T357
Test name
Test status
Simulation time 4880512273 ps
CPU time 19.08 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:17:12 PM PDT 24
Peak memory 239252 kb
Host smart-5329a717-c6c1-4703-a009-6353a29e4b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926688019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2926688019
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.1992442056
Short name T990
Test name
Test status
Simulation time 5835484433 ps
CPU time 86.91 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:18:19 PM PDT 24
Peak memory 249668 kb
Host smart-0d5654ba-a4f1-4dbe-8aa2-61d9905b76af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992442056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.1992442056
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1235042023
Short name T265
Test name
Test status
Simulation time 131919414642 ps
CPU time 244.57 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:20:55 PM PDT 24
Peak memory 264020 kb
Host smart-883db9ff-a81d-474b-9b52-b4058cade19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235042023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1235042023
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.4005552696
Short name T293
Test name
Test status
Simulation time 3570075848 ps
CPU time 16.11 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:17:04 PM PDT 24
Peak memory 235332 kb
Host smart-b2896a1d-713b-4fc5-a3c8-c11ad824541f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005552696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.4005552696
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.2580963385
Short name T258
Test name
Test status
Simulation time 2920136977 ps
CPU time 41.68 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:17:32 PM PDT 24
Peak memory 238068 kb
Host smart-7ca0b9bf-2d93-4bcf-a9a8-7aade0dd6c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580963385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.2580963385
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.416386080
Short name T812
Test name
Test status
Simulation time 20800901569 ps
CPU time 41.34 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:17:34 PM PDT 24
Peak memory 225012 kb
Host smart-3e41f999-f6f2-4383-8081-ae804bcb26e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416386080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.416386080
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2237307580
Short name T814
Test name
Test status
Simulation time 7332844901 ps
CPU time 9.12 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:16:59 PM PDT 24
Peak memory 233236 kb
Host smart-0a32a069-3a21-49ef-b347-f1988992c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237307580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2237307580
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.93617709
Short name T245
Test name
Test status
Simulation time 15152495516 ps
CPU time 19.26 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:17:12 PM PDT 24
Peak memory 224944 kb
Host smart-81a51375-f114-4ab4-9b9a-0f8155efad53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93617709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.93617709
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2927509714
Short name T637
Test name
Test status
Simulation time 42251596140 ps
CPU time 20.18 seconds
Started Jul 18 06:16:51 PM PDT 24
Finished Jul 18 06:17:14 PM PDT 24
Peak memory 241296 kb
Host smart-0394aa11-8bf3-4076-bacf-392bbc43da50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927509714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2927509714
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1177799651
Short name T881
Test name
Test status
Simulation time 1176044377 ps
CPU time 12.77 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:17:03 PM PDT 24
Peak memory 222424 kb
Host smart-d5fcf3ca-6adb-452e-a1e8-4a6dba2d3ad4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1177799651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1177799651
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1583532383
Short name T67
Test name
Test status
Simulation time 87429723 ps
CPU time 1.21 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:16:52 PM PDT 24
Peak memory 237116 kb
Host smart-754dea0e-a51b-4967-ace0-c61534417a4f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583532383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1583532383
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1006256464
Short name T264
Test name
Test status
Simulation time 15726758550 ps
CPU time 242.93 seconds
Started Jul 18 06:16:50 PM PDT 24
Finished Jul 18 06:20:56 PM PDT 24
Peak memory 274236 kb
Host smart-5bd42d37-025c-4010-9b16-afe0f3d698e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006256464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1006256464
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.674401635
Short name T887
Test name
Test status
Simulation time 6443115979 ps
CPU time 35.15 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:17:26 PM PDT 24
Peak memory 216804 kb
Host smart-d94a18e6-37d3-4e48-b675-4f0a08bc115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674401635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.674401635
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3262525033
Short name T438
Test name
Test status
Simulation time 369617132 ps
CPU time 1.81 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:16:52 PM PDT 24
Peak memory 208372 kb
Host smart-6c0dd31f-b881-4b02-b45b-24017457d71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262525033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3262525033
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1470471656
Short name T678
Test name
Test status
Simulation time 131704546 ps
CPU time 2.56 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:16:54 PM PDT 24
Peak memory 216708 kb
Host smart-2c5d5066-e249-4825-973c-cc14bdb5fa41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470471656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1470471656
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2939912859
Short name T992
Test name
Test status
Simulation time 81988480 ps
CPU time 0.98 seconds
Started Jul 18 06:16:54 PM PDT 24
Finished Jul 18 06:16:56 PM PDT 24
Peak memory 207476 kb
Host smart-c55e07a0-0354-4c73-b73f-f25ec67ce327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939912859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2939912859
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2428985011
Short name T940
Test name
Test status
Simulation time 4371950214 ps
CPU time 18.2 seconds
Started Jul 18 06:16:46 PM PDT 24
Finished Jul 18 06:17:06 PM PDT 24
Peak memory 233236 kb
Host smart-28f69bd3-507a-4a17-b7d8-53d3b58e66c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428985011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2428985011
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2229172176
Short name T304
Test name
Test status
Simulation time 53525075 ps
CPU time 0.77 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:09 PM PDT 24
Peak memory 206104 kb
Host smart-a67f79e0-c851-416a-82de-191a7746d799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229172176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2229172176
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3882601880
Short name T719
Test name
Test status
Simulation time 176840978 ps
CPU time 3.1 seconds
Started Jul 18 06:23:09 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 224884 kb
Host smart-8ac7dca6-6474-459b-96f7-4e031cbbf462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882601880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3882601880
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1279399930
Short name T855
Test name
Test status
Simulation time 62406601 ps
CPU time 0.82 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:22:50 PM PDT 24
Peak memory 207068 kb
Host smart-6e3a2b67-623e-49d4-9bd3-11f67e71ea9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279399930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1279399930
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1058736173
Short name T937
Test name
Test status
Simulation time 108494869741 ps
CPU time 188.89 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:26:17 PM PDT 24
Peak memory 249616 kb
Host smart-4dd1a937-826c-4630-8e53-d07a1d17ca2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058736173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1058736173
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2830060487
Short name T821
Test name
Test status
Simulation time 21115821797 ps
CPU time 85.21 seconds
Started Jul 18 06:23:08 PM PDT 24
Finished Jul 18 06:24:36 PM PDT 24
Peak memory 249680 kb
Host smart-5248bf06-73ec-4867-8dce-139e248d70e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830060487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2830060487
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2074722669
Short name T908
Test name
Test status
Simulation time 99404179690 ps
CPU time 113.61 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:25:01 PM PDT 24
Peak memory 257352 kb
Host smart-ed6a9df8-fdd1-43e1-987e-85295bbddb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074722669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2074722669
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1690654348
Short name T367
Test name
Test status
Simulation time 5608204620 ps
CPU time 54.89 seconds
Started Jul 18 06:23:10 PM PDT 24
Finished Jul 18 06:24:06 PM PDT 24
Peak memory 234248 kb
Host smart-7d2d88e4-0544-484a-bbd8-95dbc7b323ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690654348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1690654348
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2558063506
Short name T683
Test name
Test status
Simulation time 63099690134 ps
CPU time 154.54 seconds
Started Jul 18 06:23:08 PM PDT 24
Finished Jul 18 06:25:45 PM PDT 24
Peak memory 266992 kb
Host smart-aaecd933-83ae-431a-a87c-6b5909c221f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558063506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2558063506
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.775563345
Short name T487
Test name
Test status
Simulation time 1850132770 ps
CPU time 6.85 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:17 PM PDT 24
Peak memory 233168 kb
Host smart-9d0c9c11-f227-47fa-89da-75aae399fb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775563345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.775563345
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1186999350
Short name T45
Test name
Test status
Simulation time 1215835008 ps
CPU time 5.81 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:15 PM PDT 24
Peak memory 233176 kb
Host smart-366a2706-2be2-4bff-b1c3-82525fbb6243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186999350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1186999350
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.560159648
Short name T938
Test name
Test status
Simulation time 377534426 ps
CPU time 4.76 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 224904 kb
Host smart-68e30ce2-3dd4-4b7d-a8de-e5991acc05b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560159648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.560159648
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2928053027
Short name T467
Test name
Test status
Simulation time 4621646975 ps
CPU time 5.24 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 225044 kb
Host smart-3abc71b1-c46f-4338-acd9-77f8b8ffbd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928053027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2928053027
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1577345629
Short name T12
Test name
Test status
Simulation time 337407992 ps
CPU time 3.45 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:23:10 PM PDT 24
Peak memory 223268 kb
Host smart-c8fc8a01-0dcf-423f-b660-56b4fad1a942
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1577345629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1577345629
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1449615304
Short name T556
Test name
Test status
Simulation time 103543399003 ps
CPU time 141.31 seconds
Started Jul 18 06:23:08 PM PDT 24
Finished Jul 18 06:25:32 PM PDT 24
Peak memory 257408 kb
Host smart-20442d8c-fbd2-4f0d-a246-73519d98211e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449615304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1449615304
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1809258996
Short name T406
Test name
Test status
Simulation time 5260924180 ps
CPU time 28.27 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:23:18 PM PDT 24
Peak memory 216984 kb
Host smart-a29feeea-b4ef-46de-8270-c11bf1cc1636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809258996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1809258996
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1900187027
Short name T317
Test name
Test status
Simulation time 864262498 ps
CPU time 2.96 seconds
Started Jul 18 06:22:50 PM PDT 24
Finished Jul 18 06:22:55 PM PDT 24
Peak memory 208324 kb
Host smart-b7fe9ab2-479b-4512-bc46-95cd2e4b617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900187027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1900187027
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4086437120
Short name T935
Test name
Test status
Simulation time 237687180 ps
CPU time 1.5 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:23:07 PM PDT 24
Peak memory 216708 kb
Host smart-d70faef2-7883-41a5-aaba-dbc19e01c9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086437120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4086437120
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2649661717
Short name T32
Test name
Test status
Simulation time 43128472 ps
CPU time 0.82 seconds
Started Jul 18 06:22:47 PM PDT 24
Finished Jul 18 06:22:50 PM PDT 24
Peak memory 206260 kb
Host smart-f5f94669-9036-4c75-96fa-130c1580e2f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649661717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2649661717
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3266537203
Short name T204
Test name
Test status
Simulation time 1752501770 ps
CPU time 3.67 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:23:10 PM PDT 24
Peak memory 233120 kb
Host smart-a867ce37-36ae-41a8-a1cc-3bc8f4510de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266537203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3266537203
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3362764964
Short name T980
Test name
Test status
Simulation time 13229749 ps
CPU time 0.71 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:10 PM PDT 24
Peak memory 205932 kb
Host smart-44a3b434-8bf7-4a3b-82cf-f1214727a599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362764964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3362764964
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2020001160
Short name T361
Test name
Test status
Simulation time 90577406 ps
CPU time 3.29 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:13 PM PDT 24
Peak memory 233140 kb
Host smart-ba5cc8ba-f2ae-43f5-a892-08ac1b10738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020001160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2020001160
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.165834172
Short name T454
Test name
Test status
Simulation time 48813504 ps
CPU time 0.82 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:08 PM PDT 24
Peak memory 206092 kb
Host smart-94a2ef40-416d-4df3-8cf1-9320184e9033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165834172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.165834172
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2294362086
Short name T44
Test name
Test status
Simulation time 74705826136 ps
CPU time 121.54 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:25:08 PM PDT 24
Peak memory 249548 kb
Host smart-19c80232-2179-4b55-aeba-901a29a0e45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294362086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2294362086
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1143208913
Short name T424
Test name
Test status
Simulation time 22372943529 ps
CPU time 64.77 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:24:15 PM PDT 24
Peak memory 241444 kb
Host smart-125f2c1e-564c-446b-b3c5-6739cf9fa19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143208913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1143208913
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.270294973
Short name T494
Test name
Test status
Simulation time 13267119451 ps
CPU time 177.17 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:26:04 PM PDT 24
Peak memory 257836 kb
Host smart-7e9d9e53-08c5-46bd-a7c5-f066fbc6fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270294973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.270294973
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3541523011
Short name T136
Test name
Test status
Simulation time 1898314392 ps
CPU time 31.23 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:41 PM PDT 24
Peak memory 238632 kb
Host smart-6b685648-c226-4790-b400-a83417ae8541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541523011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3541523011
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1166918959
Short name T733
Test name
Test status
Simulation time 677091900 ps
CPU time 5.78 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:23:13 PM PDT 24
Peak memory 234352 kb
Host smart-1b08fadd-9094-4218-b092-91deee3d3020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166918959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1166918959
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2892750268
Short name T340
Test name
Test status
Simulation time 147499651 ps
CPU time 2.2 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:12 PM PDT 24
Peak memory 224144 kb
Host smart-97567078-1bb6-40b5-8c4e-96ae7eadb4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892750268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2892750268
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3341238688
Short name T508
Test name
Test status
Simulation time 6072738228 ps
CPU time 23.35 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:32 PM PDT 24
Peak memory 239860 kb
Host smart-25836710-03b2-440d-9305-bde1be7f54b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341238688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3341238688
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2790962171
Short name T208
Test name
Test status
Simulation time 3994089835 ps
CPU time 8.23 seconds
Started Jul 18 06:23:08 PM PDT 24
Finished Jul 18 06:23:19 PM PDT 24
Peak memory 251616 kb
Host smart-cefe34b7-bb28-466d-9cd6-c765346e10e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790962171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2790962171
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.3699982982
Short name T431
Test name
Test status
Simulation time 5249873118 ps
CPU time 5.53 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:15 PM PDT 24
Peak memory 225036 kb
Host smart-0faa7021-523f-4584-8eb4-c2edbbb11776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699982982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.3699982982
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1442296318
Short name T139
Test name
Test status
Simulation time 2550086875 ps
CPU time 8.91 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 223564 kb
Host smart-39126794-c1d3-42e0-aab8-85dfcdcd44ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1442296318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1442296318
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2772608646
Short name T225
Test name
Test status
Simulation time 37317385149 ps
CPU time 74.37 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:24:22 PM PDT 24
Peak memory 249612 kb
Host smart-c274f2a8-5a47-4852-900f-0bc67bc8610f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772608646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2772608646
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3026909341
Short name T831
Test name
Test status
Simulation time 1447879591 ps
CPU time 2.84 seconds
Started Jul 18 06:23:04 PM PDT 24
Finished Jul 18 06:23:08 PM PDT 24
Peak memory 216652 kb
Host smart-0d2a1967-2eac-4503-a8eb-c511c7790fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026909341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3026909341
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.4157105871
Short name T767
Test name
Test status
Simulation time 252509216 ps
CPU time 2.82 seconds
Started Jul 18 06:23:08 PM PDT 24
Finished Jul 18 06:23:13 PM PDT 24
Peak memory 216644 kb
Host smart-452938cd-e102-4a68-aa7f-4e9bd83dacc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157105871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.4157105871
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.675388200
Short name T315
Test name
Test status
Simulation time 210794986 ps
CPU time 1.43 seconds
Started Jul 18 06:23:09 PM PDT 24
Finished Jul 18 06:23:13 PM PDT 24
Peak memory 216632 kb
Host smart-b58e4d77-02c3-4eb2-b110-38c71b2de94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675388200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.675388200
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1327709894
Short name T402
Test name
Test status
Simulation time 90752836 ps
CPU time 0.93 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:09 PM PDT 24
Peak memory 206456 kb
Host smart-d789f82b-5336-47ed-ba45-4cabfe941570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327709894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1327709894
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1360604314
Short name T215
Test name
Test status
Simulation time 13158559530 ps
CPU time 28.67 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:39 PM PDT 24
Peak memory 234724 kb
Host smart-94e4bda2-59dd-4402-9a18-ba8456965aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360604314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1360604314
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2978718186
Short name T162
Test name
Test status
Simulation time 15486517 ps
CPU time 0.75 seconds
Started Jul 18 06:23:25 PM PDT 24
Finished Jul 18 06:23:27 PM PDT 24
Peak memory 205352 kb
Host smart-7056c144-67c1-431d-ba10-11442a405a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978718186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2978718186
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2984790977
Short name T549
Test name
Test status
Simulation time 410799068 ps
CPU time 6.35 seconds
Started Jul 18 06:23:23 PM PDT 24
Finished Jul 18 06:23:32 PM PDT 24
Peak memory 233100 kb
Host smart-e6c9c495-3ef4-47f1-8d91-1cfa1aa4f339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984790977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2984790977
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.941587660
Short name T512
Test name
Test status
Simulation time 22274016 ps
CPU time 0.85 seconds
Started Jul 18 06:23:07 PM PDT 24
Finished Jul 18 06:23:11 PM PDT 24
Peak memory 207072 kb
Host smart-d44a5322-d9be-42f8-b788-92bed39c2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941587660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.941587660
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3061658205
Short name T789
Test name
Test status
Simulation time 1312593448 ps
CPU time 18.88 seconds
Started Jul 18 06:23:26 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 240528 kb
Host smart-3785ab41-2805-4a7c-986b-304ec8fba392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061658205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3061658205
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.690501296
Short name T346
Test name
Test status
Simulation time 4170809677 ps
CPU time 59.92 seconds
Started Jul 18 06:23:19 PM PDT 24
Finished Jul 18 06:24:20 PM PDT 24
Peak memory 250700 kb
Host smart-c47ab39e-93fb-432c-8f05-91f89825c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690501296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.690501296
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.695215661
Short name T711
Test name
Test status
Simulation time 14643183921 ps
CPU time 53.04 seconds
Started Jul 18 06:23:28 PM PDT 24
Finished Jul 18 06:24:23 PM PDT 24
Peak memory 249476 kb
Host smart-c14f727e-cf0c-49c2-8bd2-f1b06d58634e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695215661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.695215661
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1609397605
Short name T871
Test name
Test status
Simulation time 1289651081 ps
CPU time 14.17 seconds
Started Jul 18 06:23:20 PM PDT 24
Finished Jul 18 06:23:35 PM PDT 24
Peak memory 240468 kb
Host smart-83db0ab0-cc38-4ddb-b0bc-cfaedfd4657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609397605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1609397605
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3802822041
Short name T439
Test name
Test status
Simulation time 23354674 ps
CPU time 0.73 seconds
Started Jul 18 06:23:27 PM PDT 24
Finished Jul 18 06:23:30 PM PDT 24
Peak memory 208044 kb
Host smart-351dfb51-a7ed-4c29-b88b-fa6f06b19045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802822041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3802822041
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2178929279
Short name T353
Test name
Test status
Simulation time 340498988 ps
CPU time 7.51 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:16 PM PDT 24
Peak memory 233088 kb
Host smart-42e61d73-2fd0-4281-938e-7f4d2a36467e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178929279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2178929279
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3752220072
Short name T1000
Test name
Test status
Simulation time 130199549 ps
CPU time 5.8 seconds
Started Jul 18 06:23:10 PM PDT 24
Finished Jul 18 06:23:17 PM PDT 24
Peak memory 233176 kb
Host smart-97d32db0-e7e7-451e-b42f-a3e54778c275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752220072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3752220072
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.262196232
Short name T782
Test name
Test status
Simulation time 3162032589 ps
CPU time 11.2 seconds
Started Jul 18 06:23:04 PM PDT 24
Finished Jul 18 06:23:16 PM PDT 24
Peak memory 233140 kb
Host smart-20e47f48-d1a9-42bf-9c62-e14f40b3d051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262196232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.262196232
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2789541421
Short name T723
Test name
Test status
Simulation time 11889645864 ps
CPU time 6.8 seconds
Started Jul 18 06:23:08 PM PDT 24
Finished Jul 18 06:23:18 PM PDT 24
Peak memory 233176 kb
Host smart-593e4c7f-6e42-42c6-b404-2e5d60fc8e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789541421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2789541421
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1585283046
Short name T11
Test name
Test status
Simulation time 165507590 ps
CPU time 4.79 seconds
Started Jul 18 06:23:23 PM PDT 24
Finished Jul 18 06:23:30 PM PDT 24
Peak memory 223600 kb
Host smart-1aad7223-673a-45c8-a930-55b91f92f7a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1585283046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1585283046
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3506390643
Short name T48
Test name
Test status
Simulation time 2100760612 ps
CPU time 46.06 seconds
Started Jul 18 06:23:24 PM PDT 24
Finished Jul 18 06:24:12 PM PDT 24
Peak memory 257808 kb
Host smart-b1c50676-14c4-4ddc-9e58-47a91e22fd1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506390643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3506390643
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1191162572
Short name T294
Test name
Test status
Simulation time 4143544002 ps
CPU time 13.87 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:23 PM PDT 24
Peak memory 219912 kb
Host smart-e913221a-899c-4554-a8e8-6d78282615f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191162572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1191162572
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.453054724
Short name T573
Test name
Test status
Simulation time 1949525037 ps
CPU time 2.98 seconds
Started Jul 18 06:23:04 PM PDT 24
Finished Jul 18 06:23:08 PM PDT 24
Peak memory 216668 kb
Host smart-fc4ff5fe-82fb-4f94-8800-8e448131fbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453054724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.453054724
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1994285838
Short name T321
Test name
Test status
Simulation time 1113745250 ps
CPU time 2.82 seconds
Started Jul 18 06:23:09 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 216640 kb
Host smart-834df6e4-aaa1-46c5-95f0-798710761fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994285838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1994285838
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3112838276
Short name T833
Test name
Test status
Simulation time 72734239 ps
CPU time 1.02 seconds
Started Jul 18 06:23:05 PM PDT 24
Finished Jul 18 06:23:07 PM PDT 24
Peak memory 207468 kb
Host smart-ce089e93-00e8-4aa8-9370-6413fc94f434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112838276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3112838276
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.525060059
Short name T520
Test name
Test status
Simulation time 900803789 ps
CPU time 5.79 seconds
Started Jul 18 06:23:06 PM PDT 24
Finished Jul 18 06:23:14 PM PDT 24
Peak memory 224920 kb
Host smart-17c17a5a-fe04-4cd1-9a67-ebc47c760aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525060059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.525060059
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2283472219
Short name T608
Test name
Test status
Simulation time 15744871 ps
CPU time 0.77 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:24 PM PDT 24
Peak memory 205968 kb
Host smart-4f549df8-29bb-47cd-8a71-d9e3381d6eb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283472219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2283472219
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3412525982
Short name T55
Test name
Test status
Simulation time 243688033 ps
CPU time 4.89 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:29 PM PDT 24
Peak memory 224960 kb
Host smart-790af82c-4998-4598-9514-ac72e1a77f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412525982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3412525982
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1184346410
Short name T349
Test name
Test status
Simulation time 16439717 ps
CPU time 0.77 seconds
Started Jul 18 06:23:30 PM PDT 24
Finished Jul 18 06:23:32 PM PDT 24
Peak memory 205996 kb
Host smart-bb456f1c-905f-425d-9716-038b4e1befae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184346410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1184346410
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2309376329
Short name T210
Test name
Test status
Simulation time 22291137432 ps
CPU time 32.83 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:56 PM PDT 24
Peak memory 241584 kb
Host smart-20260ee5-823b-4011-8fa6-a98e7e506559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309376329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2309376329
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3382633512
Short name T167
Test name
Test status
Simulation time 10059163197 ps
CPU time 70.31 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:24:33 PM PDT 24
Peak memory 257136 kb
Host smart-c1b1b02c-534c-4da0-9eaf-a399dcb97226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382633512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3382633512
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4087716452
Short name T561
Test name
Test status
Simulation time 168313540 ps
CPU time 4.22 seconds
Started Jul 18 06:23:20 PM PDT 24
Finished Jul 18 06:23:25 PM PDT 24
Peak memory 224968 kb
Host smart-d286ace2-4884-4585-a869-4f5bf0fbe460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087716452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4087716452
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1898760442
Short name T434
Test name
Test status
Simulation time 6788347721 ps
CPU time 23.77 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 239060 kb
Host smart-ff4265d5-edfd-4caa-8e60-ebd8449f6bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898760442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1898760442
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.819840888
Short name T703
Test name
Test status
Simulation time 149856956 ps
CPU time 5.04 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:30 PM PDT 24
Peak memory 233148 kb
Host smart-71987010-d813-4455-bf3b-7c19db39d8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819840888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.819840888
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1825365708
Short name T9
Test name
Test status
Simulation time 5693803155 ps
CPU time 27.28 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:52 PM PDT 24
Peak memory 240480 kb
Host smart-c8c3a030-e689-41d4-8689-71fd82d30b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825365708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1825365708
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2302560420
Short name T272
Test name
Test status
Simulation time 15177374248 ps
CPU time 17.71 seconds
Started Jul 18 06:23:23 PM PDT 24
Finished Jul 18 06:23:43 PM PDT 24
Peak memory 233152 kb
Host smart-b76a42a4-58e4-4f0c-9cea-9e8096c17a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302560420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2302560420
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.783671196
Short name T423
Test name
Test status
Simulation time 187307912 ps
CPU time 2.66 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:27 PM PDT 24
Peak memory 233100 kb
Host smart-631a0b0b-a570-4baf-a8c8-9fc715f930b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783671196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.783671196
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3127241195
Short name T618
Test name
Test status
Simulation time 3446835100 ps
CPU time 18.67 seconds
Started Jul 18 06:23:25 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 222640 kb
Host smart-290a7655-0b93-472d-af24-3bae22fe01a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3127241195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3127241195
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3800488285
Short name T679
Test name
Test status
Simulation time 53418032 ps
CPU time 1.17 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:25 PM PDT 24
Peak memory 207512 kb
Host smart-6d3d5d56-ce8a-470d-bbd8-bbc86fc4c7df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800488285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3800488285
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.869152839
Short name T335
Test name
Test status
Simulation time 7429159369 ps
CPU time 19.59 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:44 PM PDT 24
Peak memory 216792 kb
Host smart-86442161-ac5d-4a03-8653-7f34437e648e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869152839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.869152839
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1886690989
Short name T700
Test name
Test status
Simulation time 33606579400 ps
CPU time 8.64 seconds
Started Jul 18 06:23:24 PM PDT 24
Finished Jul 18 06:23:35 PM PDT 24
Peak memory 216788 kb
Host smart-c42cbbf7-75da-470c-9145-e892274a99cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886690989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1886690989
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.617017209
Short name T385
Test name
Test status
Simulation time 35011391 ps
CPU time 0.91 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:25 PM PDT 24
Peak memory 207228 kb
Host smart-726f049d-1453-4883-be6c-ae7689d0573a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617017209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.617017209
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2285656431
Short name T464
Test name
Test status
Simulation time 60241510 ps
CPU time 0.84 seconds
Started Jul 18 06:23:25 PM PDT 24
Finished Jul 18 06:23:28 PM PDT 24
Peak memory 206436 kb
Host smart-ec8fc80a-a83f-4b3b-b593-a2667c1c25fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285656431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2285656431
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2221965610
Short name T220
Test name
Test status
Simulation time 5329471374 ps
CPU time 14.08 seconds
Started Jul 18 06:23:24 PM PDT 24
Finished Jul 18 06:23:40 PM PDT 24
Peak memory 233172 kb
Host smart-c8cd9d93-fa12-4de8-801b-1ed7841de53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221965610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2221965610
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2037738045
Short name T685
Test name
Test status
Simulation time 23718668 ps
CPU time 0.75 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:25 PM PDT 24
Peak memory 205944 kb
Host smart-1fe5f6f3-6b80-49a5-b3ce-4eae63d721e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037738045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2037738045
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2774765229
Short name T592
Test name
Test status
Simulation time 674044047 ps
CPU time 10.28 seconds
Started Jul 18 06:23:26 PM PDT 24
Finished Jul 18 06:23:38 PM PDT 24
Peak memory 233052 kb
Host smart-c12d66bc-66bd-45b5-83d4-ddd61cf37874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774765229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2774765229
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3385626750
Short name T24
Test name
Test status
Simulation time 46423557 ps
CPU time 0.83 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:23 PM PDT 24
Peak memory 207088 kb
Host smart-7ee5d7ec-9614-40ad-96a6-c085399cc771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385626750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3385626750
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.4222975904
Short name T673
Test name
Test status
Simulation time 3106046867 ps
CPU time 68.24 seconds
Started Jul 18 06:23:27 PM PDT 24
Finished Jul 18 06:24:37 PM PDT 24
Peak memory 250636 kb
Host smart-4c85e958-a41e-4c2a-b84c-9b843afd0b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222975904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.4222975904
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3652694022
Short name T53
Test name
Test status
Simulation time 23808344087 ps
CPU time 243.63 seconds
Started Jul 18 06:23:30 PM PDT 24
Finished Jul 18 06:27:35 PM PDT 24
Peak memory 257164 kb
Host smart-882ab354-5acb-44f4-b232-082c0401e6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652694022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3652694022
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3419381784
Short name T194
Test name
Test status
Simulation time 174027895670 ps
CPU time 126.63 seconds
Started Jul 18 06:23:28 PM PDT 24
Finished Jul 18 06:25:37 PM PDT 24
Peak memory 268184 kb
Host smart-5f97cded-cf45-42c6-967a-fc7911b63e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419381784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3419381784
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1444038214
Short name T1002
Test name
Test status
Simulation time 3092355685 ps
CPU time 24.61 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:49 PM PDT 24
Peak memory 240224 kb
Host smart-bcf55a16-d86e-4745-962b-4aec3eb4801c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444038214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1444038214
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.4036990886
Short name T790
Test name
Test status
Simulation time 27086901886 ps
CPU time 240.86 seconds
Started Jul 18 06:23:28 PM PDT 24
Finished Jul 18 06:27:31 PM PDT 24
Peak memory 272592 kb
Host smart-219184fc-0188-4cad-988d-29e2e9acf074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036990886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.4036990886
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.708817561
Short name T995
Test name
Test status
Simulation time 198171543 ps
CPU time 4.08 seconds
Started Jul 18 06:23:23 PM PDT 24
Finished Jul 18 06:23:30 PM PDT 24
Peak memory 224884 kb
Host smart-314e6a56-6cb7-445d-abb8-a8b8f98c4586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708817561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.708817561
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3612072926
Short name T329
Test name
Test status
Simulation time 434321088 ps
CPU time 4.02 seconds
Started Jul 18 06:23:24 PM PDT 24
Finished Jul 18 06:23:30 PM PDT 24
Peak memory 233172 kb
Host smart-bf4dd5e0-bd10-407e-bfc5-498b649dd756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612072926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3612072926
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3857457137
Short name T218
Test name
Test status
Simulation time 113840957 ps
CPU time 4.4 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:27 PM PDT 24
Peak memory 233172 kb
Host smart-95b9d6d6-e010-4494-a388-9b1b93458548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857457137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3857457137
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.356059361
Short name T939
Test name
Test status
Simulation time 4208981128 ps
CPU time 8.79 seconds
Started Jul 18 06:23:23 PM PDT 24
Finished Jul 18 06:23:35 PM PDT 24
Peak memory 233136 kb
Host smart-c8037dd0-02a1-4c73-b243-de03e4d3e0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356059361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.356059361
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3096660118
Short name T946
Test name
Test status
Simulation time 1431796203 ps
CPU time 4.13 seconds
Started Jul 18 06:23:23 PM PDT 24
Finished Jul 18 06:23:29 PM PDT 24
Peak memory 221180 kb
Host smart-359cfffc-2865-4de2-bf83-b9165c890ee0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3096660118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3096660118
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.573990171
Short name T155
Test name
Test status
Simulation time 160746406223 ps
CPU time 282.87 seconds
Started Jul 18 06:23:27 PM PDT 24
Finished Jul 18 06:28:11 PM PDT 24
Peak memory 252220 kb
Host smart-fee83555-a25e-44c2-a7f6-54926f632887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573990171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.573990171
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.3534401928
Short name T949
Test name
Test status
Simulation time 3479241862 ps
CPU time 32.51 seconds
Started Jul 18 06:23:20 PM PDT 24
Finished Jul 18 06:23:55 PM PDT 24
Peak memory 216860 kb
Host smart-ef7302ac-2157-4cd3-bb5f-4f6fbaab583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534401928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.3534401928
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3118222833
Short name T333
Test name
Test status
Simulation time 12531321 ps
CPU time 0.72 seconds
Started Jul 18 06:23:27 PM PDT 24
Finished Jul 18 06:23:30 PM PDT 24
Peak memory 206164 kb
Host smart-60127fe1-2368-48a0-8fb9-620d708734e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118222833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3118222833
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1012216468
Short name T794
Test name
Test status
Simulation time 130505058 ps
CPU time 1.91 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:27 PM PDT 24
Peak memory 216660 kb
Host smart-0a4ce929-e0d8-482c-993e-d9833d296482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012216468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1012216468
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2627856838
Short name T404
Test name
Test status
Simulation time 286925772 ps
CPU time 0.95 seconds
Started Jul 18 06:23:21 PM PDT 24
Finished Jul 18 06:23:24 PM PDT 24
Peak memory 206444 kb
Host smart-c7c54141-7e0c-49d7-a19e-7ce51e8be78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627856838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2627856838
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3418799869
Short name T708
Test name
Test status
Simulation time 41570605076 ps
CPU time 30.35 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:54 PM PDT 24
Peak memory 233576 kb
Host smart-9a916692-5002-4713-95d7-e26572986834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418799869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3418799869
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2449708498
Short name T551
Test name
Test status
Simulation time 21052910 ps
CPU time 0.73 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:23:46 PM PDT 24
Peak memory 206320 kb
Host smart-5506d060-d2d6-4699-8993-d1a6fb80b7b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449708498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2449708498
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3784050761
Short name T809
Test name
Test status
Simulation time 216921213 ps
CPU time 2.64 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:23:49 PM PDT 24
Peak memory 233108 kb
Host smart-f2f9401a-e96c-48af-8c6c-6f97aa486d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784050761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3784050761
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1892778127
Short name T895
Test name
Test status
Simulation time 23552779 ps
CPU time 0.82 seconds
Started Jul 18 06:23:22 PM PDT 24
Finished Jul 18 06:23:25 PM PDT 24
Peak memory 207056 kb
Host smart-a3f413e3-1d5b-4ad3-92c6-27638db789f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892778127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1892778127
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.456756782
Short name T207
Test name
Test status
Simulation time 44622243896 ps
CPU time 396.38 seconds
Started Jul 18 06:23:49 PM PDT 24
Finished Jul 18 06:30:27 PM PDT 24
Peak memory 251996 kb
Host smart-a6a86c33-1766-4cf4-a405-dcaa27b4b755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456756782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.456756782
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4207500250
Short name T444
Test name
Test status
Simulation time 229039338 ps
CPU time 4.22 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:23:50 PM PDT 24
Peak memory 237260 kb
Host smart-50e08e8f-5ccd-478b-8fa3-14c47a95f16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207500250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4207500250
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3868571922
Short name T943
Test name
Test status
Simulation time 15651282366 ps
CPU time 84.05 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:25:09 PM PDT 24
Peak memory 254868 kb
Host smart-2dab8d4b-ddde-4362-b6be-63a3d2af5e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868571922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3868571922
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1641955917
Short name T686
Test name
Test status
Simulation time 4058153938 ps
CPU time 24.81 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:24:09 PM PDT 24
Peak memory 225028 kb
Host smart-faf57095-d2ef-4980-b25d-d08314d5850d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641955917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1641955917
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.321888286
Short name T705
Test name
Test status
Simulation time 57423904104 ps
CPU time 83.62 seconds
Started Jul 18 06:23:42 PM PDT 24
Finished Jul 18 06:25:07 PM PDT 24
Peak memory 233168 kb
Host smart-28f1beb3-f7ee-4433-bf0c-7b4d5eefc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321888286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.321888286
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1852975461
Short name T198
Test name
Test status
Simulation time 1540210763 ps
CPU time 6.92 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:23:52 PM PDT 24
Peak memory 224928 kb
Host smart-7e3887f9-7117-4258-8b54-a7d7809d6194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852975461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1852975461
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2928643798
Short name T676
Test name
Test status
Simulation time 6770489080 ps
CPU time 10.31 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:23:55 PM PDT 24
Peak memory 240828 kb
Host smart-317499bd-b228-4969-84d6-37e48d89dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928643798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2928643798
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2395242673
Short name T619
Test name
Test status
Simulation time 168286805 ps
CPU time 5.38 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:23:51 PM PDT 24
Peak memory 223012 kb
Host smart-4e7c3549-3934-4686-85f5-0226966c0aeb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2395242673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2395242673
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2254379133
Short name T808
Test name
Test status
Simulation time 32847106686 ps
CPU time 70.67 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:24:56 PM PDT 24
Peak memory 233380 kb
Host smart-5592e02a-2955-458a-a6b0-361fb3a1b021
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254379133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2254379133
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1822991322
Short name T957
Test name
Test status
Simulation time 3987394419 ps
CPU time 19.88 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:24:06 PM PDT 24
Peak memory 216980 kb
Host smart-d0b55d6a-a503-47c8-8146-4cb58a786a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822991322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1822991322
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2202858620
Short name T456
Test name
Test status
Simulation time 12017713568 ps
CPU time 18.53 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:24:03 PM PDT 24
Peak memory 216720 kb
Host smart-9d9ffd35-d1d9-4cec-90c6-4e5631a11e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202858620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2202858620
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3500085265
Short name T593
Test name
Test status
Simulation time 195020378 ps
CPU time 1.22 seconds
Started Jul 18 06:23:42 PM PDT 24
Finished Jul 18 06:23:44 PM PDT 24
Peak memory 208364 kb
Host smart-bdd9662b-9a9e-433e-a662-c2eb17acd018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500085265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3500085265
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.4153417731
Short name T869
Test name
Test status
Simulation time 43382523 ps
CPU time 0.77 seconds
Started Jul 18 06:23:45 PM PDT 24
Finished Jul 18 06:23:47 PM PDT 24
Peak memory 206452 kb
Host smart-28780fae-6f56-44a4-ae29-f5f2158558c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153417731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.4153417731
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.311129658
Short name T581
Test name
Test status
Simulation time 52492315264 ps
CPU time 34.23 seconds
Started Jul 18 06:23:42 PM PDT 24
Finished Jul 18 06:24:17 PM PDT 24
Peak memory 250932 kb
Host smart-f9931bc5-cad4-4983-81b8-e1bcaca44afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311129658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.311129658
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1399267626
Short name T554
Test name
Test status
Simulation time 10552064 ps
CPU time 0.73 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:10 PM PDT 24
Peak memory 205352 kb
Host smart-e5f4830a-f54c-4345-82b2-7add119de63d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399267626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1399267626
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.568994943
Short name T111
Test name
Test status
Simulation time 194745614 ps
CPU time 2.83 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:23:49 PM PDT 24
Peak memory 233060 kb
Host smart-78c62cf6-3351-4148-aa82-5e015f7100e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568994943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.568994943
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1403214207
Short name T432
Test name
Test status
Simulation time 56866724 ps
CPU time 0.77 seconds
Started Jul 18 06:23:49 PM PDT 24
Finished Jul 18 06:23:51 PM PDT 24
Peak memory 207048 kb
Host smart-5adaab3a-5392-4705-9f6b-031894694d45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403214207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1403214207
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.538376257
Short name T614
Test name
Test status
Simulation time 9257844831 ps
CPU time 78.43 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:25:29 PM PDT 24
Peak memory 250748 kb
Host smart-61eb8e12-c423-4de1-b64c-b73d0eb42987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538376257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.538376257
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1299727539
Short name T826
Test name
Test status
Simulation time 5359644993 ps
CPU time 92.68 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:25:40 PM PDT 24
Peak memory 253656 kb
Host smart-f11d7e0e-5a4c-416b-b620-5c903aa30743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299727539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1299727539
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3444997135
Short name T633
Test name
Test status
Simulation time 9073833543 ps
CPU time 33.58 seconds
Started Jul 18 06:24:06 PM PDT 24
Finished Jul 18 06:24:41 PM PDT 24
Peak memory 237684 kb
Host smart-5ab251cb-6a27-47a9-aaea-c254d20948e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444997135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3444997135
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.2986563295
Short name T909
Test name
Test status
Simulation time 275242771 ps
CPU time 4.06 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:23:50 PM PDT 24
Peak memory 225004 kb
Host smart-771d02ee-3a39-495f-b808-4030d21d95c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986563295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.2986563295
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3720423305
Short name T447
Test name
Test status
Simulation time 9613966076 ps
CPU time 41.71 seconds
Started Jul 18 06:23:45 PM PDT 24
Finished Jul 18 06:24:28 PM PDT 24
Peak memory 238072 kb
Host smart-153e088f-d0d2-4974-b624-ff90cbe5cabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720423305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3720423305
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3342725333
Short name T313
Test name
Test status
Simulation time 25035355229 ps
CPU time 36.37 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:24:23 PM PDT 24
Peak memory 220100 kb
Host smart-9727f105-33a6-4e09-bb37-449d4175e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342725333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3342725333
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.381317905
Short name T751
Test name
Test status
Simulation time 125602155 ps
CPU time 3.55 seconds
Started Jul 18 06:23:42 PM PDT 24
Finished Jul 18 06:23:47 PM PDT 24
Peak memory 224864 kb
Host smart-e519b314-312c-4ae3-a86b-f244fc556d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381317905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.381317905
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2789503598
Short name T30
Test name
Test status
Simulation time 7842205738 ps
CPU time 7.02 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:23:53 PM PDT 24
Peak memory 224980 kb
Host smart-027d990b-41d4-44b1-985e-d73119d017df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789503598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2789503598
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.797385738
Short name T781
Test name
Test status
Simulation time 868734491 ps
CPU time 5.2 seconds
Started Jul 18 06:23:44 PM PDT 24
Finished Jul 18 06:23:51 PM PDT 24
Peak memory 239208 kb
Host smart-31549809-b80f-4e1c-8ea4-4dd775a169c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797385738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.797385738
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2265922566
Short name T613
Test name
Test status
Simulation time 1409138617 ps
CPU time 8.78 seconds
Started Jul 18 06:23:45 PM PDT 24
Finished Jul 18 06:23:56 PM PDT 24
Peak memory 220600 kb
Host smart-ab4d7597-b664-4801-9774-718fd2408f88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2265922566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2265922566
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3988584790
Short name T151
Test name
Test status
Simulation time 6345466100 ps
CPU time 64.27 seconds
Started Jul 18 06:24:10 PM PDT 24
Finished Jul 18 06:25:17 PM PDT 24
Peak memory 271148 kb
Host smart-4dcdc293-1054-4db0-876c-0d231a4ff913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988584790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3988584790
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3280512701
Short name T547
Test name
Test status
Simulation time 9799942890 ps
CPU time 48.96 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:24:33 PM PDT 24
Peak memory 216608 kb
Host smart-4bc692cd-6b4c-40e3-90cd-37de8b287aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280512701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3280512701
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1893622512
Short name T674
Test name
Test status
Simulation time 959244957 ps
CPU time 5.96 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:23:51 PM PDT 24
Peak memory 216716 kb
Host smart-0303d021-ee5a-4517-b118-2d8405596694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893622512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1893622512
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3423107894
Short name T445
Test name
Test status
Simulation time 34793385 ps
CPU time 1.62 seconds
Started Jul 18 06:23:43 PM PDT 24
Finished Jul 18 06:23:47 PM PDT 24
Peak memory 216620 kb
Host smart-9ef6eec8-506b-4740-92ef-882aa80f7062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423107894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3423107894
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.187628311
Short name T157
Test name
Test status
Simulation time 260002171 ps
CPU time 0.84 seconds
Started Jul 18 06:23:42 PM PDT 24
Finished Jul 18 06:23:43 PM PDT 24
Peak memory 206448 kb
Host smart-5ddcdf49-26a5-4015-a7d1-b970cba014ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187628311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.187628311
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3965988058
Short name T756
Test name
Test status
Simulation time 2307126623 ps
CPU time 7.56 seconds
Started Jul 18 06:23:42 PM PDT 24
Finished Jul 18 06:23:51 PM PDT 24
Peak memory 233152 kb
Host smart-bfc98cbe-68cf-448f-912a-76ae0f6474fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965988058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3965988058
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.328163500
Short name T312
Test name
Test status
Simulation time 14254176 ps
CPU time 0.74 seconds
Started Jul 18 06:24:10 PM PDT 24
Finished Jul 18 06:24:13 PM PDT 24
Peak memory 205420 kb
Host smart-e4ffed55-d1af-450a-8d38-bfa15029928d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328163500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.328163500
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2041270476
Short name T177
Test name
Test status
Simulation time 1237035083 ps
CPU time 13.28 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:23 PM PDT 24
Peak memory 224892 kb
Host smart-846149b4-1d4f-44da-ab33-4ea2f027cb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041270476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2041270476
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.491709436
Short name T331
Test name
Test status
Simulation time 42595365 ps
CPU time 0.84 seconds
Started Jul 18 06:24:06 PM PDT 24
Finished Jul 18 06:24:07 PM PDT 24
Peak memory 207084 kb
Host smart-2e09980c-f247-48ce-b167-837f06443b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491709436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.491709436
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3767073466
Short name T485
Test name
Test status
Simulation time 11314063249 ps
CPU time 63.59 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:25:13 PM PDT 24
Peak memory 249852 kb
Host smart-7494d98a-8b41-4121-833d-40e6ecaf6010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767073466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3767073466
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1587894306
Short name T369
Test name
Test status
Simulation time 665236136 ps
CPU time 9.7 seconds
Started Jul 18 06:24:09 PM PDT 24
Finished Jul 18 06:24:21 PM PDT 24
Peak memory 217876 kb
Host smart-508341d4-6fd0-4ddd-a598-79670eb8e5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587894306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1587894306
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.680660768
Short name T603
Test name
Test status
Simulation time 26747746990 ps
CPU time 51.19 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:25:00 PM PDT 24
Peak memory 241424 kb
Host smart-c00e5e32-d19e-40fc-a59e-d00d95e918bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680660768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.680660768
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2990049695
Short name T599
Test name
Test status
Simulation time 93831350 ps
CPU time 3.17 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:14 PM PDT 24
Peak memory 219268 kb
Host smart-ee4a5307-82c8-4353-b84c-d38009180539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990049695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2990049695
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.804116167
Short name T451
Test name
Test status
Simulation time 116445231715 ps
CPU time 128.85 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:26:17 PM PDT 24
Peak memory 249712 kb
Host smart-a6c91037-a421-4ca8-8135-46e7d62859f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804116167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.804116167
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.834858055
Short name T656
Test name
Test status
Simulation time 203077895 ps
CPU time 2.75 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:13 PM PDT 24
Peak memory 233068 kb
Host smart-1807e4d7-f797-42ea-a97c-2fb3419419ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834858055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.834858055
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1047614662
Short name T474
Test name
Test status
Simulation time 1115654089 ps
CPU time 16.8 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:24:25 PM PDT 24
Peak memory 233084 kb
Host smart-e18a0c1f-1998-47e9-9d95-2251d1ae4d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047614662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1047614662
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2132937562
Short name T250
Test name
Test status
Simulation time 8092214569 ps
CPU time 4.12 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:24:13 PM PDT 24
Peak memory 233152 kb
Host smart-1d74f3e4-284f-4800-b166-6e9b02c1a3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132937562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2132937562
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.3615602278
Short name T231
Test name
Test status
Simulation time 8870109123 ps
CPU time 27.99 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:24:36 PM PDT 24
Peak memory 233544 kb
Host smart-002aae12-a059-44b2-9861-58085edb3e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615602278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.3615602278
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3858952096
Short name T437
Test name
Test status
Simulation time 2716291620 ps
CPU time 10.35 seconds
Started Jul 18 06:24:07 PM PDT 24
Finished Jul 18 06:24:19 PM PDT 24
Peak memory 221092 kb
Host smart-d0652c79-7aff-4b70-a9b3-1c5fe6c15417
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3858952096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3858952096
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1365331737
Short name T133
Test name
Test status
Simulation time 41179226940 ps
CPU time 513.47 seconds
Started Jul 18 06:24:09 PM PDT 24
Finished Jul 18 06:32:46 PM PDT 24
Peak memory 298764 kb
Host smart-65fd0925-e265-42a5-a615-702e3b6f5df6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365331737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1365331737
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1872637121
Short name T802
Test name
Test status
Simulation time 2070474464 ps
CPU time 16.41 seconds
Started Jul 18 06:24:06 PM PDT 24
Finished Jul 18 06:24:24 PM PDT 24
Peak memory 216728 kb
Host smart-e2bab5c8-697b-46f4-acb6-166c395f58e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872637121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1872637121
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2360549094
Short name T657
Test name
Test status
Simulation time 861688213 ps
CPU time 6.95 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:18 PM PDT 24
Peak memory 216600 kb
Host smart-37e3f0ac-6a6e-46de-9ce4-f12da641015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360549094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2360549094
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3784634949
Short name T528
Test name
Test status
Simulation time 103879706 ps
CPU time 1.95 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:13 PM PDT 24
Peak memory 216644 kb
Host smart-ff88c225-6f7b-4fe9-a56c-e10ac2186563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784634949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3784634949
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3740134710
Short name T882
Test name
Test status
Simulation time 514777326 ps
CPU time 0.8 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:11 PM PDT 24
Peak memory 206436 kb
Host smart-fcd7b0ff-0b56-49d2-96f5-deaa5d27d5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740134710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3740134710
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2457139342
Short name T830
Test name
Test status
Simulation time 363179779 ps
CPU time 3.6 seconds
Started Jul 18 06:24:06 PM PDT 24
Finished Jul 18 06:24:11 PM PDT 24
Peak memory 233064 kb
Host smart-b19dcd95-9838-468c-af0f-3b2dde3420ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457139342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2457139342
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3499473530
Short name T440
Test name
Test status
Simulation time 208402609 ps
CPU time 0.73 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:29 PM PDT 24
Peak memory 205952 kb
Host smart-722de37e-994a-4a3a-9dc1-162759cba570
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499473530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3499473530
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.4039427501
Short name T787
Test name
Test status
Simulation time 37391196 ps
CPU time 2.38 seconds
Started Jul 18 06:24:11 PM PDT 24
Finished Jul 18 06:24:17 PM PDT 24
Peak memory 233136 kb
Host smart-f0d5395e-9287-4fb7-9997-619e7cb74412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039427501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.4039427501
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2394592411
Short name T655
Test name
Test status
Simulation time 46771793 ps
CPU time 0.77 seconds
Started Jul 18 06:24:10 PM PDT 24
Finished Jul 18 06:24:13 PM PDT 24
Peak memory 207060 kb
Host smart-d3080d7b-f270-4df2-9d45-e27ff1760bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394592411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2394592411
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3564392139
Short name T43
Test name
Test status
Simulation time 387494748273 ps
CPU time 184.73 seconds
Started Jul 18 06:24:09 PM PDT 24
Finished Jul 18 06:27:17 PM PDT 24
Peak memory 249660 kb
Host smart-2dec50b5-ba8f-4873-88b7-1c58b6305b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564392139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3564392139
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1782633615
Short name T764
Test name
Test status
Simulation time 4341117806 ps
CPU time 70.09 seconds
Started Jul 18 06:24:12 PM PDT 24
Finished Jul 18 06:25:26 PM PDT 24
Peak memory 250924 kb
Host smart-1ec20fb2-ebc0-4162-b656-7006597f003d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782633615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1782633615
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2476879677
Short name T282
Test name
Test status
Simulation time 37761492997 ps
CPU time 138.57 seconds
Started Jul 18 06:24:13 PM PDT 24
Finished Jul 18 06:26:35 PM PDT 24
Peak memory 267368 kb
Host smart-57dd8769-5ffd-462d-9477-25ea8453b105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476879677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2476879677
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1197803314
Short name T771
Test name
Test status
Simulation time 774167792 ps
CPU time 6.71 seconds
Started Jul 18 06:24:12 PM PDT 24
Finished Jul 18 06:24:22 PM PDT 24
Peak memory 240228 kb
Host smart-38a9aa97-aa38-42c2-8b2b-0cc3588ac78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197803314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1197803314
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.590971724
Short name T557
Test name
Test status
Simulation time 380104854 ps
CPU time 6.14 seconds
Started Jul 18 06:24:08 PM PDT 24
Finished Jul 18 06:24:16 PM PDT 24
Peak memory 233148 kb
Host smart-e867117b-c0b7-4e67-970b-609f47832b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590971724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.590971724
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3172269874
Short name T478
Test name
Test status
Simulation time 435277329 ps
CPU time 10.05 seconds
Started Jul 18 06:24:09 PM PDT 24
Finished Jul 18 06:24:22 PM PDT 24
Peak memory 240868 kb
Host smart-75615728-39fb-4d9d-b667-8747bad2faa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172269874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3172269874
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2266388288
Short name T997
Test name
Test status
Simulation time 837244044 ps
CPU time 3.08 seconds
Started Jul 18 06:24:11 PM PDT 24
Finished Jul 18 06:24:18 PM PDT 24
Peak memory 224972 kb
Host smart-9a10733a-9160-4222-8a0f-f32103c47fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266388288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2266388288
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3479060745
Short name T563
Test name
Test status
Simulation time 1720704262 ps
CPU time 4.8 seconds
Started Jul 18 06:24:11 PM PDT 24
Finished Jul 18 06:24:20 PM PDT 24
Peak memory 233152 kb
Host smart-9e588059-95fc-4a99-a10b-230c2e140140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479060745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3479060745
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.7288951
Short name T430
Test name
Test status
Simulation time 713572678 ps
CPU time 3.73 seconds
Started Jul 18 06:24:10 PM PDT 24
Finished Jul 18 06:24:18 PM PDT 24
Peak memory 223488 kb
Host smart-f58efb26-dece-4f49-9400-739895372318
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=7288951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.7288951
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.440812895
Short name T366
Test name
Test status
Simulation time 49657092 ps
CPU time 1.06 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:28 PM PDT 24
Peak memory 208148 kb
Host smart-5e928d0f-35d8-4387-835a-1122ca20aee9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440812895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.440812895
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1392630178
Short name T507
Test name
Test status
Simulation time 8716538593 ps
CPU time 12.41 seconds
Started Jul 18 06:24:09 PM PDT 24
Finished Jul 18 06:24:24 PM PDT 24
Peak memory 216724 kb
Host smart-13344154-8308-430a-be1c-5670ec02002c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392630178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1392630178
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1379759953
Short name T553
Test name
Test status
Simulation time 5506036715 ps
CPU time 10.36 seconds
Started Jul 18 06:24:09 PM PDT 24
Finished Jul 18 06:24:22 PM PDT 24
Peak memory 216772 kb
Host smart-f5b53e2f-9e84-4727-9024-9b1a1b156864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379759953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1379759953
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2936631128
Short name T477
Test name
Test status
Simulation time 131199929 ps
CPU time 3.93 seconds
Started Jul 18 06:24:12 PM PDT 24
Finished Jul 18 06:24:19 PM PDT 24
Peak memory 216672 kb
Host smart-bdf6d84d-f18c-4bd1-b791-b41627e7a564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936631128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2936631128
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.976091382
Short name T345
Test name
Test status
Simulation time 914462338 ps
CPU time 0.9 seconds
Started Jul 18 06:24:11 PM PDT 24
Finished Jul 18 06:24:16 PM PDT 24
Peak memory 206448 kb
Host smart-de96def1-c225-4164-958b-77363b116c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976091382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.976091382
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1526920164
Short name T75
Test name
Test status
Simulation time 2881938860 ps
CPU time 7.06 seconds
Started Jul 18 06:24:11 PM PDT 24
Finished Jul 18 06:24:22 PM PDT 24
Peak memory 240808 kb
Host smart-11f6e4a7-c092-4566-a2a2-7ccbf3b9c9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526920164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1526920164
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.72863502
Short name T566
Test name
Test status
Simulation time 12404406 ps
CPU time 0.73 seconds
Started Jul 18 06:24:30 PM PDT 24
Finished Jul 18 06:24:32 PM PDT 24
Peak memory 205312 kb
Host smart-5702ce86-5585-42f1-a62b-9bb1040cd626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72863502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.72863502
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.301788581
Short name T859
Test name
Test status
Simulation time 205996454 ps
CPU time 2.69 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:30 PM PDT 24
Peak memory 224880 kb
Host smart-3a092271-4349-4ba1-a63d-2375cf744e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301788581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.301788581
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3936562946
Short name T54
Test name
Test status
Simulation time 20510055 ps
CPU time 0.74 seconds
Started Jul 18 06:24:32 PM PDT 24
Finished Jul 18 06:24:34 PM PDT 24
Peak memory 206384 kb
Host smart-8e54d1b8-e7b4-400b-a117-52092497964d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936562946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3936562946
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3367969759
Short name T761
Test name
Test status
Simulation time 16939044877 ps
CPU time 129.59 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:26:37 PM PDT 24
Peak memory 257156 kb
Host smart-11e6ccee-d4f6-4c9d-bda8-8b6ca52f236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367969759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3367969759
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.339369400
Short name T193
Test name
Test status
Simulation time 15138074000 ps
CPU time 161.7 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:27:08 PM PDT 24
Peak memory 249928 kb
Host smart-a6b5bb56-f70c-46fc-9e3f-be63c509415c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339369400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.339369400
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.433797704
Short name T203
Test name
Test status
Simulation time 17520549042 ps
CPU time 174.97 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:27:21 PM PDT 24
Peak memory 255292 kb
Host smart-dfabb45b-ab98-455e-b6b0-b32b064fe62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433797704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.433797704
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3469010796
Short name T476
Test name
Test status
Simulation time 5388396152 ps
CPU time 12.74 seconds
Started Jul 18 06:24:29 PM PDT 24
Finished Jul 18 06:24:44 PM PDT 24
Peak memory 239220 kb
Host smart-83ea7c74-67e1-44c3-bfb5-73e099a8d85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469010796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3469010796
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.408261278
Short name T577
Test name
Test status
Simulation time 109791393993 ps
CPU time 191.55 seconds
Started Jul 18 06:24:32 PM PDT 24
Finished Jul 18 06:27:45 PM PDT 24
Peak memory 257788 kb
Host smart-8b3fa04a-1213-493f-9994-8e589bea67da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408261278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.408261278
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2440809246
Short name T861
Test name
Test status
Simulation time 2408362687 ps
CPU time 9.36 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:39 PM PDT 24
Peak memory 225020 kb
Host smart-4f800c24-55e8-4153-afd2-c6d0b21ea80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440809246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2440809246
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3721391239
Short name T638
Test name
Test status
Simulation time 168241135 ps
CPU time 2.72 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:30 PM PDT 24
Peak memory 233140 kb
Host smart-f173c80b-f8f1-4758-b897-deb8eaa7ce50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721391239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3721391239
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2479498253
Short name T417
Test name
Test status
Simulation time 780689194 ps
CPU time 3.13 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:31 PM PDT 24
Peak memory 224964 kb
Host smart-c87201ca-c808-4b4f-b381-9f9122e5210e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479498253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2479498253
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2996076813
Short name T588
Test name
Test status
Simulation time 6976291180 ps
CPU time 13.38 seconds
Started Jul 18 06:24:27 PM PDT 24
Finished Jul 18 06:24:42 PM PDT 24
Peak memory 240988 kb
Host smart-487c301c-59e2-4c09-a345-2917bc7c2cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996076813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2996076813
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.571943474
Short name T740
Test name
Test status
Simulation time 196098621 ps
CPU time 5.49 seconds
Started Jul 18 06:24:26 PM PDT 24
Finished Jul 18 06:24:33 PM PDT 24
Peak memory 223520 kb
Host smart-4d323453-c927-4018-9448-8e9f50d3d840
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=571943474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.571943474
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3734894514
Short name T777
Test name
Test status
Simulation time 2026826696 ps
CPU time 11.23 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:41 PM PDT 24
Peak memory 216716 kb
Host smart-612f1991-ace8-4b24-897f-57ac9b423e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734894514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3734894514
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.2149969417
Short name T374
Test name
Test status
Simulation time 1102426427 ps
CPU time 2.42 seconds
Started Jul 18 06:24:33 PM PDT 24
Finished Jul 18 06:24:36 PM PDT 24
Peak memory 216652 kb
Host smart-a2e31ee1-ad4c-4b6b-94ff-87c2a228399d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149969417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.2149969417
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.273285803
Short name T880
Test name
Test status
Simulation time 1006235399 ps
CPU time 2.83 seconds
Started Jul 18 06:24:25 PM PDT 24
Finished Jul 18 06:24:29 PM PDT 24
Peak memory 216720 kb
Host smart-720d6380-a4d6-49a4-84b9-6184a868991d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273285803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.273285803
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3936365860
Short name T863
Test name
Test status
Simulation time 15774898 ps
CPU time 0.71 seconds
Started Jul 18 06:24:25 PM PDT 24
Finished Jul 18 06:24:26 PM PDT 24
Peak memory 206452 kb
Host smart-638af916-089b-42b5-80c3-d27176434efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936365860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3936365860
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2984633263
Short name T228
Test name
Test status
Simulation time 67851520130 ps
CPU time 13.28 seconds
Started Jul 18 06:24:28 PM PDT 24
Finished Jul 18 06:24:43 PM PDT 24
Peak memory 224944 kb
Host smart-39cd54f9-b0b8-4218-aef6-89f91d4945d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984633263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2984633263
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3513362698
Short name T925
Test name
Test status
Simulation time 22085507 ps
CPU time 0.72 seconds
Started Jul 18 06:17:03 PM PDT 24
Finished Jul 18 06:17:04 PM PDT 24
Peak memory 206052 kb
Host smart-88c6588b-3f07-43c5-944d-975baf5f75f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513362698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
513362698
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3714389586
Short name T699
Test name
Test status
Simulation time 77242653 ps
CPU time 2.46 seconds
Started Jul 18 06:17:06 PM PDT 24
Finished Jul 18 06:17:10 PM PDT 24
Peak memory 224920 kb
Host smart-75e06498-b539-48ae-be83-e9ab09fb7e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714389586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3714389586
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.893109178
Short name T555
Test name
Test status
Simulation time 14857279 ps
CPU time 0.78 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:16:51 PM PDT 24
Peak memory 207088 kb
Host smart-74349a81-76c5-489a-afdf-739ab50e6a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893109178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.893109178
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3270751561
Short name T630
Test name
Test status
Simulation time 199763308 ps
CPU time 0.92 seconds
Started Jul 18 06:17:05 PM PDT 24
Finished Jul 18 06:17:07 PM PDT 24
Peak memory 216368 kb
Host smart-edb69291-f3af-4c8e-a4d3-f46a6e35b76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270751561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3270751561
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.498438177
Short name T27
Test name
Test status
Simulation time 41625582747 ps
CPU time 204.65 seconds
Started Jul 18 06:17:06 PM PDT 24
Finished Jul 18 06:20:32 PM PDT 24
Peak memory 262400 kb
Host smart-59939841-19bd-4293-ab34-0f8c4c8369d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498438177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.498438177
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.3685103504
Short name T377
Test name
Test status
Simulation time 9319245831 ps
CPU time 78.86 seconds
Started Jul 18 06:17:06 PM PDT 24
Finished Jul 18 06:18:26 PM PDT 24
Peak memory 241448 kb
Host smart-3ad54d3f-14e6-406c-afb8-5acbf75bdae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685103504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.3685103504
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2442353435
Short name T641
Test name
Test status
Simulation time 400388319 ps
CPU time 3.26 seconds
Started Jul 18 06:17:05 PM PDT 24
Finished Jul 18 06:17:10 PM PDT 24
Peak memory 233008 kb
Host smart-5ff184d5-4788-4e38-bee5-d5029177d532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442353435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2442353435
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1504508771
Short name T469
Test name
Test status
Simulation time 3600540252 ps
CPU time 20.35 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:31 PM PDT 24
Peak memory 254984 kb
Host smart-1240f456-8a38-4f7a-8e63-89b543d22aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504508771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1504508771
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3465725417
Short name T583
Test name
Test status
Simulation time 3233035744 ps
CPU time 14.05 seconds
Started Jul 18 06:17:04 PM PDT 24
Finished Jul 18 06:17:20 PM PDT 24
Peak memory 225088 kb
Host smart-8f0f03d4-c739-43b1-952a-ddb6cb185ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465725417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3465725417
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1410040713
Short name T497
Test name
Test status
Simulation time 368744720 ps
CPU time 4.65 seconds
Started Jul 18 06:16:47 PM PDT 24
Finished Jul 18 06:16:54 PM PDT 24
Peak memory 233076 kb
Host smart-9dcc2ba5-c00f-4306-9d52-cfe1bd2bb1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410040713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1410040713
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3284258936
Short name T205
Test name
Test status
Simulation time 18260466005 ps
CPU time 13.08 seconds
Started Jul 18 06:16:49 PM PDT 24
Finished Jul 18 06:17:05 PM PDT 24
Peak memory 240000 kb
Host smart-81921d86-5c70-46cb-961b-46b94c1c39b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284258936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3284258936
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1895253694
Short name T601
Test name
Test status
Simulation time 967352063 ps
CPU time 6.39 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:18 PM PDT 24
Peak memory 223492 kb
Host smart-32e6d10a-d9fc-4ef0-bfd6-55cfd6250a36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1895253694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1895253694
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2461540124
Short name T796
Test name
Test status
Simulation time 509369416361 ps
CPU time 999.5 seconds
Started Jul 18 06:17:04 PM PDT 24
Finished Jul 18 06:33:45 PM PDT 24
Peak memory 281720 kb
Host smart-af39609e-9cb3-4e69-bbd2-494ede08bc4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461540124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2461540124
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3461456503
Short name T324
Test name
Test status
Simulation time 1082508401 ps
CPU time 4.03 seconds
Started Jul 18 06:16:51 PM PDT 24
Finished Jul 18 06:16:58 PM PDT 24
Peak memory 216880 kb
Host smart-469e5c54-7d38-4b9e-aa52-b4fcb7b44284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461456503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3461456503
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.1204637040
Short name T842
Test name
Test status
Simulation time 250700086 ps
CPU time 1.89 seconds
Started Jul 18 06:16:48 PM PDT 24
Finished Jul 18 06:16:53 PM PDT 24
Peak memory 216548 kb
Host smart-29642cb0-5aaa-4f4c-ad07-0e3f7355962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204637040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.1204637040
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4081218499
Short name T779
Test name
Test status
Simulation time 70150206 ps
CPU time 1.12 seconds
Started Jul 18 06:20:50 PM PDT 24
Finished Jul 18 06:20:51 PM PDT 24
Peak memory 208352 kb
Host smart-d4a3e25a-fe8e-488f-8ff3-9e8224fb2dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081218499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4081218499
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.340397803
Short name T651
Test name
Test status
Simulation time 118868754 ps
CPU time 0.84 seconds
Started Jul 18 06:16:54 PM PDT 24
Finished Jul 18 06:16:56 PM PDT 24
Peak memory 206392 kb
Host smart-d71d4cb4-95f5-4b91-954f-256b2bbb2ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340397803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.340397803
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3225234243
Short name T548
Test name
Test status
Simulation time 2328242719 ps
CPU time 6.24 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:18 PM PDT 24
Peak memory 233244 kb
Host smart-c592061d-cb3b-4910-b8e7-dfe0b6f33507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225234243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3225234243
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2211738818
Short name T586
Test name
Test status
Simulation time 61606274 ps
CPU time 0.74 seconds
Started Jul 18 06:17:25 PM PDT 24
Finished Jul 18 06:17:27 PM PDT 24
Peak memory 205952 kb
Host smart-9a36c647-f3d2-4bad-aba6-cfb216219b45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211738818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
211738818
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2118702643
Short name T230
Test name
Test status
Simulation time 3380906441 ps
CPU time 8.08 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:19 PM PDT 24
Peak memory 225020 kb
Host smart-8c653395-0255-4450-a7e4-e28068cb8cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118702643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2118702643
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3617119586
Short name T639
Test name
Test status
Simulation time 19134414 ps
CPU time 0.81 seconds
Started Jul 18 06:17:04 PM PDT 24
Finished Jul 18 06:17:06 PM PDT 24
Peak memory 207104 kb
Host smart-3cc01472-b1d7-4c0a-9057-ed8708413fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617119586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3617119586
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.700396320
Short name T851
Test name
Test status
Simulation time 37720025264 ps
CPU time 198.56 seconds
Started Jul 18 06:17:09 PM PDT 24
Finished Jul 18 06:20:29 PM PDT 24
Peak memory 256348 kb
Host smart-0da36116-eb78-4c7e-b01e-9865d129d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700396320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.700396320
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.2254760094
Short name T879
Test name
Test status
Simulation time 12392173667 ps
CPU time 83.81 seconds
Started Jul 18 06:17:05 PM PDT 24
Finished Jul 18 06:18:31 PM PDT 24
Peak memory 257240 kb
Host smart-f1d34e9d-714e-41b3-9d88-485c8e6ef552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254760094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2254760094
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.1646065813
Short name T113
Test name
Test status
Simulation time 39413067249 ps
CPU time 131.94 seconds
Started Jul 18 06:17:05 PM PDT 24
Finished Jul 18 06:19:18 PM PDT 24
Peak memory 250588 kb
Host smart-143a8677-79e9-425c-be62-812f54ac15ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646065813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.1646065813
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.4283376999
Short name T141
Test name
Test status
Simulation time 646655393 ps
CPU time 16.66 seconds
Started Jul 18 06:17:05 PM PDT 24
Finished Jul 18 06:17:23 PM PDT 24
Peak memory 224976 kb
Host smart-5b4b562a-2028-44ef-91f5-91c6172a88b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283376999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.4283376999
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4228191513
Short name T241
Test name
Test status
Simulation time 13577904772 ps
CPU time 152.11 seconds
Started Jul 18 06:17:06 PM PDT 24
Finished Jul 18 06:19:39 PM PDT 24
Peak memory 266652 kb
Host smart-18ef329a-6264-42a0-b4db-e1eabe871e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228191513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4228191513
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3857267067
Short name T145
Test name
Test status
Simulation time 66488940 ps
CPU time 2.58 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:13 PM PDT 24
Peak memory 224912 kb
Host smart-7a771aee-6818-432e-af35-e4b497aaed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857267067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3857267067
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.388683795
Short name T845
Test name
Test status
Simulation time 1591626653 ps
CPU time 8.04 seconds
Started Jul 18 06:17:03 PM PDT 24
Finished Jul 18 06:17:12 PM PDT 24
Peak memory 225048 kb
Host smart-e2dc5d9e-d867-4c37-b8ff-0e145db7108e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388683795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.388683795
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3422642900
Short name T1003
Test name
Test status
Simulation time 486165514 ps
CPU time 3.03 seconds
Started Jul 18 06:17:10 PM PDT 24
Finished Jul 18 06:17:14 PM PDT 24
Peak memory 224956 kb
Host smart-e353e13d-edd4-4bf6-9c15-7781de87bfa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422642900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3422642900
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.893796206
Short name T744
Test name
Test status
Simulation time 12281655565 ps
CPU time 10.65 seconds
Started Jul 18 06:17:09 PM PDT 24
Finished Jul 18 06:17:20 PM PDT 24
Peak memory 224988 kb
Host smart-155e2f3e-80b4-495d-aa17-07e151eab012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893796206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.893796206
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1298065833
Short name T388
Test name
Test status
Simulation time 4754365067 ps
CPU time 15.97 seconds
Started Jul 18 06:17:04 PM PDT 24
Finished Jul 18 06:17:21 PM PDT 24
Peak memory 222052 kb
Host smart-6f0eb623-344d-4c58-910a-8adf9105c0fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1298065833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1298065833
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1526089943
Short name T405
Test name
Test status
Simulation time 1574762220 ps
CPU time 7.36 seconds
Started Jul 18 06:17:08 PM PDT 24
Finished Jul 18 06:17:16 PM PDT 24
Peak memory 217064 kb
Host smart-6409ac3f-98f2-4459-a142-d04fa761f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526089943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1526089943
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.647179110
Short name T894
Test name
Test status
Simulation time 361842882 ps
CPU time 2.23 seconds
Started Jul 18 06:17:09 PM PDT 24
Finished Jul 18 06:17:12 PM PDT 24
Peak memory 216576 kb
Host smart-d509e1b9-9461-4a1b-b0f1-bf12230e8009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647179110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.647179110
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3190739117
Short name T606
Test name
Test status
Simulation time 327538726 ps
CPU time 4.29 seconds
Started Jul 18 06:17:09 PM PDT 24
Finished Jul 18 06:17:15 PM PDT 24
Peak memory 216728 kb
Host smart-56ffd116-70ca-4e67-8835-958ab6956220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190739117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3190739117
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.1081362972
Short name T86
Test name
Test status
Simulation time 31346396 ps
CPU time 0.81 seconds
Started Jul 18 06:17:04 PM PDT 24
Finished Jul 18 06:17:07 PM PDT 24
Peak memory 206460 kb
Host smart-6ee0bc3c-a87a-465f-a743-6b2c471afe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081362972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1081362972
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1590723871
Short name T504
Test name
Test status
Simulation time 2292102770 ps
CPU time 15.1 seconds
Started Jul 18 06:17:05 PM PDT 24
Finished Jul 18 06:17:21 PM PDT 24
Peak memory 234240 kb
Host smart-5387a2f7-8257-43b4-ae8a-9ef8b69adcda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590723871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1590723871
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.1966620383
Short name T774
Test name
Test status
Simulation time 74855790 ps
CPU time 0.73 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:51 PM PDT 24
Peak memory 205368 kb
Host smart-ce137694-0432-45e7-9fff-b38dee831a6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966620383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.1
966620383
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3730849174
Short name T632
Test name
Test status
Simulation time 64615419 ps
CPU time 3.21 seconds
Started Jul 18 06:17:24 PM PDT 24
Finished Jul 18 06:17:28 PM PDT 24
Peak memory 233136 kb
Host smart-917faffe-c263-479b-a25f-399eb90fef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730849174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3730849174
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.236427203
Short name T873
Test name
Test status
Simulation time 48676947 ps
CPU time 0.75 seconds
Started Jul 18 06:17:26 PM PDT 24
Finished Jul 18 06:17:27 PM PDT 24
Peak memory 206036 kb
Host smart-ad937426-f34e-454b-bfc2-30aac37b33e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236427203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.236427203
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3104540406
Short name T748
Test name
Test status
Simulation time 1971984823 ps
CPU time 11.09 seconds
Started Jul 18 06:17:40 PM PDT 24
Finished Jul 18 06:17:52 PM PDT 24
Peak memory 241328 kb
Host smart-5bece859-e3ef-452d-b98d-4ebab99b96a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104540406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3104540406
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2861004546
Short name T998
Test name
Test status
Simulation time 3230979395 ps
CPU time 66.85 seconds
Started Jul 18 06:17:42 PM PDT 24
Finished Jul 18 06:18:51 PM PDT 24
Peak memory 256328 kb
Host smart-9565ad77-bf45-4592-94a0-723ae3ef6351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861004546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2861004546
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.141071871
Short name T254
Test name
Test status
Simulation time 19765534151 ps
CPU time 192.55 seconds
Started Jul 18 06:17:42 PM PDT 24
Finished Jul 18 06:20:56 PM PDT 24
Peak memory 257564 kb
Host smart-22a7c202-8bf8-4166-8fb4-92a98dd97b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141071871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
141071871
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1519297354
Short name T659
Test name
Test status
Simulation time 206504536 ps
CPU time 6.1 seconds
Started Jul 18 06:17:27 PM PDT 24
Finished Jul 18 06:17:35 PM PDT 24
Peak memory 235448 kb
Host smart-c7df8f7f-dfac-472f-b62a-b79b480ad1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519297354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1519297354
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.4225690604
Short name T820
Test name
Test status
Simulation time 186935471743 ps
CPU time 516.55 seconds
Started Jul 18 06:17:49 PM PDT 24
Finished Jul 18 06:26:27 PM PDT 24
Peak memory 264272 kb
Host smart-163668de-fc43-4308-9be9-765d2d2cbb21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225690604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.4225690604
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3748459001
Short name T975
Test name
Test status
Simulation time 434250189 ps
CPU time 2.45 seconds
Started Jul 18 06:17:24 PM PDT 24
Finished Jul 18 06:17:28 PM PDT 24
Peak memory 219264 kb
Host smart-a484ebaa-88e3-4161-b094-aa854a4c2129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748459001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3748459001
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.408774834
Short name T743
Test name
Test status
Simulation time 515922774 ps
CPU time 13.08 seconds
Started Jul 18 06:17:26 PM PDT 24
Finished Jul 18 06:17:40 PM PDT 24
Peak memory 241296 kb
Host smart-722cfec3-39c3-4d5f-9597-2f4a14af375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408774834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.408774834
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1459389920
Short name T248
Test name
Test status
Simulation time 414906720 ps
CPU time 3.15 seconds
Started Jul 18 06:17:27 PM PDT 24
Finished Jul 18 06:17:31 PM PDT 24
Peak memory 233096 kb
Host smart-21e80975-ff22-4d13-8d80-f0eddbe7cc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459389920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1459389920
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.370164195
Short name T965
Test name
Test status
Simulation time 227900014 ps
CPU time 4.71 seconds
Started Jul 18 06:17:25 PM PDT 24
Finished Jul 18 06:17:31 PM PDT 24
Peak memory 234184 kb
Host smart-771e2d00-f51f-4e44-abe9-25405b2202cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370164195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.370164195
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.75226781
Short name T885
Test name
Test status
Simulation time 2238241120 ps
CPU time 5.94 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:55 PM PDT 24
Peak memory 223700 kb
Host smart-fea7f15f-14b8-4171-8f72-fb47dcb9b1e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75226781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct
.75226781
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3822898438
Short name T420
Test name
Test status
Simulation time 4283471035 ps
CPU time 27.13 seconds
Started Jul 18 06:17:25 PM PDT 24
Finished Jul 18 06:17:53 PM PDT 24
Peak memory 216712 kb
Host smart-d5d24acc-ebed-457e-b2b5-3103a309dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822898438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3822898438
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3921717749
Short name T621
Test name
Test status
Simulation time 19827960466 ps
CPU time 12.94 seconds
Started Jul 18 06:17:33 PM PDT 24
Finished Jul 18 06:17:47 PM PDT 24
Peak memory 216724 kb
Host smart-22c599f0-ae57-4099-952b-848091e98faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921717749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3921717749
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3847963395
Short name T421
Test name
Test status
Simulation time 19121399 ps
CPU time 0.7 seconds
Started Jul 18 06:17:25 PM PDT 24
Finished Jul 18 06:17:26 PM PDT 24
Peak memory 206124 kb
Host smart-94c28bf4-27fb-4641-b8da-bb2bbc2081cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847963395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3847963395
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.40592637
Short name T913
Test name
Test status
Simulation time 258532121 ps
CPU time 0.85 seconds
Started Jul 18 06:17:24 PM PDT 24
Finished Jul 18 06:17:25 PM PDT 24
Peak memory 206616 kb
Host smart-18b94c0f-d48a-489b-bb50-aaf7d2a4ebb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40592637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.40592637
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2168492018
Short name T874
Test name
Test status
Simulation time 368747717 ps
CPU time 3.25 seconds
Started Jul 18 06:17:27 PM PDT 24
Finished Jul 18 06:17:32 PM PDT 24
Peak memory 233120 kb
Host smart-caac3ec2-0c62-45b1-af8a-d6accfef81ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168492018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2168492018
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.971065131
Short name T989
Test name
Test status
Simulation time 53080498 ps
CPU time 0.74 seconds
Started Jul 18 06:17:43 PM PDT 24
Finished Jul 18 06:17:45 PM PDT 24
Peak memory 206264 kb
Host smart-0b3d67a4-06ef-4f36-baa5-4b38014ef827
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971065131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.971065131
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1451557014
Short name T79
Test name
Test status
Simulation time 437422912 ps
CPU time 3.82 seconds
Started Jul 18 06:17:49 PM PDT 24
Finished Jul 18 06:17:55 PM PDT 24
Peak memory 233176 kb
Host smart-184daa4d-c29e-415a-abdc-c1763517b83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451557014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1451557014
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1485177526
Short name T538
Test name
Test status
Simulation time 29953687 ps
CPU time 0.73 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:51 PM PDT 24
Peak memory 206388 kb
Host smart-c2f89664-8fa1-4c69-a991-a0175d534785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485177526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1485177526
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.940147695
Short name T712
Test name
Test status
Simulation time 13651976617 ps
CPU time 62.63 seconds
Started Jul 18 06:17:47 PM PDT 24
Finished Jul 18 06:18:51 PM PDT 24
Peak memory 249616 kb
Host smart-18e2184d-1c63-4547-8a28-5b7de4276b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940147695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.940147695
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2936938996
Short name T233
Test name
Test status
Simulation time 101981636743 ps
CPU time 234.12 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:21:45 PM PDT 24
Peak memory 241460 kb
Host smart-7f49eda1-49dd-40c7-9b54-2aa73d36b1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936938996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2936938996
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1541930837
Short name T262
Test name
Test status
Simulation time 40003544393 ps
CPU time 104.98 seconds
Started Jul 18 06:17:44 PM PDT 24
Finished Jul 18 06:19:30 PM PDT 24
Peak memory 249652 kb
Host smart-d9f058d8-95a0-4b5b-b2be-dddd9feaae29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541930837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1541930837
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.746006881
Short name T320
Test name
Test status
Simulation time 3426232313 ps
CPU time 37.19 seconds
Started Jul 18 06:17:41 PM PDT 24
Finished Jul 18 06:18:20 PM PDT 24
Peak memory 233224 kb
Host smart-7734c6f3-5f00-4220-be50-49227d368489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746006881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.746006881
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1760095818
Short name T227
Test name
Test status
Simulation time 6067089866 ps
CPU time 60.05 seconds
Started Jul 18 06:17:43 PM PDT 24
Finished Jul 18 06:18:45 PM PDT 24
Peak memory 251676 kb
Host smart-4edaa719-34e3-4207-8a61-5671815f96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760095818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1760095818
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.468338627
Short name T383
Test name
Test status
Simulation time 3586937327 ps
CPU time 13.44 seconds
Started Jul 18 06:17:40 PM PDT 24
Finished Jul 18 06:17:55 PM PDT 24
Peak memory 233224 kb
Host smart-56744689-c238-4f3d-a0f7-0ff3c221e2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468338627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.468338627
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2856640445
Short name T966
Test name
Test status
Simulation time 421768501 ps
CPU time 2.52 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:53 PM PDT 24
Peak memory 223504 kb
Host smart-fda08b3c-5b2b-4266-8faa-aea7c3107811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856640445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2856640445
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.233234298
Short name T709
Test name
Test status
Simulation time 21500372721 ps
CPU time 16.22 seconds
Started Jul 18 06:17:47 PM PDT 24
Finished Jul 18 06:18:05 PM PDT 24
Peak memory 233064 kb
Host smart-ffd356bf-69b0-4bd9-bdd7-b0105813383e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233234298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
233234298
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.783608806
Short name T526
Test name
Test status
Simulation time 4398461549 ps
CPU time 12.7 seconds
Started Jul 18 06:17:49 PM PDT 24
Finished Jul 18 06:18:04 PM PDT 24
Peak memory 225024 kb
Host smart-4ce9d7a4-37fc-42a6-ad38-8ae758466488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783608806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.783608806
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1782713289
Short name T631
Test name
Test status
Simulation time 3069456734 ps
CPU time 9.89 seconds
Started Jul 18 06:17:41 PM PDT 24
Finished Jul 18 06:17:52 PM PDT 24
Peak memory 222860 kb
Host smart-6293973c-a104-4bdf-9245-70738d3f5d52
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1782713289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1782713289
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.508197295
Short name T38
Test name
Test status
Simulation time 5370777783 ps
CPU time 26.89 seconds
Started Jul 18 06:17:41 PM PDT 24
Finished Jul 18 06:18:10 PM PDT 24
Peak memory 216740 kb
Host smart-ddecdd61-5e03-4c83-a4ab-a9416d23f4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508197295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.508197295
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3654002748
Short name T884
Test name
Test status
Simulation time 2267978664 ps
CPU time 3.74 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:54 PM PDT 24
Peak memory 216764 kb
Host smart-cc8076da-95b2-4d43-a820-802768a2fed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654002748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3654002748
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1522080350
Short name T815
Test name
Test status
Simulation time 1112505223 ps
CPU time 8.73 seconds
Started Jul 18 06:17:43 PM PDT 24
Finished Jul 18 06:17:53 PM PDT 24
Peak memory 216672 kb
Host smart-e501f802-2a39-473d-a711-f1b135dfa920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522080350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1522080350
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2583216473
Short name T665
Test name
Test status
Simulation time 185982813 ps
CPU time 0.89 seconds
Started Jul 18 06:17:43 PM PDT 24
Finished Jul 18 06:17:45 PM PDT 24
Peak memory 206452 kb
Host smart-e0bcf94c-4bfd-45e5-a9b1-e90876c4e891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583216473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2583216473
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1181550549
Short name T627
Test name
Test status
Simulation time 409288351 ps
CPU time 2.35 seconds
Started Jul 18 06:17:41 PM PDT 24
Finished Jul 18 06:17:45 PM PDT 24
Peak memory 224596 kb
Host smart-5ac9d12a-ab61-4741-a235-7b80593cfbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181550549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1181550549
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2168706780
Short name T486
Test name
Test status
Simulation time 94167392 ps
CPU time 0.69 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:18:22 PM PDT 24
Peak memory 205916 kb
Host smart-07459bfb-f1da-4b66-ae9a-b1c4e3406e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168706780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
168706780
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2965346890
Short name T691
Test name
Test status
Simulation time 837796497 ps
CPU time 11.71 seconds
Started Jul 18 06:18:18 PM PDT 24
Finished Jul 18 06:18:32 PM PDT 24
Peak memory 233096 kb
Host smart-fb52a3c9-aa4f-4801-b3b6-ec82a2db8aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965346890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2965346890
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2341704358
Short name T623
Test name
Test status
Simulation time 26899749 ps
CPU time 0.77 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:52 PM PDT 24
Peak memory 206028 kb
Host smart-71ffae09-145b-4fe7-87e4-0d576fd27125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341704358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2341704358
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2988825745
Short name T841
Test name
Test status
Simulation time 14930207452 ps
CPU time 21.61 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:18:44 PM PDT 24
Peak memory 225056 kb
Host smart-c90c87dd-7090-4e43-b4a2-f352e8baed9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988825745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2988825745
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.3488552163
Short name T299
Test name
Test status
Simulation time 18364360894 ps
CPU time 43.34 seconds
Started Jul 18 06:18:19 PM PDT 24
Finished Jul 18 06:19:05 PM PDT 24
Peak memory 225044 kb
Host smart-e0454e10-d1ae-4873-af37-9d5f92834604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488552163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3488552163
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.398275008
Short name T266
Test name
Test status
Simulation time 5062383431 ps
CPU time 34.54 seconds
Started Jul 18 06:18:23 PM PDT 24
Finished Jul 18 06:19:03 PM PDT 24
Peak memory 249424 kb
Host smart-5479b37c-5d50-49c6-aefa-2c6345b750c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398275008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
398275008
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3812757587
Short name T452
Test name
Test status
Simulation time 823657305 ps
CPU time 15.3 seconds
Started Jul 18 06:18:18 PM PDT 24
Finished Jul 18 06:18:36 PM PDT 24
Peak memory 234140 kb
Host smart-151059be-eb9f-426c-a0e1-69fb65f874b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812757587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3812757587
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2972630543
Short name T90
Test name
Test status
Simulation time 3985805692 ps
CPU time 8.97 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:32 PM PDT 24
Peak memory 234968 kb
Host smart-a327d1ff-fa44-47fa-a5ab-bfb283baf601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972630543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2972630543
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.609952950
Short name T822
Test name
Test status
Simulation time 652254926 ps
CPU time 5.72 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:17:56 PM PDT 24
Peak memory 224900 kb
Host smart-517b80ae-8e75-48e2-a18b-160d1ead98e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609952950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.609952950
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3478608742
Short name T626
Test name
Test status
Simulation time 10006168920 ps
CPU time 34.83 seconds
Started Jul 18 06:17:48 PM PDT 24
Finished Jul 18 06:18:26 PM PDT 24
Peak memory 233172 kb
Host smart-3d44bedb-1e14-4710-892d-c23a4c5b18da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478608742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3478608742
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2496124266
Short name T223
Test name
Test status
Simulation time 680149607 ps
CPU time 9.24 seconds
Started Jul 18 06:17:49 PM PDT 24
Finished Jul 18 06:18:00 PM PDT 24
Peak memory 224956 kb
Host smart-4b1df0a7-c902-4de8-ada2-35263365c650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496124266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2496124266
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2691238162
Short name T522
Test name
Test status
Simulation time 117934847 ps
CPU time 4.57 seconds
Started Jul 18 06:18:17 PM PDT 24
Finished Jul 18 06:18:23 PM PDT 24
Peak memory 222512 kb
Host smart-e2f7c08b-a884-4faa-bed0-7b130059810f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2691238162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2691238162
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3593515439
Short name T732
Test name
Test status
Simulation time 12292375877 ps
CPU time 25.38 seconds
Started Jul 18 06:18:50 PM PDT 24
Finished Jul 18 06:19:17 PM PDT 24
Peak memory 249684 kb
Host smart-868647f9-b8a4-454e-83f5-8869870724be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593515439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3593515439
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2560301257
Short name T569
Test name
Test status
Simulation time 2753864530 ps
CPU time 18.79 seconds
Started Jul 18 06:17:40 PM PDT 24
Finished Jul 18 06:18:00 PM PDT 24
Peak memory 216724 kb
Host smart-190380e0-af85-4ec1-b85f-f4fd4ccad2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560301257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2560301257
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.670841325
Short name T339
Test name
Test status
Simulation time 6578588842 ps
CPU time 18.4 seconds
Started Jul 18 06:17:47 PM PDT 24
Finished Jul 18 06:18:06 PM PDT 24
Peak memory 216772 kb
Host smart-312da3ef-1df0-49ab-934d-09a4818b9924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670841325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.670841325
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3283087717
Short name T25
Test name
Test status
Simulation time 1006611225 ps
CPU time 2.05 seconds
Started Jul 18 06:17:44 PM PDT 24
Finished Jul 18 06:17:47 PM PDT 24
Peak memory 216724 kb
Host smart-32846bdb-5b6f-4868-8cc0-f7a444595817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283087717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3283087717
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1324752966
Short name T770
Test name
Test status
Simulation time 372494073 ps
CPU time 0.89 seconds
Started Jul 18 06:17:41 PM PDT 24
Finished Jul 18 06:17:44 PM PDT 24
Peak memory 207472 kb
Host smart-b611d578-8fff-42d9-ad62-270da0daa28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324752966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1324752966
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1996765079
Short name T542
Test name
Test status
Simulation time 4047180403 ps
CPU time 11.36 seconds
Started Jul 18 06:18:20 PM PDT 24
Finished Jul 18 06:18:36 PM PDT 24
Peak memory 236784 kb
Host smart-2ffcfd34-43c4-4959-a1df-b66257b9f0bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996765079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1996765079
Directory /workspace/9.spi_device_upload/latest
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