Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2609858	1			T1	4136		T4	1		T5	1
all_values[1]	2609858	1			T1	4136		T4	1		T5	1
all_values[2]	2609858	1			T1	4136		T4	1		T5	1
all_values[3]	2609858	1			T1	4136		T4	1		T5	1
all_values[4]	2609858	1			T1	4136		T4	1		T5	1
all_values[5]	2609858	1			T1	4136		T4	1		T5	1
all_values[6]	2609858	1			T1	4136		T4	1		T5	1
all_values[7]	2609858	1			T1	4136		T4	1		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20645032

1

T1

33088

T4

8

T5

8

auto[1]

233832

1

T6

34086

T11

35

T19

84

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20856549

1

T1

33088

T4

8

T5

8

auto[1]

22315

1

T6

112

T9

303

T10

52

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2580966	1			T1	4136		T4	1		T5	1
all_values[0]	auto[0]	auto[1]	10234	1			T6	31		T9	186		T10	42
all_values[0]	auto[1]	auto[0]	18267	1			T6	9		T11	1		T19	6
all_values[0]	auto[1]	auto[1]	391	1			T6	5		T11	4		T19	7
all_values[1]	auto[0]	auto[0]	2575311	1			T1	4136		T4	1		T5	1
all_values[1]	auto[0]	auto[1]	6883	1			T6	9		T9	73		T10	10
all_values[1]	auto[1]	auto[0]	27383	1			T6	11331		T11	5		T19	6
all_values[1]	auto[1]	auto[1]	281	1			T6	7		T11	3		T19	8
all_values[2]	auto[0]	auto[0]	2580051	1			T1	4136		T4	1		T5	1
all_values[2]	auto[0]	auto[1]	2339	1			T6	3		T9	44		T11	3
all_values[2]	auto[1]	auto[0]	27252	1			T6	11338		T19	9		T20	11
all_values[2]	auto[1]	auto[1]	216	1			T6	6		T11	1		T19	4
all_values[3]	auto[0]	auto[0]	2600262	1			T1	4136		T4	1		T5	1
all_values[3]	auto[0]	auto[1]	206	1			T6	7		T11	3		T19	5
all_values[3]	auto[1]	auto[0]	9194	1			T6	8		T11	6		T19	5
all_values[3]	auto[1]	auto[1]	196	1			T6	7		T19	3		T20	9
all_values[4]	auto[0]	auto[0]	2583524	1			T1	4136		T4	1		T5	1
all_values[4]	auto[0]	auto[1]	219	1			T6	5		T11	3		T19	5
all_values[4]	auto[1]	auto[0]	25928	1			T6	8		T11	5		T19	5
all_values[4]	auto[1]	auto[1]	187	1			T6	5		T19	1		T20	5
all_values[5]	auto[0]	auto[0]	2547940	1			T1	4136		T4	1		T5	1
all_values[5]	auto[0]	auto[1]	171	1			T6	3		T11	1		T19	5
all_values[5]	auto[1]	auto[0]	61559	1			T6	11337		T11	3		T19	9
all_values[5]	auto[1]	auto[1]	188	1			T6	6		T11	1		T19	3
all_values[6]	auto[0]	auto[0]	2555164	1			T1	4136		T4	1		T5	1
all_values[6]	auto[0]	auto[1]	214	1			T6	8		T11	4		T19	5
all_values[6]	auto[1]	auto[0]	54272	1			T6	3		T11	3		T19	5
all_values[6]	auto[1]	auto[1]	208	1			T6	4		T11	1		T19	6
all_values[7]	auto[0]	auto[0]	2601355	1			T1	4136		T4	1		T5	1
all_values[7]	auto[0]	auto[1]	193	1			T6	5		T11	3		T19	2
all_values[7]	auto[1]	auto[0]	8121	1			T6	11		T11	2		T19	5
all_values[7]	auto[1]	auto[1]	189	1			T6	1		T19	2		T20	3