Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
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Group : spi_device_env_pkg::spi_device_env_cov::all_modes_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
72.73 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv


Summary for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 5 1 4 80.00
Crosses 6 2 4 66.67


Variables for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 1 2 66.67 100 1 1 0
cp_tpm_enabled 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::all_modes_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 6 2 4 66.67 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 3 1 2 66.67


Automatically Generated Bins for cp_mode

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[DisabledMode] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashMode] 71834 1 T1 209 T10 443 T14 200
auto[PassthroughMode] 51678 1 T6 410 T9 375 T15 634


Summary for Variable cp_tpm_enabled

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_tpm_enabled

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 29699 1 T17 10 T32 20 T38 280
auto[1] 93813 1 T1 209 T6 410 T9 375


Summary for Cross cr_all

Samples crossed: cp_mode cp_tpm_enabled
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 6 2 4 66.67 2


Automatically Generated Cross Bins for cr_all

Element holes
cp_modecp_tpm_enabledCOUNTAT LEASTNUMBERSTATUS
[auto[DisabledMode]] * -- -- 2


Covered bins
cp_modecp_tpm_enabledCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[FlashMode] auto[0] 12801 1 T80 4 T153 3 T154 432
auto[FlashMode] auto[1] 59033 1 T1 209 T10 443 T14 200
auto[PassthroughMode] auto[0] 16898 1 T17 10 T32 20 T38 280
auto[PassthroughMode] auto[1] 34780 1 T6 410 T9 375 T15 634

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