Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33243	1			T6	241		T9	56		T10	31
auto[SpiFlashAddrCfg]	7317	1			T6	56		T9	15		T10	12
auto[SpiFlashAddr3b]	8775	1			T6	46		T9	8		T10	13
auto[SpiFlashAddr4b]	7216	1			T6	40		T9	19		T10	19

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32133

1

T6

182

T9

25

T10

32

auto[1]

24418

1

T6

201

T9

73

T10

43

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30347

1

T6

236

T9

72

T10

34

auto[1]

26204

1

T6

147

T9

26

T10

41

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37583	1			T6	271		T9	65		T10	38
values[1]	1055	1			T6	1		T9	1		T10	3
values[2]	1437	1			T6	7		T9	2		T10	1
values[3]	1395	1			T6	2		T9	2		T10	4
values[4]	1458	1			T6	7		T9	3		T10	2
values[5]	1410	1			T6	11		T9	3		T10	3
values[6]	1477	1			T6	11		T9	3		T10	6
values[7]	1402	1			T6	15		T9	3		T10	3
values[8]	9334	1			T6	58		T9	16		T10	15

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30915

1

T6

383

T9

98

T15

108

auto[1]

25636

1

T10

75

T14

164

T25

153

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

53533

1

T6

361

T9

95

T10

73

write

3018

1

T6

22

T9

3

T10

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18037

1

T6

113

T9

31

T10

31

valids[0x1]

38514

1

T6

270

T9

67

T10

44

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1514	1			T6	7		T14	2		T15	9
internal_process_ops[0x5a]	1450	1			T6	4		T9	4		T10	1
internal_process_ops[0x05]	20432	1			T6	167		T9	38		T10	16
internal_process_ops[0x35]	1441	1			T6	6		T9	4		T10	3
internal_process_ops[0x15]	1475	1			T6	8		T9	3		T10	1
internal_process_ops[0x03]	1039	1			T6	12		T9	4		T10	1
internal_process_ops[0x0b]	1037	1			T6	13		T9	2		T10	2
internal_process_ops[0x3b]	1057	1			T6	10		T9	4		T10	1
internal_process_ops[0x6b]	1016	1			T6	12		T9	1		T10	1
internal_process_ops[0xbb]	1030	1			T6	13		T14	2		T15	3
internal_process_ops[0xeb]	1090	1			T6	5		T15	4		T17	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55098

1

T6

366

T9

96

T10

75

auto[1]

1453

1

T6

17

T9

2

T14

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54363

1

T6

365

T9

92

T10

72

auto[1]

2188

1

T6

18

T9

6

T10

3

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10027

1

T6

113

T9

13

T15

24

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6325

1

T6

124

T9

43

T15

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2194

1

T6

24

T9

3

T15

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1947

1

T6

26

T9

10

T15

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2604

1

T6

24

T9

3

T15

10

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2244

1

T6

15

T9

5

T15

11

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2096

1

T6

18

T9

6

T15

12

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1868

1

T6

17

T9

12

T15

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

134

1

T38

3

T39

3

T31

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

99

1

T15

1

T38

2

T39

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

93

1

T15

1

T38

1

T36

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

107

1

T6

4

T39

3

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T6

1

T37

2

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

78

1

T36

1

T39

1

T155

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T38

1

T37

3

T31

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

107

1

T6

5

T9

2

T38

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

134

1

T6

1

T32

2

T38

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

80

1

T6

1

T38

2

T31

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

86

1

T6

1

T36

4

T39

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

95

1

T6

4

T15

1

T38

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

113

1

T15

1

T38

1

T37

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

79

1

T38

1

T39

1

T156

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

86

1

T6

2

T9

1

T15

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

109

1

T6

3

T38

1

T36

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9546

1

T10

13

T14

75

T25

42

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6555

1

T10

18

T14

23

T25

29

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1265

1

T10

6

T14

9

T25

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1173

1

T10

6

T14

6

T25

11

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1616

1

T10

7

T14

8

T25

10

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1585

1

T10

4

T14

7

T25

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1271

1

T10

6

T14

17

T25

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1217

1

T10

13

T14

11

T25

16

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

70

1

T14

1

T154

2

T157

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T25

1

T63

3

T154

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

92

1

T14

3

T63

1

T154

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

88

1

T63

2

T64

1

T157

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

87

1

T25

3

T63

3

T154

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T14

1

T25

2

T157

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

80

1

T63

1

T157

1

T28

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

81

1

T14

3

T63

3

T28

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

74

1

T64

1

T157

3

T158

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

83

1

T63

1

T154

1

T28

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

97

1

T10

2

T63

5

T154

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T25

1

T64

2

T157

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

89

1

T154

3

T64

2

T28

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

85

1

T25

2

T63

3

T64

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

120

1

T25

2

T64

1

T157

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

83

1

T154

3

T65

1

T82

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3798	1			T6	40		T9	12		T15	12
auto[0]	values[0]	valids[0x1]	15458	1			T6	231		T9	53		T15	39
auto[0]	values[1]	valids[0x1]	588	1			T6	1		T9	1		T15	3
auto[0]	values[2]	valids[0x0]	583	1			T6	6		T9	2		T17	2
auto[0]	values[2]	valids[0x1]	291	1			T6	1		T15	2		T38	5
auto[0]	values[3]	valids[0x0]	540	1			T6	1		T9	1		T15	2
auto[0]	values[3]	valids[0x1]	286	1			T6	1		T9	1		T15	5
auto[0]	values[4]	valids[0x0]	614	1			T6	3		T9	2		T15	3
auto[0]	values[4]	valids[0x1]	340	1			T6	4		T9	1		T15	3
auto[0]	values[5]	valids[0x0]	541	1			T6	10		T9	3		T15	2
auto[0]	values[5]	valids[0x1]	342	1			T6	1		T38	4		T89	6
auto[0]	values[6]	valids[0x0]	563	1			T6	10		T15	3		T38	12
auto[0]	values[6]	valids[0x1]	333	1			T6	1		T9	3		T15	3
auto[0]	values[7]	valids[0x0]	558	1			T6	9		T9	3		T15	4
auto[0]	values[7]	valids[0x1]	325	1			T6	6		T15	1		T38	2
auto[0]	values[8]	valids[0x0]	3636	1			T6	34		T9	8		T15	17
auto[0]	values[8]	valids[0x1]	2119	1			T6	24		T9	8		T15	9
auto[1]	values[0]	valids[0x0]	3260	1			T10	12		T14	18		T25	31
auto[1]	values[0]	valids[0x1]	15067	1			T10	26		T14	95		T25	61
auto[1]	values[1]	valids[0x1]	467	1			T10	3		T14	1		T25	9
auto[1]	values[2]	valids[0x0]	364	1			T14	2		T25	5		T63	4
auto[1]	values[2]	valids[0x1]	199	1			T10	1		T14	4		T25	1
auto[1]	values[3]	valids[0x0]	334	1			T14	6		T25	2		T63	5
auto[1]	values[3]	valids[0x1]	235	1			T10	4		T14	2		T25	4
auto[1]	values[4]	valids[0x0]	281	1			T10	2		T14	3		T63	11
auto[1]	values[4]	valids[0x1]	223	1			T14	3		T25	1		T63	5
auto[1]	values[5]	valids[0x0]	280	1			T10	3		T14	3		T25	4
auto[1]	values[5]	valids[0x1]	247	1			T14	2		T25	1		T63	6
auto[1]	values[6]	valids[0x0]	321	1			T10	5		T25	1		T63	6
auto[1]	values[6]	valids[0x1]	260	1			T10	1		T14	1		T25	3
auto[1]	values[7]	valids[0x0]	306	1			T14	4		T25	2		T63	2
auto[1]	values[7]	valids[0x1]	213	1			T10	3		T63	1		T154	7
auto[1]	values[8]	valids[0x0]	2058	1			T10	9		T14	8		T25	16
auto[1]	values[8]	valids[0x1]	1521	1			T10	6		T14	12		T25	12