Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3210672

1

T4

1

T5

1

T6

15155

auto[1]

28509

1

T6

163

T9

39

T10

15

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

947641

1

T4

1

T5

1

T6

78

auto[1]

2291540

1

T6

15240

T9

4148

T10

283

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	646263	1			T4	1		T5	1		T6	7941
auto[524288:1048575]	403419	1			T6	153		T9	2960		T14	361
auto[1048576:1572863]	352192	1			T6	128		T10	20		T25	256
auto[1572864:2097151]	403572	1			T9	513		T10	5		T14	174
auto[2097152:2621439]	350998	1			T6	559		T15	271		T25	1171
auto[2621440:3145727]	389521	1			T6	3382		T14	348		T15	2
auto[3145728:3670015]	361710	1			T6	2864		T9	160		T10	256
auto[3670016:4194303]	331506	1			T6	291		T9	18		T10	14

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2324003

1

T4

1

T5

1

T6

15303

auto[1]

915178

1

T6

15

T14

2

T32

1

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2803661

1

T4

1

T5

1

T6

11499

auto[1]

435520

1

T6

3819

T9

2

T10

8

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	230205	1			T4	1		T5	1		T6	19
auto[0]	auto[0]	auto[0:524287]	auto[1]	350746	1			T6	7839		T9	513		T10	4
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	133408	1			T6	3		T9	2		T14	10
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	219429	1			T9	2958		T14	324		T15	512
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	102654	1			T10	6		T32	4		T38	72
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	204568	1			T6	128		T10	2		T25	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	110773	1			T9	1		T10	1		T14	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	223566	1			T9	512		T10	4		T14	171
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	91870	1			T6	6		T15	9		T25	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	195352	1			T6	1		T15	258		T25	1156
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	77779	1			T6	4		T14	1		T15	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	253813	1			T6	512		T14	347		T25	2381
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	95699	1			T6	10		T9	8		T14	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	220199	1			T6	2851		T9	131		T10	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	92062	1			T6	6		T9	4		T10	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	180132	1			T6	2		T9	2		T10	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	802	1			T6	1		T14	2		T15	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	58056	1			T6	3		T14	512		T15	1879
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	703	1			T6	3		T25	1		T32	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46789	1			T6	129		T38	5		T36	128
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	571	1			T10	2		T38	15		T36	6
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	39921	1			T36	3		T37	2		T31	3
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1969	1			T15	1		T25	6		T38	10
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	63912	1			T25	598		T39	2075		T154	11
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1728	1			T6	5		T25	4		T38	21
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59465	1			T6	514		T25	5		T63	513
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	397	1			T6	3		T38	2		T31	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55144	1			T6	2860		T31	3		T154	2824
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	2453	1			T9	2		T38	34		T36	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	40166	1			T38	516		T37	5		T64	391
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	823	1			T10	2		T14	1		T25	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	55518	1			T6	256		T10	4		T25	137
auto[1]	auto[0]	auto[0:524287]	auto[0]	490	1			T6	9		T9	1		T14	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3323	1			T6	68		T9	7		T14	35
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	340	1			T14	2		T38	5		T39	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2230	1			T14	25		T37	16		T63	19
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	410	1			T10	2		T38	8		T36	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	3343	1			T10	8		T39	1		T37	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	382	1			T15	2		T38	8		T36	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2227	1			T38	7		T39	1		T37	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	308	1			T6	1		T15	2		T25	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1521	1			T6	10		T15	2		T63	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	383	1			T25	2		T38	17		T37	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1634	1			T25	1		T37	11		T31	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	382	1			T6	1		T9	4		T25	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2270	1			T6	2		T9	15		T25	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	347	1			T6	2		T9	2		T10	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1816	1			T6	25		T9	10		T10	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	132	1			T6	1		T38	4		T67	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	2509	1			T6	1		T67	13		T29	31
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	69	1			T6	1		T32	6		T37	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	451	1			T6	17		T37	7		T31	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	79	1			T37	2		T65	1		T193	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	646	1			T37	5		T65	19		T193	24
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	86	1			T25	1		T39	1		T154	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	657	1			T25	5		T154	18		T64	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	141	1			T6	2		T38	5		T63	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	613	1			T6	20		T63	1		T65	27
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	56	1			T6	1		T31	3		T154	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	315	1			T6	2		T31	2		T154	15
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	67	1			T82	24		T207	2		T193	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	474	1			T207	24		T193	22		T66	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	73	1			T36	5		T28	1		T65	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	735	1			T28	2		T65	13		T35	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1872305	1			T4	1		T5	1		T6	11376
auto[0]	auto[0]	auto[1]	909950	1			T6	5		T14	2		T80	335
auto[0]	auto[1]	auto[0]	423837	1			T6	3772		T9	2		T10	8
auto[0]	auto[1]	auto[1]	4580	1			T6	2		T228	2		T37	1
auto[1]	auto[0]	auto[0]	20889	1			T6	111		T9	39		T10	15
auto[1]	auto[0]	auto[1]	517	1			T6	7		T32	1		T38	12
auto[1]	auto[1]	auto[0]	6972	1			T6	44		T25	6		T32	6
auto[1]	auto[1]	auto[1]	131	1			T6	1		T38	1		T36	1