Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2609858	1			T1	4136		T4	1		T5	1
all_pins[1]	2609858	1			T1	4136		T4	1		T5	1
all_pins[2]	2609858	1			T1	4136		T4	1		T5	1
all_pins[3]	2609858	1			T1	4136		T4	1		T5	1
all_pins[4]	2609858	1			T1	4136		T4	1		T5	1
all_pins[5]	2609858	1			T1	4136		T4	1		T5	1
all_pins[6]	2609858	1			T1	4136		T4	1		T5	1
all_pins[7]	2609858	1			T1	4136		T4	1		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20822118	1			T1	33088		T4	8		T5	8
values[0x1]	56746	1			T6	98		T11	10		T19	34
transitions[0x0=>0x1]	55284	1			T6	80		T11	8		T19	29
transitions[0x1=>0x0]	55297	1			T6	80		T11	8		T19	29

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2609431	1			T1	4136		T4	1		T5	1
all_pins[0]	values[0x1]	427	1			T6	5		T11	4		T19	7
all_pins[0]	transitions[0x0=>0x1]	285	1			T6	4		T11	2		T19	5
all_pins[0]	transitions[0x1=>0x0]	163	1			T6	19		T11	1		T19	6
all_pins[1]	values[0x0]	2609553	1			T1	4136		T4	1		T5	1
all_pins[1]	values[0x1]	305	1			T6	20		T11	3		T19	8
all_pins[1]	transitions[0x0=>0x1]	249	1			T6	12		T11	3		T19	7
all_pins[1]	transitions[0x1=>0x0]	168	1			T6	4		T11	1		T19	3
all_pins[2]	values[0x0]	2609634	1			T1	4136		T4	1		T5	1
all_pins[2]	values[0x1]	224	1			T6	12		T11	1		T19	4
all_pins[2]	transitions[0x0=>0x1]	177	1			T6	11		T11	1		T19	3
all_pins[2]	transitions[0x1=>0x0]	149	1			T6	6		T19	2		T20	8
all_pins[3]	values[0x0]	2609662	1			T1	4136		T4	1		T5	1
all_pins[3]	values[0x1]	196	1			T6	7		T19	3		T20	9
all_pins[3]	transitions[0x0=>0x1]	151	1			T6	4		T19	2		T20	7
all_pins[3]	transitions[0x1=>0x0]	142	1			T6	2		T20	3		T21	1
all_pins[4]	values[0x0]	2609671	1			T1	4136		T4	1		T5	1
all_pins[4]	values[0x1]	187	1			T6	5		T19	1		T20	5
all_pins[4]	transitions[0x0=>0x1]	148	1			T6	2		T19	1		T20	3
all_pins[4]	transitions[0x1=>0x0]	1942	1			T6	41		T11	1		T19	3
all_pins[5]	values[0x0]	2607877	1			T1	4136		T4	1		T5	1
all_pins[5]	values[0x1]	1981	1			T6	44		T11	1		T19	3
all_pins[5]	transitions[0x0=>0x1]	953	1			T6	42		T11	1		T19	3
all_pins[5]	transitions[0x1=>0x0]	52209	1			T6	2		T11	1		T19	6
all_pins[6]	values[0x0]	2556621	1			T1	4136		T4	1		T5	1
all_pins[6]	values[0x1]	53237	1			T6	4		T11	1		T19	6
all_pins[6]	transitions[0x0=>0x1]	53187	1			T6	4		T11	1		T19	6
all_pins[6]	transitions[0x1=>0x0]	139	1			T6	1		T19	2		T20	1
all_pins[7]	values[0x0]	2609669	1			T1	4136		T4	1		T5	1
all_pins[7]	values[0x1]	189	1			T6	1		T19	2		T20	3
all_pins[7]	transitions[0x0=>0x1]	134	1			T6	1		T19	2		T20	3
all_pins[7]	transitions[0x1=>0x0]	385	1			T6	5		T11	4		T19	7