Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17745

1

T6

182

T9

25

T15

53

auto[1]

13170

1

T6

201

T9

73

T15

55

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3941	1			T15	41		T36	60		T228	4
values[1]	4234	1			T9	57		T15	23		T17	10
values[2]	4147	1			T6	52		T9	41		T38	40
values[3]	3884	1			T6	53		T15	21		T38	20
values[4]	3836	1			T6	38		T38	60		T33	6
values[5]	3695	1			T6	23		T15	23		T38	20
values[6]	3710	1			T6	185		T38	80		T36	20
values[7]	3468	1			T6	32		T32	20		T38	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4226	1			T9	41		T15	23		T17	10
values[1]	3178	1			T6	84		T15	23		T81	2
values[2]	4357	1			T6	61		T9	37		T32	20
values[3]	3804	1			T9	20		T15	21		T38	20
values[4]	3363	1			T6	52		T15	21		T38	60
values[5]	3856	1			T15	20		T38	40		T36	20
values[6]	3797	1			T6	91		T38	60		T33	6
values[7]	4334	1			T6	95		T38	60		T36	40

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	294	1			T36	18		T35	13		T23	12
auto[0]	values[0]	values[1]	230	1			T156	8		T23	11		T169	9
auto[0]	values[0]	values[2]	425	1			T36	5		T228	4		T76	15
auto[0]	values[0]	values[3]	400	1			T37	22		T185	13		T200	10
auto[0]	values[0]	values[4]	260	1			T15	11		T192	2		T156	11
auto[0]	values[0]	values[5]	138	1			T15	10		T156	16		T155	8
auto[0]	values[0]	values[6]	240	1			T179	18		T229	12		T230	14
auto[0]	values[0]	values[7]	433	1			T39	12		T67	160		T231	7
auto[0]	values[1]	values[0]	316	1			T17	10		T36	24		T31	13
auto[0]	values[1]	values[1]	313	1			T15	12		T67	9		T48	10
auto[0]	values[1]	values[2]	403	1			T9	9		T36	13		T31	11
auto[0]	values[1]	values[3]	233	1			T9	7		T39	17		T232	6
auto[0]	values[1]	values[4]	313	1			T76	10		T186	12		T220	27
auto[0]	values[1]	values[5]	340	1			T224	10		T22	10		T233	4
auto[0]	values[1]	values[6]	280	1			T38	10		T37	34		T90	8
auto[0]	values[1]	values[7]	253	1			T38	11		T156	13		T22	8
auto[0]	values[2]	values[0]	211	1			T9	9		T39	18		T22	12
auto[0]	values[2]	values[1]	204	1			T35	11		T155	15		T66	11
auto[0]	values[2]	values[2]	228	1			T37	12		T35	15		T234	2
auto[0]	values[2]	values[3]	243	1			T90	9		T47	15		T235	20
auto[0]	values[2]	values[4]	504	1			T38	13		T84	10		T35	8
auto[0]	values[2]	values[5]	314	1			T38	11		T236	4		T23	15
auto[0]	values[2]	values[6]	239	1			T35	8		T237	12		T238	2
auto[0]	values[2]	values[7]	390	1			T6	47		T36	21		T39	16
auto[0]	values[3]	values[0]	185	1			T185	19		T239	19		T222	15
auto[0]	values[3]	values[1]	127	1			T31	14		T240	6		T173	18
auto[0]	values[3]	values[2]	364	1			T22	10		T67	49		T50	14
auto[0]	values[3]	values[3]	287	1			T15	13		T90	11		T241	58
auto[0]	values[3]	values[4]	226	1			T37	28		T35	10		T76	9
auto[0]	values[3]	values[5]	245	1			T31	13		T156	8		T211	11
auto[0]	values[3]	values[6]	243	1			T6	9		T194	6		T185	7
auto[0]	values[3]	values[7]	355	1			T6	12		T38	14		T31	29
auto[0]	values[4]	values[0]	241	1			T22	6		T223	14		T186	13
auto[0]	values[4]	values[1]	204	1			T31	12		T155	9		T186	10
auto[0]	values[4]	values[2]	409	1			T6	8		T242	6		T243	2
auto[0]	values[4]	values[3]	323	1			T38	14		T35	11		T244	18
auto[0]	values[4]	values[4]	292	1			T38	13		T36	19		T35	14
auto[0]	values[4]	values[5]	309	1			T245	2		T67	30		T186	14
auto[0]	values[4]	values[6]	294	1			T38	13		T33	6		T170	2
auto[0]	values[4]	values[7]	152	1			T156	15		T155	25		T211	13
auto[0]	values[5]	values[0]	283	1			T15	7		T66	13		T23	11
auto[0]	values[5]	values[1]	304	1			T246	4		T194	14		T247	16
auto[0]	values[5]	values[2]	420	1			T6	11		T42	35		T186	51
auto[0]	values[5]	values[3]	199	1			T39	16		T156	14		T248	4
auto[0]	values[5]	values[4]	144	1			T37	9		T21	24		T67	8
auto[0]	values[5]	values[5]	286	1			T38	14		T67	28		T180	8
auto[0]	values[5]	values[6]	190	1			T23	22		T249	2		T171	13
auto[0]	values[5]	values[7]	356	1			T155	11		T250	4		T251	10
auto[0]	values[6]	values[0]	141	1			T38	25		T76	9		T23	13
auto[0]	values[6]	values[1]	289	1			T6	8		T88	16		T252	4
auto[0]	values[6]	values[2]	258	1			T23	16		T42	9		T173	16
auto[0]	values[6]	values[3]	194	1			T90	22		T253	6		T76	10
auto[0]	values[6]	values[4]	133	1			T6	12		T38	8		T254	8
auto[0]	values[6]	values[5]	421	1			T36	11		T155	12		T255	20
auto[0]	values[6]	values[6]	511	1			T6	37		T38	13		T31	12
auto[0]	values[6]	values[7]	212	1			T6	14		T37	15		T256	6
auto[0]	values[7]	values[0]	456	1			T21	11		T76	26		T47	11
auto[0]	values[7]	values[1]	192	1			T81	2		T257	4		T23	32
auto[0]	values[7]	values[2]	213	1			T32	10		T31	18		T217	38
auto[0]	values[7]	values[3]	260	1			T89	8		T39	7		T37	12
auto[0]	values[7]	values[4]	171	1			T6	24		T42	15		T175	16
auto[0]	values[7]	values[5]	243	1			T215	16		T184	41		T258	6
auto[0]	values[7]	values[6]	158	1			T214	10		T212	12		T47	20
auto[0]	values[7]	values[7]	251	1			T38	12		T23	17		T186	9
auto[1]	values[0]	values[0]	174	1			T36	22		T35	11		T23	8
auto[1]	values[0]	values[1]	218	1			T156	12		T23	10		T169	11
auto[1]	values[0]	values[2]	148	1			T36	15		T76	5		T42	6
auto[1]	values[0]	values[3]	270	1			T37	12		T185	7		T200	10
auto[1]	values[0]	values[4]	221	1			T15	10		T156	9		T76	9
auto[1]	values[0]	values[5]	124	1			T15	10		T156	4		T155	12
auto[1]	values[0]	values[6]	170	1			T259	8		T230	13		T260	7
auto[1]	values[0]	values[7]	196	1			T39	8		T67	3		T231	13
auto[1]	values[1]	values[0]	221	1			T36	16		T31	9		T156	9
auto[1]	values[1]	values[1]	228	1			T15	11		T67	19		T48	10
auto[1]	values[1]	values[2]	272	1			T9	28		T36	7		T31	9
auto[1]	values[1]	values[3]	196	1			T9	13		T39	6		T171	6
auto[1]	values[1]	values[4]	209	1			T76	10		T186	8		T220	16
auto[1]	values[1]	values[5]	222	1			T22	10		T185	10		T67	46
auto[1]	values[1]	values[6]	174	1			T38	10		T37	11		T90	14
auto[1]	values[1]	values[7]	261	1			T38	9		T156	7		T22	13
auto[1]	values[2]	values[0]	291	1			T9	32		T219	4		T39	7
auto[1]	values[2]	values[1]	103	1			T35	9		T155	5		T66	9
auto[1]	values[2]	values[2]	216	1			T37	9		T35	25		T211	9
auto[1]	values[2]	values[3]	307	1			T90	11		T210	16		T47	5
auto[1]	values[2]	values[4]	200	1			T38	7		T35	12		T66	19
auto[1]	values[2]	values[5]	291	1			T38	9		T261	10		T23	58
auto[1]	values[2]	values[6]	179	1			T35	19		T42	7		T29	8
auto[1]	values[2]	values[7]	227	1			T6	5		T36	19		T39	8
auto[1]	values[3]	values[0]	182	1			T185	25		T239	29		T222	11
auto[1]	values[3]	values[1]	59	1			T31	6		T173	2		T262	9
auto[1]	values[3]	values[2]	160	1			T22	10		T67	9		T220	10
auto[1]	values[3]	values[3]	222	1			T15	8		T90	16		T211	6
auto[1]	values[3]	values[4]	106	1			T37	10		T35	10		T76	11
auto[1]	values[3]	values[5]	319	1			T31	8		T156	44		T211	9
auto[1]	values[3]	values[6]	416	1			T6	24		T194	14		T185	13
auto[1]	values[3]	values[7]	388	1			T6	8		T38	6		T31	18
auto[1]	values[4]	values[0]	208	1			T22	14		T186	9		T171	9
auto[1]	values[4]	values[1]	163	1			T31	9		T155	11		T186	10
auto[1]	values[4]	values[2]	258	1			T6	30		T24	7		T42	19
auto[1]	values[4]	values[3]	188	1			T38	6		T35	28		T263	16
auto[1]	values[4]	values[4]	164	1			T38	7		T36	21		T35	13
auto[1]	values[4]	values[5]	214	1			T204	22		T67	10		T264	12
auto[1]	values[4]	values[6]	202	1			T38	7		T216	12		T190	16
auto[1]	values[4]	values[7]	215	1			T156	5		T155	15		T211	7
auto[1]	values[5]	values[0]	499	1			T15	16		T66	7		T23	11
auto[1]	values[5]	values[1]	87	1			T194	6		T265	11		T266	7
auto[1]	values[5]	values[2]	135	1			T6	12		T42	12		T186	5
auto[1]	values[5]	values[3]	165	1			T39	8		T156	9		T76	12
auto[1]	values[5]	values[4]	137	1			T37	11		T21	7		T67	28
auto[1]	values[5]	values[5]	78	1			T38	6		T67	3		T180	12
auto[1]	values[5]	values[6]	136	1			T23	11		T171	7		T222	6
auto[1]	values[5]	values[7]	276	1			T198	24		T155	11		T48	5
auto[1]	values[6]	values[0]	136	1			T38	15		T267	18		T76	11
auto[1]	values[6]	values[1]	246	1			T6	76		T211	21		T46	9
auto[1]	values[6]	values[2]	227	1			T23	8		T42	11		T173	28
auto[1]	values[6]	values[3]	136	1			T90	18		T76	10		T180	10
auto[1]	values[6]	values[4]	226	1			T6	8		T38	12		T184	10
auto[1]	values[6]	values[5]	220	1			T36	9		T41	20		T155	11
auto[1]	values[6]	values[6]	210	1			T6	21		T38	7		T31	12
auto[1]	values[6]	values[7]	150	1			T6	9		T37	5		T23	10
auto[1]	values[7]	values[0]	388	1			T21	9		T76	14		T47	13
auto[1]	values[7]	values[1]	211	1			T183	18		T23	2		T48	8
auto[1]	values[7]	values[2]	221	1			T32	10		T40	12		T31	6
auto[1]	values[7]	values[3]	181	1			T39	15		T37	10		T31	15
auto[1]	values[7]	values[4]	57	1			T6	8		T42	7		T125	8
auto[1]	values[7]	values[5]	92	1			T268	10		T184	8		T269	9
auto[1]	values[7]	values[6]	155	1			T34	20		T47	3		T222	7
auto[1]	values[7]	values[7]	219	1			T38	8		T23	8		T186	12