Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	419	1			T6	4		T15	4		T38	5
auto[ReadAddrCrossIntoMailbox]	315	1			T6	4		T15	3		T38	3
auto[ReadAddrCrossOutOfMailbox]	315	1			T6	3		T15	1		T38	7
auto[ReadAddrCrossAllMailbox]	219	1			T6	3		T15	1		T38	4
auto[ReadAddrOutsideMailbox]	3663	1			T6	51		T9	11		T15	17

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2361

1

T6

30

T9

5

T15

12

auto[1]

2570

1

T6

35

T9

6

T15

14

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	838	1			T6	12		T9	4		T15	6
read_ops[0x0b]	801	1			T6	13		T9	2		T15	6
read_ops[0x3b]	835	1			T6	10		T9	4		T15	4
read_ops[0x6b]	773	1			T6	12		T9	1		T15	3
read_ops[0xbb]	806	1			T6	13		T15	3		T17	2
read_ops[0xeb]	878	1			T6	5		T15	4		T17	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T37	1		T90	1		T155	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T6	1		T15	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T6	1		T15	1		T36	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T36	1		T211	1		T270	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T35	1		T211	1		T47	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T15	1		T38	2		T36	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T6	1		T35	1		T155	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T36	2		T31	1		T21	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T9	3		T15	2		T38	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T6	9		T9	1		T15	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T6	2		T214	1		T35	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	47	1			T15	2		T38	1		T214	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T6	2		T38	1		T36	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T15	1		T35	1		T251	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T36	1		T214	1		T156	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T214	1		T22	1		T169	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T251	1		T169	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T155	1		T251	1		T76	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T6	5		T9	2		T15	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	307	1			T6	4		T15	2		T32	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T37	2		T256	1		T90	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	45	1			T256	1		T35	1		T23	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T15	1		T23	1		T42	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	34	1			T48	1		T186	1		T190	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T39	1		T35	2		T66	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T36	1		T35	1		T67	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T155	1		T66	1		T186	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	24	1			T6	1		T38	1		T21	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T6	5		T15	2		T32	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T6	4		T9	4		T15	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T38	1		T211	1		T185	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T36	2		T37	1		T31	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T35	1		T24	1		T169	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	27	1			T156	1		T211	1		T67	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T38	1		T90	1		T47	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T6	2		T156	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T194	1		T185	1		T48	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T6	1		T66	1		T23	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	259	1			T6	4		T36	1		T81	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	308	1			T6	5		T9	1		T15	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T6	1		T38	2		T36	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T15	1		T36	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T6	1		T38	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T38	1		T31	2		T185	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T38	1		T214	1		T155	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T38	1		T31	1		T214	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T38	1		T22	1		T76	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T156	1		T155	1		T42	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	310	1			T6	6		T15	2		T17	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	303	1			T6	5		T17	1		T38	4
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T36	2		T35	2		T155	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T224	1		T22	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T36	1		T39	2		T31	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T37	1		T76	1		T67	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T6	1		T31	1		T155	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T38	2		T76	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T15	1		T155	2		T251	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T38	2		T156	1		T35	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	337	1			T6	1		T15	2		T17	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	347	1			T6	3		T15	1		T17	1