Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3658	1			T6	38		T9	61		T15	23
values[1]	3269	1			T6	78		T9	37		T38	20
values[2]	3786	1			T15	21		T38	20		T36	20
values[3]	4097	1			T6	192		T38	40		T36	20
values[4]	4083	1			T15	43		T32	20		T38	40
values[5]	4005	1			T6	52		T15	21		T38	60
values[6]	3715	1			T6	23		T17	10		T39	25
values[7]	4302	1			T38	60		T36	40		T81	2

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3238	1			T6	23		T9	78		T38	100
values[1]	4086	1			T6	52		T17	10		T38	80
values[2]	4688	1			T6	32		T15	21		T219	4
values[3]	4004	1			T6	38		T15	23		T38	100
values[4]	4128	1			T6	122		T9	20		T36	60
values[5]	3820	1			T6	93		T15	23		T32	20
values[6]	3851	1			T15	41		T36	80		T37	34
values[7]	3100	1			T6	23		T81	2		T88	16

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30161

1

T6

366

T9

96

T15

106

auto[1]

754

1

T6

17

T9

2

T15

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	385	1			T9	41		T38	20		T271	8
auto[0]	values[0]	values[1]	402	1			T37	21		T66	25		T24	26
auto[0]	values[0]	values[2]	672	1			T183	18		T211	20		T66	19
auto[0]	values[0]	values[3]	311	1			T15	22		T38	20		T36	19
auto[0]	values[0]	values[4]	573	1			T6	38		T9	20		T36	18
auto[0]	values[0]	values[5]	356	1			T170	2		T250	4		T76	20
auto[0]	values[0]	values[6]	474	1			T36	20		T37	34		T90	26
auto[0]	values[0]	values[7]	409	1			T31	26		T21	20		T210	16
auto[0]	values[1]	values[0]	415	1			T9	35		T35	23		T185	20
auto[0]	values[1]	values[1]	269	1			T38	20		T33	6		T84	10
auto[0]	values[1]	values[2]	508	1			T192	2		T35	37		T48	28
auto[0]	values[1]	values[3]	276	1			T6	33		T272	4		T273	8
auto[0]	values[1]	values[4]	301	1			T90	20		T155	20		T194	20
auto[0]	values[1]	values[5]	637	1			T6	38		T156	20		T220	19
auto[0]	values[1]	values[6]	536	1			T36	40		T42	20		T184	22
auto[0]	values[1]	values[7]	226	1			T90	20		T22	20		T225	6
auto[0]	values[2]	values[0]	433	1			T38	17		T39	24		T35	20
auto[0]	values[2]	values[1]	327	1			T31	22		T155	19		T212	12
auto[0]	values[2]	values[2]	626	1			T76	19		T185	19		T42	25
auto[0]	values[2]	values[3]	440	1			T35	23		T155	19		T185	20
auto[0]	values[2]	values[4]	582	1			T36	20		T42	25		T197	10
auto[0]	values[2]	values[5]	361	1			T39	22		T156	19		T239	28
auto[0]	values[2]	values[6]	473	1			T15	21		T253	6		T156	18
auto[0]	values[2]	values[7]	443	1			T37	36		T263	16		T76	19
auto[0]	values[3]	values[0]	385	1			T6	23		T199	21		T171	28
auto[0]	values[3]	values[1]	732	1			T38	19		T31	20		T267	18
auto[0]	values[3]	values[2]	482	1			T6	32		T204	22		T274	4
auto[0]	values[3]	values[3]	602	1			T38	18		T31	20		T241	58
auto[0]	values[3]	values[4]	563	1			T6	78		T36	20		T155	22
auto[0]	values[3]	values[5]	545	1			T6	51		T31	23		T76	20
auto[0]	values[3]	values[6]	314	1			T261	8		T23	22		T235	20
auto[0]	values[3]	values[7]	359	1			T224	10		T23	21		T249	2
auto[0]	values[4]	values[0]	438	1			T38	19		T31	20		T35	24
auto[0]	values[4]	values[1]	552	1			T35	40		T255	20		T48	18
auto[0]	values[4]	values[2]	349	1			T219	4		T228	4		T39	19
auto[0]	values[4]	values[3]	542	1			T38	20		T36	20		T31	21
auto[0]	values[4]	values[4]	642	1			T155	19		T42	21		T190	44
auto[0]	values[4]	values[5]	428	1			T15	22		T32	20		T236	4
auto[0]	values[4]	values[6]	458	1			T15	20		T156	22		T155	21
auto[0]	values[4]	values[7]	575	1			T88	16		T275	10		T42	30
auto[0]	values[5]	values[0]	398	1			T38	20		T156	70		T244	18
auto[0]	values[5]	values[1]	712	1			T6	50		T38	19		T23	33
auto[0]	values[5]	values[2]	812	1			T15	21		T39	41		T35	20
auto[0]	values[5]	values[3]	336	1			T38	20		T242	6		T67	27
auto[0]	values[5]	values[4]	357	1			T214	10		T156	99		T22	20
auto[0]	values[5]	values[5]	484	1			T36	19		T31	22		T35	22
auto[0]	values[5]	values[6]	404	1			T156	18		T238	2		T42	24
auto[0]	values[5]	values[7]	410	1			T40	10		T76	19		T169	18
auto[0]	values[6]	values[0]	299	1			T259	8		T31	23		T218	12
auto[0]	values[6]	values[1]	365	1			T17	10		T37	41		T252	4
auto[0]	values[6]	values[2]	540	1			T39	25		T37	45		T198	24
auto[0]	values[6]	values[3]	475	1			T217	38		T233	4		T66	22
auto[0]	values[6]	values[4]	703	1			T76	20		T232	6		T66	24
auto[0]	values[6]	values[5]	407	1			T35	40		T155	20		T23	19
auto[0]	values[6]	values[6]	518	1			T246	4		T156	20		T251	10
auto[0]	values[6]	values[7]	326	1			T6	23		T67	40		T23	24
auto[0]	values[7]	values[0]	395	1			T38	19		T211	22		T185	24
auto[0]	values[7]	values[1]	624	1			T38	19		T36	20		T156	20
auto[0]	values[7]	values[2]	593	1			T90	22		T240	6		T156	52
auto[0]	values[7]	values[3]	917	1			T38	20		T37	20		T155	20
auto[0]	values[7]	values[4]	301	1			T89	8		T188	43		T223	14
auto[0]	values[7]	values[5]	507	1			T156	18		T76	15		T185	23
auto[0]	values[7]	values[6]	581	1			T36	20		T257	4		T90	20
auto[0]	values[7]	values[7]	296	1			T81	2		T21	20		T211	20
auto[1]	values[0]	values[0]	9	1			T220	1		T125	2		T177	1
auto[1]	values[0]	values[1]	12	1			T66	1		T24	1		T200	1
auto[1]	values[0]	values[2]	12	1			T211	1		T66	1		T186	1
auto[1]	values[0]	values[3]	7	1			T15	1		T36	1		T23	2
auto[1]	values[0]	values[4]	16	1			T36	2		T22	3		T23	2
auto[1]	values[0]	values[5]	4	1			T125	1		T276	1		T277	1
auto[1]	values[0]	values[6]	13	1			T90	1		T76	2		T185	3
auto[1]	values[0]	values[7]	3	1			T31	1		T278	1		T279	1
auto[1]	values[1]	values[0]	19	1			T9	2		T35	4		T125	2
auto[1]	values[1]	values[1]	9	1			T226	3		T280	1		T281	1
auto[1]	values[1]	values[2]	14	1			T35	2		T48	1		T169	2
auto[1]	values[1]	values[3]	21	1			T6	5		T176	2		T266	1
auto[1]	values[1]	values[4]	5	1			T24	1		T282	2		T151	2
auto[1]	values[1]	values[5]	17	1			T6	2		T220	1		T283	2
auto[1]	values[1]	values[6]	10	1			T200	1		T269	2		T266	2
auto[1]	values[1]	values[7]	6	1			T225	6		-	-		-	-
auto[1]	values[2]	values[0]	14	1			T38	3		T211	2		T185	1
auto[1]	values[2]	values[1]	12	1			T31	2		T155	1		T216	1
auto[1]	values[2]	values[2]	10	1			T76	1		T185	1		T42	1
auto[1]	values[2]	values[3]	18	1			T35	4		T155	1		T186	2
auto[1]	values[2]	values[4]	15	1			T42	1		T171	1		T262	1
auto[1]	values[2]	values[5]	12	1			T156	1		T284	3		T282	4
auto[1]	values[2]	values[6]	8	1			T156	2		T186	1		T285	1
auto[1]	values[2]	values[7]	12	1			T37	2		T76	1		T29	2
auto[1]	values[3]	values[0]	8	1			T171	1		T222	2		T176	1
auto[1]	values[3]	values[1]	15	1			T38	1		T67	2		T286	1
auto[1]	values[3]	values[2]	14	1			T287	6		T276	2		T288	2
auto[1]	values[3]	values[3]	18	1			T38	2		T41	2		T211	1
auto[1]	values[3]	values[4]	20	1			T6	6		T155	1		T67	2
auto[1]	values[3]	values[5]	16	1			T6	2		T180	2		T265	2
auto[1]	values[3]	values[6]	17	1			T261	2		T169	3		T196	5
auto[1]	values[3]	values[7]	7	1			T23	1		T125	1		T289	2
auto[1]	values[4]	values[0]	10	1			T38	1		T31	1		T23	1
auto[1]	values[4]	values[1]	19	1			T48	2		T169	1		T284	1
auto[1]	values[4]	values[2]	10	1			T39	1		T200	3		T290	1
auto[1]	values[4]	values[3]	17	1			T21	1		T42	2		T191	2
auto[1]	values[4]	values[4]	16	1			T155	1		T42	1		T190	1
auto[1]	values[4]	values[5]	12	1			T15	1		T23	1		T195	1
auto[1]	values[4]	values[6]	6	1			T156	1		T155	1		T184	1
auto[1]	values[4]	values[7]	9	1			T186	1		T184	1		T200	1
auto[1]	values[5]	values[0]	9	1			T156	2		T185	2		T42	1
auto[1]	values[5]	values[1]	11	1			T6	2		T38	1		T220	1
auto[1]	values[5]	values[2]	34	1			T39	6		T67	2		T178	4
auto[1]	values[5]	values[3]	8	1			T67	1		T266	2		T151	2
auto[1]	values[5]	values[4]	3	1			T156	1		T22	1		T291	1
auto[1]	values[5]	values[5]	10	1			T36	1		T292	2		T176	2
auto[1]	values[5]	values[6]	10	1			T156	2		T180	2		T176	1
auto[1]	values[5]	values[7]	7	1			T40	2		T76	1		T169	2
auto[1]	values[6]	values[0]	11	1			T31	1		T180	3		T285	1
auto[1]	values[6]	values[1]	8	1			T37	1		T22	2		T262	1
auto[1]	values[6]	values[2]	4	1			T196	4		-	-		-	-
auto[1]	values[6]	values[3]	8	1			T66	1		T293	1		T269	2
auto[1]	values[6]	values[4]	23	1			T66	2		T42	4		T171	3
auto[1]	values[6]	values[5]	8	1			T35	1		T23	2		T125	2
auto[1]	values[6]	values[6]	16	1			T76	1		T180	2		T265	3
auto[1]	values[6]	values[7]	4	1			T23	1		T125	1		T43	2
auto[1]	values[7]	values[0]	10	1			T38	1		T200	1		T291	1
auto[1]	values[7]	values[1]	17	1			T38	1		T29	1		T189	1
auto[1]	values[7]	values[2]	8	1			T185	2		T205	1		T294	1
auto[1]	values[7]	values[3]	8	1			T190	1		T230	2		T295	2
auto[1]	values[7]	values[4]	8	1			T188	2		T205	2		T196	1
auto[1]	values[7]	values[5]	16	1			T156	2		T76	5		T239	1
auto[1]	values[7]	values[6]	13	1			T47	1		T205	3		T296	3
auto[1]	values[7]	values[7]	8	1			T184	1		T177	4		T297	1