Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	833	1			T6	21		T11	8		T19	17
all_values[1]	833	1			T6	21		T11	8		T19	17
all_values[2]	833	1			T6	21		T11	8		T19	17
all_values[3]	833	1			T6	21		T11	8		T19	17
all_values[4]	833	1			T6	21		T11	8		T19	17
all_values[5]	833	1			T6	21		T11	8		T19	17
all_values[6]	833	1			T6	21		T11	8		T19	17
all_values[7]	833	1			T6	21		T11	8		T19	17

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3565

1

T6

85

T11

42

T19

65

auto[1]

3099

1

T6

83

T11

22

T19

71

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2617

1

T6

58

T11

28

T19

51

auto[1]

4047

1

T6

110

T11

36

T19

85

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3795

1

T6

82

T11

39

T19

73

auto[1]

2869

1

T6

86

T11

25

T19

63

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	163	1			T6	4		T11	2		T19	1
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T6	1		T11	1		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	143	1			T6	3		T19	2		T20	2
all_values[0]	auto[0]	auto[1]	auto[1]	64	1			T11	2		T19	2		T20	4
all_values[0]	auto[1]	auto[0]	auto[1]	203	1			T6	6		T11	1		T19	6
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T6	7		T11	2		T19	5
all_values[1]	auto[0]	auto[0]	auto[0]	155	1			T6	2		T19	2		T21	2
all_values[1]	auto[0]	auto[0]	auto[1]	94	1			T6	3		T19	1		T20	4
all_values[1]	auto[0]	auto[1]	auto[0]	133	1			T6	1		T11	2		T19	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T6	4		T11	2		T19	5
all_values[1]	auto[1]	auto[0]	auto[1]	215	1			T6	8		T11	4		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T6	3		T19	6		T20	3
all_values[2]	auto[0]	auto[0]	auto[0]	172	1			T6	6		T11	4		T19	4
all_values[2]	auto[0]	auto[0]	auto[1]	71	1			T6	1		T11	1		T20	4
all_values[2]	auto[0]	auto[1]	auto[0]	151	1			T6	3		T19	6		T20	3
all_values[2]	auto[0]	auto[1]	auto[1]	93	1			T6	2		T19	2		T20	5
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T6	4		T11	3		T19	1
all_values[2]	auto[1]	auto[1]	auto[1]	162	1			T6	5		T19	4		T20	5
all_values[3]	auto[0]	auto[0]	auto[0]	167	1			T11	1		T19	3		T20	7
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T6	2		T11	1		T19	3
all_values[3]	auto[0]	auto[1]	auto[0]	133	1			T6	4		T11	3		T19	4
all_values[3]	auto[0]	auto[1]	auto[1]	82	1			T6	3		T20	5		T21	1
all_values[3]	auto[1]	auto[0]	auto[1]	201	1			T6	4		T11	2		T19	2
all_values[3]	auto[1]	auto[1]	auto[1]	163	1			T6	8		T11	1		T19	5
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T6	4		T19	4		T20	8
all_values[4]	auto[0]	auto[0]	auto[1]	89	1			T6	2		T11	1		T19	1
all_values[4]	auto[0]	auto[1]	auto[0]	146	1			T6	3		T11	4		T19	2
all_values[4]	auto[0]	auto[1]	auto[1]	90	1			T6	3		T19	1		T20	2
all_values[4]	auto[1]	auto[0]	auto[1]	202	1			T6	5		T11	3		T19	6
all_values[4]	auto[1]	auto[1]	auto[1]	152	1			T6	4		T19	3		T20	2
all_values[5]	auto[0]	auto[0]	auto[0]	246	1			T6	2		T11	5		T19	3
all_values[5]	auto[0]	auto[1]	auto[0]	228	1			T6	10		T11	1		T19	6
all_values[5]	auto[1]	auto[0]	auto[1]	187	1			T6	5		T11	1		T19	7
all_values[5]	auto[1]	auto[1]	auto[1]	172	1			T6	4		T11	1		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	142	1			T6	3		T11	1		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	83	1			T6	2		T11	1		T19	1
all_values[6]	auto[0]	auto[1]	auto[0]	139	1			T6	1		T11	2		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	82	1			T19	3		T20	2		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	223	1			T6	9		T11	4		T19	5
all_values[6]	auto[1]	auto[1]	auto[1]	164	1			T6	6		T19	5		T20	3
all_values[7]	auto[0]	auto[0]	auto[0]	170	1			T6	4		T11	2		T19	6
all_values[7]	auto[0]	auto[0]	auto[1]	89	1			T6	1		T11	2		T19	2
all_values[7]	auto[0]	auto[1]	auto[0]	175	1			T6	8		T11	1		T19	4
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T20	2		T21	1		T22	2
all_values[7]	auto[1]	auto[0]	auto[1]	174	1			T6	7		T11	2		T19	3
all_values[7]	auto[1]	auto[1]	auto[1]	144	1			T6	1		T11	1		T19	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal