Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1795

1

T1

5

T6

2

T9

7

auto[1]

1828

1

T1

2

T9

10

T10

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1834

1

T1

7

T6

2

T9

17

auto[1]

1789

1

T10

1

T14

1

T15

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2904

1

T1

4

T6

2

T9

10

auto[1]

719

1

T1

3

T9

7

T10

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	689	1			T1	3		T6	1		T9	2
valid[1]	728	1			T1	1		T9	2		T10	1
valid[2]	746	1			T1	1		T9	2		T10	4
valid[3]	736	1			T1	1		T6	1		T9	9
valid[4]	724	1			T1	1		T9	2		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	117	1			T1	1		T6	1		T9	1
auto[0]	auto[0]	valid[0]	auto[1]	153	1			T15	1		T324	3		T325	2
auto[0]	auto[0]	valid[1]	auto[0]	123	1			T1	1		T9	1		T15	2
auto[0]	auto[0]	valid[1]	auto[1]	167	1			T324	1		T325	4		T326	4
auto[0]	auto[0]	valid[2]	auto[0]	105	1			T1	1		T15	1		T90	1
auto[0]	auto[0]	valid[2]	auto[1]	179	1			T15	1		T325	3		T326	1
auto[0]	auto[0]	valid[3]	auto[0]	109	1			T6	1		T9	2		T91	1
auto[0]	auto[0]	valid[3]	auto[1]	188	1			T72	1		T75	1		T39	1
auto[0]	auto[0]	valid[4]	auto[0]	108	1			T10	1		T15	3		T26	2
auto[0]	auto[0]	valid[4]	auto[1]	191	1			T25	1		T75	1		T39	2
auto[0]	auto[1]	valid[0]	auto[0]	100	1			T1	1		T15	2		T39	3
auto[0]	auto[1]	valid[0]	auto[1]	169	1			T73	2		T75	1		T324	2
auto[0]	auto[1]	valid[1]	auto[0]	97	1			T15	2		T25	1		T39	1
auto[0]	auto[1]	valid[1]	auto[1]	203	1			T72	1		T39	1		T324	2
auto[0]	auto[1]	valid[2]	auto[0]	113	1			T9	2		T10	2		T15	1
auto[0]	auto[1]	valid[2]	auto[1]	199	1			T10	1		T14	1		T72	1
auto[0]	auto[1]	valid[3]	auto[0]	122	1			T9	3		T10	2		T15	1
auto[0]	auto[1]	valid[3]	auto[1]	167	1			T327	3		T325	3		T63	1
auto[0]	auto[1]	valid[4]	auto[0]	121	1			T9	1		T15	1		T39	1
auto[0]	auto[1]	valid[4]	auto[1]	173	1			T73	1		T75	2		T324	3
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T1	1		T15	1		T25	1
auto[1]	auto[0]	valid[1]	auto[0]	63	1			T9	1		T10	1		T15	1
auto[1]	auto[0]	valid[2]	auto[0]	72	1			T15	1		T27	1		T39	2
auto[1]	auto[0]	valid[3]	auto[0]	81	1			T9	2		T27	1		T91	1
auto[1]	auto[0]	valid[4]	auto[0]	61	1			T1	1		T10	1		T14	1
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T9	1		T15	1		T39	1
auto[1]	auto[1]	valid[1]	auto[0]	75	1			T15	1		T37	1		T65	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T10	1		T64	2		T312	1
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T1	1		T9	2		T10	1
auto[1]	auto[1]	valid[4]	auto[0]	70	1			T9	1		T15	2		T25	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal