Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46696

1

T1

209

T6

27

T9

277

auto[1]

18694

1

T10

36

T14

18

T15

55

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48244

1

T1

135

T6

21

T9

184

auto[1]

17146

1

T1

74

T6

6

T9

93

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33680	1			T1	113		T6	11		T9	144
others[1]	5473	1			T1	18		T6	1		T9	29
others[2]	5414	1			T1	15		T6	3		T9	18
others[3]	6340	1			T1	18		T6	1		T9	20
interest[1]	3611	1			T1	13		T6	1		T9	12
interest[4]	22046	1			T1	68		T6	8		T9	83
interest[64]	10872	1			T1	32		T6	10		T9	54

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15247	1			T1	73		T6	8		T9	100
auto[0]	auto[0]	others[1]	2519	1			T1	10		T9	17		T10	11
auto[0]	auto[0]	others[2]	2463	1			T1	10		T6	3		T9	14
auto[0]	auto[0]	others[3]	2805	1			T1	13		T6	1		T9	11
auto[0]	auto[0]	interest[1]	1613	1			T1	9		T9	7		T10	8
auto[0]	auto[0]	interest[4]	9860	1			T1	41		T6	6		T9	57
auto[0]	auto[0]	interest[64]	4903	1			T1	20		T6	9		T9	35
auto[0]	auto[1]	others[0]	9768	1			T10	19		T14	12		T15	31
auto[0]	auto[1]	others[1]	1544	1			T10	1		T14	2		T15	1
auto[0]	auto[1]	others[2]	1520	1			T10	4		T15	1		T25	1
auto[0]	auto[1]	others[3]	1780	1			T10	3		T14	2		T15	8
auto[0]	auto[1]	interest[1]	1031	1			T10	2		T15	3		T25	1
auto[0]	auto[1]	interest[4]	6482	1			T10	14		T14	8		T15	21
auto[0]	auto[1]	interest[64]	3051	1			T10	7		T14	2		T15	11
auto[1]	auto[0]	others[0]	8665	1			T1	40		T6	3		T9	44
auto[1]	auto[0]	others[1]	1410	1			T1	8		T6	1		T9	12
auto[1]	auto[0]	others[2]	1431	1			T1	5		T9	4		T10	20
auto[1]	auto[0]	others[3]	1755	1			T1	5		T9	9		T10	17
auto[1]	auto[0]	interest[1]	967	1			T1	4		T6	1		T9	5
auto[1]	auto[0]	interest[4]	5704	1			T1	27		T6	2		T9	26
auto[1]	auto[0]	interest[64]	2918	1			T1	12		T6	1		T9	19

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal