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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 94.01 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1131
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T69 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.251535629 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:23 PM PDT 24 20499180 ps
T1031 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3962678552 Jul 19 04:47:53 PM PDT 24 Jul 19 04:48:15 PM PDT 24 623275744 ps
T1032 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1944388477 Jul 19 04:47:56 PM PDT 24 Jul 19 04:48:28 PM PDT 24 7574855640 ps
T112 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1331751616 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:35 PM PDT 24 100949362 ps
T1033 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2067379831 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:23 PM PDT 24 82979640 ps
T94 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3838693255 Jul 19 04:48:10 PM PDT 24 Jul 19 04:48:30 PM PDT 24 73753935 ps
T1034 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.265760523 Jul 19 04:48:06 PM PDT 24 Jul 19 04:48:24 PM PDT 24 15023923 ps
T113 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3958624942 Jul 19 04:47:48 PM PDT 24 Jul 19 04:48:10 PM PDT 24 135655110 ps
T1035 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.263991652 Jul 19 04:48:13 PM PDT 24 Jul 19 04:48:33 PM PDT 24 33246970 ps
T114 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.214140919 Jul 19 04:47:55 PM PDT 24 Jul 19 04:48:48 PM PDT 24 7216920235 ps
T159 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3731636548 Jul 19 04:47:42 PM PDT 24 Jul 19 04:48:18 PM PDT 24 1521874792 ps
T115 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3642581352 Jul 19 04:48:01 PM PDT 24 Jul 19 04:48:20 PM PDT 24 239722065 ps
T116 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.957479485 Jul 19 04:47:52 PM PDT 24 Jul 19 04:48:13 PM PDT 24 446970217 ps
T98 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4000202514 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:35 PM PDT 24 59811566 ps
T70 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2084761859 Jul 19 04:47:48 PM PDT 24 Jul 19 04:48:08 PM PDT 24 78741132 ps
T160 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1273520676 Jul 19 04:47:55 PM PDT 24 Jul 19 04:48:26 PM PDT 24 834782113 ps
T1036 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2893767855 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:36 PM PDT 24 11065169 ps
T1037 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3206903534 Jul 19 04:48:13 PM PDT 24 Jul 19 04:48:33 PM PDT 24 23709068 ps
T1038 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.50390321 Jul 19 04:47:53 PM PDT 24 Jul 19 04:48:14 PM PDT 24 73952074 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2336028925 Jul 19 04:48:05 PM PDT 24 Jul 19 04:48:26 PM PDT 24 642156375 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4180861482 Jul 19 04:48:05 PM PDT 24 Jul 19 04:48:26 PM PDT 24 792487928 ps
T117 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.584427472 Jul 19 04:47:56 PM PDT 24 Jul 19 04:48:16 PM PDT 24 30882343 ps
T1041 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.46109481 Jul 19 04:48:17 PM PDT 24 Jul 19 04:48:41 PM PDT 24 1271044396 ps
T1042 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3404987069 Jul 19 04:48:07 PM PDT 24 Jul 19 04:48:25 PM PDT 24 11810396 ps
T118 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3401598285 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:20 PM PDT 24 6780415061 ps
T161 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1868931817 Jul 19 04:48:02 PM PDT 24 Jul 19 04:48:27 PM PDT 24 680186889 ps
T1043 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2153593320 Jul 19 04:47:54 PM PDT 24 Jul 19 04:48:14 PM PDT 24 150737041 ps
T1044 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2998889304 Jul 19 04:48:00 PM PDT 24 Jul 19 04:48:18 PM PDT 24 60144339 ps
T99 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1989702318 Jul 19 04:48:19 PM PDT 24 Jul 19 04:48:42 PM PDT 24 309047743 ps
T1045 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3346837385 Jul 19 04:47:46 PM PDT 24 Jul 19 04:48:08 PM PDT 24 90601548 ps
T95 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3822297501 Jul 19 04:47:58 PM PDT 24 Jul 19 04:48:17 PM PDT 24 195462334 ps
T1046 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2648040414 Jul 19 04:47:57 PM PDT 24 Jul 19 04:48:37 PM PDT 24 7538934042 ps
T119 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2006551217 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:23 PM PDT 24 38853028 ps
T1047 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.212465953 Jul 19 04:47:55 PM PDT 24 Jul 19 04:48:13 PM PDT 24 20130533 ps
T1048 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3536678894 Jul 19 04:48:00 PM PDT 24 Jul 19 04:48:18 PM PDT 24 13202914 ps
T1049 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3724087551 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:22 PM PDT 24 17434517 ps
T1050 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.272792705 Jul 19 04:47:45 PM PDT 24 Jul 19 04:48:05 PM PDT 24 16807259 ps
T1051 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4152061497 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:39 PM PDT 24 18040321 ps
T1052 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1188199044 Jul 19 04:48:11 PM PDT 24 Jul 19 04:48:33 PM PDT 24 500129384 ps
T120 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3800722040 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:06 PM PDT 24 198380435 ps
T1053 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1936249862 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:23 PM PDT 24 89151614 ps
T97 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2673656411 Jul 19 04:48:18 PM PDT 24 Jul 19 04:48:55 PM PDT 24 599069006 ps
T1054 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3677971212 Jul 19 04:47:57 PM PDT 24 Jul 19 04:48:17 PM PDT 24 63102981 ps
T167 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1800347297 Jul 19 04:48:01 PM PDT 24 Jul 19 04:48:37 PM PDT 24 606715240 ps
T1055 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2789576750 Jul 19 04:48:10 PM PDT 24 Jul 19 04:48:30 PM PDT 24 100004912 ps
T1056 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3146843344 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:48 PM PDT 24 791651012 ps
T100 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2037419846 Jul 19 04:47:56 PM PDT 24 Jul 19 04:48:18 PM PDT 24 173638219 ps
T1057 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3898326530 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:22 PM PDT 24 130228701 ps
T1058 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1644004988 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:23 PM PDT 24 203407735 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1985773377 Jul 19 04:47:43 PM PDT 24 Jul 19 04:48:04 PM PDT 24 61320172 ps
T1060 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.106726086 Jul 19 04:47:57 PM PDT 24 Jul 19 04:48:17 PM PDT 24 87588969 ps
T1061 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.944670760 Jul 19 04:47:51 PM PDT 24 Jul 19 04:48:16 PM PDT 24 989782259 ps
T101 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.873959938 Jul 19 04:47:47 PM PDT 24 Jul 19 04:48:10 PM PDT 24 565771311 ps
T1062 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1669618584 Jul 19 04:48:19 PM PDT 24 Jul 19 04:48:40 PM PDT 24 60849523 ps
T1063 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.831574997 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:39 PM PDT 24 337531279 ps
T1064 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3267215068 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:07 PM PDT 24 109154484 ps
T168 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3329179244 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:14 PM PDT 24 776198508 ps
T166 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3909000505 Jul 19 04:48:00 PM PDT 24 Jul 19 04:48:29 PM PDT 24 371357553 ps
T1065 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.829868414 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:22 PM PDT 24 67949878 ps
T121 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2393749778 Jul 19 04:47:59 PM PDT 24 Jul 19 04:48:18 PM PDT 24 30592475 ps
T163 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.258825539 Jul 19 04:48:13 PM PDT 24 Jul 19 04:48:48 PM PDT 24 729872879 ps
T1066 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1254526356 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:36 PM PDT 24 1513930707 ps
T1067 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3430636746 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:24 PM PDT 24 220129482 ps
T1068 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3766728858 Jul 19 04:48:12 PM PDT 24 Jul 19 04:48:34 PM PDT 24 154602226 ps
T1069 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2584894011 Jul 19 04:47:57 PM PDT 24 Jul 19 04:48:37 PM PDT 24 6198764156 ps
T1070 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3104475151 Jul 19 04:47:46 PM PDT 24 Jul 19 04:48:05 PM PDT 24 14033686 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3542431941 Jul 19 04:47:47 PM PDT 24 Jul 19 04:48:09 PM PDT 24 561745856 ps
T164 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.450440006 Jul 19 04:48:00 PM PDT 24 Jul 19 04:48:35 PM PDT 24 1196212619 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.926432597 Jul 19 04:48:06 PM PDT 24 Jul 19 04:48:24 PM PDT 24 14865022 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1391535566 Jul 19 04:47:56 PM PDT 24 Jul 19 04:48:18 PM PDT 24 261464378 ps
T1074 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1951888836 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:40 PM PDT 24 61108150 ps
T1075 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3161784107 Jul 19 04:48:01 PM PDT 24 Jul 19 04:48:20 PM PDT 24 40955045 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.781570958 Jul 19 04:47:54 PM PDT 24 Jul 19 04:48:13 PM PDT 24 203002088 ps
T1077 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2083237343 Jul 19 04:48:21 PM PDT 24 Jul 19 04:48:42 PM PDT 24 306569535 ps
T1078 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1658874187 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:22 PM PDT 24 21308893 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3731800705 Jul 19 04:48:05 PM PDT 24 Jul 19 04:48:26 PM PDT 24 185424156 ps
T1080 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1081334442 Jul 19 04:48:01 PM PDT 24 Jul 19 04:48:26 PM PDT 24 6226438059 ps
T1081 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2569295794 Jul 19 04:47:43 PM PDT 24 Jul 19 04:48:14 PM PDT 24 609697342 ps
T1082 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3476678277 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:22 PM PDT 24 160414341 ps
T1083 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3366019405 Jul 19 04:48:00 PM PDT 24 Jul 19 04:48:22 PM PDT 24 159792916 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3177430414 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:24 PM PDT 24 48335701 ps
T1085 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3398699792 Jul 19 04:48:14 PM PDT 24 Jul 19 04:48:33 PM PDT 24 28853726 ps
T1086 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1700110938 Jul 19 04:47:46 PM PDT 24 Jul 19 04:48:11 PM PDT 24 340944336 ps
T1087 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2104669843 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:22 PM PDT 24 13275785 ps
T1088 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4167198440 Jul 19 04:48:20 PM PDT 24 Jul 19 04:48:39 PM PDT 24 17569866 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1475627867 Jul 19 04:47:46 PM PDT 24 Jul 19 04:48:06 PM PDT 24 62374895 ps
T1090 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.25329098 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:21 PM PDT 24 39824696 ps
T1091 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2140318063 Jul 19 04:47:47 PM PDT 24 Jul 19 04:48:08 PM PDT 24 31149729 ps
T1092 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1833129236 Jul 19 04:48:08 PM PDT 24 Jul 19 04:48:27 PM PDT 24 13639503 ps
T1093 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2773759123 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:04 PM PDT 24 34088184 ps
T1094 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2802023394 Jul 19 04:47:57 PM PDT 24 Jul 19 04:48:18 PM PDT 24 101530872 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.727403251 Jul 19 04:47:54 PM PDT 24 Jul 19 04:48:16 PM PDT 24 535974048 ps
T162 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3574385790 Jul 19 04:47:53 PM PDT 24 Jul 19 04:48:18 PM PDT 24 113292666 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2967410930 Jul 19 04:47:45 PM PDT 24 Jul 19 04:48:09 PM PDT 24 112580854 ps
T1097 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.408186705 Jul 19 04:48:04 PM PDT 24 Jul 19 04:48:22 PM PDT 24 31672515 ps
T1098 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2999120614 Jul 19 04:47:52 PM PDT 24 Jul 19 04:48:14 PM PDT 24 121613333 ps
T1099 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2653057005 Jul 19 04:47:42 PM PDT 24 Jul 19 04:48:09 PM PDT 24 1530068896 ps
T1100 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1565198830 Jul 19 04:48:06 PM PDT 24 Jul 19 04:48:24 PM PDT 24 68681652 ps
T1101 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.818655474 Jul 19 04:47:53 PM PDT 24 Jul 19 04:48:13 PM PDT 24 105788029 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.335397815 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:06 PM PDT 24 450714299 ps
T1103 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1341803985 Jul 19 04:48:05 PM PDT 24 Jul 19 04:48:24 PM PDT 24 140379178 ps
T1104 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1528408569 Jul 19 04:48:05 PM PDT 24 Jul 19 04:48:38 PM PDT 24 682647671 ps
T1105 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2709332523 Jul 19 04:47:43 PM PDT 24 Jul 19 04:48:03 PM PDT 24 14908229 ps
T1106 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.556959775 Jul 19 04:47:43 PM PDT 24 Jul 19 04:48:10 PM PDT 24 523438367 ps
T1107 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3286315360 Jul 19 04:47:57 PM PDT 24 Jul 19 04:48:16 PM PDT 24 35545355 ps
T1108 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1818824052 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:05 PM PDT 24 43062700 ps
T71 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3032001365 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:03 PM PDT 24 24604350 ps
T1109 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.914896270 Jul 19 04:47:52 PM PDT 24 Jul 19 04:48:15 PM PDT 24 262615175 ps
T1110 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2078172475 Jul 19 04:47:59 PM PDT 24 Jul 19 04:48:18 PM PDT 24 243943771 ps
T1111 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4191736465 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:26 PM PDT 24 655787120 ps
T1112 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.254165305 Jul 19 04:48:08 PM PDT 24 Jul 19 04:48:29 PM PDT 24 102277725 ps
T1113 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2618988289 Jul 19 04:48:02 PM PDT 24 Jul 19 04:48:21 PM PDT 24 48592281 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.777960158 Jul 19 04:47:48 PM PDT 24 Jul 19 04:48:08 PM PDT 24 12044864 ps
T1115 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.47796553 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:06 PM PDT 24 177987081 ps
T1116 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1367923992 Jul 19 04:48:02 PM PDT 24 Jul 19 04:48:21 PM PDT 24 262223150 ps
T1117 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3070927467 Jul 19 04:48:07 PM PDT 24 Jul 19 04:48:27 PM PDT 24 223951550 ps
T1118 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2864408928 Jul 19 04:47:48 PM PDT 24 Jul 19 04:48:10 PM PDT 24 48623288 ps
T1119 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2535340107 Jul 19 04:47:54 PM PDT 24 Jul 19 04:48:14 PM PDT 24 86103871 ps
T1120 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2154654385 Jul 19 04:47:43 PM PDT 24 Jul 19 04:48:04 PM PDT 24 105642371 ps
T1121 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2566449655 Jul 19 04:48:16 PM PDT 24 Jul 19 04:48:39 PM PDT 24 97650446 ps
T1122 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.71074041 Jul 19 04:48:07 PM PDT 24 Jul 19 04:48:39 PM PDT 24 2230426242 ps
T1123 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2269829559 Jul 19 04:48:06 PM PDT 24 Jul 19 04:48:24 PM PDT 24 14211321 ps
T1124 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1063782397 Jul 19 04:47:45 PM PDT 24 Jul 19 04:48:06 PM PDT 24 90036659 ps
T1125 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3472081185 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:35 PM PDT 24 18896798 ps
T1126 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3790190651 Jul 19 04:47:46 PM PDT 24 Jul 19 04:48:08 PM PDT 24 27897490 ps
T1127 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1874085527 Jul 19 04:48:15 PM PDT 24 Jul 19 04:48:35 PM PDT 24 126535647 ps
T1128 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.374385249 Jul 19 04:48:10 PM PDT 24 Jul 19 04:48:28 PM PDT 24 29001756 ps
T165 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.935047599 Jul 19 04:48:05 PM PDT 24 Jul 19 04:48:30 PM PDT 24 3564719984 ps
T1129 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1661546748 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:21 PM PDT 24 15594923 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3791685388 Jul 19 04:47:44 PM PDT 24 Jul 19 04:48:03 PM PDT 24 38389120 ps
T1131 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3275869304 Jul 19 04:48:03 PM PDT 24 Jul 19 04:48:22 PM PDT 24 29547015 ps

Test location /workspace/coverage/default/12.spi_device_stress_all.2379225272
Short name T6
Test name
Test status
Simulation time 43697567937 ps
CPU time 350.84 seconds
Started Jul 19 06:17:37 PM PDT 24
Finished Jul 19 06:23:29 PM PDT 24
Peak memory 268516 kb
Host smart-03c2cfea-f7f4-44cb-a4ef-6157927c9370
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379225272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2379225272
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3312876356
Short name T1
Test name
Test status
Simulation time 15901068268 ps
CPU time 20.93 seconds
Started Jul 19 06:20:06 PM PDT 24
Finished Jul 19 06:20:29 PM PDT 24
Peak memory 216708 kb
Host smart-2abce129-920d-4472-8f8a-4b9496edea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312876356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3312876356
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1124896320
Short name T15
Test name
Test status
Simulation time 16582187019 ps
CPU time 166.7 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:22:59 PM PDT 24
Peak memory 241480 kb
Host smart-5497bb70-4aef-4f35-b9b4-46d50d3a5c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124896320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1124896320
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1430345982
Short name T58
Test name
Test status
Simulation time 675548326 ps
CPU time 13.7 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 215108 kb
Host smart-33c7537e-59b7-4801-a1a2-fb1e50a4fd97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430345982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1430345982
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1612944255
Short name T66
Test name
Test status
Simulation time 74720855407 ps
CPU time 355.03 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:27:28 PM PDT 24
Peak memory 257880 kb
Host smart-98f90cc6-61b1-46a7-bba7-ed58b3d53930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612944255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1612944255
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2096885815
Short name T157
Test name
Test status
Simulation time 6746077135 ps
CPU time 105.92 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 253120 kb
Host smart-b73d2f89-ef93-4b2b-8006-36c9e42a90c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096885815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2096885815
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.134141383
Short name T59
Test name
Test status
Simulation time 22964769 ps
CPU time 0.75 seconds
Started Jul 19 06:14:43 PM PDT 24
Finished Jul 19 06:14:44 PM PDT 24
Peak memory 216532 kb
Host smart-c900ee0c-f9eb-47b0-b77d-62d6b58584f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134141383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.134141383
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1339803153
Short name T23
Test name
Test status
Simulation time 79644013687 ps
CPU time 655.53 seconds
Started Jul 19 06:15:40 PM PDT 24
Finished Jul 19 06:26:37 PM PDT 24
Peak memory 274072 kb
Host smart-65fb78bf-edff-4c92-a96b-678d9bf1d14e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339803153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1339803153
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1405556917
Short name T22
Test name
Test status
Simulation time 410841183448 ps
CPU time 351.33 seconds
Started Jul 19 06:21:18 PM PDT 24
Finished Jul 19 06:27:10 PM PDT 24
Peak memory 252348 kb
Host smart-efd3e8ac-202b-4c8b-ac18-19e83fe13dd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405556917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1405556917
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2022957642
Short name T38
Test name
Test status
Simulation time 316277579895 ps
CPU time 550.39 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:28:51 PM PDT 24
Peak memory 265964 kb
Host smart-a7302663-4d7a-4086-a638-8b4c8135a8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022957642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2022957642
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2938829659
Short name T42
Test name
Test status
Simulation time 37197707707 ps
CPU time 356.59 seconds
Started Jul 19 06:16:30 PM PDT 24
Finished Jul 19 06:22:27 PM PDT 24
Peak memory 272940 kb
Host smart-f98559f5-d9b9-48d4-b07a-71ef9e918d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938829659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2938829659
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.240565521
Short name T56
Test name
Test status
Simulation time 437472310 ps
CPU time 5.03 seconds
Started Jul 19 04:48:11 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 215404 kb
Host smart-e93d9eac-2a66-44cb-a724-86e35470a528
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240565521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.240565521
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1220683346
Short name T18
Test name
Test status
Simulation time 45225598 ps
CPU time 1.01 seconds
Started Jul 19 06:15:04 PM PDT 24
Finished Jul 19 06:15:06 PM PDT 24
Peak memory 236580 kb
Host smart-1afa8635-87e4-4277-8abf-8379211a5746
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220683346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1220683346
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1734413870
Short name T200
Test name
Test status
Simulation time 76483144506 ps
CPU time 184.82 seconds
Started Jul 19 06:19:44 PM PDT 24
Finished Jul 19 06:22:50 PM PDT 24
Peak memory 257848 kb
Host smart-969e7fb6-2c36-4fb9-966e-2132bceddebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734413870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1734413870
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1269094816
Short name T142
Test name
Test status
Simulation time 3936510132 ps
CPU time 14.5 seconds
Started Jul 19 06:14:50 PM PDT 24
Finished Jul 19 06:15:06 PM PDT 24
Peak memory 225016 kb
Host smart-5db3f0a2-361f-485f-82b0-7ed7fdefed66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269094816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1269094816
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.3993465215
Short name T35
Test name
Test status
Simulation time 71439803466 ps
CPU time 627.17 seconds
Started Jul 19 06:18:36 PM PDT 24
Finished Jul 19 06:29:04 PM PDT 24
Peak memory 264860 kb
Host smart-cca3c715-5806-453e-8ad5-ff0f5dd0e22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993465215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.3993465215
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.1287927221
Short name T76
Test name
Test status
Simulation time 59690741189 ps
CPU time 174.02 seconds
Started Jul 19 06:21:02 PM PDT 24
Finished Jul 19 06:23:57 PM PDT 24
Peak memory 254636 kb
Host smart-c1b5e4b0-5028-4fe6-ad8c-5ea262fe82e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287927221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.1287927221
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.251535629
Short name T69
Test name
Test status
Simulation time 20499180 ps
CPU time 1.16 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:23 PM PDT 24
Peak memory 206960 kb
Host smart-024ef7bb-20dd-47c8-b370-cddae658e24b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251535629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.251535629
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1242337032
Short name T48
Test name
Test status
Simulation time 37560138170 ps
CPU time 200.08 seconds
Started Jul 19 06:16:21 PM PDT 24
Finished Jul 19 06:19:42 PM PDT 24
Peak memory 249616 kb
Host smart-da6369ec-6733-4bd6-be3d-216a428142d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242337032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1242337032
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.850072134
Short name T63
Test name
Test status
Simulation time 16956297904 ps
CPU time 200.1 seconds
Started Jul 19 06:15:34 PM PDT 24
Finished Jul 19 06:18:55 PM PDT 24
Peak memory 249664 kb
Host smart-26bcbfbc-22d9-4bb2-a53a-0a76c1177b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850072134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
850072134
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2582966005
Short name T226
Test name
Test status
Simulation time 65540757461 ps
CPU time 473.18 seconds
Started Jul 19 06:19:44 PM PDT 24
Finished Jul 19 06:27:38 PM PDT 24
Peak memory 265932 kb
Host smart-ea3d84cb-1ac9-4cd2-a4d3-b8a932d137b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582966005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2582966005
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1796779112
Short name T125
Test name
Test status
Simulation time 19642515224 ps
CPU time 202.53 seconds
Started Jul 19 06:21:16 PM PDT 24
Finished Jul 19 06:24:39 PM PDT 24
Peak memory 273704 kb
Host smart-baf069a0-19e6-450c-9dc9-25926d7fdde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796779112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1796779112
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.2189896012
Short name T24
Test name
Test status
Simulation time 11682857694 ps
CPU time 160.53 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:22:20 PM PDT 24
Peak memory 251340 kb
Host smart-34a6df6c-04f5-42a4-a90d-ec1c6f3aad31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189896012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.2189896012
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3485134630
Short name T794
Test name
Test status
Simulation time 2925553525 ps
CPU time 64.78 seconds
Started Jul 19 06:18:36 PM PDT 24
Finished Jul 19 06:19:42 PM PDT 24
Peak memory 249676 kb
Host smart-f320cefc-5dc4-490e-b3e9-444378c6ade4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485134630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3485134630
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4009302550
Short name T297
Test name
Test status
Simulation time 36683328590 ps
CPU time 242.59 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:23:51 PM PDT 24
Peak memory 252616 kb
Host smart-e34d64f3-e43c-4e18-adb5-9f7fb52c425b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009302550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4009302550
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2950673805
Short name T279
Test name
Test status
Simulation time 71534787332 ps
CPU time 288.72 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:22:19 PM PDT 24
Peak memory 281916 kb
Host smart-b9693176-6ec2-4dde-a46e-8f7996a5ea49
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950673805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2950673805
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3320554385
Short name T737
Test name
Test status
Simulation time 23603994361 ps
CPU time 148.8 seconds
Started Jul 19 06:16:38 PM PDT 24
Finished Jul 19 06:19:07 PM PDT 24
Peak memory 256828 kb
Host smart-2ae38b0d-47ad-4b26-a3e8-adddbcae3b05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320554385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3320554385
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1046693567
Short name T384
Test name
Test status
Simulation time 25953636 ps
CPU time 0.71 seconds
Started Jul 19 06:17:14 PM PDT 24
Finished Jul 19 06:17:15 PM PDT 24
Peak memory 205924 kb
Host smart-eac0ade3-1ddb-4c51-8789-d68ca511ad17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046693567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1046693567
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.522033547
Short name T196
Test name
Test status
Simulation time 58839093070 ps
CPU time 130.15 seconds
Started Jul 19 06:20:10 PM PDT 24
Finished Jul 19 06:22:21 PM PDT 24
Peak memory 256876 kb
Host smart-a505bfdc-e002-4ded-b2c7-a5cb0049f496
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522033547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.522033547
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2400383183
Short name T211
Test name
Test status
Simulation time 114261674401 ps
CPU time 294.7 seconds
Started Jul 19 06:14:56 PM PDT 24
Finished Jul 19 06:19:51 PM PDT 24
Peak memory 255500 kb
Host smart-61a8b610-5be7-4fdc-b6e6-c0e6dd0b8447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400383183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2400383183
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3585271014
Short name T302
Test name
Test status
Simulation time 6651534910 ps
CPU time 13 seconds
Started Jul 19 06:20:18 PM PDT 24
Finished Jul 19 06:20:32 PM PDT 24
Peak memory 225112 kb
Host smart-55cde2a8-8abd-44e1-b16b-d0d0b7e8ae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585271014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3585271014
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.990701315
Short name T136
Test name
Test status
Simulation time 38152588614 ps
CPU time 280.38 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:22:23 PM PDT 24
Peak memory 250568 kb
Host smart-d2e91a0d-4909-445e-bddc-54e2cbde3137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990701315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle
.990701315
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3329179244
Short name T168
Test name
Test status
Simulation time 776198508 ps
CPU time 11.34 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 215304 kb
Host smart-13db5a7c-abc5-42f2-b054-52b0c001f47f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329179244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3329179244
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1723470028
Short name T296
Test name
Test status
Simulation time 29709271771 ps
CPU time 255.1 seconds
Started Jul 19 06:15:24 PM PDT 24
Finished Jul 19 06:19:39 PM PDT 24
Peak memory 252792 kb
Host smart-162b8d05-f448-4fd2-b5db-0f1f4e91bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723470028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1723470028
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1844033011
Short name T171
Test name
Test status
Simulation time 545092860131 ps
CPU time 336.88 seconds
Started Jul 19 06:18:48 PM PDT 24
Finished Jul 19 06:24:27 PM PDT 24
Peak memory 264680 kb
Host smart-fffc7da1-7dfb-4f57-b865-efa13d67d488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844033011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1844033011
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3054855912
Short name T190
Test name
Test status
Simulation time 24052191567 ps
CPU time 86.5 seconds
Started Jul 19 06:18:04 PM PDT 24
Finished Jul 19 06:19:31 PM PDT 24
Peak memory 255932 kb
Host smart-4bd2304d-5a3a-495b-9887-814ec6372199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054855912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3054855912
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1212355364
Short name T169
Test name
Test status
Simulation time 28455483418 ps
CPU time 107.5 seconds
Started Jul 19 06:18:03 PM PDT 24
Finished Jul 19 06:19:51 PM PDT 24
Peak memory 273872 kb
Host smart-0e6a2f62-22bf-4619-8ce6-1e707a01a972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212355364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1212355364
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3488947769
Short name T39
Test name
Test status
Simulation time 52963416301 ps
CPU time 476.78 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:29:22 PM PDT 24
Peak memory 255836 kb
Host smart-dfacb9e8-79df-471c-91f5-3a770e60ff07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488947769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3488947769
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.123858887
Short name T560
Test name
Test status
Simulation time 12186834002 ps
CPU time 157.51 seconds
Started Jul 19 06:21:37 PM PDT 24
Finished Jul 19 06:24:16 PM PDT 24
Peak memory 249616 kb
Host smart-05e9f340-ca4d-49f9-93df-42732f14f528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123858887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.123858887
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2775207334
Short name T225
Test name
Test status
Simulation time 4547176657 ps
CPU time 12.95 seconds
Started Jul 19 06:18:10 PM PDT 24
Finished Jul 19 06:18:23 PM PDT 24
Peak memory 241236 kb
Host smart-4d5a6009-31b7-496e-a0b7-8c799b8cf7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775207334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2775207334
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3366019405
Short name T1083
Test name
Test status
Simulation time 159792916 ps
CPU time 4.87 seconds
Started Jul 19 04:48:00 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 215444 kb
Host smart-361306cd-60c0-4178-82d9-ddc1bef6f4f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366019405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3366019405
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.450440006
Short name T164
Test name
Test status
Simulation time 1196212619 ps
CPU time 17.92 seconds
Started Jul 19 04:48:00 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 215616 kb
Host smart-1723a1d0-4a7f-44a3-b667-0ede7b337a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450440006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.450440006
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3909000505
Short name T166
Test name
Test status
Simulation time 371357553 ps
CPU time 11.81 seconds
Started Jul 19 04:48:00 PM PDT 24
Finished Jul 19 04:48:29 PM PDT 24
Peak memory 216712 kb
Host smart-3c3c1019-71ba-418a-883e-79932725a636
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909000505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3909000505
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.3574385790
Short name T162
Test name
Test status
Simulation time 113292666 ps
CPU time 7.28 seconds
Started Jul 19 04:47:53 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 215232 kb
Host smart-3edae419-b624-433c-8923-dc2bdc75c64c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574385790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.3574385790
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4288039879
Short name T131
Test name
Test status
Simulation time 1595231010 ps
CPU time 9.4 seconds
Started Jul 19 06:15:20 PM PDT 24
Finished Jul 19 06:15:30 PM PDT 24
Peak memory 241344 kb
Host smart-d48d84ac-6f53-4de7-8bc9-eda6ccd74f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288039879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4288039879
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2028185842
Short name T282
Test name
Test status
Simulation time 51508042875 ps
CPU time 178.05 seconds
Started Jul 19 06:17:45 PM PDT 24
Finished Jul 19 06:20:43 PM PDT 24
Peak memory 253020 kb
Host smart-08a8c0c4-d715-4a06-b5bf-b80412b02857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028185842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2028185842
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2397847146
Short name T288
Test name
Test status
Simulation time 20861729769 ps
CPU time 215.89 seconds
Started Jul 19 06:18:07 PM PDT 24
Finished Jul 19 06:21:43 PM PDT 24
Peak memory 268972 kb
Host smart-02a8ac84-4337-40f5-b0ac-a7d6f7290da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397847146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2397847146
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3485605027
Short name T301
Test name
Test status
Simulation time 2837697332 ps
CPU time 13.22 seconds
Started Jul 19 06:19:52 PM PDT 24
Finished Jul 19 06:20:06 PM PDT 24
Peak memory 224940 kb
Host smart-ff6e943d-ae1c-4f63-bb58-b6cce9356b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485605027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3485605027
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.111977314
Short name T365
Test name
Test status
Simulation time 6965823323 ps
CPU time 19.7 seconds
Started Jul 19 06:15:19 PM PDT 24
Finished Jul 19 06:15:39 PM PDT 24
Peak memory 219876 kb
Host smart-5847d4f4-722c-4dcc-ac67-0bac9be2eb70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=111977314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.111977314
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2673656411
Short name T97
Test name
Test status
Simulation time 599069006 ps
CPU time 17.52 seconds
Started Jul 19 04:48:18 PM PDT 24
Finished Jul 19 04:48:55 PM PDT 24
Peak memory 215316 kb
Host smart-9648d6a7-e4df-4127-9e51-f683ba68f9c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673656411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2673656411
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3032001365
Short name T71
Test name
Test status
Simulation time 24604350 ps
CPU time 0.98 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:03 PM PDT 24
Peak memory 206804 kb
Host smart-c0323026-d99c-4171-b5b6-69d56ceb46a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032001365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3032001365
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1997524624
Short name T807
Test name
Test status
Simulation time 83936503017 ps
CPU time 191.37 seconds
Started Jul 19 06:15:06 PM PDT 24
Finished Jul 19 06:18:18 PM PDT 24
Peak memory 250676 kb
Host smart-cfa83419-a086-40fb-b48a-5e36a4ef05a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997524624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1997524624
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2410449683
Short name T84
Test name
Test status
Simulation time 2939838639 ps
CPU time 11.8 seconds
Started Jul 19 06:18:01 PM PDT 24
Finished Jul 19 06:18:13 PM PDT 24
Peak memory 238996 kb
Host smart-c91e50e3-647d-45f3-9ab2-af0cf535122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410449683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2410449683
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.2653057005
Short name T1099
Test name
Test status
Simulation time 1530068896 ps
CPU time 8.11 seconds
Started Jul 19 04:47:42 PM PDT 24
Finished Jul 19 04:48:09 PM PDT 24
Peak memory 207200 kb
Host smart-eb737b64-8dd3-4cc4-a466-200515c2c4f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653057005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.2653057005
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2648040414
Short name T1046
Test name
Test status
Simulation time 7538934042 ps
CPU time 22.33 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 215232 kb
Host smart-ff600265-e345-4807-ad58-2d8b1f292887
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648040414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2648040414
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1818824052
Short name T1108
Test name
Test status
Simulation time 43062700 ps
CPU time 1.37 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:05 PM PDT 24
Peak memory 206968 kb
Host smart-bdd02f7a-fd07-40b0-a8ed-8f95befe726f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818824052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1818824052
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1985773377
Short name T1059
Test name
Test status
Simulation time 61320172 ps
CPU time 1.84 seconds
Started Jul 19 04:47:43 PM PDT 24
Finished Jul 19 04:48:04 PM PDT 24
Peak memory 216360 kb
Host smart-6d95188f-101e-479b-88ed-70684249c6c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985773377 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1985773377
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.335397815
Short name T1102
Test name
Test status
Simulation time 450714299 ps
CPU time 2.83 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:06 PM PDT 24
Peak memory 215204 kb
Host smart-687c8f5e-28f6-4198-a3ce-1d1936005301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335397815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.335397815
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2773759123
Short name T1093
Test name
Test status
Simulation time 34088184 ps
CPU time 0.79 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:04 PM PDT 24
Peak memory 203824 kb
Host smart-270328f6-0374-410a-b866-8d79de167fc3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773759123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
773759123
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3800722040
Short name T120
Test name
Test status
Simulation time 198380435 ps
CPU time 1.71 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:06 PM PDT 24
Peak memory 215308 kb
Host smart-8c148334-afee-4598-8837-70310fe89fe1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800722040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3800722040
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.777960158
Short name T1114
Test name
Test status
Simulation time 12044864 ps
CPU time 0.67 seconds
Started Jul 19 04:47:48 PM PDT 24
Finished Jul 19 04:48:08 PM PDT 24
Peak memory 203604 kb
Host smart-c2ed04c5-72fd-4489-863d-cbb136a0e7d2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777960158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.777960158
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.49922457
Short name T147
Test name
Test status
Simulation time 584757438 ps
CPU time 3.65 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:19 PM PDT 24
Peak memory 215276 kb
Host smart-f48b338b-bc70-42b4-a164-8c7fcd803fed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49922457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_same_csr_outstanding.49922457
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1391535566
Short name T1073
Test name
Test status
Simulation time 261464378 ps
CPU time 3.14 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 215404 kb
Host smart-56f61d3a-702b-4d7a-a5b8-eb5975912650
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391535566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
391535566
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3401598285
Short name T118
Test name
Test status
Simulation time 6780415061 ps
CPU time 16.69 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:20 PM PDT 24
Peak memory 207188 kb
Host smart-36deb84b-6a83-45a8-b542-b4e6e9de9bc6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401598285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3401598285
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2569295794
Short name T1081
Test name
Test status
Simulation time 609697342 ps
CPU time 12.31 seconds
Started Jul 19 04:47:43 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 207156 kb
Host smart-e024d1e6-ad8b-4417-9f78-2b9233111aca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569295794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2569295794
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.47796553
Short name T1115
Test name
Test status
Simulation time 177987081 ps
CPU time 1.67 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:06 PM PDT 24
Peak memory 215520 kb
Host smart-2308f268-fe5e-45a5-8105-942f9872a4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47796553 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.47796553
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3677971212
Short name T1054
Test name
Test status
Simulation time 63102981 ps
CPU time 1.35 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:17 PM PDT 24
Peak memory 207072 kb
Host smart-f475703f-078f-441f-839a-4bc5ab4051ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677971212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
677971212
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2709332523
Short name T1105
Test name
Test status
Simulation time 14908229 ps
CPU time 0.75 seconds
Started Jul 19 04:47:43 PM PDT 24
Finished Jul 19 04:48:03 PM PDT 24
Peak memory 203948 kb
Host smart-2fc12048-3f54-4d80-93db-f0a3e51c8263
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709332523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
709332523
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2154654385
Short name T1120
Test name
Test status
Simulation time 105642371 ps
CPU time 2.13 seconds
Started Jul 19 04:47:43 PM PDT 24
Finished Jul 19 04:48:04 PM PDT 24
Peak memory 215364 kb
Host smart-47ab0d7c-974b-48b7-a11f-84e07d6394d3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154654385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2154654385
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3286315360
Short name T1107
Test name
Test status
Simulation time 35545355 ps
CPU time 0.68 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:16 PM PDT 24
Peak memory 203676 kb
Host smart-e6f975d6-f385-4c1a-aeec-5dd6bed187d3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286315360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3286315360
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3790190651
Short name T1126
Test name
Test status
Simulation time 27897490 ps
CPU time 1.8 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:08 PM PDT 24
Peak memory 215312 kb
Host smart-600e4fad-2dda-4a0a-ad84-80e669a4d46f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790190651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3790190651
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2864408928
Short name T1118
Test name
Test status
Simulation time 48623288 ps
CPU time 2.81 seconds
Started Jul 19 04:47:48 PM PDT 24
Finished Jul 19 04:48:10 PM PDT 24
Peak memory 215288 kb
Host smart-b7d4ecd0-c775-40c7-868e-d1d0a467382c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864408928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
864408928
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.556959775
Short name T1106
Test name
Test status
Simulation time 523438367 ps
CPU time 7.6 seconds
Started Jul 19 04:47:43 PM PDT 24
Finished Jul 19 04:48:10 PM PDT 24
Peak memory 215224 kb
Host smart-63bb027e-be52-4f5e-a905-1c2b11a9ca09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556959775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.556959775
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.818655474
Short name T1101
Test name
Test status
Simulation time 105788029 ps
CPU time 1.89 seconds
Started Jul 19 04:47:53 PM PDT 24
Finished Jul 19 04:48:13 PM PDT 24
Peak memory 216256 kb
Host smart-d373e530-af7c-4e22-bc29-4edc63441010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818655474 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.818655474
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.829868414
Short name T1065
Test name
Test status
Simulation time 67949878 ps
CPU time 1.32 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 206968 kb
Host smart-2a790aeb-8786-47cb-aeec-a70e0546c719
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829868414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.829868414
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3398699792
Short name T1085
Test name
Test status
Simulation time 28853726 ps
CPU time 0.69 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 203824 kb
Host smart-2abb8dd1-918f-4930-b39d-9fb35a457056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398699792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3398699792
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.781570958
Short name T1076
Test name
Test status
Simulation time 203002088 ps
CPU time 1.94 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:13 PM PDT 24
Peak memory 215156 kb
Host smart-0d0aef9f-f3dc-4beb-97a6-85c44b6865e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781570958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.781570958
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3430636746
Short name T1067
Test name
Test status
Simulation time 220129482 ps
CPU time 4.04 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 215552 kb
Host smart-81d27489-8aa7-449d-84b6-6cffa569b5ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430636746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3430636746
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.727403251
Short name T1095
Test name
Test status
Simulation time 535974048 ps
CPU time 3.98 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:16 PM PDT 24
Peak memory 216952 kb
Host smart-e5389f5a-73d5-4b43-a64f-39c7708ad905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727403251 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.727403251
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2961320333
Short name T108
Test name
Test status
Simulation time 21286500 ps
CPU time 1.27 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 207020 kb
Host smart-c22d1f36-8c9e-4cbb-aa22-25fbd73837e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961320333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2961320333
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3773977058
Short name T1028
Test name
Test status
Simulation time 38178319 ps
CPU time 0.76 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:12 PM PDT 24
Peak memory 204088 kb
Host smart-9884b382-0d00-431f-9b81-1c04160d2c39
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773977058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3773977058
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.4191736465
Short name T1111
Test name
Test status
Simulation time 655787120 ps
CPU time 4.74 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:26 PM PDT 24
Peak memory 215204 kb
Host smart-f53cac4f-d87f-496b-937e-3ae5d85da1c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191736465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.4191736465
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.925097410
Short name T85
Test name
Test status
Simulation time 199710228 ps
CPU time 5.12 seconds
Started Jul 19 04:48:06 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 215456 kb
Host smart-ca2dd984-7c65-4959-baa5-74a7957f1433
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925097410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.925097410
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.935047599
Short name T165
Test name
Test status
Simulation time 3564719984 ps
CPU time 7.72 seconds
Started Jul 19 04:48:05 PM PDT 24
Finished Jul 19 04:48:30 PM PDT 24
Peak memory 215440 kb
Host smart-102d8fbc-eb6a-4c4b-b7e6-4c7550f63f04
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935047599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.935047599
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1669618584
Short name T1062
Test name
Test status
Simulation time 60849523 ps
CPU time 1.69 seconds
Started Jul 19 04:48:19 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 215568 kb
Host smart-86d9e579-1a2e-47cc-95e9-9908cf4fc2e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669618584 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1669618584
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2535340107
Short name T1119
Test name
Test status
Simulation time 86103871 ps
CPU time 2.21 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 215176 kb
Host smart-1d8a5fe1-b896-4e02-ab1d-ae01eee2a8e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535340107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2535340107
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3183484091
Short name T1024
Test name
Test status
Simulation time 120718879 ps
CPU time 0.73 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:12 PM PDT 24
Peak memory 203812 kb
Host smart-0d54c4c6-1f95-409b-855a-8a4892480146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183484091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3183484091
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3962678552
Short name T1031
Test name
Test status
Simulation time 623275744 ps
CPU time 4.08 seconds
Started Jul 19 04:47:53 PM PDT 24
Finished Jul 19 04:48:15 PM PDT 24
Peak memory 215264 kb
Host smart-c1315da7-66d4-4221-bda1-8e87a41871c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962678552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3962678552
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1392898570
Short name T86
Test name
Test status
Simulation time 617459006 ps
CPU time 7.61 seconds
Started Jul 19 04:47:53 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 215248 kb
Host smart-a317ea17-6c32-40a3-b8c6-6879c3e3718e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392898570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1392898570
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.557849060
Short name T103
Test name
Test status
Simulation time 233865129 ps
CPU time 2.67 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:31 PM PDT 24
Peak memory 216432 kb
Host smart-117c143b-48bd-48fa-a153-460d0732a69d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557849060 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.557849060
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1644004988
Short name T1058
Test name
Test status
Simulation time 203407735 ps
CPU time 2.23 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:23 PM PDT 24
Peak memory 215340 kb
Host smart-88022409-17b0-4b5a-b23f-a0a7ca720aca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1644004988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1644004988
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2035490818
Short name T1020
Test name
Test status
Simulation time 13606490 ps
CPU time 0.74 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 203748 kb
Host smart-f740c51d-2f24-4817-9bf7-f41bce73fcf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035490818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2035490818
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.831574997
Short name T1063
Test name
Test status
Simulation time 337531279 ps
CPU time 4.17 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 215164 kb
Host smart-711db54a-ec46-4e27-bb4e-29b15ec0ac2c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831574997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.831574997
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1254526356
Short name T1066
Test name
Test status
Simulation time 1513930707 ps
CPU time 3.39 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 216376 kb
Host smart-78bc573f-f0a1-40d1-8d51-5d15c944dbed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254526356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1254526356
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1936249862
Short name T1053
Test name
Test status
Simulation time 89151614 ps
CPU time 1.75 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:23 PM PDT 24
Peak memory 215300 kb
Host smart-132ef38d-54af-4d8b-9471-dbde8ead9135
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936249862 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1936249862
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3161784107
Short name T1075
Test name
Test status
Simulation time 40955045 ps
CPU time 1.36 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:20 PM PDT 24
Peak memory 207060 kb
Host smart-ff0c6ea4-3490-4bda-828a-d4ee212ae99e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161784107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3161784107
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.926432597
Short name T1072
Test name
Test status
Simulation time 14865022 ps
CPU time 0.71 seconds
Started Jul 19 04:48:06 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 203832 kb
Host smart-68704de9-3e31-4a1e-9427-564ebd389095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926432597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.926432597
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2566449655
Short name T1121
Test name
Test status
Simulation time 97650446 ps
CPU time 2.65 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 215300 kb
Host smart-9e41a66a-e6ac-4d13-acee-fb052db93433
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566449655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2566449655
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1989702318
Short name T99
Test name
Test status
Simulation time 309047743 ps
CPU time 3.63 seconds
Started Jul 19 04:48:19 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 215436 kb
Host smart-7673f638-863a-42e3-bd05-f0a1fb758240
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989702318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1989702318
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2130543521
Short name T87
Test name
Test status
Simulation time 2589569581 ps
CPU time 7.74 seconds
Started Jul 19 04:48:00 PM PDT 24
Finished Jul 19 04:48:25 PM PDT 24
Peak memory 215488 kb
Host smart-7fc3f298-5ab6-42c8-b074-252ec453b1af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130543521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2130543521
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.254165305
Short name T1112
Test name
Test status
Simulation time 102277725 ps
CPU time 3.33 seconds
Started Jul 19 04:48:08 PM PDT 24
Finished Jul 19 04:48:29 PM PDT 24
Peak memory 217140 kb
Host smart-0bc956fb-047b-4a59-9102-e36d281dbbd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254165305 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.254165305
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3766728858
Short name T1068
Test name
Test status
Simulation time 154602226 ps
CPU time 2.67 seconds
Started Jul 19 04:48:12 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 207124 kb
Host smart-08513b3f-148a-4692-8cc9-8bbbb2c3190c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766728858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3766728858
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2067379831
Short name T1033
Test name
Test status
Simulation time 82979640 ps
CPU time 0.75 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:23 PM PDT 24
Peak memory 203800 kb
Host smart-eb8ae794-4e17-4ead-a0d0-2809ff617fb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067379831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2067379831
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4002253176
Short name T146
Test name
Test status
Simulation time 1277258597 ps
CPU time 3.98 seconds
Started Jul 19 04:48:17 PM PDT 24
Finished Jul 19 04:48:41 PM PDT 24
Peak memory 215076 kb
Host smart-8d0f663f-db6a-4e45-ad48-29aea7ff8e9c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002253176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4002253176
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4000202514
Short name T98
Test name
Test status
Simulation time 59811566 ps
CPU time 1.87 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 215336 kb
Host smart-3b58277a-6d14-4cea-8c0c-7d4f8c82acfd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000202514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4000202514
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.258825539
Short name T163
Test name
Test status
Simulation time 729872879 ps
CPU time 16.22 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:48 PM PDT 24
Peak memory 215272 kb
Host smart-596897ec-7a4d-408c-92bb-374cc5fa2951
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258825539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.258825539
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.46109481
Short name T1041
Test name
Test status
Simulation time 1271044396 ps
CPU time 3.55 seconds
Started Jul 19 04:48:17 PM PDT 24
Finished Jul 19 04:48:41 PM PDT 24
Peak memory 218124 kb
Host smart-e3834721-b939-4348-b4cc-ff29884307d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46109481 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.46109481
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2393749778
Short name T121
Test name
Test status
Simulation time 30592475 ps
CPU time 1.92 seconds
Started Jul 19 04:47:59 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 207128 kb
Host smart-30e771ea-6f26-42d6-b690-88ae189209e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393749778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2393749778
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1661546748
Short name T1129
Test name
Test status
Simulation time 15594923 ps
CPU time 0.76 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 204124 kb
Host smart-7440e2bc-2a22-44c7-a8c2-2f48c075a516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661546748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1661546748
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.4180861482
Short name T1040
Test name
Test status
Simulation time 792487928 ps
CPU time 3.89 seconds
Started Jul 19 04:48:05 PM PDT 24
Finished Jul 19 04:48:26 PM PDT 24
Peak memory 215236 kb
Host smart-22245bb7-f757-46ec-bea1-be7d36270503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180861482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.4180861482
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2083237343
Short name T1077
Test name
Test status
Simulation time 306569535 ps
CPU time 2.37 seconds
Started Jul 19 04:48:21 PM PDT 24
Finished Jul 19 04:48:42 PM PDT 24
Peak memory 215204 kb
Host smart-abcd45f1-8f64-405c-97bf-82998fc87df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083237343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2083237343
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3146843344
Short name T1056
Test name
Test status
Simulation time 791651012 ps
CPU time 11.96 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:48 PM PDT 24
Peak memory 215328 kb
Host smart-1d77f0e9-774e-485e-8757-2a25b19858da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146843344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3146843344
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.1367923992
Short name T1116
Test name
Test status
Simulation time 262223150 ps
CPU time 2.33 seconds
Started Jul 19 04:48:02 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 216372 kb
Host smart-270ffbfc-eb23-4af4-8bc5-4eec4f2bf3ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367923992 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.1367923992
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1876207059
Short name T111
Test name
Test status
Simulation time 98565475 ps
CPU time 2.71 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 215272 kb
Host smart-c3ba3484-46e7-4611-915b-89a7199b16d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876207059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1876207059
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3536678894
Short name T1048
Test name
Test status
Simulation time 13202914 ps
CPU time 0.74 seconds
Started Jul 19 04:48:00 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 203740 kb
Host smart-3125389e-189f-4c70-a9b4-e576f3c9147b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536678894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3536678894
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2336028925
Short name T1039
Test name
Test status
Simulation time 642156375 ps
CPU time 4.07 seconds
Started Jul 19 04:48:05 PM PDT 24
Finished Jul 19 04:48:26 PM PDT 24
Peak memory 215108 kb
Host smart-bdfd33ba-8b54-49bb-89c3-9bbb838f9d3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336028925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2336028925
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1800347297
Short name T167
Test name
Test status
Simulation time 606715240 ps
CPU time 18.57 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 215728 kb
Host smart-614e3bc3-2e58-4193-9f0b-9c75c4825531
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800347297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1800347297
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3731800705
Short name T1079
Test name
Test status
Simulation time 185424156 ps
CPU time 3.55 seconds
Started Jul 19 04:48:05 PM PDT 24
Finished Jul 19 04:48:26 PM PDT 24
Peak memory 217968 kb
Host smart-155d7341-42fb-4f51-8522-135724c66609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731800705 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3731800705
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1331751616
Short name T112
Test name
Test status
Simulation time 100949362 ps
CPU time 2.41 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 215220 kb
Host smart-8eaa6b35-f6b4-454b-921b-8097acfa2a84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331751616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1331751616
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2389186405
Short name T1015
Test name
Test status
Simulation time 39122000 ps
CPU time 0.71 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 203812 kb
Host smart-6a9a1633-9534-414d-afb2-0c751dd305b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389186405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2389186405
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3744555519
Short name T138
Test name
Test status
Simulation time 857356875 ps
CPU time 4.32 seconds
Started Jul 19 04:48:02 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 215188 kb
Host smart-d430ce47-6807-41f7-a797-0fec34c80ad2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744555519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3744555519
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3822297501
Short name T95
Test name
Test status
Simulation time 195462334 ps
CPU time 1.65 seconds
Started Jul 19 04:47:58 PM PDT 24
Finished Jul 19 04:48:17 PM PDT 24
Peak memory 215512 kb
Host smart-96edaf15-910a-4b72-bc1e-3632d5228114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822297501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3822297501
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3070927467
Short name T1117
Test name
Test status
Simulation time 223951550 ps
CPU time 2.77 seconds
Started Jul 19 04:48:07 PM PDT 24
Finished Jul 19 04:48:27 PM PDT 24
Peak memory 217772 kb
Host smart-56b09cbd-92ed-4f5c-b9ce-5c5dbba97f93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070927467 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3070927467
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1874085527
Short name T1127
Test name
Test status
Simulation time 126535647 ps
CPU time 2.1 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 207036 kb
Host smart-4cffe43f-11ee-4cb7-a08f-34e7bd337844
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874085527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1874085527
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2915415154
Short name T1018
Test name
Test status
Simulation time 71125331 ps
CPU time 0.7 seconds
Started Jul 19 04:48:12 PM PDT 24
Finished Jul 19 04:48:31 PM PDT 24
Peak memory 204136 kb
Host smart-3adcd38f-1eeb-4978-b574-634318fb9b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915415154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2915415154
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1188199044
Short name T1052
Test name
Test status
Simulation time 500129384 ps
CPU time 3.15 seconds
Started Jul 19 04:48:11 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 215304 kb
Host smart-f06c8eae-ab7a-4bcc-b20b-f1feae07fb59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188199044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1188199044
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3838693255
Short name T94
Test name
Test status
Simulation time 73753935 ps
CPU time 2.44 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:30 PM PDT 24
Peak memory 215340 kb
Host smart-f6cf6dbb-200d-4490-b469-b116e5f0de7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838693255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3838693255
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1081334442
Short name T1080
Test name
Test status
Simulation time 6226438059 ps
CPU time 7.45 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:26 PM PDT 24
Peak memory 215348 kb
Host smart-de53c8bd-1559-4d01-b051-f4023aa00526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081334442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1081334442
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2584894011
Short name T1069
Test name
Test status
Simulation time 6198764156 ps
CPU time 22.35 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 207116 kb
Host smart-1fc6ffaf-5cff-4a03-8571-1eed612dcb96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584894011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2584894011
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1944388477
Short name T1032
Test name
Test status
Simulation time 7574855640 ps
CPU time 13.11 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 207096 kb
Host smart-4fe589bf-9e12-4e6f-91b8-5a0b9943b669
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944388477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1944388477
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.50390321
Short name T1038
Test name
Test status
Simulation time 73952074 ps
CPU time 2.62 seconds
Started Jul 19 04:47:53 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 217836 kb
Host smart-a05b71fd-cd0d-4fae-b73a-fb6b3a84d97b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50390321 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.50390321
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3346837385
Short name T1045
Test name
Test status
Simulation time 90601548 ps
CPU time 2.66 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:08 PM PDT 24
Peak memory 215232 kb
Host smart-b1a4068d-0371-4536-8bdc-2c9bb6281779
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346837385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
346837385
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.272792705
Short name T1050
Test name
Test status
Simulation time 16807259 ps
CPU time 0.76 seconds
Started Jul 19 04:47:45 PM PDT 24
Finished Jul 19 04:48:05 PM PDT 24
Peak memory 204004 kb
Host smart-c50e6ea6-bf6d-4f3f-bd2a-59d836858bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272792705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.272792705
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2115799777
Short name T109
Test name
Test status
Simulation time 94288116 ps
CPU time 1.78 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:17 PM PDT 24
Peak memory 215332 kb
Host smart-5e95e44e-f6af-43d1-b1f1-4e559d01ed9e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115799777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2115799777
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2301405572
Short name T1014
Test name
Test status
Simulation time 27760942 ps
CPU time 0.65 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:16 PM PDT 24
Peak memory 203972 kb
Host smart-acc3b87a-2f05-43b8-afa9-0df0f4e035ad
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301405572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2301405572
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.2967410930
Short name T1096
Test name
Test status
Simulation time 112580854 ps
CPU time 3.99 seconds
Started Jul 19 04:47:45 PM PDT 24
Finished Jul 19 04:48:09 PM PDT 24
Peak memory 215248 kb
Host smart-302f113a-f24d-425b-ab5c-a5f1084e8047
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967410930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.2967410930
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.106726086
Short name T1060
Test name
Test status
Simulation time 87588969 ps
CPU time 1.53 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:17 PM PDT 24
Peak memory 215448 kb
Host smart-77b64129-a1c2-4cc4-ac0b-756555472ef7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106726086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.106726086
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.2625868016
Short name T106
Test name
Test status
Simulation time 663879210 ps
CPU time 14.45 seconds
Started Jul 19 04:48:18 PM PDT 24
Finished Jul 19 04:48:52 PM PDT 24
Peak memory 215280 kb
Host smart-f96c2e21-ead0-49cf-b6eb-7bbab670ab52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625868016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.2625868016
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3601543038
Short name T1012
Test name
Test status
Simulation time 15420067 ps
CPU time 0.69 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 204136 kb
Host smart-5264959b-d6aa-437d-a7ce-d6783fea5b9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601543038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3601543038
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.4266009925
Short name T1017
Test name
Test status
Simulation time 11244369 ps
CPU time 0.78 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:20 PM PDT 24
Peak memory 203800 kb
Host smart-0c20331e-3713-45e8-bcb5-94104aa365d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266009925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
4266009925
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3206903534
Short name T1037
Test name
Test status
Simulation time 23709068 ps
CPU time 0.72 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 203768 kb
Host smart-bf17de02-6beb-48e5-8763-58b477f8bf11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206903534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3206903534
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.408186705
Short name T1097
Test name
Test status
Simulation time 31672515 ps
CPU time 0.82 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 203784 kb
Host smart-e8162b8a-53f0-40ff-bae2-4c758af27e73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408186705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.408186705
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.374385249
Short name T1128
Test name
Test status
Simulation time 29001756 ps
CPU time 0.7 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 203784 kb
Host smart-4de94472-ae76-4bd8-8187-234e07ed1df3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374385249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.374385249
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3472081185
Short name T1125
Test name
Test status
Simulation time 18896798 ps
CPU time 0.74 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:35 PM PDT 24
Peak memory 204112 kb
Host smart-a776032d-df4d-4513-a3a6-f70b6a5f7c77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472081185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3472081185
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2269829559
Short name T1123
Test name
Test status
Simulation time 14211321 ps
CPU time 0.75 seconds
Started Jul 19 04:48:06 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 204144 kb
Host smart-04ebc875-fbee-4eb1-9212-c63423963598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269829559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2269829559
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2893767855
Short name T1036
Test name
Test status
Simulation time 11065169 ps
CPU time 0.67 seconds
Started Jul 19 04:48:15 PM PDT 24
Finished Jul 19 04:48:36 PM PDT 24
Peak memory 204064 kb
Host smart-eb83d896-fe41-4719-bc1a-e61281f398de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893767855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2893767855
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1109541486
Short name T1013
Test name
Test status
Simulation time 85942875 ps
CPU time 0.76 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:19 PM PDT 24
Peak memory 203804 kb
Host smart-3c819343-4136-4959-9dbf-964590852f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109541486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1109541486
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1565198830
Short name T1100
Test name
Test status
Simulation time 68681652 ps
CPU time 0.72 seconds
Started Jul 19 04:48:06 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 204100 kb
Host smart-b2b38989-e5c2-4e52-9e90-32b57ce8f966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565198830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1565198830
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1226330436
Short name T1011
Test name
Test status
Simulation time 116055764 ps
CPU time 7.61 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:13 PM PDT 24
Peak memory 215244 kb
Host smart-066f1caf-20b6-4f4e-a1a4-e46007e9f389
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226330436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1226330436
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1624533009
Short name T110
Test name
Test status
Simulation time 10808622916 ps
CPU time 38.83 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:53 PM PDT 24
Peak memory 215304 kb
Host smart-03be7cf0-53ce-45ec-a738-a3f5bcf9ce3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624533009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1624533009
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2443230415
Short name T68
Test name
Test status
Simulation time 109732480 ps
CPU time 1.19 seconds
Started Jul 19 04:47:47 PM PDT 24
Finished Jul 19 04:48:08 PM PDT 24
Peak memory 216224 kb
Host smart-20a61744-6534-41e8-aaed-4695feb3e703
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443230415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2443230415
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3267215068
Short name T1064
Test name
Test status
Simulation time 109154484 ps
CPU time 4.29 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:07 PM PDT 24
Peak memory 217060 kb
Host smart-55dc9211-0ccd-4b08-bef5-a789c9ca69a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267215068 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3267215068
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2140318063
Short name T1091
Test name
Test status
Simulation time 31149729 ps
CPU time 1.86 seconds
Started Jul 19 04:47:47 PM PDT 24
Finished Jul 19 04:48:08 PM PDT 24
Peak memory 215228 kb
Host smart-9a84b675-3697-4b7d-91a2-3e8eab340381
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140318063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
140318063
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3791685388
Short name T1130
Test name
Test status
Simulation time 38389120 ps
CPU time 0.74 seconds
Started Jul 19 04:47:44 PM PDT 24
Finished Jul 19 04:48:03 PM PDT 24
Peak memory 203756 kb
Host smart-d7d0f58e-d16c-4ac9-b090-3f98245d26ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791685388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
791685388
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1063782397
Short name T1124
Test name
Test status
Simulation time 90036659 ps
CPU time 1.79 seconds
Started Jul 19 04:47:45 PM PDT 24
Finished Jul 19 04:48:06 PM PDT 24
Peak memory 215348 kb
Host smart-b3730128-1868-4d94-871a-79b8851e24d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063782397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1063782397
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3104475151
Short name T1070
Test name
Test status
Simulation time 14033686 ps
CPU time 0.65 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:05 PM PDT 24
Peak memory 203556 kb
Host smart-6d32fef6-96f4-421f-94c1-bbdf46e6e65b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104475151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3104475151
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3542431941
Short name T1071
Test name
Test status
Simulation time 561745856 ps
CPU time 2.8 seconds
Started Jul 19 04:47:47 PM PDT 24
Finished Jul 19 04:48:09 PM PDT 24
Peak memory 215140 kb
Host smart-4b354443-5c2a-4567-991c-e5d26dff95e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542431941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3542431941
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.1700110938
Short name T1086
Test name
Test status
Simulation time 340944336 ps
CPU time 4.83 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:11 PM PDT 24
Peak memory 216464 kb
Host smart-4ab89fc5-c5b1-4ef5-97a8-4ab825175ae1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700110938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1
700110938
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3731636548
Short name T159
Test name
Test status
Simulation time 1521874792 ps
CPU time 16.98 seconds
Started Jul 19 04:47:42 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 223436 kb
Host smart-5c9c6bae-ac24-4dbc-beec-fe3a47e7fdb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731636548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3731636548
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2584484942
Short name T1026
Test name
Test status
Simulation time 27250449 ps
CPU time 0.79 seconds
Started Jul 19 04:48:02 PM PDT 24
Finished Jul 19 04:48:20 PM PDT 24
Peak memory 203740 kb
Host smart-16c45ca8-cc96-4165-9fb9-8c4368fa4ce6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584484942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2584484942
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1204840769
Short name T1025
Test name
Test status
Simulation time 14559435 ps
CPU time 0.72 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 204064 kb
Host smart-c8b6a5a6-c056-44ae-b7d7-859c65ad8aee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204840769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1204840769
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1833129236
Short name T1092
Test name
Test status
Simulation time 13639503 ps
CPU time 0.69 seconds
Started Jul 19 04:48:08 PM PDT 24
Finished Jul 19 04:48:27 PM PDT 24
Peak memory 203752 kb
Host smart-f179614e-e7ee-4826-b7c3-a93db4660fda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833129236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1833129236
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3275869304
Short name T1131
Test name
Test status
Simulation time 29547015 ps
CPU time 0.74 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 204124 kb
Host smart-f441e1ca-1e37-4165-aed4-79fa1050bdec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275869304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3275869304
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2104669843
Short name T1087
Test name
Test status
Simulation time 13275785 ps
CPU time 0.73 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 204072 kb
Host smart-7214aecb-d627-402b-9c1d-9a86cf80b2b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104669843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2104669843
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3898326530
Short name T1057
Test name
Test status
Simulation time 130228701 ps
CPU time 0.75 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 204124 kb
Host smart-e47e441e-c0b5-42e9-a48d-47eeb98aff42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898326530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3898326530
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3724087551
Short name T1049
Test name
Test status
Simulation time 17434517 ps
CPU time 0.77 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 203812 kb
Host smart-493934c2-63ff-4782-9f1f-7f7539838e4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724087551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3724087551
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2618988289
Short name T1113
Test name
Test status
Simulation time 48592281 ps
CPU time 0.79 seconds
Started Jul 19 04:48:02 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 203732 kb
Host smart-47b76184-f709-4eb3-b72a-7a7f24e45ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618988289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2618988289
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2762733122
Short name T1019
Test name
Test status
Simulation time 61921375 ps
CPU time 0.77 seconds
Started Jul 19 04:48:02 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 203728 kb
Host smart-903d94ce-22d7-4d09-ad10-f7db61d4b351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762733122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2762733122
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.603728381
Short name T1023
Test name
Test status
Simulation time 51695557 ps
CPU time 0.73 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 203832 kb
Host smart-3e1a02c3-d4d8-4f74-ae2d-b3c66aa85ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603728381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.603728381
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.71074041
Short name T1122
Test name
Test status
Simulation time 2230426242 ps
CPU time 14.62 seconds
Started Jul 19 04:48:07 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 215320 kb
Host smart-691290cc-40cd-4a23-8cde-68a6d4372b2a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71074041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.71074041
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.214140919
Short name T114
Test name
Test status
Simulation time 7216920235 ps
CPU time 35.26 seconds
Started Jul 19 04:47:55 PM PDT 24
Finished Jul 19 04:48:48 PM PDT 24
Peak memory 206908 kb
Host smart-82331b33-2c20-4e25-97ab-2e7ad172ed05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214140919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.214140919
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2084761859
Short name T70
Test name
Test status
Simulation time 78741132 ps
CPU time 0.96 seconds
Started Jul 19 04:47:48 PM PDT 24
Finished Jul 19 04:48:08 PM PDT 24
Peak memory 206772 kb
Host smart-e5cfa361-01cf-4856-a738-b56b7aaea296
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084761859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2084761859
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3177430414
Short name T1084
Test name
Test status
Simulation time 48335701 ps
CPU time 3.08 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 216636 kb
Host smart-01e89557-bc55-4327-b317-6424161cf5e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177430414 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3177430414
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4083432938
Short name T107
Test name
Test status
Simulation time 43107123 ps
CPU time 1.36 seconds
Started Jul 19 04:47:48 PM PDT 24
Finished Jul 19 04:48:09 PM PDT 24
Peak memory 215156 kb
Host smart-fcf33e46-f662-49ab-8816-e52126dbc112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083432938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
083432938
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1475627867
Short name T1089
Test name
Test status
Simulation time 62374895 ps
CPU time 0.79 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:06 PM PDT 24
Peak memory 204076 kb
Host smart-a4132b63-7ba8-48ad-97ae-5b515ac201f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475627867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
475627867
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3958624942
Short name T113
Test name
Test status
Simulation time 135655110 ps
CPU time 2.38 seconds
Started Jul 19 04:47:48 PM PDT 24
Finished Jul 19 04:48:10 PM PDT 24
Peak memory 215408 kb
Host smart-22a826fb-cbf9-4924-8a47-7661d157a4a4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958624942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3958624942
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.4232382588
Short name T1016
Test name
Test status
Simulation time 14746488 ps
CPU time 0.69 seconds
Started Jul 19 04:47:46 PM PDT 24
Finished Jul 19 04:48:05 PM PDT 24
Peak memory 203576 kb
Host smart-09d7fcab-f817-4045-b815-8fc00551e12f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232382588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.4232382588
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4275043962
Short name T137
Test name
Test status
Simulation time 84656750 ps
CPU time 2.76 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:17 PM PDT 24
Peak memory 215124 kb
Host smart-02363bbe-538c-4dfa-9605-6ce813b5e0ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275043962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.4275043962
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.873959938
Short name T101
Test name
Test status
Simulation time 565771311 ps
CPU time 3.62 seconds
Started Jul 19 04:47:47 PM PDT 24
Finished Jul 19 04:48:10 PM PDT 24
Peak memory 216476 kb
Host smart-fbee29c7-ffad-4bd1-b81f-4b8fc92c10ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873959938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.873959938
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4152061497
Short name T1051
Test name
Test status
Simulation time 18040321 ps
CPU time 0.76 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 203768 kb
Host smart-0041cc40-5ce2-4c15-919b-750fff0be62a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152061497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4152061497
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2560019086
Short name T1029
Test name
Test status
Simulation time 11810897 ps
CPU time 0.68 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:28 PM PDT 24
Peak memory 203796 kb
Host smart-2048bdda-65db-42aa-bb72-e8f2edc9eff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560019086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2560019086
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.2086799762
Short name T1021
Test name
Test status
Simulation time 16914053 ps
CPU time 0.68 seconds
Started Jul 19 04:48:14 PM PDT 24
Finished Jul 19 04:48:34 PM PDT 24
Peak memory 203836 kb
Host smart-c990a700-7075-43c1-adc0-c7882d396825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086799762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
2086799762
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.112345070
Short name T1022
Test name
Test status
Simulation time 19101747 ps
CPU time 0.79 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 203804 kb
Host smart-65b9ec48-5fa4-4805-87a2-15f8cf824317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112345070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.112345070
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1951888836
Short name T1074
Test name
Test status
Simulation time 61108150 ps
CPU time 0.71 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:40 PM PDT 24
Peak memory 203804 kb
Host smart-e19f9aeb-81ff-49cd-8896-c2a9304282c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951888836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1951888836
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1658874187
Short name T1078
Test name
Test status
Simulation time 21308893 ps
CPU time 0.86 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 203848 kb
Host smart-4838a58a-fc77-42b0-b451-0bdd5ec3cf2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658874187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1658874187
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3404987069
Short name T1042
Test name
Test status
Simulation time 11810396 ps
CPU time 0.73 seconds
Started Jul 19 04:48:07 PM PDT 24
Finished Jul 19 04:48:25 PM PDT 24
Peak memory 203796 kb
Host smart-0f40ee33-d568-4c9e-87c8-75eec31a4f26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404987069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3404987069
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.263991652
Short name T1035
Test name
Test status
Simulation time 33246970 ps
CPU time 0.68 seconds
Started Jul 19 04:48:13 PM PDT 24
Finished Jul 19 04:48:33 PM PDT 24
Peak memory 203824 kb
Host smart-5a4ef46c-33a4-4deb-871d-574ce12161f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263991652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.263991652
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.4167198440
Short name T1088
Test name
Test status
Simulation time 17569866 ps
CPU time 0.75 seconds
Started Jul 19 04:48:20 PM PDT 24
Finished Jul 19 04:48:39 PM PDT 24
Peak memory 203824 kb
Host smart-011bbffa-d881-4887-82a5-6c9469764e0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167198440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
4167198440
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.4062611776
Short name T1030
Test name
Test status
Simulation time 36885590 ps
CPU time 0.73 seconds
Started Jul 19 04:48:16 PM PDT 24
Finished Jul 19 04:48:37 PM PDT 24
Peak memory 203772 kb
Host smart-72ae4cbd-677f-4425-9494-0bd0664e434d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062611776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
4062611776
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3221775505
Short name T105
Test name
Test status
Simulation time 127935179 ps
CPU time 3.58 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:15 PM PDT 24
Peak memory 217064 kb
Host smart-bffea7a1-5093-4aa0-a2d5-c09edd0aee37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221775505 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3221775505
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1341803985
Short name T1103
Test name
Test status
Simulation time 140379178 ps
CPU time 2.28 seconds
Started Jul 19 04:48:05 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 215252 kb
Host smart-c5a03547-93bb-40ed-88d3-79605b6abe65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341803985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
341803985
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.265760523
Short name T1034
Test name
Test status
Simulation time 15023923 ps
CPU time 0.76 seconds
Started Jul 19 04:48:06 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 204132 kb
Host smart-fd5f9bbf-3e86-439c-b974-a10a4df8d92e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265760523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.265760523
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4261230297
Short name T1027
Test name
Test status
Simulation time 106785163 ps
CPU time 2.97 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:24 PM PDT 24
Peak memory 215152 kb
Host smart-178aeab1-22d7-4504-8c24-6e05ad9c737d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261230297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4261230297
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.182378613
Short name T57
Test name
Test status
Simulation time 256987788 ps
CPU time 2.11 seconds
Started Jul 19 04:48:08 PM PDT 24
Finished Jul 19 04:48:27 PM PDT 24
Peak memory 215376 kb
Host smart-bf750d18-8624-4ed7-a960-bc30206611b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182378613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.182378613
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1528408569
Short name T1104
Test name
Test status
Simulation time 682647671 ps
CPU time 15.4 seconds
Started Jul 19 04:48:05 PM PDT 24
Finished Jul 19 04:48:38 PM PDT 24
Peak memory 215488 kb
Host smart-5bd29387-66fb-4747-9f20-721a2c290c26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528408569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1528408569
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3657074093
Short name T102
Test name
Test status
Simulation time 158759192 ps
CPU time 4.06 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 218016 kb
Host smart-25edf30d-01f6-433f-a588-5b225a9a7dc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657074093 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3657074093
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.584427472
Short name T117
Test name
Test status
Simulation time 30882343 ps
CPU time 1.75 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:16 PM PDT 24
Peak memory 206964 kb
Host smart-80d280bd-dab1-4d36-b39b-b85227cf3699
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584427472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.584427472
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.212465953
Short name T1047
Test name
Test status
Simulation time 20130533 ps
CPU time 0.82 seconds
Started Jul 19 04:47:55 PM PDT 24
Finished Jul 19 04:48:13 PM PDT 24
Peak memory 203784 kb
Host smart-493322a4-89bc-4b5e-949b-7f677178477d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212465953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.212465953
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.275017001
Short name T139
Test name
Test status
Simulation time 587857178 ps
CPU time 4.28 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:16 PM PDT 24
Peak memory 215244 kb
Host smart-50961296-770e-471a-9b2a-a5d70d172a40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275017001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.275017001
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2037419846
Short name T100
Test name
Test status
Simulation time 173638219 ps
CPU time 4.4 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 215352 kb
Host smart-668dc5e3-6327-49d1-a10e-b330d77ef4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037419846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
037419846
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1273520676
Short name T160
Test name
Test status
Simulation time 834782113 ps
CPU time 13.69 seconds
Started Jul 19 04:47:55 PM PDT 24
Finished Jul 19 04:48:26 PM PDT 24
Peak memory 215668 kb
Host smart-b2c36855-3ee0-4c7a-9051-df5acfdc0943
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273520676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1273520676
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2789576750
Short name T1055
Test name
Test status
Simulation time 100004912 ps
CPU time 2.09 seconds
Started Jul 19 04:48:10 PM PDT 24
Finished Jul 19 04:48:30 PM PDT 24
Peak memory 216352 kb
Host smart-f66cbe89-28b5-4abc-9de1-8a23c4be0788
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789576750 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2789576750
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.957479485
Short name T116
Test name
Test status
Simulation time 446970217 ps
CPU time 2.74 seconds
Started Jul 19 04:47:52 PM PDT 24
Finished Jul 19 04:48:13 PM PDT 24
Peak memory 215228 kb
Host smart-df289582-56a4-4ab3-948e-d122fa1612f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957479485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.957479485
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.25329098
Short name T1090
Test name
Test status
Simulation time 39824696 ps
CPU time 0.69 seconds
Started Jul 19 04:48:03 PM PDT 24
Finished Jul 19 04:48:21 PM PDT 24
Peak memory 203912 kb
Host smart-4e1aed67-490f-4382-b03a-630ff9ae8a47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.25329098
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2999120614
Short name T1098
Test name
Test status
Simulation time 121613333 ps
CPU time 4.02 seconds
Started Jul 19 04:47:52 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 215256 kb
Host smart-1c72d5d4-3845-4ad7-abeb-d7310865e5af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999120614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2999120614
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.914896270
Short name T1109
Test name
Test status
Simulation time 262615175 ps
CPU time 4.2 seconds
Started Jul 19 04:47:52 PM PDT 24
Finished Jul 19 04:48:15 PM PDT 24
Peak memory 215676 kb
Host smart-fae17313-6421-4d77-b281-5dbadd447010
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914896270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.914896270
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1868931817
Short name T161
Test name
Test status
Simulation time 680186889 ps
CPU time 6.94 seconds
Started Jul 19 04:48:02 PM PDT 24
Finished Jul 19 04:48:27 PM PDT 24
Peak memory 215084 kb
Host smart-f3f75169-f7e2-4f8b-9abd-43dd00bff59c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868931817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1868931817
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2153593320
Short name T1043
Test name
Test status
Simulation time 150737041 ps
CPU time 2.73 seconds
Started Jul 19 04:47:54 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 217720 kb
Host smart-56e4a2d8-288c-42e3-a060-7982f7a60f77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153593320 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2153593320
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2006551217
Short name T119
Test name
Test status
Simulation time 38853028 ps
CPU time 1.37 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:23 PM PDT 24
Peak memory 206940 kb
Host smart-e7752f73-e3f7-4f6c-a280-d1722af69ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006551217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
006551217
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2998889304
Short name T1044
Test name
Test status
Simulation time 60144339 ps
CPU time 0.7 seconds
Started Jul 19 04:48:00 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 203704 kb
Host smart-a3f80f43-f334-419a-9593-aec084023260
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998889304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
998889304
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2078172475
Short name T1110
Test name
Test status
Simulation time 243943771 ps
CPU time 1.85 seconds
Started Jul 19 04:47:59 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 215264 kb
Host smart-b71fd002-73b0-4704-a5c8-6b21366b738a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078172475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2078172475
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.169969480
Short name T96
Test name
Test status
Simulation time 102935335 ps
CPU time 2.91 seconds
Started Jul 19 04:47:53 PM PDT 24
Finished Jul 19 04:48:14 PM PDT 24
Peak memory 215552 kb
Host smart-26b552d7-88e0-4feb-85de-e670df2873df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169969480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.169969480
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.10410416
Short name T104
Test name
Test status
Simulation time 230367255 ps
CPU time 3.55 seconds
Started Jul 19 04:47:56 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 217404 kb
Host smart-f0e06273-6da4-4fbb-962b-97794baa1a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10410416 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.10410416
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3642581352
Short name T115
Test name
Test status
Simulation time 239722065 ps
CPU time 1.96 seconds
Started Jul 19 04:48:01 PM PDT 24
Finished Jul 19 04:48:20 PM PDT 24
Peak memory 215228 kb
Host smart-d8c6dbb8-b308-46d7-ae77-f439e5a125d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642581352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
642581352
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3476678277
Short name T1082
Test name
Test status
Simulation time 160414341 ps
CPU time 0.77 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:22 PM PDT 24
Peak memory 203824 kb
Host smart-153164d6-3625-4bd9-bb0c-d76e08a05c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476678277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
476678277
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2802023394
Short name T1094
Test name
Test status
Simulation time 101530872 ps
CPU time 2.97 seconds
Started Jul 19 04:47:57 PM PDT 24
Finished Jul 19 04:48:18 PM PDT 24
Peak memory 215164 kb
Host smart-748809c0-2579-435c-ae9b-92612041bc7e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802023394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2802023394
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1218219980
Short name T93
Test name
Test status
Simulation time 129500898 ps
CPU time 3.72 seconds
Started Jul 19 04:48:04 PM PDT 24
Finished Jul 19 04:48:25 PM PDT 24
Peak memory 215572 kb
Host smart-9b503afe-d73d-4a43-b323-0aca1178357f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218219980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
218219980
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.944670760
Short name T1061
Test name
Test status
Simulation time 989782259 ps
CPU time 7.07 seconds
Started Jul 19 04:47:51 PM PDT 24
Finished Jul 19 04:48:16 PM PDT 24
Peak memory 215740 kb
Host smart-4600ae42-5f7b-419f-a3b3-3770599ef0b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944670760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.944670760
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2822113842
Short name T589
Test name
Test status
Simulation time 12210588 ps
CPU time 0.7 seconds
Started Jul 19 06:15:03 PM PDT 24
Finished Jul 19 06:15:04 PM PDT 24
Peak memory 206268 kb
Host smart-1efcd4d2-2709-4107-9455-56f6f601ed78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822113842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
822113842
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1973576561
Short name T498
Test name
Test status
Simulation time 2153487963 ps
CPU time 9.82 seconds
Started Jul 19 06:14:49 PM PDT 24
Finished Jul 19 06:14:59 PM PDT 24
Peak memory 224952 kb
Host smart-f089f8fc-8fc8-429b-bc03-1a4c48ef68b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973576561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1973576561
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1885597601
Short name T955
Test name
Test status
Simulation time 19436578 ps
CPU time 0.77 seconds
Started Jul 19 06:14:41 PM PDT 24
Finished Jul 19 06:14:43 PM PDT 24
Peak memory 206012 kb
Host smart-6b8c6034-ffba-495b-be5d-95ea2dcdd893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885597601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1885597601
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.903161682
Short name T652
Test name
Test status
Simulation time 20088079245 ps
CPU time 111.52 seconds
Started Jul 19 06:14:56 PM PDT 24
Finished Jul 19 06:16:48 PM PDT 24
Peak memory 262896 kb
Host smart-d07adeca-9be8-4e7c-91dc-58d8577f2029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903161682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.903161682
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3717529523
Short name T25
Test name
Test status
Simulation time 8042943967 ps
CPU time 103.7 seconds
Started Jul 19 06:15:01 PM PDT 24
Finished Jul 19 06:16:45 PM PDT 24
Peak memory 249844 kb
Host smart-14ba4334-27e7-4414-af21-f3274f4d06e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717529523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3717529523
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1400321576
Short name T291
Test name
Test status
Simulation time 1910970226 ps
CPU time 51.28 seconds
Started Jul 19 06:14:52 PM PDT 24
Finished Jul 19 06:15:43 PM PDT 24
Peak memory 252696 kb
Host smart-0c731bb4-6201-4d03-97b9-4c015819136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400321576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1400321576
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.481326673
Short name T514
Test name
Test status
Simulation time 2157410747 ps
CPU time 8.8 seconds
Started Jul 19 06:14:50 PM PDT 24
Finished Jul 19 06:15:00 PM PDT 24
Peak memory 233180 kb
Host smart-f0a285f0-d1fd-4820-a868-45814c13c2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481326673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.481326673
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3538513558
Short name T234
Test name
Test status
Simulation time 13865598280 ps
CPU time 114.86 seconds
Started Jul 19 06:14:50 PM PDT 24
Finished Jul 19 06:16:46 PM PDT 24
Peak memory 252200 kb
Host smart-c823fb8e-2583-4227-91a0-ab29cdb2652c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538513558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3538513558
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.4158458969
Short name T398
Test name
Test status
Simulation time 364139647 ps
CPU time 3.5 seconds
Started Jul 19 06:14:52 PM PDT 24
Finished Jul 19 06:14:56 PM PDT 24
Peak memory 224924 kb
Host smart-73829f92-c674-48ce-90e5-821360ad3d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158458969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.4158458969
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1240842880
Short name T748
Test name
Test status
Simulation time 621083317 ps
CPU time 6.1 seconds
Started Jul 19 06:14:49 PM PDT 24
Finished Jul 19 06:14:56 PM PDT 24
Peak memory 233140 kb
Host smart-005170e0-d972-4c83-ac51-d82266cca8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240842880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1240842880
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2965881981
Short name T432
Test name
Test status
Simulation time 769719142 ps
CPU time 4.18 seconds
Started Jul 19 06:14:58 PM PDT 24
Finished Jul 19 06:15:02 PM PDT 24
Peak memory 220636 kb
Host smart-dc2c209f-84b6-4a6c-9ef3-a486c7784b4a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2965881981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2965881981
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3939104999
Short name T545
Test name
Test status
Simulation time 9741251808 ps
CPU time 26.64 seconds
Started Jul 19 06:14:43 PM PDT 24
Finished Jul 19 06:15:10 PM PDT 24
Peak memory 216712 kb
Host smart-49e8f723-946b-4429-ab78-bec599deee09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939104999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3939104999
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.147703885
Short name T908
Test name
Test status
Simulation time 4354448588 ps
CPU time 8.05 seconds
Started Jul 19 06:14:41 PM PDT 24
Finished Jul 19 06:14:50 PM PDT 24
Peak memory 216780 kb
Host smart-71a932ff-2e5e-4a88-9d49-30572643d223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147703885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.147703885
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.468332285
Short name T765
Test name
Test status
Simulation time 84599311 ps
CPU time 1.33 seconds
Started Jul 19 06:14:51 PM PDT 24
Finished Jul 19 06:14:53 PM PDT 24
Peak memory 216628 kb
Host smart-8655b713-f184-4374-bad8-c5217e805453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468332285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.468332285
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1617275559
Short name T781
Test name
Test status
Simulation time 116676382 ps
CPU time 0.83 seconds
Started Jul 19 06:14:41 PM PDT 24
Finished Jul 19 06:14:43 PM PDT 24
Peak memory 206452 kb
Host smart-ae7d53e9-8801-45c7-aabf-473395f73bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617275559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1617275559
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2616329355
Short name T702
Test name
Test status
Simulation time 420734931 ps
CPU time 2.35 seconds
Started Jul 19 06:14:49 PM PDT 24
Finished Jul 19 06:14:52 PM PDT 24
Peak memory 224120 kb
Host smart-61ffbc71-79e3-439c-8cea-65aaaaeef569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616329355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2616329355
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.185306213
Short name T932
Test name
Test status
Simulation time 38481761 ps
CPU time 0.73 seconds
Started Jul 19 06:15:19 PM PDT 24
Finished Jul 19 06:15:20 PM PDT 24
Peak memory 206248 kb
Host smart-406e01d0-5f23-4245-8172-f58d15aad8f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185306213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.185306213
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.110623847
Short name T272
Test name
Test status
Simulation time 855084194 ps
CPU time 3.74 seconds
Started Jul 19 06:15:21 PM PDT 24
Finished Jul 19 06:15:25 PM PDT 24
Peak memory 233068 kb
Host smart-ed48a470-0177-4177-bdb6-0ec1ed00eaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110623847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.110623847
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3746072606
Short name T472
Test name
Test status
Simulation time 90312924 ps
CPU time 0.73 seconds
Started Jul 19 06:15:03 PM PDT 24
Finished Jul 19 06:15:04 PM PDT 24
Peak memory 206048 kb
Host smart-a51260b3-14f7-4edd-aa9c-e40547825376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746072606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3746072606
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1677452925
Short name T269
Test name
Test status
Simulation time 103773340586 ps
CPU time 239.21 seconds
Started Jul 19 06:15:19 PM PDT 24
Finished Jul 19 06:19:19 PM PDT 24
Peak memory 263696 kb
Host smart-c3deea5d-2454-487e-8918-fd7bbfa5464f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677452925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1677452925
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2900887580
Short name T404
Test name
Test status
Simulation time 81819609099 ps
CPU time 149.75 seconds
Started Jul 19 06:15:19 PM PDT 24
Finished Jul 19 06:17:49 PM PDT 24
Peak memory 257768 kb
Host smart-4fce2439-bff5-4d1f-a226-07469f978b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900887580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2900887580
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.1793107193
Short name T290
Test name
Test status
Simulation time 11702104687 ps
CPU time 79.85 seconds
Started Jul 19 06:15:20 PM PDT 24
Finished Jul 19 06:16:40 PM PDT 24
Peak memory 240204 kb
Host smart-e044c1b1-832b-4a0b-a294-7edbfdabbc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793107193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.1793107193
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1643319741
Short name T992
Test name
Test status
Simulation time 1066228789 ps
CPU time 3.43 seconds
Started Jul 19 06:15:11 PM PDT 24
Finished Jul 19 06:15:15 PM PDT 24
Peak memory 220176 kb
Host smart-a0987f17-60a9-4617-b871-6dc4a28adefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643319741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1643319741
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3972176940
Short name T643
Test name
Test status
Simulation time 797682983 ps
CPU time 18.51 seconds
Started Jul 19 06:15:12 PM PDT 24
Finished Jul 19 06:15:31 PM PDT 24
Peak memory 234404 kb
Host smart-e07e2611-fa75-4133-92bd-50ae05530eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972176940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3972176940
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2512601341
Short name T208
Test name
Test status
Simulation time 8075752024 ps
CPU time 7.72 seconds
Started Jul 19 06:15:12 PM PDT 24
Finished Jul 19 06:15:21 PM PDT 24
Peak memory 233132 kb
Host smart-df3bfd26-cce7-4577-98d3-f67f31758f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512601341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2512601341
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.639149808
Short name T640
Test name
Test status
Simulation time 25402957551 ps
CPU time 23.32 seconds
Started Jul 19 06:15:11 PM PDT 24
Finished Jul 19 06:15:35 PM PDT 24
Peak memory 236388 kb
Host smart-30ad66f3-24a5-4b3c-b7e8-3ae1b1df9439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639149808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.639149808
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2126593084
Short name T13
Test name
Test status
Simulation time 81173159 ps
CPU time 0.95 seconds
Started Jul 19 06:15:21 PM PDT 24
Finished Jul 19 06:15:23 PM PDT 24
Peak memory 235520 kb
Host smart-a464ec70-2ecb-4e9e-abe1-c19cad3e00a2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126593084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2126593084
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3215033146
Short name T47
Test name
Test status
Simulation time 8094223956 ps
CPU time 97.07 seconds
Started Jul 19 06:15:20 PM PDT 24
Finished Jul 19 06:16:58 PM PDT 24
Peak memory 241476 kb
Host smart-2168d64a-e52b-4101-adbf-97f9a88da701
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215033146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3215033146
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2894228992
Short name T318
Test name
Test status
Simulation time 7935797814 ps
CPU time 22.82 seconds
Started Jul 19 06:15:13 PM PDT 24
Finished Jul 19 06:15:36 PM PDT 24
Peak memory 217060 kb
Host smart-ff7f6755-e502-4033-be9d-78121fa9f8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894228992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2894228992
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3115802841
Short name T801
Test name
Test status
Simulation time 35174190327 ps
CPU time 20.06 seconds
Started Jul 19 06:15:11 PM PDT 24
Finished Jul 19 06:15:32 PM PDT 24
Peak memory 216716 kb
Host smart-eae08079-7cb8-45dc-9003-705081476526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115802841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3115802841
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2477237432
Short name T322
Test name
Test status
Simulation time 180686796 ps
CPU time 2.79 seconds
Started Jul 19 06:15:09 PM PDT 24
Finished Jul 19 06:15:13 PM PDT 24
Peak memory 216640 kb
Host smart-1334a8d7-5d13-4da7-a62e-704e1694b338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477237432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2477237432
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2555236592
Short name T999
Test name
Test status
Simulation time 166739956 ps
CPU time 0.81 seconds
Started Jul 19 06:15:10 PM PDT 24
Finished Jul 19 06:15:11 PM PDT 24
Peak memory 206400 kb
Host smart-ba90ff08-90ad-4c53-8b0a-45f3eb0a7049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555236592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2555236592
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2836237082
Short name T712
Test name
Test status
Simulation time 7087034499 ps
CPU time 13.95 seconds
Started Jul 19 06:15:23 PM PDT 24
Finished Jul 19 06:15:37 PM PDT 24
Peak memory 240800 kb
Host smart-f90b6b02-5f62-4bea-83b6-58020261031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836237082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2836237082
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2112356300
Short name T575
Test name
Test status
Simulation time 1167697740 ps
CPU time 11.95 seconds
Started Jul 19 06:17:15 PM PDT 24
Finished Jul 19 06:17:27 PM PDT 24
Peak memory 233132 kb
Host smart-f97810ae-fe55-43f7-b97b-038226ee6ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112356300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2112356300
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.590559718
Short name T447
Test name
Test status
Simulation time 43002927 ps
CPU time 0.81 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:06 PM PDT 24
Peak memory 207076 kb
Host smart-0f284e5b-e72a-453e-9376-4442ea9d7d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590559718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.590559718
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2839767517
Short name T431
Test name
Test status
Simulation time 10285595753 ps
CPU time 109.47 seconds
Started Jul 19 06:17:13 PM PDT 24
Finished Jul 19 06:19:03 PM PDT 24
Peak memory 257896 kb
Host smart-715128f7-16a6-46b2-8d7c-459ced8e10d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839767517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2839767517
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2339871207
Short name T830
Test name
Test status
Simulation time 27427856421 ps
CPU time 264.65 seconds
Started Jul 19 06:17:11 PM PDT 24
Finished Jul 19 06:21:36 PM PDT 24
Peak memory 257228 kb
Host smart-ef2d36a2-138c-43f6-b53b-21987abc7280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339871207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2339871207
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3708023249
Short name T158
Test name
Test status
Simulation time 34441055725 ps
CPU time 95.53 seconds
Started Jul 19 06:17:13 PM PDT 24
Finished Jul 19 06:18:50 PM PDT 24
Peak memory 251708 kb
Host smart-a7c6e023-4e36-4741-933c-53cee49f03a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708023249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3708023249
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4294249453
Short name T300
Test name
Test status
Simulation time 6868631612 ps
CPU time 25.21 seconds
Started Jul 19 06:17:14 PM PDT 24
Finished Jul 19 06:17:40 PM PDT 24
Peak memory 224932 kb
Host smart-739d73a8-d83e-40cc-bddd-79741faaf459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294249453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4294249453
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.10137958
Short name T285
Test name
Test status
Simulation time 27860639150 ps
CPU time 197.22 seconds
Started Jul 19 06:17:14 PM PDT 24
Finished Jul 19 06:20:32 PM PDT 24
Peak memory 256168 kb
Host smart-8216a4b8-9b79-4348-8a63-0f3ec4a8f359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10137958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.10137958
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.960402970
Short name T890
Test name
Test status
Simulation time 5108562165 ps
CPU time 17.02 seconds
Started Jul 19 06:17:12 PM PDT 24
Finished Jul 19 06:17:30 PM PDT 24
Peak memory 225028 kb
Host smart-a9d93849-9a13-453e-b8d5-29efbe6de982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960402970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.960402970
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1428854816
Short name T767
Test name
Test status
Simulation time 970933395 ps
CPU time 10.28 seconds
Started Jul 19 06:17:13 PM PDT 24
Finished Jul 19 06:17:24 PM PDT 24
Peak memory 224896 kb
Host smart-10bdb575-9bf2-4877-bfdc-47c322cf7d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428854816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1428854816
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2636452180
Short name T198
Test name
Test status
Simulation time 940277524 ps
CPU time 5.53 seconds
Started Jul 19 06:17:13 PM PDT 24
Finished Jul 19 06:17:20 PM PDT 24
Peak memory 233068 kb
Host smart-18c7e6fa-9dcf-4d7e-9036-17a932f2b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636452180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2636452180
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1485952659
Short name T833
Test name
Test status
Simulation time 379642912 ps
CPU time 6.53 seconds
Started Jul 19 06:17:12 PM PDT 24
Finished Jul 19 06:17:19 PM PDT 24
Peak memory 234144 kb
Host smart-7af65945-dacc-47ef-b10d-74165f9372bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485952659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1485952659
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1514349077
Short name T581
Test name
Test status
Simulation time 3729229615 ps
CPU time 8.42 seconds
Started Jul 19 06:17:12 PM PDT 24
Finished Jul 19 06:17:21 PM PDT 24
Peak memory 219348 kb
Host smart-bc4c343c-62c0-4fbe-be4f-566118fad37b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1514349077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1514349077
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1781141894
Short name T959
Test name
Test status
Simulation time 23948243718 ps
CPU time 35.13 seconds
Started Jul 19 06:17:15 PM PDT 24
Finished Jul 19 06:17:51 PM PDT 24
Peak memory 253740 kb
Host smart-4cacf91e-0c3c-4be3-b80e-07017d5e4e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781141894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1781141894
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.3612635389
Short name T761
Test name
Test status
Simulation time 43926800250 ps
CPU time 52.84 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:58 PM PDT 24
Peak memory 216688 kb
Host smart-7b2312b9-2ef5-4d33-8711-d1e614967d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612635389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.3612635389
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1569786802
Short name T856
Test name
Test status
Simulation time 3379176114 ps
CPU time 6.13 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:11 PM PDT 24
Peak memory 216716 kb
Host smart-6a981bdd-a19e-4612-83e2-0f99308fe066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569786802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1569786802
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2576625992
Short name T774
Test name
Test status
Simulation time 118805789 ps
CPU time 1.51 seconds
Started Jul 19 06:17:13 PM PDT 24
Finished Jul 19 06:17:15 PM PDT 24
Peak memory 216640 kb
Host smart-31431216-421a-4911-85bd-7da1d1d5146e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576625992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2576625992
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3027951899
Short name T698
Test name
Test status
Simulation time 93092059 ps
CPU time 0.73 seconds
Started Jul 19 06:17:06 PM PDT 24
Finished Jul 19 06:17:08 PM PDT 24
Peak memory 206376 kb
Host smart-6561dddb-54fc-424c-b917-a724fc68d8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027951899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3027951899
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.4127165820
Short name T544
Test name
Test status
Simulation time 3293768296 ps
CPU time 13.03 seconds
Started Jul 19 06:17:12 PM PDT 24
Finished Jul 19 06:17:26 PM PDT 24
Peak memory 224948 kb
Host smart-b0fa1e75-692d-4543-95e2-23cb9c7726f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127165820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4127165820
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.650842254
Short name T483
Test name
Test status
Simulation time 37721217 ps
CPU time 0.72 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:17:29 PM PDT 24
Peak memory 205928 kb
Host smart-f56fdc64-e3fe-48a0-953e-bd97c492110e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650842254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.650842254
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3950348685
Short name T175
Test name
Test status
Simulation time 1758461865 ps
CPU time 7.21 seconds
Started Jul 19 06:17:20 PM PDT 24
Finished Jul 19 06:17:27 PM PDT 24
Peak memory 233140 kb
Host smart-762c6b76-ab91-427a-8ce5-d77a234af324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950348685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3950348685
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4062365237
Short name T901
Test name
Test status
Simulation time 24334281 ps
CPU time 0.79 seconds
Started Jul 19 06:17:15 PM PDT 24
Finished Jul 19 06:17:16 PM PDT 24
Peak memory 206056 kb
Host smart-75d64d4e-c442-46d1-9067-5bfba818b748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062365237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4062365237
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.522638134
Short name T647
Test name
Test status
Simulation time 1610487385 ps
CPU time 36.74 seconds
Started Jul 19 06:17:22 PM PDT 24
Finished Jul 19 06:17:59 PM PDT 24
Peak memory 256652 kb
Host smart-15b9bcf8-a175-4e6b-bc62-a29ae20cf0d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522638134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.522638134
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3952839119
Short name T977
Test name
Test status
Simulation time 37908767028 ps
CPU time 404.85 seconds
Started Jul 19 06:17:33 PM PDT 24
Finished Jul 19 06:24:19 PM PDT 24
Peak memory 266032 kb
Host smart-43eb1f7e-d76c-402f-9654-26ca07142877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952839119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3952839119
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.93432656
Short name T840
Test name
Test status
Simulation time 35686698794 ps
CPU time 61.96 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:18:31 PM PDT 24
Peak memory 233228 kb
Host smart-bb2da757-2184-4c36-a795-573475edaef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93432656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.93432656
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3339240324
Short name T723
Test name
Test status
Simulation time 310145514 ps
CPU time 7.03 seconds
Started Jul 19 06:17:22 PM PDT 24
Finished Jul 19 06:17:29 PM PDT 24
Peak memory 233172 kb
Host smart-f25ddea2-1ce8-4203-a016-7661e9dbba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339240324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3339240324
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4097202758
Short name T231
Test name
Test status
Simulation time 6200276855 ps
CPU time 15.76 seconds
Started Jul 19 06:17:24 PM PDT 24
Finished Jul 19 06:17:40 PM PDT 24
Peak memory 233224 kb
Host smart-c5b250b9-65af-48cc-9191-f669890f270f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097202758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4097202758
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3792023070
Short name T965
Test name
Test status
Simulation time 235765386 ps
CPU time 3.7 seconds
Started Jul 19 06:17:24 PM PDT 24
Finished Jul 19 06:17:28 PM PDT 24
Peak memory 224904 kb
Host smart-d23653f6-1a01-4ad1-ab8c-48356e7db384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792023070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3792023070
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.121895265
Short name T676
Test name
Test status
Simulation time 4425983939 ps
CPU time 12.2 seconds
Started Jul 19 06:17:19 PM PDT 24
Finished Jul 19 06:17:31 PM PDT 24
Peak memory 233124 kb
Host smart-4d989f0b-2813-4e1d-a7ab-f6b84345844c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121895265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.121895265
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1144692331
Short name T201
Test name
Test status
Simulation time 2605251624 ps
CPU time 5.76 seconds
Started Jul 19 06:17:22 PM PDT 24
Finished Jul 19 06:17:28 PM PDT 24
Peak memory 224996 kb
Host smart-edd3483c-58b5-46b1-862e-49442cf951ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144692331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1144692331
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.1447859025
Short name T672
Test name
Test status
Simulation time 1921637053 ps
CPU time 8.72 seconds
Started Jul 19 06:17:22 PM PDT 24
Finished Jul 19 06:17:31 PM PDT 24
Peak memory 224884 kb
Host smart-61dfb1bb-85f0-4161-968f-40d6f0a143b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447859025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1447859025
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3464105421
Short name T143
Test name
Test status
Simulation time 546315651 ps
CPU time 8.74 seconds
Started Jul 19 06:17:25 PM PDT 24
Finished Jul 19 06:17:34 PM PDT 24
Peak memory 223528 kb
Host smart-fafe7321-aa03-4272-bbf5-11b1923117d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3464105421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3464105421
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.329978886
Short name T591
Test name
Test status
Simulation time 544837970 ps
CPU time 9.16 seconds
Started Jul 19 06:17:21 PM PDT 24
Finished Jul 19 06:17:31 PM PDT 24
Peak memory 216656 kb
Host smart-ed963bbe-d886-4f8f-bd19-a3ece2dcddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329978886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.329978886
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3940081244
Short name T734
Test name
Test status
Simulation time 427580764 ps
CPU time 1.73 seconds
Started Jul 19 06:17:22 PM PDT 24
Finished Jul 19 06:17:25 PM PDT 24
Peak memory 207592 kb
Host smart-52a6ae76-33dc-4877-87d2-8bb2cd33db58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940081244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3940081244
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3521923304
Short name T887
Test name
Test status
Simulation time 477469453 ps
CPU time 2.12 seconds
Started Jul 19 06:17:22 PM PDT 24
Finished Jul 19 06:17:25 PM PDT 24
Peak memory 216720 kb
Host smart-7abe32ca-0a70-46b9-a695-245c6a64c7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521923304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3521923304
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.510509001
Short name T811
Test name
Test status
Simulation time 54120255 ps
CPU time 0.76 seconds
Started Jul 19 06:17:21 PM PDT 24
Finished Jul 19 06:17:22 PM PDT 24
Peak memory 206448 kb
Host smart-02ea886e-df38-468d-b497-4cf8ff5405d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510509001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.510509001
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.845864704
Short name T564
Test name
Test status
Simulation time 1216255769 ps
CPU time 9.23 seconds
Started Jul 19 06:17:25 PM PDT 24
Finished Jul 19 06:17:34 PM PDT 24
Peak memory 233168 kb
Host smart-b13200b9-3514-41d9-927b-7e26774e77ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845864704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.845864704
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2997438283
Short name T433
Test name
Test status
Simulation time 156227881 ps
CPU time 0.74 seconds
Started Jul 19 06:17:36 PM PDT 24
Finished Jul 19 06:17:38 PM PDT 24
Peak memory 205860 kb
Host smart-d40cf305-9c27-4ae1-99e8-2709351a4c46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997438283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2997438283
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1430323663
Short name T243
Test name
Test status
Simulation time 336034662 ps
CPU time 4.57 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:17:35 PM PDT 24
Peak memory 224896 kb
Host smart-370af22d-1a8e-4e88-afe7-9bea9a8a558a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430323663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1430323663
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2664540862
Short name T600
Test name
Test status
Simulation time 15851568 ps
CPU time 0.77 seconds
Started Jul 19 06:17:30 PM PDT 24
Finished Jul 19 06:17:32 PM PDT 24
Peak memory 207072 kb
Host smart-a5925b45-1475-4c48-afbe-39ce5367b860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664540862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2664540862
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.434390609
Short name T850
Test name
Test status
Simulation time 278097302248 ps
CPU time 272.63 seconds
Started Jul 19 06:17:30 PM PDT 24
Finished Jul 19 06:22:04 PM PDT 24
Peak memory 270684 kb
Host smart-a0264731-f211-40a5-a09a-7e3c86db6a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434390609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.434390609
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1445614015
Short name T476
Test name
Test status
Simulation time 5627117413 ps
CPU time 23.15 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:17:53 PM PDT 24
Peak memory 218164 kb
Host smart-83e0fec3-0e52-4691-aadd-d0ae9bea1cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445614015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1445614015
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3099181009
Short name T155
Test name
Test status
Simulation time 54334446359 ps
CPU time 277.86 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:22:08 PM PDT 24
Peak memory 252996 kb
Host smart-2daa0d7c-ad5d-4526-be62-343f5ffe0cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099181009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3099181009
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3958537360
Short name T359
Test name
Test status
Simulation time 303861480 ps
CPU time 3.46 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:17:32 PM PDT 24
Peak memory 233124 kb
Host smart-7e73765c-c2f1-4239-8706-55dd418156d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958537360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3958537360
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3085887592
Short name T782
Test name
Test status
Simulation time 2418913317 ps
CPU time 13.95 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:17:43 PM PDT 24
Peak memory 224980 kb
Host smart-66c99d14-8e60-4519-8d1b-6528ab2e3f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085887592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3085887592
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3610044405
Short name T218
Test name
Test status
Simulation time 17222336685 ps
CPU time 23.2 seconds
Started Jul 19 06:17:31 PM PDT 24
Finished Jul 19 06:17:55 PM PDT 24
Peak memory 224976 kb
Host smart-c065819c-9fd7-4e37-92d0-b2d669478f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610044405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3610044405
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.30041084
Short name T665
Test name
Test status
Simulation time 8239844922 ps
CPU time 30.15 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:18:00 PM PDT 24
Peak memory 227936 kb
Host smart-5d2f1ff6-4245-4edd-b36b-eb7708f393d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30041084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.30041084
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.4130611331
Short name T261
Test name
Test status
Simulation time 1416114957 ps
CPU time 4.87 seconds
Started Jul 19 06:17:30 PM PDT 24
Finished Jul 19 06:17:36 PM PDT 24
Peak memory 238572 kb
Host smart-231d6ed0-39f4-4445-befb-b3aa6a45c800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130611331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.4130611331
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2595117302
Short name T252
Test name
Test status
Simulation time 685623240 ps
CPU time 3.16 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:17:34 PM PDT 24
Peak memory 233060 kb
Host smart-1fa7d392-2537-4d0d-9cea-a1e79e8d2dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595117302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2595117302
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1613509369
Short name T603
Test name
Test status
Simulation time 354938742 ps
CPU time 3.72 seconds
Started Jul 19 06:17:30 PM PDT 24
Finished Jul 19 06:17:35 PM PDT 24
Peak memory 223000 kb
Host smart-d72365e6-7621-4658-940b-8195b103cebc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1613509369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1613509369
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.1952046179
Short name T893
Test name
Test status
Simulation time 6257042767 ps
CPU time 34.43 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:18:03 PM PDT 24
Peak memory 216744 kb
Host smart-07c4613b-178d-43eb-b8c0-198ca4efe2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952046179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.1952046179
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3992602242
Short name T425
Test name
Test status
Simulation time 14378266336 ps
CPU time 18.38 seconds
Started Jul 19 06:17:30 PM PDT 24
Finished Jul 19 06:17:50 PM PDT 24
Peak memory 216748 kb
Host smart-9b4b4128-e079-4750-b7f1-9b04d298a9a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992602242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3992602242
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1349904701
Short name T319
Test name
Test status
Simulation time 173161251 ps
CPU time 2.63 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:17:32 PM PDT 24
Peak memory 216716 kb
Host smart-7b23b45d-91f2-43f4-a1de-1ec8d2a0ac75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349904701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1349904701
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3062025481
Short name T839
Test name
Test status
Simulation time 272367613 ps
CPU time 0.95 seconds
Started Jul 19 06:17:29 PM PDT 24
Finished Jul 19 06:17:31 PM PDT 24
Peak memory 207456 kb
Host smart-fb9bb580-d80c-45b1-a1de-f74abc50ad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062025481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3062025481
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1696753270
Short name T450
Test name
Test status
Simulation time 76641735 ps
CPU time 2.48 seconds
Started Jul 19 06:17:28 PM PDT 24
Finished Jul 19 06:17:31 PM PDT 24
Peak memory 224948 kb
Host smart-b622d21c-4d01-4a95-ae79-d8bed496379f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696753270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1696753270
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3304241674
Short name T345
Test name
Test status
Simulation time 23382616 ps
CPU time 0.72 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:17:44 PM PDT 24
Peak memory 206260 kb
Host smart-ea8e5009-82bb-4a70-9a51-bbbe8fe4d441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304241674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3304241674
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1572145919
Short name T549
Test name
Test status
Simulation time 285719404 ps
CPU time 3.42 seconds
Started Jul 19 06:17:34 PM PDT 24
Finished Jul 19 06:17:38 PM PDT 24
Peak memory 233064 kb
Host smart-d93c6344-1585-452c-bc1d-29b00dadaf52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572145919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1572145919
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2197805083
Short name T691
Test name
Test status
Simulation time 42732690 ps
CPU time 0.77 seconds
Started Jul 19 06:17:37 PM PDT 24
Finished Jul 19 06:17:38 PM PDT 24
Peak memory 207068 kb
Host smart-e995ccd7-4540-4cda-a953-a341617f03eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197805083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2197805083
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.1801647318
Short name T568
Test name
Test status
Simulation time 12341837790 ps
CPU time 86.53 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:19:10 PM PDT 24
Peak memory 249572 kb
Host smart-62e14c65-e5a1-44e3-97f9-bc541a07465e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801647318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1801647318
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.3667044827
Short name T678
Test name
Test status
Simulation time 611062827 ps
CPU time 3.75 seconds
Started Jul 19 06:17:37 PM PDT 24
Finished Jul 19 06:17:41 PM PDT 24
Peak memory 224880 kb
Host smart-7e8f4b6e-976b-49ae-b701-4e587cc22e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667044827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.3667044827
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2401348250
Short name T831
Test name
Test status
Simulation time 78531177175 ps
CPU time 207.32 seconds
Started Jul 19 06:17:34 PM PDT 24
Finished Jul 19 06:21:02 PM PDT 24
Peak memory 255572 kb
Host smart-3bde57b0-3d48-4cf6-86ef-9efb8708c791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401348250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2401348250
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.573716613
Short name T585
Test name
Test status
Simulation time 115625851 ps
CPU time 4.53 seconds
Started Jul 19 06:17:36 PM PDT 24
Finished Jul 19 06:17:41 PM PDT 24
Peak memory 233076 kb
Host smart-fd148d8a-e286-41c1-8283-e3fbb9cda8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573716613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.573716613
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1322414668
Short name T1003
Test name
Test status
Simulation time 35612194211 ps
CPU time 104.83 seconds
Started Jul 19 06:17:35 PM PDT 24
Finished Jul 19 06:19:20 PM PDT 24
Peak memory 231764 kb
Host smart-3d58af18-6035-443f-8bcd-ed0f4591d500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322414668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1322414668
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.189858959
Short name T939
Test name
Test status
Simulation time 4073045022 ps
CPU time 22.2 seconds
Started Jul 19 06:17:36 PM PDT 24
Finished Jul 19 06:17:59 PM PDT 24
Peak memory 239892 kb
Host smart-c8ca9f10-1cc8-44a1-86d1-4409d40390f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189858959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.189858959
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2380216757
Short name T667
Test name
Test status
Simulation time 125389094 ps
CPU time 2.56 seconds
Started Jul 19 06:17:34 PM PDT 24
Finished Jul 19 06:17:37 PM PDT 24
Peak memory 233076 kb
Host smart-29008753-a2fd-4c42-a142-21a16c843c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380216757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2380216757
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3244580065
Short name T868
Test name
Test status
Simulation time 2185282929 ps
CPU time 10.3 seconds
Started Jul 19 06:17:37 PM PDT 24
Finished Jul 19 06:17:48 PM PDT 24
Peak memory 222472 kb
Host smart-133cb5c5-6d39-4416-a3a4-ec83a4873a8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3244580065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3244580065
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3603801156
Short name T286
Test name
Test status
Simulation time 116680985114 ps
CPU time 242.75 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:21:46 PM PDT 24
Peak memory 283240 kb
Host smart-0468d009-63ae-4bce-a3c6-babe3f5a1fe8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603801156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3603801156
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.92450814
Short name T818
Test name
Test status
Simulation time 1025887015 ps
CPU time 2.62 seconds
Started Jul 19 06:17:36 PM PDT 24
Finished Jul 19 06:17:40 PM PDT 24
Peak memory 216780 kb
Host smart-e3f8289f-8662-4b07-ab19-c7ca869acfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92450814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.92450814
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.4237289934
Short name T775
Test name
Test status
Simulation time 6434092864 ps
CPU time 18.13 seconds
Started Jul 19 06:17:36 PM PDT 24
Finished Jul 19 06:17:55 PM PDT 24
Peak memory 216764 kb
Host smart-6315fca0-686a-4c07-8715-4ff9665bdee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237289934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.4237289934
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3857866437
Short name T529
Test name
Test status
Simulation time 865533556 ps
CPU time 3.03 seconds
Started Jul 19 06:17:35 PM PDT 24
Finished Jul 19 06:17:38 PM PDT 24
Peak memory 216720 kb
Host smart-4e2285cf-d5dc-4bb4-afa7-b1a847146735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857866437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3857866437
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1239193514
Short name T551
Test name
Test status
Simulation time 72363276 ps
CPU time 1.01 seconds
Started Jul 19 06:17:34 PM PDT 24
Finished Jul 19 06:17:36 PM PDT 24
Peak memory 207512 kb
Host smart-68b8d698-11b2-4579-a7ff-b24b2cdea113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239193514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1239193514
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.859430947
Short name T213
Test name
Test status
Simulation time 14634955935 ps
CPU time 8.97 seconds
Started Jul 19 06:17:36 PM PDT 24
Finished Jul 19 06:17:46 PM PDT 24
Peak memory 224992 kb
Host smart-eef86c1d-f073-4df6-a90e-e6b251a9e880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859430947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.859430947
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2150768589
Short name T681
Test name
Test status
Simulation time 11657032 ps
CPU time 0.7 seconds
Started Jul 19 06:17:51 PM PDT 24
Finished Jul 19 06:17:53 PM PDT 24
Peak memory 205940 kb
Host smart-ee79893e-97b9-479f-89bb-bcb30b038b5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150768589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2150768589
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1172047690
Short name T246
Test name
Test status
Simulation time 2688294395 ps
CPU time 10.29 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:18:04 PM PDT 24
Peak memory 233204 kb
Host smart-d0e46142-5fab-48a6-847e-ee76a9b84dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172047690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1172047690
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.1763304315
Short name T331
Test name
Test status
Simulation time 139120938 ps
CPU time 0.8 seconds
Started Jul 19 06:17:42 PM PDT 24
Finished Jul 19 06:17:44 PM PDT 24
Peak memory 207376 kb
Host smart-253e6ce0-6398-475e-889f-4accef4d01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763304315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1763304315
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1832711700
Short name T193
Test name
Test status
Simulation time 17026011159 ps
CPU time 52.97 seconds
Started Jul 19 06:17:54 PM PDT 24
Finished Jul 19 06:18:48 PM PDT 24
Peak memory 249936 kb
Host smart-b60d6a18-2322-4a89-8ffe-b6a31601c8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832711700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1832711700
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.3861305751
Short name T779
Test name
Test status
Simulation time 33851936121 ps
CPU time 59.92 seconds
Started Jul 19 06:17:52 PM PDT 24
Finished Jul 19 06:18:52 PM PDT 24
Peak memory 238624 kb
Host smart-27c01e39-f924-4149-a0f3-491c822ad060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861305751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.3861305751
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3218066313
Short name T838
Test name
Test status
Simulation time 76442744119 ps
CPU time 179.08 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:20:53 PM PDT 24
Peak memory 257992 kb
Host smart-bd5148f2-697b-459d-98ed-332bc8a23dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218066313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3218066313
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3053949878
Short name T884
Test name
Test status
Simulation time 146311332 ps
CPU time 3.63 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:17:57 PM PDT 24
Peak memory 224936 kb
Host smart-67954af1-8e12-4a64-94d9-080d1e11acb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053949878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3053949878
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.745587943
Short name T216
Test name
Test status
Simulation time 10418399033 ps
CPU time 32.45 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:18:26 PM PDT 24
Peak memory 235848 kb
Host smart-5cd29833-ed83-4d9e-8489-955a4f33467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745587943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.745587943
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1276345035
Short name T631
Test name
Test status
Simulation time 372214850 ps
CPU time 6.69 seconds
Started Jul 19 06:17:44 PM PDT 24
Finished Jul 19 06:17:51 PM PDT 24
Peak memory 220168 kb
Host smart-f3e67fec-4fc6-4251-90b4-842fc163e0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276345035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1276345035
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.820569473
Short name T192
Test name
Test status
Simulation time 24925731397 ps
CPU time 45.85 seconds
Started Jul 19 06:17:44 PM PDT 24
Finished Jul 19 06:18:30 PM PDT 24
Peak memory 249072 kb
Host smart-2218a9e8-f59c-4680-9081-0afc38489d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820569473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.820569473
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1826284269
Short name T718
Test name
Test status
Simulation time 2140931860 ps
CPU time 2.77 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:17:47 PM PDT 24
Peak memory 224964 kb
Host smart-449531f7-375c-46f5-b3a8-d14e3635f878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826284269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1826284269
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3272275034
Short name T970
Test name
Test status
Simulation time 413680230 ps
CPU time 3.49 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:17:47 PM PDT 24
Peak memory 233100 kb
Host smart-7f3b9b06-bf98-4a04-a9a9-e3965d0bc366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272275034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3272275034
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3558755825
Short name T140
Test name
Test status
Simulation time 3405830943 ps
CPU time 11.47 seconds
Started Jul 19 06:17:52 PM PDT 24
Finished Jul 19 06:18:04 PM PDT 24
Peak memory 221316 kb
Host smart-fadf706c-7f7a-45c2-bdf1-2e66d0caa9f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3558755825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3558755825
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1950905504
Short name T277
Test name
Test status
Simulation time 122600813270 ps
CPU time 1137.72 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:36:52 PM PDT 24
Peak memory 280888 kb
Host smart-4bcd77bf-9375-4590-9341-e258f257b16a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950905504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1950905504
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1402971978
Short name T423
Test name
Test status
Simulation time 3058515139 ps
CPU time 25.25 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:18:09 PM PDT 24
Peak memory 217004 kb
Host smart-f2c2b73d-af53-4d08-9833-165e6d9f79ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402971978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1402971978
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3640661472
Short name T459
Test name
Test status
Simulation time 23759836209 ps
CPU time 19.16 seconds
Started Jul 19 06:17:44 PM PDT 24
Finished Jul 19 06:18:04 PM PDT 24
Peak memory 216784 kb
Host smart-7c8a2d19-5c12-4d0f-a496-0e4185706e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640661472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3640661472
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1194755184
Short name T16
Test name
Test status
Simulation time 92542909 ps
CPU time 4.6 seconds
Started Jul 19 06:17:42 PM PDT 24
Finished Jul 19 06:17:47 PM PDT 24
Peak memory 216676 kb
Host smart-e5d22845-cf2b-401d-8942-028a717fdbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194755184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1194755184
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2194846359
Short name T627
Test name
Test status
Simulation time 46249631 ps
CPU time 0.79 seconds
Started Jul 19 06:17:43 PM PDT 24
Finished Jul 19 06:17:45 PM PDT 24
Peak memory 206452 kb
Host smart-dedd9e05-bcf6-4227-90fd-0cd32426bcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194846359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2194846359
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1750733539
Short name T943
Test name
Test status
Simulation time 883091103 ps
CPU time 4.4 seconds
Started Jul 19 06:17:54 PM PDT 24
Finished Jul 19 06:17:59 PM PDT 24
Peak memory 236036 kb
Host smart-daaed50d-9bc6-4ff9-a586-83e4854f8b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750733539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1750733539
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2246660926
Short name T480
Test name
Test status
Simulation time 45419388 ps
CPU time 0.73 seconds
Started Jul 19 06:17:59 PM PDT 24
Finished Jul 19 06:18:01 PM PDT 24
Peak memory 205372 kb
Host smart-e90199ae-26fe-4b3a-886b-83ebd8d7e528
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246660926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2246660926
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.606331967
Short name T257
Test name
Test status
Simulation time 384887298 ps
CPU time 5.72 seconds
Started Jul 19 06:18:05 PM PDT 24
Finished Jul 19 06:18:11 PM PDT 24
Peak memory 233104 kb
Host smart-cbb28940-dd6d-445a-a0f6-d840cfb69f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606331967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.606331967
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2478067158
Short name T693
Test name
Test status
Simulation time 16743289 ps
CPU time 0.79 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:17:55 PM PDT 24
Peak memory 206044 kb
Host smart-140d5423-5d74-4add-bd06-61c384c02cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478067158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2478067158
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.688961381
Short name T917
Test name
Test status
Simulation time 20089021658 ps
CPU time 103.45 seconds
Started Jul 19 06:18:09 PM PDT 24
Finished Jul 19 06:19:54 PM PDT 24
Peak memory 257216 kb
Host smart-4b4fc285-c87c-4f84-9e6c-d47c5a2f2460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688961381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.688961381
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.4178559970
Short name T800
Test name
Test status
Simulation time 4133182753 ps
CPU time 84.47 seconds
Started Jul 19 06:18:00 PM PDT 24
Finished Jul 19 06:19:25 PM PDT 24
Peak memory 253400 kb
Host smart-7b4f6719-d7a1-40af-abfa-a589c6ff1df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178559970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.4178559970
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2378174984
Short name T874
Test name
Test status
Simulation time 2524543205 ps
CPU time 21.6 seconds
Started Jul 19 06:18:04 PM PDT 24
Finished Jul 19 06:18:27 PM PDT 24
Peak memory 233124 kb
Host smart-c57a3675-84cd-4546-b27e-514796a62614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378174984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2378174984
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3473424291
Short name T49
Test name
Test status
Simulation time 137072394 ps
CPU time 2.09 seconds
Started Jul 19 06:18:05 PM PDT 24
Finished Jul 19 06:18:08 PM PDT 24
Peak memory 224868 kb
Host smart-0a53ad95-f74d-4e4e-a835-29b85922eab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473424291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3473424291
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2037656619
Short name T1004
Test name
Test status
Simulation time 940579678 ps
CPU time 6.41 seconds
Started Jul 19 06:18:01 PM PDT 24
Finished Jul 19 06:18:08 PM PDT 24
Peak memory 224884 kb
Host smart-a8552144-6da5-459b-8d0b-695ed0ccc9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037656619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2037656619
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1094351778
Short name T235
Test name
Test status
Simulation time 11613209176 ps
CPU time 12.95 seconds
Started Jul 19 06:18:05 PM PDT 24
Finished Jul 19 06:18:18 PM PDT 24
Peak memory 225000 kb
Host smart-f8a3527c-dea3-460b-a595-301f2b8f167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094351778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1094351778
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.866135164
Short name T506
Test name
Test status
Simulation time 191242452 ps
CPU time 3.65 seconds
Started Jul 19 06:18:00 PM PDT 24
Finished Jul 19 06:18:04 PM PDT 24
Peak memory 220632 kb
Host smart-373e2c3d-a162-496c-ba20-6d4058f3b307
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=866135164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.866135164
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2771552717
Short name T683
Test name
Test status
Simulation time 2701408308 ps
CPU time 25.39 seconds
Started Jul 19 06:18:05 PM PDT 24
Finished Jul 19 06:18:31 PM PDT 24
Peak memory 241388 kb
Host smart-b390e14e-79f7-4af5-8c0a-8fd57c1282c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771552717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2771552717
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.3982623735
Short name T313
Test name
Test status
Simulation time 11772279137 ps
CPU time 10.87 seconds
Started Jul 19 06:17:54 PM PDT 24
Finished Jul 19 06:18:06 PM PDT 24
Peak memory 216772 kb
Host smart-e38a27cb-406e-41db-a927-aa94d5e652a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982623735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3982623735
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.1704694826
Short name T615
Test name
Test status
Simulation time 2819708172 ps
CPU time 9.6 seconds
Started Jul 19 06:17:52 PM PDT 24
Finished Jul 19 06:18:03 PM PDT 24
Peak memory 216776 kb
Host smart-6c7faf1c-de66-43e6-ba59-002e73627fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704694826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.1704694826
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2532499010
Short name T366
Test name
Test status
Simulation time 597786823 ps
CPU time 3.45 seconds
Started Jul 19 06:18:03 PM PDT 24
Finished Jul 19 06:18:07 PM PDT 24
Peak memory 216644 kb
Host smart-69aae2b8-3bac-4729-a415-b01de3cc3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532499010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2532499010
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3416109023
Short name T871
Test name
Test status
Simulation time 86750026 ps
CPU time 0.79 seconds
Started Jul 19 06:17:53 PM PDT 24
Finished Jul 19 06:17:54 PM PDT 24
Peak memory 206432 kb
Host smart-38498244-8228-40c6-8fcb-688decc614b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416109023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3416109023
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1549249396
Short name T215
Test name
Test status
Simulation time 13011354516 ps
CPU time 42.64 seconds
Started Jul 19 06:17:59 PM PDT 24
Finished Jul 19 06:18:42 PM PDT 24
Peak memory 236096 kb
Host smart-e3bea6b7-9e37-4172-87ef-4c8cbc88dcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549249396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1549249396
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.215967908
Short name T395
Test name
Test status
Simulation time 49731944 ps
CPU time 0.74 seconds
Started Jul 19 06:18:08 PM PDT 24
Finished Jul 19 06:18:09 PM PDT 24
Peak memory 205316 kb
Host smart-20aa1b25-0685-490b-b94b-5e3cad9ad5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215967908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.215967908
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1530688432
Short name T715
Test name
Test status
Simulation time 363748566 ps
CPU time 3.01 seconds
Started Jul 19 06:18:09 PM PDT 24
Finished Jul 19 06:18:13 PM PDT 24
Peak memory 224944 kb
Host smart-7cfc9a6f-0a9c-4ae4-99e0-4b41c65ec108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530688432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1530688432
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1391428339
Short name T886
Test name
Test status
Simulation time 12813550 ps
CPU time 0.76 seconds
Started Jul 19 06:18:03 PM PDT 24
Finished Jul 19 06:18:04 PM PDT 24
Peak memory 206048 kb
Host smart-b4bc5d98-2e03-432c-951b-aeb689f025f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391428339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1391428339
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.2094231559
Short name T824
Test name
Test status
Simulation time 1273519841 ps
CPU time 6.41 seconds
Started Jul 19 06:18:08 PM PDT 24
Finished Jul 19 06:18:15 PM PDT 24
Peak memory 224892 kb
Host smart-b0f51e0a-ee1b-4425-9ec4-680758a7ef88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094231559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.2094231559
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.764674444
Short name T14
Test name
Test status
Simulation time 1291714873 ps
CPU time 28.01 seconds
Started Jul 19 06:18:06 PM PDT 24
Finished Jul 19 06:18:35 PM PDT 24
Peak memory 251612 kb
Host smart-4d01efda-71e5-4db0-bfc2-a4314fb3cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764674444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.764674444
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.933193166
Short name T562
Test name
Test status
Simulation time 673788450 ps
CPU time 3.93 seconds
Started Jul 19 06:18:07 PM PDT 24
Finished Jul 19 06:18:12 PM PDT 24
Peak memory 235328 kb
Host smart-324fbbfd-23e0-492e-9208-81328f22295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933193166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.933193166
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3675887872
Short name T181
Test name
Test status
Simulation time 12125732995 ps
CPU time 44.42 seconds
Started Jul 19 06:18:09 PM PDT 24
Finished Jul 19 06:18:54 PM PDT 24
Peak memory 224996 kb
Host smart-8a36b9bd-6497-4667-bc3a-a72c0226b19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675887872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3675887872
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.582764162
Short name T766
Test name
Test status
Simulation time 4680635801 ps
CPU time 24.2 seconds
Started Jul 19 06:18:07 PM PDT 24
Finished Jul 19 06:18:32 PM PDT 24
Peak memory 233152 kb
Host smart-9049df8f-737f-4255-bec1-8bde4708dc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582764162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.582764162
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4167199574
Short name T513
Test name
Test status
Simulation time 161997835 ps
CPU time 4.5 seconds
Started Jul 19 06:18:07 PM PDT 24
Finished Jul 19 06:18:12 PM PDT 24
Peak memory 233104 kb
Host smart-0548b280-b788-4b3e-aeb7-6d9d03a5303c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167199574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4167199574
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1972592891
Short name T511
Test name
Test status
Simulation time 62324056490 ps
CPU time 43.56 seconds
Started Jul 19 06:18:09 PM PDT 24
Finished Jul 19 06:18:53 PM PDT 24
Peak memory 233224 kb
Host smart-068c1b36-60ef-4b09-a854-e0f57c20d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972592891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1972592891
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1312210455
Short name T812
Test name
Test status
Simulation time 1007521110 ps
CPU time 6.17 seconds
Started Jul 19 06:18:10 PM PDT 24
Finished Jul 19 06:18:17 PM PDT 24
Peak memory 222948 kb
Host smart-b14883b7-12ac-4947-8020-41e32fc7813c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1312210455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1312210455
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3118714700
Short name T641
Test name
Test status
Simulation time 175705139 ps
CPU time 0.95 seconds
Started Jul 19 06:18:08 PM PDT 24
Finished Jul 19 06:18:09 PM PDT 24
Peak memory 207856 kb
Host smart-8334a524-bf64-4e14-95fb-b4b7a96790be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118714700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3118714700
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2345720575
Short name T945
Test name
Test status
Simulation time 2592697046 ps
CPU time 32.11 seconds
Started Jul 19 06:18:08 PM PDT 24
Finished Jul 19 06:18:41 PM PDT 24
Peak memory 217132 kb
Host smart-a811ba84-3910-4005-a536-d863e8280ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345720575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2345720575
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2976777575
Short name T957
Test name
Test status
Simulation time 2831130144 ps
CPU time 7.74 seconds
Started Jul 19 06:18:08 PM PDT 24
Finished Jul 19 06:18:16 PM PDT 24
Peak memory 216708 kb
Host smart-a75b0786-5d3d-49cd-9e69-fb514c57e521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976777575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2976777575
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1422853550
Short name T688
Test name
Test status
Simulation time 74290928 ps
CPU time 0.9 seconds
Started Jul 19 06:18:07 PM PDT 24
Finished Jul 19 06:18:09 PM PDT 24
Peak memory 207468 kb
Host smart-0f7808b4-ccdd-4cb3-b23c-14ffc105f8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1422853550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1422853550
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.1836830427
Short name T930
Test name
Test status
Simulation time 107396022 ps
CPU time 0.85 seconds
Started Jul 19 06:18:07 PM PDT 24
Finished Jul 19 06:18:08 PM PDT 24
Peak memory 206424 kb
Host smart-afafcb38-17b4-4d19-b838-307d34b22382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836830427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1836830427
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3640167047
Short name T202
Test name
Test status
Simulation time 638377651 ps
CPU time 4.13 seconds
Started Jul 19 06:18:09 PM PDT 24
Finished Jul 19 06:18:14 PM PDT 24
Peak memory 233120 kb
Host smart-3f52b2ac-bc74-4633-8e23-c37192768198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640167047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3640167047
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3331058868
Short name T52
Test name
Test status
Simulation time 33936457 ps
CPU time 0.72 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:18:18 PM PDT 24
Peak memory 205332 kb
Host smart-0df42e20-7db3-40b2-a814-4d87af212fc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331058868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3331058868
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1412194301
Short name T526
Test name
Test status
Simulation time 1096438308 ps
CPU time 13.75 seconds
Started Jul 19 06:18:15 PM PDT 24
Finished Jul 19 06:18:29 PM PDT 24
Peak memory 224872 kb
Host smart-7279ade8-c176-47f9-83e1-41d11ceb462b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412194301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1412194301
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1969217761
Short name T758
Test name
Test status
Simulation time 188691738 ps
CPU time 0.75 seconds
Started Jul 19 06:18:08 PM PDT 24
Finished Jul 19 06:18:09 PM PDT 24
Peak memory 207380 kb
Host smart-81ccf6f5-c0b9-4cf0-9b43-f77429feea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969217761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1969217761
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3715242862
Short name T985
Test name
Test status
Simulation time 10824144855 ps
CPU time 43.06 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 257400 kb
Host smart-71ff9058-30ba-402d-86fc-c5c6600e55d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715242862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3715242862
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2672697576
Short name T617
Test name
Test status
Simulation time 7238331272 ps
CPU time 83.28 seconds
Started Jul 19 06:18:15 PM PDT 24
Finished Jul 19 06:19:39 PM PDT 24
Peak memory 249580 kb
Host smart-f43609ae-6c05-4916-b2e9-b7f3c6d840ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672697576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2672697576
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2814344399
Short name T64
Test name
Test status
Simulation time 5238823009 ps
CPU time 87.6 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:19:44 PM PDT 24
Peak memory 249644 kb
Host smart-f1ae5b54-40bc-4747-8ff4-2cf843c6494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814344399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2814344399
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3425636153
Short name T769
Test name
Test status
Simulation time 596374090 ps
CPU time 4.06 seconds
Started Jul 19 06:18:14 PM PDT 24
Finished Jul 19 06:18:19 PM PDT 24
Peak memory 233148 kb
Host smart-c3e05589-7da6-44c5-a89e-8e82ae1c3c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425636153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3425636153
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.449372931
Short name T512
Test name
Test status
Simulation time 99733438487 ps
CPU time 184.74 seconds
Started Jul 19 06:18:17 PM PDT 24
Finished Jul 19 06:21:22 PM PDT 24
Peak memory 252852 kb
Host smart-47519b19-36b3-454e-a196-c161a4b85e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449372931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.449372931
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3116372518
Short name T78
Test name
Test status
Simulation time 3333468822 ps
CPU time 10.88 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:18:28 PM PDT 24
Peak memory 233148 kb
Host smart-f48008bf-1703-4231-b9da-40fbf326cb88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116372518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3116372518
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2263385069
Short name T464
Test name
Test status
Simulation time 1283486196 ps
CPU time 9.35 seconds
Started Jul 19 06:18:15 PM PDT 24
Finished Jul 19 06:18:25 PM PDT 24
Peak memory 236808 kb
Host smart-9833bd4e-6a34-480c-9d63-6425679252db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263385069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2263385069
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3078304584
Short name T851
Test name
Test status
Simulation time 59821078231 ps
CPU time 15.92 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:18:33 PM PDT 24
Peak memory 233164 kb
Host smart-361a2730-b23a-49e6-a3c3-8618f1966c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078304584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3078304584
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.4063426897
Short name T849
Test name
Test status
Simulation time 1029142228 ps
CPU time 4.43 seconds
Started Jul 19 06:18:14 PM PDT 24
Finished Jul 19 06:18:19 PM PDT 24
Peak memory 233092 kb
Host smart-c06ec7a4-e8ac-492f-abfb-a18d774724cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063426897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4063426897
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1985807720
Short name T983
Test name
Test status
Simulation time 648425346 ps
CPU time 4.65 seconds
Started Jul 19 06:18:14 PM PDT 24
Finished Jul 19 06:18:20 PM PDT 24
Peak memory 219452 kb
Host smart-6df5fe62-1ae2-4de6-adef-170dfa86826d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1985807720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1985807720
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3121643198
Short name T19
Test name
Test status
Simulation time 228659639 ps
CPU time 1.12 seconds
Started Jul 19 06:18:17 PM PDT 24
Finished Jul 19 06:18:19 PM PDT 24
Peak memory 208100 kb
Host smart-84357a51-508a-44b4-84f6-78e7fa6bcf2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121643198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3121643198
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3396214710
Short name T415
Test name
Test status
Simulation time 1018541466 ps
CPU time 19.91 seconds
Started Jul 19 06:18:14 PM PDT 24
Finished Jul 19 06:18:35 PM PDT 24
Peak memory 216716 kb
Host smart-5e59e581-33ab-4729-b977-dab360c7be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396214710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3396214710
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1452774761
Short name T363
Test name
Test status
Simulation time 20287279 ps
CPU time 0.73 seconds
Started Jul 19 06:18:09 PM PDT 24
Finished Jul 19 06:18:11 PM PDT 24
Peak memory 206160 kb
Host smart-1f62af0e-760d-419a-bc38-0e932770d3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452774761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1452774761
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3518704098
Short name T743
Test name
Test status
Simulation time 245923665 ps
CPU time 0.98 seconds
Started Jul 19 06:18:15 PM PDT 24
Finished Jul 19 06:18:17 PM PDT 24
Peak memory 208344 kb
Host smart-2b4e339f-c78d-4123-904e-05029f7f7baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518704098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3518704098
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3854185568
Short name T993
Test name
Test status
Simulation time 570216705 ps
CPU time 0.9 seconds
Started Jul 19 06:18:17 PM PDT 24
Finished Jul 19 06:18:18 PM PDT 24
Peak memory 206480 kb
Host smart-da28c97b-c4b0-4056-ac13-1824cc25f24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854185568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3854185568
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.184843233
Short name T343
Test name
Test status
Simulation time 534749971 ps
CPU time 3.03 seconds
Started Jul 19 06:18:14 PM PDT 24
Finished Jul 19 06:18:18 PM PDT 24
Peak memory 233100 kb
Host smart-e06be794-5d88-466a-9bd3-60961a565313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184843233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.184843233
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2931809206
Short name T393
Test name
Test status
Simulation time 33305249 ps
CPU time 0.69 seconds
Started Jul 19 06:18:25 PM PDT 24
Finished Jul 19 06:18:27 PM PDT 24
Peak memory 206292 kb
Host smart-7e74886a-3b23-4673-ab74-22c18ad5c5b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931809206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2931809206
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3133173594
Short name T556
Test name
Test status
Simulation time 7410557395 ps
CPU time 13.74 seconds
Started Jul 19 06:18:27 PM PDT 24
Finished Jul 19 06:18:42 PM PDT 24
Peak memory 224968 kb
Host smart-7e41f8ab-e589-445b-8836-0ec2f39b1bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133173594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3133173594
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2716011237
Short name T938
Test name
Test status
Simulation time 33917693 ps
CPU time 0.74 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:18:17 PM PDT 24
Peak memory 206356 kb
Host smart-4239019a-c7f2-4a14-bdae-6339597e06ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716011237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2716011237
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2194813598
Short name T206
Test name
Test status
Simulation time 12226541609 ps
CPU time 87.93 seconds
Started Jul 19 06:18:26 PM PDT 24
Finished Jul 19 06:19:55 PM PDT 24
Peak memory 237216 kb
Host smart-8b8308b5-cb05-485d-8dd0-e2f8d02ca552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194813598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2194813598
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.555989115
Short name T802
Test name
Test status
Simulation time 107743430082 ps
CPU time 246.48 seconds
Started Jul 19 06:18:26 PM PDT 24
Finished Jul 19 06:22:33 PM PDT 24
Peak memory 260892 kb
Host smart-6398ada9-6f31-4d62-96fd-d4cc197ff05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555989115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.555989115
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3239272567
Short name T134
Test name
Test status
Simulation time 4570076400 ps
CPU time 26.73 seconds
Started Jul 19 06:18:27 PM PDT 24
Finished Jul 19 06:18:54 PM PDT 24
Peak memory 224268 kb
Host smart-a5c818b5-be9c-49f2-8e88-41d3ed3da9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239272567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3239272567
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1674364568
Short name T303
Test name
Test status
Simulation time 741949377 ps
CPU time 7.97 seconds
Started Jul 19 06:18:25 PM PDT 24
Finished Jul 19 06:18:33 PM PDT 24
Peak memory 239892 kb
Host smart-0f9c1a6a-308e-4680-b536-4f9806617d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674364568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1674364568
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.4183804908
Short name T82
Test name
Test status
Simulation time 10322029949 ps
CPU time 37.6 seconds
Started Jul 19 06:18:24 PM PDT 24
Finished Jul 19 06:19:02 PM PDT 24
Peak memory 241024 kb
Host smart-9f12e16f-29b9-4b63-a7db-57aa3399d038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183804908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.4183804908
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3235827015
Short name T616
Test name
Test status
Simulation time 534479322 ps
CPU time 6.19 seconds
Started Jul 19 06:18:24 PM PDT 24
Finished Jul 19 06:18:30 PM PDT 24
Peak memory 224912 kb
Host smart-121f9ff4-b285-403e-bb25-6345457de47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235827015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3235827015
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.817208917
Short name T610
Test name
Test status
Simulation time 37026973592 ps
CPU time 50.32 seconds
Started Jul 19 06:18:24 PM PDT 24
Finished Jul 19 06:19:15 PM PDT 24
Peak memory 237540 kb
Host smart-205d7246-05a2-4849-a7cc-c915ab06fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817208917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.817208917
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3490696975
Short name T668
Test name
Test status
Simulation time 1279221031 ps
CPU time 4.02 seconds
Started Jul 19 06:18:26 PM PDT 24
Finished Jul 19 06:18:31 PM PDT 24
Peak memory 233140 kb
Host smart-41288577-c019-4b98-bafc-e9840bfb6178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490696975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3490696975
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2049278570
Short name T434
Test name
Test status
Simulation time 8691550107 ps
CPU time 4.03 seconds
Started Jul 19 06:18:28 PM PDT 24
Finished Jul 19 06:18:33 PM PDT 24
Peak memory 233148 kb
Host smart-2ae49337-d8ab-4c79-9234-0ed9875e91d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049278570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2049278570
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3210956743
Short name T449
Test name
Test status
Simulation time 2037659580 ps
CPU time 7.11 seconds
Started Jul 19 06:18:25 PM PDT 24
Finished Jul 19 06:18:33 PM PDT 24
Peak memory 220484 kb
Host smart-d202c43e-f6f9-44b8-be30-6a9690f2f08e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3210956743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3210956743
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2880088701
Short name T586
Test name
Test status
Simulation time 86069633 ps
CPU time 1.02 seconds
Started Jul 19 06:18:25 PM PDT 24
Finished Jul 19 06:18:27 PM PDT 24
Peak memory 207516 kb
Host smart-a9880079-06bc-4275-9a76-83be44ca8212
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880088701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2880088701
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3048303023
Short name T798
Test name
Test status
Simulation time 10067848770 ps
CPU time 31.69 seconds
Started Jul 19 06:18:18 PM PDT 24
Finished Jul 19 06:18:51 PM PDT 24
Peak memory 220328 kb
Host smart-b9ab2336-bc90-46f0-8e05-266abb994aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048303023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3048303023
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2787547113
Short name T326
Test name
Test status
Simulation time 51139927363 ps
CPU time 11.83 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:18:29 PM PDT 24
Peak memory 216768 kb
Host smart-a1614870-d67a-4e8a-bb91-9a3489795ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787547113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2787547113
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.1664202399
Short name T826
Test name
Test status
Simulation time 76412929 ps
CPU time 1.17 seconds
Started Jul 19 06:18:25 PM PDT 24
Finished Jul 19 06:18:26 PM PDT 24
Peak memory 208344 kb
Host smart-44f43c45-8cb2-449e-9e1f-fc422746fac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664202399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1664202399
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2437196046
Short name T354
Test name
Test status
Simulation time 176373364 ps
CPU time 0.85 seconds
Started Jul 19 06:18:16 PM PDT 24
Finished Jul 19 06:18:17 PM PDT 24
Peak memory 206400 kb
Host smart-ea7bc380-d770-4a3d-8bea-a562ad8cc138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437196046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2437196046
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1650088553
Short name T772
Test name
Test status
Simulation time 8866847763 ps
CPU time 13.99 seconds
Started Jul 19 06:18:26 PM PDT 24
Finished Jul 19 06:18:40 PM PDT 24
Peak memory 250900 kb
Host smart-d952aa80-0923-4fde-8116-4944c2d4fa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650088553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1650088553
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.10054028
Short name T662
Test name
Test status
Simulation time 89256341 ps
CPU time 0.76 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:18:37 PM PDT 24
Peak memory 205932 kb
Host smart-ff442f5a-dada-4d2d-8a17-a614ce8c5d98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10054028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.10054028
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3706954721
Short name T482
Test name
Test status
Simulation time 187826283 ps
CPU time 3.79 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:18:40 PM PDT 24
Peak memory 224948 kb
Host smart-0a89b68e-3cba-4a6b-b0a0-2b24ca9db395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706954721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3706954721
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4289121350
Short name T595
Test name
Test status
Simulation time 15878413 ps
CPU time 0.82 seconds
Started Jul 19 06:18:26 PM PDT 24
Finished Jul 19 06:18:28 PM PDT 24
Peak memory 207388 kb
Host smart-383f12f3-11d8-41b1-8ba8-f36fb8f25a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289121350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4289121350
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2517606587
Short name T880
Test name
Test status
Simulation time 23333432078 ps
CPU time 78.09 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:19:54 PM PDT 24
Peak memory 257804 kb
Host smart-cdd13c5f-7657-43e5-a5fd-bb8c43fe6b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517606587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2517606587
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4126354152
Short name T177
Test name
Test status
Simulation time 5737249996 ps
CPU time 41.53 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:19:18 PM PDT 24
Peak memory 257460 kb
Host smart-0265d4e8-8c5d-4e3a-a501-4ae6d463fe72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126354152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4126354152
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3420609787
Short name T362
Test name
Test status
Simulation time 264881432 ps
CPU time 4.25 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:18:39 PM PDT 24
Peak memory 225072 kb
Host smart-a181b6ed-9d55-4a9b-8f5e-667cd893af3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420609787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3420609787
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1015566292
Short name T280
Test name
Test status
Simulation time 1176340765 ps
CPU time 28.05 seconds
Started Jul 19 06:18:32 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 249528 kb
Host smart-a85f9ae0-16f4-44f9-81a1-71f9e7a78105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015566292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1015566292
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3523745585
Short name T452
Test name
Test status
Simulation time 31309289 ps
CPU time 2.56 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:18:38 PM PDT 24
Peak memory 232792 kb
Host smart-37c54b67-c10d-45df-a5c5-ca885cc8dd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523745585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3523745585
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.1689144786
Short name T952
Test name
Test status
Simulation time 2639860638 ps
CPU time 31.31 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:19:07 PM PDT 24
Peak memory 225056 kb
Host smart-96cabcab-2c94-4625-9251-db0b374d6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689144786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.1689144786
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3106912524
Short name T267
Test name
Test status
Simulation time 432684878 ps
CPU time 7.86 seconds
Started Jul 19 06:18:38 PM PDT 24
Finished Jul 19 06:18:46 PM PDT 24
Peak memory 238724 kb
Host smart-f2049d59-1389-49c1-9269-b81df281178d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106912524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3106912524
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3392235581
Short name T813
Test name
Test status
Simulation time 1121807246 ps
CPU time 8.5 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:18:43 PM PDT 24
Peak memory 240984 kb
Host smart-6579c83f-bbe2-4e3b-aecd-5a02dae48eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392235581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3392235581
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1537504249
Short name T392
Test name
Test status
Simulation time 554217516 ps
CPU time 5.53 seconds
Started Jul 19 06:18:33 PM PDT 24
Finished Jul 19 06:18:39 PM PDT 24
Peak memory 220924 kb
Host smart-2f182499-db28-4e4f-9abd-444ec04a82b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1537504249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1537504249
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2888045036
Short name T638
Test name
Test status
Simulation time 18785026061 ps
CPU time 25.33 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:19:01 PM PDT 24
Peak memory 216772 kb
Host smart-caae9d3f-d0fc-465c-909b-f085108a802d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888045036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2888045036
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2824469158
Short name T75
Test name
Test status
Simulation time 2473219135 ps
CPU time 2.34 seconds
Started Jul 19 06:18:30 PM PDT 24
Finished Jul 19 06:18:33 PM PDT 24
Peak memory 216596 kb
Host smart-58a5e09c-63d1-41a1-af42-e587c007046f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824469158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2824469158
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3840125175
Short name T316
Test name
Test status
Simulation time 201327784 ps
CPU time 1.53 seconds
Started Jul 19 06:18:33 PM PDT 24
Finished Jul 19 06:18:35 PM PDT 24
Peak memory 216628 kb
Host smart-7f1f5f4e-d6d8-43a0-a671-13bfce332c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840125175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3840125175
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2915750628
Short name T523
Test name
Test status
Simulation time 45794689 ps
CPU time 0.9 seconds
Started Jul 19 06:18:33 PM PDT 24
Finished Jul 19 06:18:35 PM PDT 24
Peak memory 207440 kb
Host smart-09504804-5935-414e-be99-ffb94a6e0a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915750628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2915750628
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2626229520
Short name T852
Test name
Test status
Simulation time 5010025214 ps
CPU time 7.29 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:18:42 PM PDT 24
Peak memory 233244 kb
Host smart-40b7a184-7461-448b-84ba-d4fe70dd8b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626229520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2626229520
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3661618651
Short name T956
Test name
Test status
Simulation time 14459039 ps
CPU time 0.73 seconds
Started Jul 19 06:15:34 PM PDT 24
Finished Jul 19 06:15:36 PM PDT 24
Peak memory 205972 kb
Host smart-d7199d5a-9253-440f-b9cd-bc5c2527f88e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661618651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
661618651
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.3040436644
Short name T558
Test name
Test status
Simulation time 39078808 ps
CPU time 2.5 seconds
Started Jul 19 06:15:36 PM PDT 24
Finished Jul 19 06:15:40 PM PDT 24
Peak memory 232808 kb
Host smart-f5164991-1aa5-4c18-b0e6-fc0eb980919e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040436644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.3040436644
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.860858095
Short name T671
Test name
Test status
Simulation time 20886970 ps
CPU time 0.77 seconds
Started Jul 19 06:15:19 PM PDT 24
Finished Jul 19 06:15:20 PM PDT 24
Peak memory 207072 kb
Host smart-40154635-aed1-427a-9e1a-68ed7936aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860858095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.860858095
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2897085475
Short name T726
Test name
Test status
Simulation time 76819480316 ps
CPU time 67.68 seconds
Started Jul 19 06:15:40 PM PDT 24
Finished Jul 19 06:16:48 PM PDT 24
Peak memory 249548 kb
Host smart-32710da7-0422-4fce-9d1b-e4d105a28791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897085475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2897085475
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2633304171
Short name T205
Test name
Test status
Simulation time 98134261328 ps
CPU time 182.18 seconds
Started Jul 19 06:15:41 PM PDT 24
Finished Jul 19 06:18:44 PM PDT 24
Peak memory 269844 kb
Host smart-ed647e9c-58f3-4490-b2b2-55874dda4778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633304171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2633304171
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1033736369
Short name T780
Test name
Test status
Simulation time 2675845151 ps
CPU time 9.01 seconds
Started Jul 19 06:15:34 PM PDT 24
Finished Jul 19 06:15:44 PM PDT 24
Peak memory 233356 kb
Host smart-79ce4e8e-df98-4eff-bdac-a537322619d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033736369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1033736369
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1929718976
Short name T1006
Test name
Test status
Simulation time 16525984014 ps
CPU time 26.4 seconds
Started Jul 19 06:15:40 PM PDT 24
Finished Jul 19 06:16:07 PM PDT 24
Peak memory 224972 kb
Host smart-ad401eb1-6f27-4e32-b4c7-730af4b25eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929718976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1929718976
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4088448440
Short name T646
Test name
Test status
Simulation time 330481990 ps
CPU time 3.22 seconds
Started Jul 19 06:15:26 PM PDT 24
Finished Jul 19 06:15:30 PM PDT 24
Peak memory 224964 kb
Host smart-674ea3e8-2857-489b-b7fe-acc4bf15dad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088448440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4088448440
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.4280989835
Short name T399
Test name
Test status
Simulation time 262773084 ps
CPU time 9.46 seconds
Started Jul 19 06:15:28 PM PDT 24
Finished Jul 19 06:15:38 PM PDT 24
Peak memory 233380 kb
Host smart-fe0b8e66-b769-423e-8994-394759d7bb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280989835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.4280989835
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2560880781
Short name T607
Test name
Test status
Simulation time 4537567172 ps
CPU time 10.47 seconds
Started Jul 19 06:15:29 PM PDT 24
Finished Jul 19 06:15:40 PM PDT 24
Peak memory 233092 kb
Host smart-ae35805d-4528-4c43-a4a2-75f074f3c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560880781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2560880781
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.1907427910
Short name T929
Test name
Test status
Simulation time 2278755820 ps
CPU time 10.08 seconds
Started Jul 19 06:15:31 PM PDT 24
Finished Jul 19 06:15:41 PM PDT 24
Peak memory 224980 kb
Host smart-919c724f-8e90-4817-a0b6-aa160660e5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907427910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.1907427910
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.4215171925
Short name T408
Test name
Test status
Simulation time 590090938 ps
CPU time 6.91 seconds
Started Jul 19 06:15:35 PM PDT 24
Finished Jul 19 06:15:44 PM PDT 24
Peak memory 220368 kb
Host smart-bee3e076-3143-40f3-a678-05da7d88ea62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4215171925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.4215171925
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.111673045
Short name T62
Test name
Test status
Simulation time 73789974 ps
CPU time 0.98 seconds
Started Jul 19 06:15:39 PM PDT 24
Finished Jul 19 06:15:41 PM PDT 24
Peak memory 235844 kb
Host smart-d0ce459b-c385-4cad-bff4-dd57afb8ec73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111673045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.111673045
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2027354999
Short name T92
Test name
Test status
Simulation time 2509742715 ps
CPU time 23.08 seconds
Started Jul 19 06:15:26 PM PDT 24
Finished Jul 19 06:15:50 PM PDT 24
Peak memory 216688 kb
Host smart-8b80e8af-87b2-49f4-9894-aca428730193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027354999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2027354999
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3810956201
Short name T1005
Test name
Test status
Simulation time 20180175722 ps
CPU time 12.34 seconds
Started Jul 19 06:15:27 PM PDT 24
Finished Jul 19 06:15:39 PM PDT 24
Peak memory 216788 kb
Host smart-e5778eca-a001-4460-a90e-975ccfc47369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810956201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3810956201
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1002140018
Short name T933
Test name
Test status
Simulation time 21668992 ps
CPU time 0.97 seconds
Started Jul 19 06:15:27 PM PDT 24
Finished Jul 19 06:15:29 PM PDT 24
Peak memory 207528 kb
Host smart-d9e2d392-fc84-4a8e-9dc3-71bd0e2fccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002140018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1002140018
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3535191815
Short name T530
Test name
Test status
Simulation time 67044301 ps
CPU time 0.87 seconds
Started Jul 19 06:15:26 PM PDT 24
Finished Jul 19 06:15:28 PM PDT 24
Peak memory 206396 kb
Host smart-30c2e310-bc33-40ff-8364-ff490f9048b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535191815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3535191815
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3653814855
Short name T496
Test name
Test status
Simulation time 4420009919 ps
CPU time 14.26 seconds
Started Jul 19 06:15:27 PM PDT 24
Finished Jul 19 06:15:42 PM PDT 24
Peak memory 241364 kb
Host smart-9e6a3b6d-b624-4e28-bf70-cc81e4906036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653814855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3653814855
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3210587348
Short name T55
Test name
Test status
Simulation time 51956895 ps
CPU time 0.73 seconds
Started Jul 19 06:18:48 PM PDT 24
Finished Jul 19 06:18:50 PM PDT 24
Peak memory 205376 kb
Host smart-be558237-a69b-4945-872a-82a3f819abb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210587348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3210587348
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.92117090
Short name T328
Test name
Test status
Simulation time 2575846191 ps
CPU time 7.11 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:18:58 PM PDT 24
Peak memory 225032 kb
Host smart-1b3d4bec-28f7-4c7e-8e1e-388965437855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92117090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.92117090
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1070102202
Short name T986
Test name
Test status
Simulation time 61337655 ps
CPU time 0.75 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:18:37 PM PDT 24
Peak memory 206052 kb
Host smart-972b4835-81df-4f91-9be3-60e3e9af4f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070102202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1070102202
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.887295544
Short name T154
Test name
Test status
Simulation time 42216202968 ps
CPU time 181.09 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:21:49 PM PDT 24
Peak memory 249624 kb
Host smart-5bd07280-8b1e-4e2d-9440-07d7e22713e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887295544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.887295544
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3812172792
Short name T828
Test name
Test status
Simulation time 162210271264 ps
CPU time 397.87 seconds
Started Jul 19 06:18:46 PM PDT 24
Finished Jul 19 06:25:25 PM PDT 24
Peak memory 257816 kb
Host smart-d9587d28-b633-4713-b425-3e0c9d303522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812172792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3812172792
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2096327838
Short name T656
Test name
Test status
Simulation time 2803467878 ps
CPU time 16.43 seconds
Started Jul 19 06:18:46 PM PDT 24
Finished Jul 19 06:19:03 PM PDT 24
Peak memory 241400 kb
Host smart-af414b9d-c825-4943-822c-42778b761dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096327838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2096327838
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3503794561
Short name T32
Test name
Test status
Simulation time 8589612314 ps
CPU time 29.2 seconds
Started Jul 19 06:18:46 PM PDT 24
Finished Jul 19 06:19:16 PM PDT 24
Peak memory 224984 kb
Host smart-c0dae471-803a-4cab-ac8e-d149c7fb3d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503794561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3503794561
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.288442770
Short name T238
Test name
Test status
Simulation time 4085709927 ps
CPU time 12.66 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:01 PM PDT 24
Peak memory 233152 kb
Host smart-e70803ef-0139-4c77-9cc3-378ac9ec8479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288442770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.288442770
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.550322848
Short name T555
Test name
Test status
Simulation time 1642314344 ps
CPU time 12.25 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 234480 kb
Host smart-703206c0-f71b-43e7-8fc7-2198bcacfc4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550322848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.550322848
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.963227782
Short name T461
Test name
Test status
Simulation time 663200672 ps
CPU time 4.59 seconds
Started Jul 19 06:18:50 PM PDT 24
Finished Jul 19 06:18:56 PM PDT 24
Peak memory 233120 kb
Host smart-87469643-8d10-4a73-b117-3e3a380be3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963227782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.963227782
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1319939244
Short name T248
Test name
Test status
Simulation time 2654170115 ps
CPU time 3.16 seconds
Started Jul 19 06:18:35 PM PDT 24
Finished Jul 19 06:18:39 PM PDT 24
Peak memory 225040 kb
Host smart-b6c3db85-8b4a-406f-88ef-70e56fe17250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319939244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1319939244
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3242726439
Short name T569
Test name
Test status
Simulation time 2926093528 ps
CPU time 11.1 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 221280 kb
Host smart-597024c7-fc2b-4c86-8a3c-3a1a9685018a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3242726439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3242726439
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.116573874
Short name T841
Test name
Test status
Simulation time 50069964 ps
CPU time 1.07 seconds
Started Jul 19 06:19:00 PM PDT 24
Finished Jul 19 06:19:01 PM PDT 24
Peak memory 207436 kb
Host smart-e06fadaf-ded6-4152-ae56-51df13165b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116573874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stres
s_all.116573874
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.694747142
Short name T309
Test name
Test status
Simulation time 19834928657 ps
CPU time 45.44 seconds
Started Jul 19 06:18:36 PM PDT 24
Finished Jul 19 06:19:22 PM PDT 24
Peak memory 216624 kb
Host smart-52aab645-e5b0-45ff-b5e4-502ff14524f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694747142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.694747142
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1657027737
Short name T941
Test name
Test status
Simulation time 1054512184 ps
CPU time 4.68 seconds
Started Jul 19 06:18:36 PM PDT 24
Finished Jul 19 06:18:42 PM PDT 24
Peak memory 216584 kb
Host smart-b9aa316d-81b9-40fc-af52-93a9850b7761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657027737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1657027737
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.346192205
Short name T679
Test name
Test status
Simulation time 26980325 ps
CPU time 1.1 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:18:36 PM PDT 24
Peak memory 207928 kb
Host smart-e5b3a15f-ecba-41c1-8ecd-948fda1457d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346192205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.346192205
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2334890746
Short name T74
Test name
Test status
Simulation time 22872803 ps
CPU time 0.8 seconds
Started Jul 19 06:18:34 PM PDT 24
Finished Jul 19 06:18:36 PM PDT 24
Peak memory 206444 kb
Host smart-36e89781-f8db-4876-9cc4-31a8bf02105b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334890746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2334890746
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.562218657
Short name T237
Test name
Test status
Simulation time 4489170464 ps
CPU time 3.77 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:18:52 PM PDT 24
Peak memory 233220 kb
Host smart-e8beaf7b-0394-48ea-bddf-da4135ef6efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562218657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.562218657
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3115079494
Short name T557
Test name
Test status
Simulation time 50720980 ps
CPU time 0.73 seconds
Started Jul 19 06:18:48 PM PDT 24
Finished Jul 19 06:18:50 PM PDT 24
Peak memory 205352 kb
Host smart-5c8aacc0-f0ca-4b20-8a94-6280daddcf0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115079494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3115079494
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3223504053
Short name T601
Test name
Test status
Simulation time 185496085 ps
CPU time 3.97 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:18:54 PM PDT 24
Peak memory 224804 kb
Host smart-ff286594-ffeb-4561-bdbe-b53b8bf53afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223504053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3223504053
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2119940937
Short name T546
Test name
Test status
Simulation time 33188357 ps
CPU time 0.87 seconds
Started Jul 19 06:18:50 PM PDT 24
Finished Jul 19 06:18:52 PM PDT 24
Peak memory 207036 kb
Host smart-7297e951-e5a2-4199-9485-3f313f03970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119940937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2119940937
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4260715170
Short name T340
Test name
Test status
Simulation time 42062664 ps
CPU time 0.76 seconds
Started Jul 19 06:18:48 PM PDT 24
Finished Jul 19 06:18:50 PM PDT 24
Peak memory 216244 kb
Host smart-a528489b-5d00-4347-adf6-d7fb2c81d0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260715170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4260715170
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.1655073259
Short name T961
Test name
Test status
Simulation time 52300794206 ps
CPU time 465.75 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:26:34 PM PDT 24
Peak memory 252224 kb
Host smart-a7a7df8d-676d-4004-9f4a-a9ac92239bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655073259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1655073259
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.749110357
Short name T207
Test name
Test status
Simulation time 1919866984 ps
CPU time 52.41 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:41 PM PDT 24
Peak memory 250984 kb
Host smart-a555ebd0-3e2c-4b6d-bcd6-433400527266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749110357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.749110357
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1721238228
Short name T428
Test name
Test status
Simulation time 320058031 ps
CPU time 4.46 seconds
Started Jul 19 06:18:50 PM PDT 24
Finished Jul 19 06:18:56 PM PDT 24
Peak memory 238408 kb
Host smart-a47b3ca1-c582-497b-9f25-568718b73172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721238228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1721238228
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2472884639
Short name T265
Test name
Test status
Simulation time 40109532461 ps
CPU time 293.4 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:23:44 PM PDT 24
Peak memory 253004 kb
Host smart-f86ffe9e-1927-476c-a584-7d5d37371808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472884639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2472884639
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3898056984
Short name T479
Test name
Test status
Simulation time 995383934 ps
CPU time 4.52 seconds
Started Jul 19 06:18:46 PM PDT 24
Finished Jul 19 06:18:51 PM PDT 24
Peak memory 224848 kb
Host smart-656da25d-ce3b-4e94-88f2-f74baf8e2eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898056984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3898056984
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.406976924
Short name T865
Test name
Test status
Simulation time 16693335568 ps
CPU time 41.48 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:19:32 PM PDT 24
Peak memory 233164 kb
Host smart-bf4c3567-e967-44ba-a4a7-f1ebabec2908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406976924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.406976924
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1833424532
Short name T41
Test name
Test status
Simulation time 5948712125 ps
CPU time 7.68 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:18:57 PM PDT 24
Peak memory 224964 kb
Host smart-b048ae77-f87a-4bef-bd85-b711cf977ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833424532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1833424532
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.3411011601
Short name T240
Test name
Test status
Simulation time 6145640594 ps
CPU time 20.86 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:19:11 PM PDT 24
Peak memory 239136 kb
Host smart-54445b30-ba4a-4acd-8102-a709a430b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411011601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3411011601
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3417379493
Short name T367
Test name
Test status
Simulation time 11482081606 ps
CPU time 9.87 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:18:58 PM PDT 24
Peak memory 219856 kb
Host smart-1a5f265d-c570-4568-b13c-2fcac86c79ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3417379493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3417379493
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1498521941
Short name T152
Test name
Test status
Simulation time 30144250621 ps
CPU time 183.31 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:21:52 PM PDT 24
Peak memory 274224 kb
Host smart-61b0f7b7-97aa-4121-b209-8eaed9c6efbb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498521941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1498521941
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3413313749
Short name T629
Test name
Test status
Simulation time 28780441947 ps
CPU time 36.11 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:25 PM PDT 24
Peak memory 216684 kb
Host smart-a2956d75-dbcb-4b09-8680-d20fe122dd39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413313749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3413313749
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3491693983
Short name T750
Test name
Test status
Simulation time 1131675638 ps
CPU time 4.59 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:18:53 PM PDT 24
Peak memory 216732 kb
Host smart-ae9e9141-f6b9-4dde-9f5d-a1363ac6a2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491693983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3491693983
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3722782393
Short name T443
Test name
Test status
Simulation time 89076317 ps
CPU time 2.47 seconds
Started Jul 19 06:18:48 PM PDT 24
Finished Jul 19 06:18:52 PM PDT 24
Peak memory 216700 kb
Host smart-e2ec74db-abb4-4da4-a988-5d14163e7706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722782393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3722782393
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1778218343
Short name T485
Test name
Test status
Simulation time 13710532 ps
CPU time 0.76 seconds
Started Jul 19 06:18:58 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 206436 kb
Host smart-591e17fa-c58f-4789-8d76-0f452c09c130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778218343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1778218343
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.681567106
Short name T543
Test name
Test status
Simulation time 4191543827 ps
CPU time 15.73 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:04 PM PDT 24
Peak memory 233180 kb
Host smart-03359dd9-6346-444b-afdf-0858418eb00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681567106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.681567106
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.3566467233
Short name T654
Test name
Test status
Simulation time 12979739 ps
CPU time 0.76 seconds
Started Jul 19 06:18:56 PM PDT 24
Finished Jul 19 06:18:58 PM PDT 24
Peak memory 205344 kb
Host smart-c3802dbd-ba0b-4b98-8fdd-51c178d2ed75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566467233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
3566467233
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3790426391
Short name T236
Test name
Test status
Simulation time 948768808 ps
CPU time 6.49 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:19:03 PM PDT 24
Peak memory 233080 kb
Host smart-088c0736-314e-4482-be65-e15c1c5d7fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790426391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3790426391
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1586794947
Short name T878
Test name
Test status
Simulation time 15014494 ps
CPU time 0.81 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:18:52 PM PDT 24
Peak memory 207072 kb
Host smart-0b152830-56a8-4bc9-b068-9cf9567e775c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586794947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1586794947
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.763484224
Short name T185
Test name
Test status
Simulation time 50918658865 ps
CPU time 235.47 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:22:52 PM PDT 24
Peak memory 255104 kb
Host smart-d3683421-b5ed-4cac-b5b8-8c19dd3f9e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763484224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.763484224
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.399763576
Short name T293
Test name
Test status
Simulation time 3355527720 ps
CPU time 87.4 seconds
Started Jul 19 06:18:56 PM PDT 24
Finished Jul 19 06:20:24 PM PDT 24
Peak memory 250532 kb
Host smart-73d40839-04eb-495d-8d87-fbaba37bb8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399763576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.399763576
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2356479855
Short name T221
Test name
Test status
Simulation time 309074683659 ps
CPU time 325.67 seconds
Started Jul 19 06:18:59 PM PDT 24
Finished Jul 19 06:24:26 PM PDT 24
Peak memory 257848 kb
Host smart-013469c4-af82-4c96-a134-e3f49e362ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356479855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2356479855
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.73781589
Short name T528
Test name
Test status
Simulation time 2080898295 ps
CPU time 32.95 seconds
Started Jul 19 06:18:56 PM PDT 24
Finished Jul 19 06:19:30 PM PDT 24
Peak memory 233160 kb
Host smart-834c6a60-9f42-40e9-92b2-ff153aa76b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73781589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.73781589
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3903716074
Short name T194
Test name
Test status
Simulation time 68447474340 ps
CPU time 125.99 seconds
Started Jul 19 06:18:58 PM PDT 24
Finished Jul 19 06:21:04 PM PDT 24
Peak memory 249592 kb
Host smart-f0c85219-f49b-43b1-87ea-18e2bc060f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903716074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3903716074
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1293433641
Short name T203
Test name
Test status
Simulation time 547867668 ps
CPU time 8.03 seconds
Started Jul 19 06:18:48 PM PDT 24
Finished Jul 19 06:18:57 PM PDT 24
Peak memory 220272 kb
Host smart-9f8f52b9-a082-4b50-aa88-6df60ed5baed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293433641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1293433641
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1455077767
Short name T214
Test name
Test status
Simulation time 16019122937 ps
CPU time 72.92 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:20:10 PM PDT 24
Peak memory 241104 kb
Host smart-4d2619e5-2be8-4ef3-8283-e110c3993e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455077767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1455077767
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1204138655
Short name T613
Test name
Test status
Simulation time 13413455503 ps
CPU time 18.76 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:19:09 PM PDT 24
Peak memory 224884 kb
Host smart-e1b2526a-35df-4309-b066-8a3be8d9bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204138655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1204138655
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.533159387
Short name T663
Test name
Test status
Simulation time 168513802 ps
CPU time 2.47 seconds
Started Jul 19 06:18:49 PM PDT 24
Finished Jul 19 06:18:53 PM PDT 24
Peak memory 233108 kb
Host smart-f3d69ad9-8984-4e89-91e5-80d46da95522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533159387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.533159387
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1800963470
Short name T776
Test name
Test status
Simulation time 117862170 ps
CPU time 4.16 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 223064 kb
Host smart-9ad923b4-a196-4cf3-b626-38ebbfe1291c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1800963470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1800963470
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3766788457
Short name T148
Test name
Test status
Simulation time 63216911 ps
CPU time 1.06 seconds
Started Jul 19 06:18:56 PM PDT 24
Finished Jul 19 06:18:58 PM PDT 24
Peak memory 208072 kb
Host smart-87d39055-eedb-4acf-970e-d9d67e86b159
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766788457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3766788457
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3989167452
Short name T532
Test name
Test status
Simulation time 26436694655 ps
CPU time 53.02 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:19:42 PM PDT 24
Peak memory 216784 kb
Host smart-aa75db9d-f311-4587-989e-dbc67fe02c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989167452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3989167452
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.627870763
Short name T364
Test name
Test status
Simulation time 1496663461 ps
CPU time 6.23 seconds
Started Jul 19 06:18:47 PM PDT 24
Finished Jul 19 06:18:55 PM PDT 24
Peak memory 216660 kb
Host smart-aa827a49-8847-45a1-b71f-6fb6228e47da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627870763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.627870763
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2298343248
Short name T27
Test name
Test status
Simulation time 814184655 ps
CPU time 4.42 seconds
Started Jul 19 06:18:59 PM PDT 24
Finished Jul 19 06:19:04 PM PDT 24
Peak memory 216656 kb
Host smart-25fd8738-f360-4eb9-a3f7-ea9cd7f4a044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298343248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2298343248
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3627731139
Short name T847
Test name
Test status
Simulation time 36282241 ps
CPU time 0.71 seconds
Started Jul 19 06:18:59 PM PDT 24
Finished Jul 19 06:19:00 PM PDT 24
Peak memory 206092 kb
Host smart-14b4e13a-832f-4385-a64d-a6ac05bbcf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627731139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3627731139
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1726669659
Short name T784
Test name
Test status
Simulation time 204169183 ps
CPU time 4.8 seconds
Started Jul 19 06:18:57 PM PDT 24
Finished Jul 19 06:19:03 PM PDT 24
Peak memory 224964 kb
Host smart-90b34a1a-89a5-4fe3-aefd-9b41b165c454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726669659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1726669659
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1523374386
Short name T540
Test name
Test status
Simulation time 14199733 ps
CPU time 0.78 seconds
Started Jul 19 06:19:01 PM PDT 24
Finished Jul 19 06:19:04 PM PDT 24
Peak memory 205932 kb
Host smart-3f1be480-32c6-463a-bd13-e7ef6163fac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523374386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1523374386
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2479144499
Short name T4
Test name
Test status
Simulation time 90806678 ps
CPU time 2.16 seconds
Started Jul 19 06:18:56 PM PDT 24
Finished Jul 19 06:18:59 PM PDT 24
Peak memory 224484 kb
Host smart-8fa48eb5-d3b4-49ea-964e-d1a87e07e253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479144499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2479144499
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.4189425840
Short name T684
Test name
Test status
Simulation time 28853253 ps
CPU time 0.75 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:18:57 PM PDT 24
Peak memory 207084 kb
Host smart-5f170196-e6a7-4036-a042-081a0316ee39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189425840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.4189425840
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1338547802
Short name T173
Test name
Test status
Simulation time 19157929285 ps
CPU time 171.61 seconds
Started Jul 19 06:19:01 PM PDT 24
Finished Jul 19 06:21:54 PM PDT 24
Peak memory 253144 kb
Host smart-dbb0cc5e-7088-4a99-aade-610dc683eb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338547802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1338547802
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.4120914067
Short name T618
Test name
Test status
Simulation time 1176843444 ps
CPU time 23.67 seconds
Started Jul 19 06:19:04 PM PDT 24
Finished Jul 19 06:19:29 PM PDT 24
Peak memory 251728 kb
Host smart-98bcc8b7-7e5b-4a5c-98e0-e759db1ac7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120914067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.4120914067
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.4113375566
Short name T37
Test name
Test status
Simulation time 34506696323 ps
CPU time 271.64 seconds
Started Jul 19 06:19:02 PM PDT 24
Finished Jul 19 06:23:35 PM PDT 24
Peak memory 257836 kb
Host smart-3c7292a0-7cac-44eb-91ab-832d70071243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113375566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.4113375566
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2750156883
Short name T565
Test name
Test status
Simulation time 537962173 ps
CPU time 10.35 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:19:07 PM PDT 24
Peak memory 241408 kb
Host smart-60424fdd-9184-4338-9ed7-8fcfa1e60718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750156883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2750156883
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1881481178
Short name T892
Test name
Test status
Simulation time 2790465466 ps
CPU time 20.66 seconds
Started Jul 19 06:19:02 PM PDT 24
Finished Jul 19 06:19:24 PM PDT 24
Peak memory 254052 kb
Host smart-e6bb85dc-719b-4785-ad73-41572a754de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881481178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1881481178
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.966851560
Short name T336
Test name
Test status
Simulation time 1324801259 ps
CPU time 5.31 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:19:02 PM PDT 24
Peak memory 233164 kb
Host smart-26f6c227-193a-4ac3-a2a8-fd810fa5babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966851560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.966851560
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1650964001
Short name T888
Test name
Test status
Simulation time 4176652272 ps
CPU time 7.33 seconds
Started Jul 19 06:18:54 PM PDT 24
Finished Jul 19 06:19:02 PM PDT 24
Peak memory 234324 kb
Host smart-2d07a4da-8aaa-47ba-8079-fee465d04cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650964001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1650964001
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3269028989
Short name T650
Test name
Test status
Simulation time 6024022110 ps
CPU time 8.22 seconds
Started Jul 19 06:18:54 PM PDT 24
Finished Jul 19 06:19:04 PM PDT 24
Peak memory 224928 kb
Host smart-60d4c21f-7b50-4c24-b02e-acbad34bb7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269028989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3269028989
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4184692422
Short name T707
Test name
Test status
Simulation time 115519537 ps
CPU time 2.05 seconds
Started Jul 19 06:18:54 PM PDT 24
Finished Jul 19 06:18:57 PM PDT 24
Peak memory 224908 kb
Host smart-a047321c-1380-4b41-9133-fc876e5a3d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184692422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4184692422
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.611736259
Short name T373
Test name
Test status
Simulation time 1306627845 ps
CPU time 13.08 seconds
Started Jul 19 06:19:04 PM PDT 24
Finished Jul 19 06:19:19 PM PDT 24
Peak memory 220708 kb
Host smart-ece97c8f-6f87-4258-9cba-5dffab24a579
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611736259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.611736259
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2194068304
Short name T222
Test name
Test status
Simulation time 39934598586 ps
CPU time 300.92 seconds
Started Jul 19 06:19:01 PM PDT 24
Finished Jul 19 06:24:04 PM PDT 24
Peak memory 266000 kb
Host smart-12154638-c776-4db4-81c7-14e0a00bf46e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194068304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2194068304
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2637285620
Short name T969
Test name
Test status
Simulation time 7048648426 ps
CPU time 21.38 seconds
Started Jul 19 06:19:00 PM PDT 24
Finished Jul 19 06:19:21 PM PDT 24
Peak memory 216708 kb
Host smart-12632144-5ec8-4b0a-9193-ffadfeff2323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637285620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2637285620
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2844969939
Short name T907
Test name
Test status
Simulation time 567127885 ps
CPU time 3.72 seconds
Started Jul 19 06:18:54 PM PDT 24
Finished Jul 19 06:18:58 PM PDT 24
Peak memory 216544 kb
Host smart-dc78491c-bfd6-45db-a570-7221d6516442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844969939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2844969939
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3245538461
Short name T819
Test name
Test status
Simulation time 834229851 ps
CPU time 2.43 seconds
Started Jul 19 06:19:00 PM PDT 24
Finished Jul 19 06:19:03 PM PDT 24
Peak memory 216744 kb
Host smart-c5a62bd6-947c-4d0b-88aa-cce0533b4567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245538461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3245538461
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.647076118
Short name T620
Test name
Test status
Simulation time 13929475 ps
CPU time 0.69 seconds
Started Jul 19 06:18:55 PM PDT 24
Finished Jul 19 06:18:56 PM PDT 24
Peak memory 206048 kb
Host smart-bc8ebc0d-2dd6-457e-80e2-68bedf7e424b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647076118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.647076118
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3405028977
Short name T792
Test name
Test status
Simulation time 4000559103 ps
CPU time 7.18 seconds
Started Jul 19 06:18:56 PM PDT 24
Finished Jul 19 06:19:04 PM PDT 24
Peak memory 224996 kb
Host smart-481841d2-925e-4ce3-a2aa-7a53ba79aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405028977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3405028977
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1102539956
Short name T422
Test name
Test status
Simulation time 41897134 ps
CPU time 0.75 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:19:12 PM PDT 24
Peak memory 206232 kb
Host smart-51655af9-cf2e-45f0-b2d4-6bac12ddef59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102539956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1102539956
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.377612672
Short name T736
Test name
Test status
Simulation time 1704130509 ps
CPU time 12.78 seconds
Started Jul 19 06:19:08 PM PDT 24
Finished Jul 19 06:19:22 PM PDT 24
Peak memory 224948 kb
Host smart-80dc39c9-4c42-4c65-9ba2-f78a2f66a70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377612672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.377612672
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2460979421
Short name T473
Test name
Test status
Simulation time 46087172 ps
CPU time 0.74 seconds
Started Jul 19 06:19:03 PM PDT 24
Finished Jul 19 06:19:05 PM PDT 24
Peak memory 206028 kb
Host smart-0350b119-de98-4f31-b218-6aa7b538cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460979421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2460979421
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4123470272
Short name T470
Test name
Test status
Simulation time 114320884 ps
CPU time 0.83 seconds
Started Jul 19 06:19:08 PM PDT 24
Finished Jul 19 06:19:10 PM PDT 24
Peak memory 216368 kb
Host smart-cc087254-6c97-49a6-bd4d-ba70db76ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123470272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4123470272
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3630563689
Short name T188
Test name
Test status
Simulation time 8438996993 ps
CPU time 41.17 seconds
Started Jul 19 06:19:10 PM PDT 24
Finished Jul 19 06:19:52 PM PDT 24
Peak memory 224616 kb
Host smart-d968312c-68c9-41ec-9dd5-21764945e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630563689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3630563689
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3328883766
Short name T239
Test name
Test status
Simulation time 1233831592 ps
CPU time 33.16 seconds
Started Jul 19 06:19:13 PM PDT 24
Finished Jul 19 06:19:47 PM PDT 24
Peak memory 254512 kb
Host smart-790e60f4-b60a-40bd-b48f-f39b704c58ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328883766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3328883766
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2374746871
Short name T515
Test name
Test status
Simulation time 2091866324 ps
CPU time 9.42 seconds
Started Jul 19 06:19:11 PM PDT 24
Finished Jul 19 06:19:21 PM PDT 24
Peak memory 224884 kb
Host smart-5c422599-edab-47df-b57d-95c9763e47fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374746871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2374746871
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2411087340
Short name T980
Test name
Test status
Simulation time 27855590129 ps
CPU time 194.57 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:22:25 PM PDT 24
Peak memory 252812 kb
Host smart-ae590bb7-6b9e-4f09-b020-e1277b265775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411087340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2411087340
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3503136132
Short name T256
Test name
Test status
Simulation time 1282713595 ps
CPU time 9.97 seconds
Started Jul 19 06:19:08 PM PDT 24
Finished Jul 19 06:19:20 PM PDT 24
Peak memory 233072 kb
Host smart-7a5b8a73-293e-4438-b5fc-a151a9038edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503136132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3503136132
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1662685800
Short name T270
Test name
Test status
Simulation time 3609256216 ps
CPU time 32.89 seconds
Started Jul 19 06:19:10 PM PDT 24
Finished Jul 19 06:19:44 PM PDT 24
Peak memory 241128 kb
Host smart-481daed2-a154-41f9-a3f5-a98fcf644e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662685800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1662685800
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1121552225
Short name T283
Test name
Test status
Simulation time 19584651390 ps
CPU time 17.76 seconds
Started Jul 19 06:19:08 PM PDT 24
Finished Jul 19 06:19:26 PM PDT 24
Peak memory 241308 kb
Host smart-15857198-815c-454a-99fb-1b0ddb99b5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121552225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1121552225
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3175599373
Short name T481
Test name
Test status
Simulation time 6749591080 ps
CPU time 11.39 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:19:23 PM PDT 24
Peak memory 241220 kb
Host smart-d8738ede-72e7-456a-9a1e-1132e8bfd532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175599373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3175599373
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1052749686
Short name T937
Test name
Test status
Simulation time 4706155642 ps
CPU time 9.09 seconds
Started Jul 19 06:19:10 PM PDT 24
Finished Jul 19 06:19:20 PM PDT 24
Peak memory 221356 kb
Host smart-455d1cce-205d-4f74-a6e8-450412402878
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1052749686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1052749686
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3178263656
Short name T150
Test name
Test status
Simulation time 42295840211 ps
CPU time 78.15 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:20:29 PM PDT 24
Peak memory 225004 kb
Host smart-9fda7083-73d3-4cf5-bc1e-cc29c3090b93
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178263656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3178263656
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3150938376
Short name T507
Test name
Test status
Simulation time 898689681 ps
CPU time 5.43 seconds
Started Jul 19 06:19:03 PM PDT 24
Finished Jul 19 06:19:10 PM PDT 24
Peak memory 216716 kb
Host smart-ce0f8505-df7c-43d8-a061-b57c57853dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150938376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3150938376
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.4094521598
Short name T349
Test name
Test status
Simulation time 2212861034 ps
CPU time 4.66 seconds
Started Jul 19 06:19:04 PM PDT 24
Finished Jul 19 06:19:10 PM PDT 24
Peak memory 216620 kb
Host smart-49c7babc-ec3f-44ac-9078-591c5a96df87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094521598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.4094521598
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.404437482
Short name T1009
Test name
Test status
Simulation time 15906412 ps
CPU time 0.71 seconds
Started Jul 19 06:19:08 PM PDT 24
Finished Jul 19 06:19:10 PM PDT 24
Peak memory 206116 kb
Host smart-6b5c7f3f-1bf5-4186-934e-5ef10761a134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404437482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.404437482
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4132668710
Short name T436
Test name
Test status
Simulation time 27333972 ps
CPU time 0.81 seconds
Started Jul 19 06:19:02 PM PDT 24
Finished Jul 19 06:19:04 PM PDT 24
Peak memory 206416 kb
Host smart-eae53c47-8c71-4ae2-bca8-25f1cdc5ba08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132668710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4132668710
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2839906763
Short name T462
Test name
Test status
Simulation time 7014183827 ps
CPU time 18.73 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:19:30 PM PDT 24
Peak memory 233220 kb
Host smart-2fd140de-6e95-402e-8910-44067c711b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839906763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2839906763
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3466169865
Short name T870
Test name
Test status
Simulation time 41991745 ps
CPU time 0.72 seconds
Started Jul 19 06:19:16 PM PDT 24
Finished Jul 19 06:19:17 PM PDT 24
Peak memory 205960 kb
Host smart-e79e19e5-8c83-46b6-b30e-ea2ff786513a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466169865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3466169865
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1695980723
Short name T661
Test name
Test status
Simulation time 1405408741 ps
CPU time 4.49 seconds
Started Jul 19 06:19:19 PM PDT 24
Finished Jul 19 06:19:24 PM PDT 24
Peak memory 233144 kb
Host smart-5d594214-a81b-4467-a1b9-58e2bde71f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695980723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1695980723
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3491295832
Short name T963
Test name
Test status
Simulation time 19236690 ps
CPU time 0.82 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:19:12 PM PDT 24
Peak memory 207064 kb
Host smart-f21426e6-2eea-4052-889e-1a41455a661c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491295832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3491295832
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.91087691
Short name T911
Test name
Test status
Simulation time 8213181709 ps
CPU time 55.92 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:20:15 PM PDT 24
Peak memory 233224 kb
Host smart-a16783c1-98b1-4464-8610-8091d75607b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91087691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.91087691
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3552458343
Short name T29
Test name
Test status
Simulation time 8255096926 ps
CPU time 23.12 seconds
Started Jul 19 06:19:17 PM PDT 24
Finished Jul 19 06:19:40 PM PDT 24
Peak memory 255568 kb
Host smart-84a0312a-3485-4d6c-9ab4-028d0a94a530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552458343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3552458343
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1545259026
Short name T28
Test name
Test status
Simulation time 97752077028 ps
CPU time 481.94 seconds
Started Jul 19 06:19:16 PM PDT 24
Finished Jul 19 06:27:19 PM PDT 24
Peak memory 257272 kb
Host smart-f903b217-ad29-4408-b3bf-0995b4a3b782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545259026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1545259026
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2770987470
Short name T307
Test name
Test status
Simulation time 2133362195 ps
CPU time 15.93 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 224948 kb
Host smart-3168cc0b-25d1-47c7-8b4f-1c444ec4645a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770987470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2770987470
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.589033622
Short name T499
Test name
Test status
Simulation time 692039227246 ps
CPU time 296.7 seconds
Started Jul 19 06:19:19 PM PDT 24
Finished Jul 19 06:24:16 PM PDT 24
Peak memory 257788 kb
Host smart-b34f06aa-8914-4167-a7a3-bf2ad8741093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589033622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds
.589033622
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3776750060
Short name T876
Test name
Test status
Simulation time 2940244669 ps
CPU time 21.78 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:19:40 PM PDT 24
Peak memory 233160 kb
Host smart-97cd6267-3ffc-471c-8b28-71a6d26f5af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776750060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3776750060
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4275848727
Short name T251
Test name
Test status
Simulation time 1884175659 ps
CPU time 11.28 seconds
Started Jul 19 06:19:16 PM PDT 24
Finished Jul 19 06:19:28 PM PDT 24
Peak memory 233196 kb
Host smart-3e0096ae-5830-4a2b-88c1-6415be4da76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275848727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4275848727
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1335348126
Short name T40
Test name
Test status
Simulation time 18836127615 ps
CPU time 11.08 seconds
Started Jul 19 06:19:17 PM PDT 24
Finished Jul 19 06:19:29 PM PDT 24
Peak memory 233144 kb
Host smart-fba44991-5eac-4d05-b8d1-891cbce45c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335348126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1335348126
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.4229821943
Short name T50
Test name
Test status
Simulation time 7499849858 ps
CPU time 11.07 seconds
Started Jul 19 06:19:19 PM PDT 24
Finished Jul 19 06:19:31 PM PDT 24
Peak memory 233148 kb
Host smart-a04464ad-04da-4fd2-949b-7932bb25148c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229821943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4229821943
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2842297261
Short name T622
Test name
Test status
Simulation time 149574711 ps
CPU time 4.71 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:19:23 PM PDT 24
Peak memory 219680 kb
Host smart-0fa0429a-bd5d-4bc1-89ca-150c4b7e398f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2842297261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2842297261
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2181138266
Short name T151
Test name
Test status
Simulation time 105291504299 ps
CPU time 199.76 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:22:39 PM PDT 24
Peak memory 254136 kb
Host smart-3198acb9-b74c-45b0-a5f2-cd26f9dfbb04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181138266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2181138266
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2089733855
Short name T804
Test name
Test status
Simulation time 30224029870 ps
CPU time 50.36 seconds
Started Jul 19 06:19:09 PM PDT 24
Finished Jul 19 06:20:02 PM PDT 24
Peak memory 216540 kb
Host smart-0c42ba84-0706-40c3-9427-160fb56433aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089733855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2089733855
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.4198314560
Short name T637
Test name
Test status
Simulation time 7012308990 ps
CPU time 20.25 seconds
Started Jul 19 06:19:10 PM PDT 24
Finished Jul 19 06:19:32 PM PDT 24
Peak memory 216716 kb
Host smart-48c7ee68-056d-45f0-93f4-747c5f6f949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198314560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4198314560
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1793689441
Short name T317
Test name
Test status
Simulation time 271058426 ps
CPU time 5.94 seconds
Started Jul 19 06:19:17 PM PDT 24
Finished Jul 19 06:19:24 PM PDT 24
Peak memory 216720 kb
Host smart-20d8a088-ac45-4c48-8976-b38a048ed978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793689441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1793689441
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.344736150
Short name T429
Test name
Test status
Simulation time 48568366 ps
CPU time 0.85 seconds
Started Jul 19 06:19:17 PM PDT 24
Finished Jul 19 06:19:18 PM PDT 24
Peak memory 206384 kb
Host smart-4dc1db87-6e8f-45c3-88c0-273c9cef9b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344736150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.344736150
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3919158432
Short name T689
Test name
Test status
Simulation time 1842330437 ps
CPU time 8.44 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:19:27 PM PDT 24
Peak memory 233116 kb
Host smart-d066c95b-663d-4983-8184-877121f42762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919158432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3919158432
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3725034636
Short name T879
Test name
Test status
Simulation time 38434250 ps
CPU time 0.69 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 205376 kb
Host smart-8bd3e3d1-6b83-4e0f-8c67-382a57fd1fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725034636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3725034636
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.354893590
Short name T862
Test name
Test status
Simulation time 105114004 ps
CPU time 2.55 seconds
Started Jul 19 06:19:27 PM PDT 24
Finished Jul 19 06:19:30 PM PDT 24
Peak memory 224920 kb
Host smart-05e1499e-4d7d-4655-aefa-eecb785a0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354893590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.354893590
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1534022366
Short name T635
Test name
Test status
Simulation time 19348372 ps
CPU time 0.79 seconds
Started Jul 19 06:19:19 PM PDT 24
Finished Jul 19 06:19:21 PM PDT 24
Peak memory 207072 kb
Host smart-012a66ca-2d3b-49a0-91d5-53da47521aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534022366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1534022366
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2797264307
Short name T451
Test name
Test status
Simulation time 978177202 ps
CPU time 20.78 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:54 PM PDT 24
Peak memory 238112 kb
Host smart-84e7a3a3-10fc-4114-8948-975b1fe2061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797264307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2797264307
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3599461577
Short name T230
Test name
Test status
Simulation time 21554452731 ps
CPU time 182.9 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:22:38 PM PDT 24
Peak memory 254568 kb
Host smart-9f527985-025d-4cb8-a9d5-43c4ade58b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599461577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3599461577
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2214637842
Short name T867
Test name
Test status
Simulation time 11610782564 ps
CPU time 47.67 seconds
Started Jul 19 06:19:26 PM PDT 24
Finished Jul 19 06:20:14 PM PDT 24
Peak memory 252420 kb
Host smart-c9fc949f-327d-49f4-b972-6e8259108cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214637842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2214637842
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.1542625932
Short name T859
Test name
Test status
Simulation time 77531947846 ps
CPU time 552.83 seconds
Started Jul 19 06:19:26 PM PDT 24
Finished Jul 19 06:28:39 PM PDT 24
Peak memory 265988 kb
Host smart-83cd7792-bc40-47d9-9b5e-d279585b8209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542625932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.1542625932
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2525403113
Short name T254
Test name
Test status
Simulation time 299952972 ps
CPU time 5.19 seconds
Started Jul 19 06:19:24 PM PDT 24
Finished Jul 19 06:19:30 PM PDT 24
Peak memory 233168 kb
Host smart-ba0396c9-5241-4e70-8eb6-f356071f8516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525403113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2525403113
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.992706436
Short name T809
Test name
Test status
Simulation time 95049647216 ps
CPU time 113.31 seconds
Started Jul 19 06:19:26 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 234200 kb
Host smart-d05ed520-0151-4bf6-9f35-7c7ac861d4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992706436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.992706436
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.352629189
Short name T489
Test name
Test status
Simulation time 285627519 ps
CPU time 2.7 seconds
Started Jul 19 06:19:29 PM PDT 24
Finished Jul 19 06:19:32 PM PDT 24
Peak memory 227644 kb
Host smart-f0e91e61-70a3-435c-b1b7-a88db3a93b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352629189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.352629189
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.416322520
Short name T212
Test name
Test status
Simulation time 2002710684 ps
CPU time 5.86 seconds
Started Jul 19 06:19:24 PM PDT 24
Finished Jul 19 06:19:30 PM PDT 24
Peak memory 224860 kb
Host smart-2bb9163b-876d-432e-a3b0-1e8b7cc021e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416322520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.416322520
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3162213175
Short name T648
Test name
Test status
Simulation time 1274114512 ps
CPU time 12.24 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:46 PM PDT 24
Peak memory 219324 kb
Host smart-72123605-7a83-4a24-9885-e759f446f133
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3162213175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3162213175
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2018355739
Short name T11
Test name
Test status
Simulation time 54479891 ps
CPU time 1.06 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 208104 kb
Host smart-7a57275a-2386-41dd-a56f-c7441faa44aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018355739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2018355739
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2716175093
Short name T762
Test name
Test status
Simulation time 5156052106 ps
CPU time 28.85 seconds
Started Jul 19 06:19:17 PM PDT 24
Finished Jul 19 06:19:47 PM PDT 24
Peak memory 216640 kb
Host smart-df9eb7a7-3d03-4943-8eb1-18add8d57078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716175093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2716175093
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.721356343
Short name T407
Test name
Test status
Simulation time 4447788771 ps
CPU time 13.82 seconds
Started Jul 19 06:19:17 PM PDT 24
Finished Jul 19 06:19:32 PM PDT 24
Peak memory 216664 kb
Host smart-048d8bfa-a4cf-429d-a0a4-2b6a36222bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721356343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.721356343
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.725679936
Short name T453
Test name
Test status
Simulation time 16145315 ps
CPU time 0.94 seconds
Started Jul 19 06:19:18 PM PDT 24
Finished Jul 19 06:19:20 PM PDT 24
Peak memory 207436 kb
Host smart-0de3bea9-e188-4558-a585-85a7f702844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725679936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.725679936
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2479664153
Short name T1000
Test name
Test status
Simulation time 99252452 ps
CPU time 0.87 seconds
Started Jul 19 06:19:16 PM PDT 24
Finished Jul 19 06:19:17 PM PDT 24
Peak memory 207460 kb
Host smart-9ab2bac0-68f4-4e34-9e9c-0c4b2567077f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479664153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2479664153
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.622210348
Short name T899
Test name
Test status
Simulation time 6655229442 ps
CPU time 9.67 seconds
Started Jul 19 06:19:26 PM PDT 24
Finished Jul 19 06:19:36 PM PDT 24
Peak memory 233168 kb
Host smart-97d7e491-4240-4a86-9626-141285a009fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622210348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.622210348
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3368343781
Short name T674
Test name
Test status
Simulation time 24796882 ps
CPU time 0.71 seconds
Started Jul 19 06:19:32 PM PDT 24
Finished Jul 19 06:19:34 PM PDT 24
Peak memory 205932 kb
Host smart-717c0e2b-b9e1-4ee7-88be-c969961d055e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368343781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3368343781
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2538559982
Short name T885
Test name
Test status
Simulation time 470357796 ps
CPU time 2.91 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:37 PM PDT 24
Peak memory 225112 kb
Host smart-2639fb3c-1e6d-46ec-bcaa-bff9fc39758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538559982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2538559982
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.188277500
Short name T951
Test name
Test status
Simulation time 14579794 ps
CPU time 0.79 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 207052 kb
Host smart-e3eb0875-2db8-4a6e-bf48-72f62891d674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188277500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.188277500
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2391620873
Short name T567
Test name
Test status
Simulation time 27564759944 ps
CPU time 93.2 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:21:07 PM PDT 24
Peak memory 254952 kb
Host smart-af7d006b-cbd9-48bb-824e-d199e038dcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391620873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2391620873
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2982037681
Short name T220
Test name
Test status
Simulation time 3391390154 ps
CPU time 87.51 seconds
Started Jul 19 06:19:34 PM PDT 24
Finished Jul 19 06:21:03 PM PDT 24
Peak memory 249648 kb
Host smart-5b794fc2-9e80-4c30-b916-73c24070808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982037681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2982037681
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4134105048
Short name T582
Test name
Test status
Simulation time 13679744223 ps
CPU time 47.28 seconds
Started Jul 19 06:19:35 PM PDT 24
Finished Jul 19 06:20:23 PM PDT 24
Peak memory 249564 kb
Host smart-9b6ac085-b629-4dee-9c8a-23bbfd2b8d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134105048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4134105048
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3535152038
Short name T909
Test name
Test status
Simulation time 12884430353 ps
CPU time 56.41 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:20:31 PM PDT 24
Peak memory 233188 kb
Host smart-56484618-2ba7-443c-8cd2-c165996aadf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535152038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3535152038
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.787856443
Short name T284
Test name
Test status
Simulation time 44086562089 ps
CPU time 110.43 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:21:25 PM PDT 24
Peak memory 249580 kb
Host smart-f6fe715d-936b-479e-92e2-8a4245828585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787856443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.787856443
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.211593367
Short name T574
Test name
Test status
Simulation time 3908655528 ps
CPU time 7.72 seconds
Started Jul 19 06:19:32 PM PDT 24
Finished Jul 19 06:19:41 PM PDT 24
Peak memory 225040 kb
Host smart-73579608-24da-4bba-aa15-06426155195c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211593367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.211593367
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1574091643
Short name T773
Test name
Test status
Simulation time 1627941165 ps
CPU time 9.26 seconds
Started Jul 19 06:19:34 PM PDT 24
Finished Jul 19 06:19:45 PM PDT 24
Peak memory 233100 kb
Host smart-1562d17e-57b3-4088-bb44-9f9c70b366bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574091643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1574091643
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3285340857
Short name T803
Test name
Test status
Simulation time 738269417 ps
CPU time 3.96 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:38 PM PDT 24
Peak memory 224904 kb
Host smart-1f43d065-3ec0-41a4-b59c-d81e61ee0ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285340857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3285340857
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3231280676
Short name T197
Test name
Test status
Simulation time 9520225313 ps
CPU time 11.35 seconds
Started Jul 19 06:19:34 PM PDT 24
Finished Jul 19 06:19:46 PM PDT 24
Peak memory 233232 kb
Host smart-007da370-e32e-4774-b56b-c2103bdb391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231280676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3231280676
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2275802426
Short name T559
Test name
Test status
Simulation time 7452311326 ps
CPU time 12.4 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:47 PM PDT 24
Peak memory 223136 kb
Host smart-14e8651f-eb70-4d07-b8eb-8a208c4563ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2275802426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2275802426
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.4004804873
Short name T135
Test name
Test status
Simulation time 69594029973 ps
CPU time 178.13 seconds
Started Jul 19 06:19:34 PM PDT 24
Finished Jul 19 06:22:33 PM PDT 24
Peak memory 252924 kb
Host smart-59e76618-4c08-45e6-96af-1f39fddc4850
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004804873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.4004804873
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1238348553
Short name T745
Test name
Test status
Simulation time 1363546417 ps
CPU time 15.95 seconds
Started Jul 19 06:19:31 PM PDT 24
Finished Jul 19 06:19:47 PM PDT 24
Peak memory 216600 kb
Host smart-47f2a098-b584-4a27-acb1-7a2eb9e9b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238348553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1238348553
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.845444713
Short name T832
Test name
Test status
Simulation time 16403532 ps
CPU time 0.72 seconds
Started Jul 19 06:19:32 PM PDT 24
Finished Jul 19 06:19:33 PM PDT 24
Peak memory 206120 kb
Host smart-087a61a1-c731-407a-948a-81e1cdca7eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845444713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.845444713
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.469516098
Short name T385
Test name
Test status
Simulation time 532403134 ps
CPU time 1.97 seconds
Started Jul 19 06:19:30 PM PDT 24
Finished Jul 19 06:19:32 PM PDT 24
Peak memory 216728 kb
Host smart-37944df3-7a78-493d-a41f-5c905526b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469516098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.469516098
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1456796004
Short name T357
Test name
Test status
Simulation time 67647235 ps
CPU time 0.96 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:34 PM PDT 24
Peak memory 207480 kb
Host smart-26bd14c0-8ebe-49ed-980d-f5327de481bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456796004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1456796004
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.497293851
Short name T584
Test name
Test status
Simulation time 54291656 ps
CPU time 2.49 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:37 PM PDT 24
Peak memory 224628 kb
Host smart-72f0bca4-1f61-4f41-9073-5561606acdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497293851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.497293851
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.596292195
Short name T881
Test name
Test status
Simulation time 144976268 ps
CPU time 0.72 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:19:46 PM PDT 24
Peak memory 205920 kb
Host smart-1bb83549-881d-4113-ae51-01373a97d02f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596292195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.596292195
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1666674640
Short name T273
Test name
Test status
Simulation time 37622525 ps
CPU time 2.25 seconds
Started Jul 19 06:19:38 PM PDT 24
Finished Jul 19 06:19:40 PM PDT 24
Peak memory 224956 kb
Host smart-949106dc-0427-40e2-bf48-0c43bfe726ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666674640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1666674640
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2378811104
Short name T516
Test name
Test status
Simulation time 20814404 ps
CPU time 0.77 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 207060 kb
Host smart-44b44552-aab2-4e10-abda-2d139fa94d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378811104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2378811104
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1219353048
Short name T987
Test name
Test status
Simulation time 27547726092 ps
CPU time 132.28 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:21:52 PM PDT 24
Peak memory 268072 kb
Host smart-f1a819d5-30aa-4df8-a906-ff090788f6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219353048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1219353048
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1888216208
Short name T126
Test name
Test status
Simulation time 895587049 ps
CPU time 11.77 seconds
Started Jul 19 06:19:38 PM PDT 24
Finished Jul 19 06:19:51 PM PDT 24
Peak memory 219792 kb
Host smart-2075f4dc-bcdb-48a8-b4f6-3582e4771407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888216208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1888216208
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.251293042
Short name T912
Test name
Test status
Simulation time 476664128 ps
CPU time 5.1 seconds
Started Jul 19 06:19:38 PM PDT 24
Finished Jul 19 06:19:44 PM PDT 24
Peak memory 224912 kb
Host smart-8edaf738-9af6-47a8-90f0-e7089b3983b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251293042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.251293042
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2141024383
Short name T594
Test name
Test status
Simulation time 4388036959 ps
CPU time 29.62 seconds
Started Jul 19 06:19:46 PM PDT 24
Finished Jul 19 06:20:16 PM PDT 24
Peak memory 249584 kb
Host smart-00655b68-66d4-4f8d-bc94-c1197787e5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141024383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2141024383
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2132983265
Short name T400
Test name
Test status
Simulation time 405705100 ps
CPU time 5.5 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:19:54 PM PDT 24
Peak memory 224888 kb
Host smart-d99c31d9-cafe-4cea-81c8-0feddad9cfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132983265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2132983265
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2899531853
Short name T466
Test name
Test status
Simulation time 359880949 ps
CPU time 4.14 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:19:45 PM PDT 24
Peak memory 224920 kb
Host smart-24658341-9792-48fe-8f00-90b1da7c4ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899531853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2899531853
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3222297201
Short name T409
Test name
Test status
Simulation time 15617139399 ps
CPU time 13.93 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:55 PM PDT 24
Peak memory 224328 kb
Host smart-4440f632-1f30-4566-b738-0674c7e331a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222297201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3222297201
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4221964560
Short name T605
Test name
Test status
Simulation time 216372631 ps
CPU time 2.26 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:44 PM PDT 24
Peak memory 223620 kb
Host smart-8a12f6b6-e515-4e6f-a2de-40e0670a1386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221964560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4221964560
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3863602192
Short name T806
Test name
Test status
Simulation time 250974534 ps
CPU time 4.35 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:19:44 PM PDT 24
Peak memory 220568 kb
Host smart-0d3c119d-91fe-478b-ab34-759806b7a0f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3863602192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3863602192
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.4195164643
Short name T919
Test name
Test status
Simulation time 6496738728 ps
CPU time 102.08 seconds
Started Jul 19 06:19:38 PM PDT 24
Finished Jul 19 06:21:21 PM PDT 24
Peak memory 257836 kb
Host smart-e6a7be15-2649-4435-8f08-03a4cdcd32b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195164643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.4195164643
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1031308480
Short name T1001
Test name
Test status
Simulation time 1221738826 ps
CPU time 10.01 seconds
Started Jul 19 06:19:31 PM PDT 24
Finished Jul 19 06:19:42 PM PDT 24
Peak memory 216748 kb
Host smart-f95f2e1c-06c3-4d9f-bc3b-83815037aa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031308480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1031308480
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2354826929
Short name T866
Test name
Test status
Simulation time 91142781 ps
CPU time 1.12 seconds
Started Jul 19 06:19:33 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 208240 kb
Host smart-fcc455c6-3694-4d3b-aaba-7703e383b4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354826929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2354826929
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2621276356
Short name T655
Test name
Test status
Simulation time 248536477 ps
CPU time 2.29 seconds
Started Jul 19 06:19:32 PM PDT 24
Finished Jul 19 06:19:35 PM PDT 24
Peak memory 216632 kb
Host smart-166b09ad-482a-4228-89fb-289eb40e8582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621276356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2621276356
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1177404730
Short name T619
Test name
Test status
Simulation time 31045291 ps
CPU time 0.83 seconds
Started Jul 19 06:19:32 PM PDT 24
Finished Jul 19 06:19:33 PM PDT 24
Peak memory 206424 kb
Host smart-1119d543-c360-4b16-8fa4-2083ac2f4655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177404730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1177404730
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1886036601
Short name T570
Test name
Test status
Simulation time 135871602 ps
CPU time 3.11 seconds
Started Jul 19 06:19:41 PM PDT 24
Finished Jul 19 06:19:45 PM PDT 24
Peak memory 225028 kb
Host smart-3e98ad48-0794-4094-99eb-4671bbae5c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886036601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1886036601
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.316109045
Short name T771
Test name
Test status
Simulation time 73034842 ps
CPU time 0.72 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:42 PM PDT 24
Peak memory 206276 kb
Host smart-97a41947-6f6b-4f1c-8316-aba461374418
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316109045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.316109045
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2882355988
Short name T508
Test name
Test status
Simulation time 259737919 ps
CPU time 5.12 seconds
Started Jul 19 06:19:41 PM PDT 24
Finished Jul 19 06:19:47 PM PDT 24
Peak memory 233120 kb
Host smart-3e30a885-9dd2-4eac-a92d-4b2ec8df59c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882355988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2882355988
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.4127061996
Short name T606
Test name
Test status
Simulation time 43124819 ps
CPU time 0.77 seconds
Started Jul 19 06:19:41 PM PDT 24
Finished Jul 19 06:19:43 PM PDT 24
Peak memory 206080 kb
Host smart-8a48c5ff-7326-4e36-87de-4828afd7a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127061996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.4127061996
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3272451815
Short name T191
Test name
Test status
Simulation time 130782797736 ps
CPU time 315.39 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:24:55 PM PDT 24
Peak memory 266068 kb
Host smart-5b0ba50b-076e-4555-b1cf-15f98ca6ef04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272451815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3272451815
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3106565393
Short name T262
Test name
Test status
Simulation time 14689125189 ps
CPU time 139.04 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:22:08 PM PDT 24
Peak memory 249656 kb
Host smart-80473611-5f11-418e-bad1-147c0cbac88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106565393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3106565393
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.574834505
Short name T741
Test name
Test status
Simulation time 193393804897 ps
CPU time 285.52 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:24:35 PM PDT 24
Peak memory 256988 kb
Host smart-6c50bcd3-42c5-476c-b43d-192af4c2fb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574834505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.574834505
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.472363824
Short name T145
Test name
Test status
Simulation time 979449508 ps
CPU time 18.86 seconds
Started Jul 19 06:19:38 PM PDT 24
Finished Jul 19 06:19:58 PM PDT 24
Peak memory 238688 kb
Host smart-43418a5d-e9a0-4b22-a7de-8aa79f57db14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472363824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.472363824
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.1788696039
Short name T902
Test name
Test status
Simulation time 1835037485 ps
CPU time 15.84 seconds
Started Jul 19 06:19:41 PM PDT 24
Finished Jul 19 06:19:58 PM PDT 24
Peak memory 224972 kb
Host smart-e9ebdc7f-ff71-4dd0-b441-10e865e5d1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788696039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.1788696039
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.400914702
Short name T895
Test name
Test status
Simulation time 1405766168 ps
CPU time 3.68 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:45 PM PDT 24
Peak memory 224292 kb
Host smart-babe83c7-1740-4d2d-a561-ac7ee2f53e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400914702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.400914702
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2143864021
Short name T183
Test name
Test status
Simulation time 13980892002 ps
CPU time 15.39 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:19:55 PM PDT 24
Peak memory 233164 kb
Host smart-e0906462-e98d-46c8-a2d9-645f6acda3db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143864021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2143864021
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3742121737
Short name T242
Test name
Test status
Simulation time 19526902435 ps
CPU time 8.76 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:19:49 PM PDT 24
Peak memory 233164 kb
Host smart-3f7efae8-c70d-4a84-b065-c808cb882448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742121737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3742121737
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1947441594
Short name T897
Test name
Test status
Simulation time 338374557 ps
CPU time 4.71 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:46 PM PDT 24
Peak memory 223620 kb
Host smart-757c8f5f-4cfb-40b4-b867-242079048080
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1947441594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1947441594
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3443506199
Short name T788
Test name
Test status
Simulation time 351650313 ps
CPU time 3.63 seconds
Started Jul 19 06:19:37 PM PDT 24
Finished Jul 19 06:19:41 PM PDT 24
Peak memory 219324 kb
Host smart-476d00ae-7476-4779-939c-167d1d6b48e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443506199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3443506199
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1315251508
Short name T471
Test name
Test status
Simulation time 13535693515 ps
CPU time 10.46 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:52 PM PDT 24
Peak memory 216728 kb
Host smart-f3fcdad5-62e8-43f0-9aab-1e28844ddfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315251508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1315251508
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3407967112
Short name T45
Test name
Test status
Simulation time 10962609 ps
CPU time 0.72 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:19:46 PM PDT 24
Peak memory 206116 kb
Host smart-05b08fc0-37fa-4420-839a-bffa54463da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407967112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3407967112
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3037338618
Short name T686
Test name
Test status
Simulation time 851504360 ps
CPU time 0.93 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:43 PM PDT 24
Peak memory 206436 kb
Host smart-c55ca8c4-f8fe-4398-9764-1f8b9e53de36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037338618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3037338618
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.623701244
Short name T995
Test name
Test status
Simulation time 992871649 ps
CPU time 8.95 seconds
Started Jul 19 06:19:38 PM PDT 24
Finished Jul 19 06:19:47 PM PDT 24
Peak memory 233068 kb
Host smart-d7409b5c-2cb9-4b5a-9c67-3f080e57f246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623701244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.623701244
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.979289138
Short name T439
Test name
Test status
Simulation time 14922869 ps
CPU time 0.74 seconds
Started Jul 19 06:15:57 PM PDT 24
Finished Jul 19 06:15:58 PM PDT 24
Peak memory 205356 kb
Host smart-1b555978-97ad-464f-931d-f43e474ea103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979289138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.979289138
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.742751938
Short name T497
Test name
Test status
Simulation time 14524000779 ps
CPU time 10.14 seconds
Started Jul 19 06:15:38 PM PDT 24
Finished Jul 19 06:15:49 PM PDT 24
Peak memory 224972 kb
Host smart-7bd375cf-7add-40e0-bcb9-4df5f95089fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742751938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.742751938
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.1968754763
Short name T863
Test name
Test status
Simulation time 18588222 ps
CPU time 0.79 seconds
Started Jul 19 06:15:34 PM PDT 24
Finished Jul 19 06:15:36 PM PDT 24
Peak memory 206044 kb
Host smart-ddb9f734-5af3-46d5-840e-d7be5658d139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968754763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.1968754763
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3966737590
Short name T981
Test name
Test status
Simulation time 28775557762 ps
CPU time 109.84 seconds
Started Jul 19 06:15:49 PM PDT 24
Finished Jul 19 06:17:39 PM PDT 24
Peak memory 240616 kb
Host smart-186605e6-317c-4b1d-a12a-c4cd52626285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966737590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3966737590
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1864929126
Short name T413
Test name
Test status
Simulation time 3702963538 ps
CPU time 85.55 seconds
Started Jul 19 06:15:48 PM PDT 24
Finished Jul 19 06:17:13 PM PDT 24
Peak memory 251264 kb
Host smart-f8ddbf3b-7c56-42ea-aaa6-d868868a480b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864929126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1864929126
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3309468649
Short name T65
Test name
Test status
Simulation time 4793975445 ps
CPU time 88 seconds
Started Jul 19 06:15:55 PM PDT 24
Finished Jul 19 06:17:24 PM PDT 24
Peak memory 256352 kb
Host smart-94d87c0b-096b-4927-8c5e-6a81335eaae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309468649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3309468649
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.641590291
Short name T815
Test name
Test status
Simulation time 302078078 ps
CPU time 4.01 seconds
Started Jul 19 06:15:50 PM PDT 24
Finished Jul 19 06:15:54 PM PDT 24
Peak memory 233256 kb
Host smart-ab293c07-2d8f-4a7d-a880-3386e2dc1abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641590291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.641590291
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.4128832039
Short name T991
Test name
Test status
Simulation time 5520769077 ps
CPU time 76.03 seconds
Started Jul 19 06:15:49 PM PDT 24
Finished Jul 19 06:17:05 PM PDT 24
Peak memory 249596 kb
Host smart-ff9418f2-5ff2-4fb0-8662-980f1e8f1202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128832039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.4128832039
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.81564762
Short name T928
Test name
Test status
Simulation time 623909792 ps
CPU time 4.2 seconds
Started Jul 19 06:15:40 PM PDT 24
Finished Jul 19 06:15:45 PM PDT 24
Peak memory 224916 kb
Host smart-41e99d4d-fa90-4975-9b8d-2cbf9ebfbecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81564762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.81564762
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3933506229
Short name T577
Test name
Test status
Simulation time 49062310116 ps
CPU time 148.89 seconds
Started Jul 19 06:15:39 PM PDT 24
Finished Jul 19 06:18:09 PM PDT 24
Peak memory 225016 kb
Host smart-e3bc9761-7fda-42b5-b8d4-81ca13cdd765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933506229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3933506229
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.379601889
Short name T913
Test name
Test status
Simulation time 6065623355 ps
CPU time 13.43 seconds
Started Jul 19 06:15:39 PM PDT 24
Finished Jul 19 06:15:53 PM PDT 24
Peak memory 241324 kb
Host smart-5ee49b31-94c1-4f3a-a56c-64f8a2e799d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379601889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.
379601889
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.965369059
Short name T446
Test name
Test status
Simulation time 161644306 ps
CPU time 3.27 seconds
Started Jul 19 06:15:37 PM PDT 24
Finished Jul 19 06:15:41 PM PDT 24
Peak memory 224908 kb
Host smart-21441706-6f76-4d82-bdea-9987d910d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965369059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.965369059
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2581701430
Short name T8
Test name
Test status
Simulation time 1747830152 ps
CPU time 11.61 seconds
Started Jul 19 06:15:47 PM PDT 24
Finished Jul 19 06:15:59 PM PDT 24
Peak memory 220552 kb
Host smart-c73186da-20ff-45fa-8355-a692abc8fd81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2581701430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2581701430
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.376601537
Short name T61
Test name
Test status
Simulation time 78849691 ps
CPU time 1.09 seconds
Started Jul 19 06:15:54 PM PDT 24
Finished Jul 19 06:15:56 PM PDT 24
Peak memory 235944 kb
Host smart-7e8aed03-acdd-430a-b6cf-601f7b4d5f5d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376601537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.376601537
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2965505956
Short name T669
Test name
Test status
Simulation time 185762385 ps
CPU time 0.95 seconds
Started Jul 19 06:15:56 PM PDT 24
Finished Jul 19 06:15:58 PM PDT 24
Peak memory 207264 kb
Host smart-1e4c4c01-4acd-433d-90e0-b904853f9c08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965505956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2965505956
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1867678541
Short name T312
Test name
Test status
Simulation time 7193988331 ps
CPU time 25.58 seconds
Started Jul 19 06:15:38 PM PDT 24
Finished Jul 19 06:16:04 PM PDT 24
Peak memory 216816 kb
Host smart-72142d55-174b-426f-9243-0a7479cf7c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867678541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1867678541
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.1214909111
Short name T352
Test name
Test status
Simulation time 3629975549 ps
CPU time 10.55 seconds
Started Jul 19 06:15:35 PM PDT 24
Finished Jul 19 06:15:46 PM PDT 24
Peak memory 216740 kb
Host smart-855bee81-cba6-42b5-8034-0de3fd66ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214909111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.1214909111
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1738019544
Short name T358
Test name
Test status
Simulation time 129080857 ps
CPU time 2.68 seconds
Started Jul 19 06:15:38 PM PDT 24
Finished Jul 19 06:15:42 PM PDT 24
Peak memory 216624 kb
Host smart-737d527a-db4b-44a6-91b0-14926566b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738019544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1738019544
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.4121541352
Short name T509
Test name
Test status
Simulation time 80902658 ps
CPU time 0.79 seconds
Started Jul 19 06:15:43 PM PDT 24
Finished Jul 19 06:15:44 PM PDT 24
Peak memory 206436 kb
Host smart-e21c959f-ce4a-49a7-87e5-cc83a6ae6553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121541352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.4121541352
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2150947016
Short name T946
Test name
Test status
Simulation time 2878154962 ps
CPU time 17.27 seconds
Started Jul 19 06:15:44 PM PDT 24
Finished Jul 19 06:16:02 PM PDT 24
Peak memory 249564 kb
Host smart-d144b597-e6de-4f29-a09b-5378d863b72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150947016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2150947016
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3493932815
Short name T967
Test name
Test status
Simulation time 25122222 ps
CPU time 0.74 seconds
Started Jul 19 06:19:43 PM PDT 24
Finished Jul 19 06:19:44 PM PDT 24
Peak memory 205352 kb
Host smart-d3a81814-0636-4741-82db-643e0bc90b98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493932815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3493932815
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3548650803
Short name T356
Test name
Test status
Simulation time 444589998 ps
CPU time 2.9 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:19:49 PM PDT 24
Peak memory 224952 kb
Host smart-0df1810e-de2a-41b1-8757-ba97ef71514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548650803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3548650803
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.467857515
Short name T573
Test name
Test status
Simulation time 32896232 ps
CPU time 0.77 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:19:40 PM PDT 24
Peak memory 206052 kb
Host smart-6bb355f0-64c1-4524-930b-3b88de4cdc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467857515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.467857515
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.688868405
Short name T381
Test name
Test status
Simulation time 20725511862 ps
CPU time 51.62 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:20:38 PM PDT 24
Peak memory 249576 kb
Host smart-e4cba0a3-2b61-4d35-a600-bf1b423b483c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688868405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.688868405
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3593903866
Short name T30
Test name
Test status
Simulation time 37088972139 ps
CPU time 201.86 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:23:08 PM PDT 24
Peak memory 264736 kb
Host smart-9c48e51a-ac3d-4b97-b90d-0afa7ca31236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593903866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3593903866
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4270230872
Short name T394
Test name
Test status
Simulation time 2343573497 ps
CPU time 12.33 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:19:58 PM PDT 24
Peak memory 233208 kb
Host smart-2896fdbd-e1fc-4bfa-a97e-93a8050f2988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270230872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4270230872
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.293106328
Short name T417
Test name
Test status
Simulation time 369115712 ps
CPU time 3.81 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:19:53 PM PDT 24
Peak memory 233096 kb
Host smart-6c76e6c6-4234-49c1-a651-2d788c93d4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293106328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.293106328
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.446039487
Short name T705
Test name
Test status
Simulation time 7773494249 ps
CPU time 43.59 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:20:32 PM PDT 24
Peak memory 249472 kb
Host smart-7f7b1787-86b1-462c-9556-4b96f689273e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446039487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.446039487
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1378991951
Short name T430
Test name
Test status
Simulation time 5923691162 ps
CPU time 23.82 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:20:10 PM PDT 24
Peak memory 233336 kb
Host smart-3a061291-234b-4711-9702-82d0e5165aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378991951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1378991951
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1340848866
Short name T730
Test name
Test status
Simulation time 33772362 ps
CPU time 2.42 seconds
Started Jul 19 06:19:48 PM PDT 24
Finished Jul 19 06:19:51 PM PDT 24
Peak memory 233120 kb
Host smart-c780af8a-0de1-49f9-a696-725d28647aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340848866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1340848866
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.986692366
Short name T2
Test name
Test status
Simulation time 5658176121 ps
CPU time 18.46 seconds
Started Jul 19 06:19:44 PM PDT 24
Finished Jul 19 06:20:04 PM PDT 24
Peak memory 219336 kb
Host smart-55f473fb-17f1-4de5-8872-40144e628040
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=986692366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.986692366
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.1476019770
Short name T460
Test name
Test status
Simulation time 32977289749 ps
CPU time 326.14 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:25:12 PM PDT 24
Peak memory 252260 kb
Host smart-1e44a86b-fe44-42c5-8f99-e57fd412cda1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476019770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.1476019770
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.3803766922
Short name T525
Test name
Test status
Simulation time 3331834956 ps
CPU time 18.17 seconds
Started Jul 19 06:19:44 PM PDT 24
Finished Jul 19 06:20:03 PM PDT 24
Peak memory 216684 kb
Host smart-ff06eb2a-02d6-4763-8d4b-9a16b4db29ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803766922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3803766922
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2785174030
Short name T348
Test name
Test status
Simulation time 5668065737 ps
CPU time 17.32 seconds
Started Jul 19 06:19:39 PM PDT 24
Finished Jul 19 06:19:57 PM PDT 24
Peak memory 216760 kb
Host smart-c740b18c-ed18-4762-a30d-d9f396fcde98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785174030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2785174030
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3932907526
Short name T370
Test name
Test status
Simulation time 69678409 ps
CPU time 0.97 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:42 PM PDT 24
Peak memory 207140 kb
Host smart-874b6da0-956c-45c2-b7c2-bfd5e53225f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932907526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3932907526
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.783280703
Short name T988
Test name
Test status
Simulation time 66890562 ps
CPU time 0.87 seconds
Started Jul 19 06:19:40 PM PDT 24
Finished Jul 19 06:19:41 PM PDT 24
Peak memory 207456 kb
Host smart-d778ba8c-26b2-4335-a6b1-2ba6c27c3da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783280703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.783280703
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.422890123
Short name T587
Test name
Test status
Simulation time 153056468 ps
CPU time 2.54 seconds
Started Jul 19 06:19:45 PM PDT 24
Finished Jul 19 06:19:48 PM PDT 24
Peak memory 224544 kb
Host smart-15e7cfce-c151-490b-8a5d-fdbfc593446c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422890123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.422890123
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.760035542
Short name T757
Test name
Test status
Simulation time 17476602 ps
CPU time 0.68 seconds
Started Jul 19 06:20:02 PM PDT 24
Finished Jul 19 06:20:03 PM PDT 24
Peak memory 205336 kb
Host smart-11d1ba2b-0f0e-48a4-8b6e-89f0e5248d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760035542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.760035542
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2595945016
Short name T696
Test name
Test status
Simulation time 622514860 ps
CPU time 5.2 seconds
Started Jul 19 06:19:52 PM PDT 24
Finished Jul 19 06:19:58 PM PDT 24
Peak memory 224892 kb
Host smart-8830ce9c-2672-4c87-9b02-69d57c76a85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595945016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2595945016
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.907191236
Short name T419
Test name
Test status
Simulation time 16374466 ps
CPU time 0.77 seconds
Started Jul 19 06:19:52 PM PDT 24
Finished Jul 19 06:19:53 PM PDT 24
Peak memory 207356 kb
Host smart-5e27c592-2a40-4c1e-b32e-d60ce44b86e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907191236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.907191236
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.489333701
Short name T156
Test name
Test status
Simulation time 46159986563 ps
CPU time 277.18 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:24:37 PM PDT 24
Peak memory 265128 kb
Host smart-c90cff0b-11e9-4eb3-a55c-750a6321a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489333701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.489333701
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1425468444
Short name T44
Test name
Test status
Simulation time 33011820473 ps
CPU time 158.72 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:22:39 PM PDT 24
Peak memory 250412 kb
Host smart-3e4d4694-f9e1-43ee-af77-83a6d2235572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425468444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1425468444
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3771988746
Short name T67
Test name
Test status
Simulation time 8877139079 ps
CPU time 117.55 seconds
Started Jul 19 06:20:02 PM PDT 24
Finished Jul 19 06:22:00 PM PDT 24
Peak memory 272452 kb
Host smart-2996abbe-c051-462b-bade-e612b8a1c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771988746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3771988746
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3342342648
Short name T996
Test name
Test status
Simulation time 80097022768 ps
CPU time 122.42 seconds
Started Jul 19 06:20:01 PM PDT 24
Finished Jul 19 06:22:04 PM PDT 24
Peak memory 255416 kb
Host smart-58ee8ca0-b76e-476c-a3a6-1f48f79cf98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342342648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3342342648
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3333052924
Short name T825
Test name
Test status
Simulation time 8890170499 ps
CPU time 25.72 seconds
Started Jul 19 06:19:53 PM PDT 24
Finished Jul 19 06:20:19 PM PDT 24
Peak memory 233220 kb
Host smart-cc100281-1e03-4624-bb61-b61fb78bf28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333052924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3333052924
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.4125236581
Short name T759
Test name
Test status
Simulation time 1779663830 ps
CPU time 9.53 seconds
Started Jul 19 06:19:50 PM PDT 24
Finished Jul 19 06:20:00 PM PDT 24
Peak memory 233052 kb
Host smart-abf9592d-b764-4aa1-8a39-99e018ebae6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125236581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.4125236581
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1917513073
Short name T644
Test name
Test status
Simulation time 61417531 ps
CPU time 2.44 seconds
Started Jul 19 06:19:53 PM PDT 24
Finished Jul 19 06:19:56 PM PDT 24
Peak memory 232724 kb
Host smart-604693ff-b20b-493b-a17c-529790136052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917513073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1917513073
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.672847112
Short name T846
Test name
Test status
Simulation time 1367635284 ps
CPU time 6.05 seconds
Started Jul 19 06:19:53 PM PDT 24
Finished Jul 19 06:20:00 PM PDT 24
Peak memory 233072 kb
Host smart-d72fcb8b-7f64-4b01-bf61-618962ee085d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672847112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.672847112
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.424465675
Short name T7
Test name
Test status
Simulation time 211141524 ps
CPU time 4.47 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:20:04 PM PDT 24
Peak memory 220968 kb
Host smart-d84a2b0a-38fa-491d-8765-74e229627f6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=424465675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.424465675
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2032773257
Short name T733
Test name
Test status
Simulation time 40514311036 ps
CPU time 17.01 seconds
Started Jul 19 06:20:03 PM PDT 24
Finished Jul 19 06:20:21 PM PDT 24
Peak memory 223848 kb
Host smart-64274c33-507d-4f33-b578-3c8424d6be0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032773257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2032773257
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2333104453
Short name T441
Test name
Test status
Simulation time 12366149508 ps
CPU time 13.17 seconds
Started Jul 19 06:19:52 PM PDT 24
Finished Jul 19 06:20:06 PM PDT 24
Peak memory 216760 kb
Host smart-ba55bac1-1313-4821-a651-9a1b31841a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333104453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2333104453
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1791389408
Short name T687
Test name
Test status
Simulation time 1471406052 ps
CPU time 8.28 seconds
Started Jul 19 06:19:52 PM PDT 24
Finished Jul 19 06:20:00 PM PDT 24
Peak memory 216552 kb
Host smart-3e2a261c-2ca9-4873-990a-5f9d1c35ca05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791389408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1791389408
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2713888481
Short name T474
Test name
Test status
Simulation time 22581322 ps
CPU time 0.94 seconds
Started Jul 19 06:19:52 PM PDT 24
Finished Jul 19 06:19:54 PM PDT 24
Peak memory 207504 kb
Host smart-977c7d42-fffa-4751-8e6b-4fe4df7bf6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713888481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2713888481
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.257568566
Short name T796
Test name
Test status
Simulation time 29135514 ps
CPU time 0.9 seconds
Started Jul 19 06:19:53 PM PDT 24
Finished Jul 19 06:19:54 PM PDT 24
Peak memory 206456 kb
Host smart-cfa125e6-17a0-4237-b75a-cc080ab52c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257568566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.257568566
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.772039232
Short name T535
Test name
Test status
Simulation time 2066332897 ps
CPU time 9.21 seconds
Started Jul 19 06:19:51 PM PDT 24
Finished Jul 19 06:20:01 PM PDT 24
Peak memory 224860 kb
Host smart-76fad741-aba1-4fb4-ba7a-41bbe7228ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772039232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.772039232
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.4183211889
Short name T54
Test name
Test status
Simulation time 52971033 ps
CPU time 0.73 seconds
Started Jul 19 06:20:06 PM PDT 24
Finished Jul 19 06:20:07 PM PDT 24
Peak memory 205376 kb
Host smart-1817c45a-1d75-4e4a-b166-6004a65e0c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183211889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
4183211889
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.283662386
Short name T857
Test name
Test status
Simulation time 286268196 ps
CPU time 3.67 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:20:03 PM PDT 24
Peak memory 233136 kb
Host smart-fe3ccc0d-0135-40ad-8e43-828a977b00b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283662386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.283662386
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.889448879
Short name T673
Test name
Test status
Simulation time 142652528 ps
CPU time 0.75 seconds
Started Jul 19 06:20:00 PM PDT 24
Finished Jul 19 06:20:02 PM PDT 24
Peak memory 207056 kb
Host smart-46c548c6-f3d5-43da-a098-875179ba50ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889448879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.889448879
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.4235480171
Short name T944
Test name
Test status
Simulation time 2925794977 ps
CPU time 12.64 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:20:21 PM PDT 24
Peak memory 241416 kb
Host smart-0022c5c2-e59d-4cfa-9df3-86cbb227f960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235480171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.4235480171
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2439361838
Short name T724
Test name
Test status
Simulation time 43762250469 ps
CPU time 74.15 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:21:23 PM PDT 24
Peak memory 251788 kb
Host smart-2ef15955-dbe7-46dc-ac8c-5525970d7ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439361838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2439361838
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2832296141
Short name T822
Test name
Test status
Simulation time 56522309720 ps
CPU time 155.4 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:22:43 PM PDT 24
Peak memory 254768 kb
Host smart-263a68e0-21ae-434f-95f1-6e00867aac4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832296141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2832296141
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2781406227
Short name T304
Test name
Test status
Simulation time 1348971790 ps
CPU time 27.57 seconds
Started Jul 19 06:20:00 PM PDT 24
Finished Jul 19 06:20:28 PM PDT 24
Peak memory 240600 kb
Host smart-1e15b49a-5930-4c1b-b21e-4d21099e4c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781406227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2781406227
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2693971662
Short name T83
Test name
Test status
Simulation time 20148720467 ps
CPU time 160.61 seconds
Started Jul 19 06:20:06 PM PDT 24
Finished Jul 19 06:22:48 PM PDT 24
Peak memory 252104 kb
Host smart-5d3c5c68-2239-4f92-b318-6cdd43257f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693971662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2693971662
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3718620109
Short name T490
Test name
Test status
Simulation time 57481800 ps
CPU time 3.36 seconds
Started Jul 19 06:20:01 PM PDT 24
Finished Jul 19 06:20:05 PM PDT 24
Peak memory 233168 kb
Host smart-57bb1db6-6ac7-4aa9-b55b-f2a182407864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718620109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3718620109
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2251523972
Short name T701
Test name
Test status
Simulation time 14857255221 ps
CPU time 40.98 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:20:41 PM PDT 24
Peak memory 224972 kb
Host smart-362570d9-0cf4-465e-bace-15d1c8fccbdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251523972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2251523972
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.566315664
Short name T872
Test name
Test status
Simulation time 281082219 ps
CPU time 5.23 seconds
Started Jul 19 06:19:58 PM PDT 24
Finished Jul 19 06:20:04 PM PDT 24
Peak memory 233040 kb
Host smart-6df02659-e883-464a-901d-b49ac3b7cbd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566315664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.566315664
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3457504381
Short name T632
Test name
Test status
Simulation time 77749225 ps
CPU time 2.51 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:20:02 PM PDT 24
Peak memory 233104 kb
Host smart-90229e93-0b8b-4d8d-ba4b-9445897150cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457504381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3457504381
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2747129912
Short name T440
Test name
Test status
Simulation time 2759238661 ps
CPU time 13.62 seconds
Started Jul 19 06:20:10 PM PDT 24
Finished Jul 19 06:20:25 PM PDT 24
Peak memory 221168 kb
Host smart-6ac62b0c-bd23-4336-b850-1a25dd414a8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2747129912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2747129912
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.650732481
Short name T132
Test name
Test status
Simulation time 57839746731 ps
CPU time 92.11 seconds
Started Jul 19 06:20:08 PM PDT 24
Finished Jul 19 06:21:41 PM PDT 24
Peak memory 255196 kb
Host smart-f94e0227-fd74-457b-a29b-9c7e6162ae12
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650732481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.650732481
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1976996717
Short name T854
Test name
Test status
Simulation time 4209658007 ps
CPU time 21.8 seconds
Started Jul 19 06:20:01 PM PDT 24
Finished Jul 19 06:20:23 PM PDT 24
Peak memory 216708 kb
Host smart-94622b2f-fb44-4543-a732-7a1fa338a9ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976996717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1976996717
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.111953412
Short name T424
Test name
Test status
Simulation time 15069383798 ps
CPU time 9.21 seconds
Started Jul 19 06:20:01 PM PDT 24
Finished Jul 19 06:20:11 PM PDT 24
Peak memory 216780 kb
Host smart-d44afb5e-4b54-49df-8add-e1ae21581915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111953412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.111953412
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3654085269
Short name T372
Test name
Test status
Simulation time 41464791 ps
CPU time 0.76 seconds
Started Jul 19 06:20:01 PM PDT 24
Finished Jul 19 06:20:02 PM PDT 24
Peak memory 206380 kb
Host smart-5939c93a-6408-4d4a-be1a-5fd9414ebfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654085269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3654085269
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2925520795
Short name T327
Test name
Test status
Simulation time 84080470 ps
CPU time 0.75 seconds
Started Jul 19 06:20:00 PM PDT 24
Finished Jul 19 06:20:02 PM PDT 24
Peak memory 206436 kb
Host smart-0e9f2ba5-4fe4-4d7c-8340-a3a261edf26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925520795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2925520795
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1928661657
Short name T383
Test name
Test status
Simulation time 353596457 ps
CPU time 4.73 seconds
Started Jul 19 06:19:59 PM PDT 24
Finished Jul 19 06:20:04 PM PDT 24
Peak memory 233120 kb
Host smart-a6a1aa25-d0af-4ea2-8be2-2c722d5d7067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928661657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1928661657
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3803607422
Short name T918
Test name
Test status
Simulation time 29885141 ps
CPU time 0.72 seconds
Started Jul 19 06:20:12 PM PDT 24
Finished Jul 19 06:20:14 PM PDT 24
Peak memory 205904 kb
Host smart-99a9625f-2eaa-42fc-a3dd-e48b6cd7a2a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803607422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3803607422
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.739566717
Short name T834
Test name
Test status
Simulation time 558404294 ps
CPU time 2.92 seconds
Started Jul 19 06:20:05 PM PDT 24
Finished Jul 19 06:20:08 PM PDT 24
Peak memory 224828 kb
Host smart-72eece14-3b05-4fed-8ec8-2957f0ff59fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739566717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.739566717
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.4266403993
Short name T379
Test name
Test status
Simulation time 14942041 ps
CPU time 0.79 seconds
Started Jul 19 06:20:08 PM PDT 24
Finished Jul 19 06:20:10 PM PDT 24
Peak memory 207076 kb
Host smart-6859620c-2ba4-470b-b2ed-945b2d9266af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266403993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4266403993
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1742061124
Short name T975
Test name
Test status
Simulation time 8085871826 ps
CPU time 86.47 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:21:38 PM PDT 24
Peak memory 250796 kb
Host smart-5ad974e7-b383-4d27-a426-73cb6e6a950f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742061124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1742061124
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1050726539
Short name T910
Test name
Test status
Simulation time 3963925480 ps
CPU time 102.4 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:21:54 PM PDT 24
Peak memory 266812 kb
Host smart-86b026fb-0990-4882-927b-1897ce36ca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050726539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1050726539
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.4074412117
Short name T334
Test name
Test status
Simulation time 825974592 ps
CPU time 6.82 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:20:15 PM PDT 24
Peak memory 233180 kb
Host smart-96306f4a-a198-4a6b-be3c-2ba0095ea6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074412117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.4074412117
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1238295927
Short name T1007
Test name
Test status
Simulation time 3095711393 ps
CPU time 54.36 seconds
Started Jul 19 06:20:10 PM PDT 24
Finished Jul 19 06:21:05 PM PDT 24
Peak memory 236300 kb
Host smart-fbf61e07-9edd-4931-af75-57cc3a42ae05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238295927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1238295927
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2840941881
Short name T245
Test name
Test status
Simulation time 241154590 ps
CPU time 2.68 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:20:11 PM PDT 24
Peak memory 224876 kb
Host smart-0250a3c2-bd5d-4007-80fb-c1108efe6740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840941881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2840941881
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1293398580
Short name T791
Test name
Test status
Simulation time 8708503517 ps
CPU time 24.72 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:20:33 PM PDT 24
Peak memory 224944 kb
Host smart-dcba9cf4-0516-4200-88c0-b2917e0f01d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293398580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1293398580
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.893980540
Short name T204
Test name
Test status
Simulation time 29078165932 ps
CPU time 22.44 seconds
Started Jul 19 06:20:08 PM PDT 24
Finished Jul 19 06:20:31 PM PDT 24
Peak memory 240008 kb
Host smart-4a229cff-2f4b-447b-bcc2-f0dbb1078949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893980540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.893980540
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1517127766
Short name T538
Test name
Test status
Simulation time 2768315649 ps
CPU time 3.46 seconds
Started Jul 19 06:20:06 PM PDT 24
Finished Jul 19 06:20:11 PM PDT 24
Peak memory 233188 kb
Host smart-17887c2f-c4a1-41e6-a174-93d5f6989dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517127766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1517127766
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1518701710
Short name T141
Test name
Test status
Simulation time 829593445 ps
CPU time 4.22 seconds
Started Jul 19 06:20:12 PM PDT 24
Finished Jul 19 06:20:17 PM PDT 24
Peak memory 219752 kb
Host smart-1f2d0cf5-cb36-471f-8f0b-0e86a57b446a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1518701710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1518701710
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.347046611
Short name T580
Test name
Test status
Simulation time 930547402 ps
CPU time 6.99 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:20:15 PM PDT 24
Peak memory 216604 kb
Host smart-b302d060-d4c3-40e7-a43d-1f1d836147f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347046611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.347046611
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.773609591
Short name T949
Test name
Test status
Simulation time 50145958 ps
CPU time 1.95 seconds
Started Jul 19 06:20:07 PM PDT 24
Finished Jul 19 06:20:10 PM PDT 24
Peak memory 216632 kb
Host smart-d2db10ed-2880-4d5e-a6f0-13b228dfe983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773609591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.773609591
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3314090521
Short name T633
Test name
Test status
Simulation time 194344361 ps
CPU time 0.89 seconds
Started Jul 19 06:20:06 PM PDT 24
Finished Jul 19 06:20:07 PM PDT 24
Peak memory 206448 kb
Host smart-df94debf-755d-4f7d-8041-2155faec720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314090521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3314090521
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1174439162
Short name T88
Test name
Test status
Simulation time 204405674 ps
CPU time 4.62 seconds
Started Jul 19 06:20:06 PM PDT 24
Finished Jul 19 06:20:11 PM PDT 24
Peak memory 233072 kb
Host smart-ea6f53b0-140d-4836-bb06-194a362f352c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174439162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1174439162
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3226726315
Short name T342
Test name
Test status
Simulation time 14459322 ps
CPU time 0.72 seconds
Started Jul 19 06:20:20 PM PDT 24
Finished Jul 19 06:20:22 PM PDT 24
Peak memory 205936 kb
Host smart-eaca17ff-7a86-4a34-becb-3b27c6f16613
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226726315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3226726315
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3076123220
Short name T903
Test name
Test status
Simulation time 529347355 ps
CPU time 10.58 seconds
Started Jul 19 06:20:10 PM PDT 24
Finished Jul 19 06:20:21 PM PDT 24
Peak memory 233048 kb
Host smart-78862941-a87f-4003-85df-f9bccfd84c41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076123220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3076123220
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1341472051
Short name T624
Test name
Test status
Simulation time 27757944 ps
CPU time 0.74 seconds
Started Jul 19 06:20:14 PM PDT 24
Finished Jul 19 06:20:15 PM PDT 24
Peak memory 207084 kb
Host smart-97a7c71c-ffb6-4c20-b3d3-37e7bda6aaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341472051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1341472051
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1829640042
Short name T829
Test name
Test status
Simulation time 1980280501 ps
CPU time 11.49 seconds
Started Jul 19 06:20:18 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 249500 kb
Host smart-2b551f77-9656-42b1-b706-0b780a07c1be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829640042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1829640042
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1696857989
Short name T950
Test name
Test status
Simulation time 98818292784 ps
CPU time 171.86 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:23:12 PM PDT 24
Peak memory 250704 kb
Host smart-4f8c63b3-9bc2-4ec4-ac5c-544dcc93e287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696857989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1696857989
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.4228000870
Short name T199
Test name
Test status
Simulation time 28870780620 ps
CPU time 145.81 seconds
Started Jul 19 06:20:17 PM PDT 24
Finished Jul 19 06:22:43 PM PDT 24
Peak memory 233252 kb
Host smart-97444e58-b28d-42c5-9b07-f26295999a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228000870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.4228000870
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.1151578590
Short name T816
Test name
Test status
Simulation time 8389536755 ps
CPU time 14.89 seconds
Started Jul 19 06:20:15 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 233224 kb
Host smart-4cbf41d9-3c9f-4db5-9b81-9bff9e15c0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151578590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1151578590
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3992153225
Short name T922
Test name
Test status
Simulation time 11508612838 ps
CPU time 73.07 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:21:25 PM PDT 24
Peak memory 241408 kb
Host smart-210cde2c-ccea-4296-ae60-3d666342c961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992153225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3992153225
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2949209116
Short name T889
Test name
Test status
Simulation time 111971473 ps
CPU time 2.43 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:20:14 PM PDT 24
Peak memory 224856 kb
Host smart-211f83a1-f992-4c24-a590-5723e909e71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949209116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2949209116
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3575575409
Short name T590
Test name
Test status
Simulation time 2921022957 ps
CPU time 29.71 seconds
Started Jul 19 06:20:10 PM PDT 24
Finished Jul 19 06:20:41 PM PDT 24
Peak memory 238828 kb
Host smart-1db5785f-6a20-4228-9f62-e40e28b81713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575575409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3575575409
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.616215701
Short name T948
Test name
Test status
Simulation time 15031065006 ps
CPU time 11.57 seconds
Started Jul 19 06:20:14 PM PDT 24
Finished Jul 19 06:20:27 PM PDT 24
Peak memory 233180 kb
Host smart-e32f1207-99e2-4e26-a480-8daa8cba9b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616215701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.616215701
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2546016477
Short name T735
Test name
Test status
Simulation time 3425066965 ps
CPU time 6.62 seconds
Started Jul 19 06:20:12 PM PDT 24
Finished Jul 19 06:20:19 PM PDT 24
Peak memory 240696 kb
Host smart-468b25d5-737e-48ba-b24e-676768403c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546016477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2546016477
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.139684465
Short name T642
Test name
Test status
Simulation time 304325557 ps
CPU time 3.88 seconds
Started Jul 19 06:20:14 PM PDT 24
Finished Jul 19 06:20:19 PM PDT 24
Peak memory 223536 kb
Host smart-7fb766fc-87d1-4a63-aa6f-9bbc973658c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=139684465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.139684465
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.454320104
Short name T276
Test name
Test status
Simulation time 75105230798 ps
CPU time 630.33 seconds
Started Jul 19 06:20:20 PM PDT 24
Finished Jul 19 06:30:51 PM PDT 24
Peak memory 272644 kb
Host smart-e5e0cb48-4e51-47df-bee3-218220285a50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454320104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.454320104
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3155321763
Short name T311
Test name
Test status
Simulation time 1607288411 ps
CPU time 16.72 seconds
Started Jul 19 06:20:12 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 216848 kb
Host smart-ad617d10-c20a-46cd-a436-5169fb6fce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155321763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3155321763
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4199854017
Short name T406
Test name
Test status
Simulation time 64395061042 ps
CPU time 10.72 seconds
Started Jul 19 06:20:13 PM PDT 24
Finished Jul 19 06:20:25 PM PDT 24
Peak memory 216632 kb
Host smart-45af73cd-7fbf-4350-bf87-ef24abdc2a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199854017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4199854017
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2372400904
Short name T435
Test name
Test status
Simulation time 1076521026 ps
CPU time 11.96 seconds
Started Jul 19 06:20:14 PM PDT 24
Finished Jul 19 06:20:27 PM PDT 24
Peak memory 216692 kb
Host smart-719ce68a-7422-4e4c-92b7-521e6ed88139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372400904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2372400904
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.51054212
Short name T566
Test name
Test status
Simulation time 78998923 ps
CPU time 0.86 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:20:13 PM PDT 24
Peak memory 206464 kb
Host smart-d5e29134-412c-4b52-9821-cbf25d2b758d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51054212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.51054212
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2501135569
Short name T869
Test name
Test status
Simulation time 329602614 ps
CPU time 2.33 seconds
Started Jul 19 06:20:11 PM PDT 24
Finished Jul 19 06:20:15 PM PDT 24
Peak memory 224556 kb
Host smart-5d983666-c6fb-4d07-bfd9-b46f82d5c085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501135569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2501135569
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1682817270
Short name T426
Test name
Test status
Simulation time 31810742 ps
CPU time 0.68 seconds
Started Jul 19 06:20:18 PM PDT 24
Finished Jul 19 06:20:19 PM PDT 24
Peak memory 205920 kb
Host smart-51a35992-b2a5-4cb1-8ab3-e01be207c294
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682817270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1682817270
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2634955679
Short name T274
Test name
Test status
Simulation time 778033923 ps
CPU time 4.58 seconds
Started Jul 19 06:20:20 PM PDT 24
Finished Jul 19 06:20:25 PM PDT 24
Peak memory 224848 kb
Host smart-4f96c54a-10c0-468d-942a-448d0c2eb82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634955679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2634955679
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.1354686327
Short name T338
Test name
Test status
Simulation time 24732580 ps
CPU time 0.82 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:21 PM PDT 24
Peak memory 207060 kb
Host smart-a217da95-3736-4d66-8397-ddd3b9486830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354686327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.1354686327
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2006730602
Short name T925
Test name
Test status
Simulation time 31757704625 ps
CPU time 25.6 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:46 PM PDT 24
Peak memory 233296 kb
Host smart-c30cdcd9-cda0-4034-bab1-3c477806a29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006730602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2006730602
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2132690019
Short name T186
Test name
Test status
Simulation time 80360452094 ps
CPU time 682.85 seconds
Started Jul 19 06:20:18 PM PDT 24
Finished Jul 19 06:31:42 PM PDT 24
Peak memory 265604 kb
Host smart-aafdbec6-4f68-4c09-ac21-5b5eb39a7fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132690019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2132690019
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1955848871
Short name T947
Test name
Test status
Simulation time 29741397584 ps
CPU time 300.77 seconds
Started Jul 19 06:20:17 PM PDT 24
Finished Jul 19 06:25:18 PM PDT 24
Peak memory 265856 kb
Host smart-aad2b126-b8b6-48e7-b90e-3ee673ddfce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955848871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1955848871
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3684193777
Short name T711
Test name
Test status
Simulation time 9745407891 ps
CPU time 39.18 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:59 PM PDT 24
Peak memory 249548 kb
Host smart-3a8f6c1c-7a66-46b0-b40c-31add5d6869b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684193777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3684193777
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.3112213444
Short name T81
Test name
Test status
Simulation time 408230141 ps
CPU time 3.65 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:23 PM PDT 24
Peak memory 224852 kb
Host smart-47e52b1e-9cfe-479b-98ac-9257aad84e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112213444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.3112213444
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2676863645
Short name T554
Test name
Test status
Simulation time 4155212187 ps
CPU time 45.4 seconds
Started Jul 19 06:20:18 PM PDT 24
Finished Jul 19 06:21:04 PM PDT 24
Peak memory 233168 kb
Host smart-8407fb32-8c7b-469b-89be-dd2487399822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676863645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2676863645
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3027123433
Short name T458
Test name
Test status
Simulation time 7206876253 ps
CPU time 10.62 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:31 PM PDT 24
Peak memory 224956 kb
Host smart-f23f29fd-65fc-4fc4-98d9-44273d49a32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027123433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3027123433
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2425809512
Short name T579
Test name
Test status
Simulation time 10955157637 ps
CPU time 30.46 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:52 PM PDT 24
Peak memory 233216 kb
Host smart-feb5a562-eb5d-4065-a940-10fc82a0f116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425809512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2425809512
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1834808856
Short name T787
Test name
Test status
Simulation time 1121918381 ps
CPU time 4.27 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:26 PM PDT 24
Peak memory 219144 kb
Host smart-4740d79c-9e78-4671-99a0-71e9c5645465
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1834808856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1834808856
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2806067852
Short name T1002
Test name
Test status
Simulation time 57094587 ps
CPU time 0.94 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:23 PM PDT 24
Peak memory 207544 kb
Host smart-dbf6fc78-8a37-4aca-9083-2b898b79d617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806067852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2806067852
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.63429992
Short name T467
Test name
Test status
Simulation time 4201662298 ps
CPU time 18.87 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:40 PM PDT 24
Peak memory 216696 kb
Host smart-4ce61b50-4a95-4539-aa54-65b8dae4b97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63429992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.63429992
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.789365673
Short name T592
Test name
Test status
Simulation time 18773692073 ps
CPU time 20.23 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:41 PM PDT 24
Peak memory 216584 kb
Host smart-2c4f53bd-21c3-425c-bdbc-138cf0330642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789365673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.789365673
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2603475940
Short name T492
Test name
Test status
Simulation time 46445999 ps
CPU time 0.83 seconds
Started Jul 19 06:20:20 PM PDT 24
Finished Jul 19 06:20:22 PM PDT 24
Peak memory 206352 kb
Host smart-3ee2bfd9-3d87-4a98-bcee-c2aaae91d43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603475940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2603475940
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.4237633776
Short name T73
Test name
Test status
Simulation time 88444462 ps
CPU time 0.73 seconds
Started Jul 19 06:20:18 PM PDT 24
Finished Jul 19 06:20:19 PM PDT 24
Peak memory 206480 kb
Host smart-fa62b9b4-ed25-42c2-9608-8dd1c4644136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237633776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.4237633776
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.241562494
Short name T217
Test name
Test status
Simulation time 607639723 ps
CPU time 4.2 seconds
Started Jul 19 06:20:19 PM PDT 24
Finished Jul 19 06:20:24 PM PDT 24
Peak memory 233108 kb
Host smart-3b0d1a73-3b31-419b-9acd-fa334f048557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241562494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.241562494
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2434926673
Short name T953
Test name
Test status
Simulation time 40151787 ps
CPU time 0.73 seconds
Started Jul 19 06:20:29 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 205848 kb
Host smart-3c3de486-2ee5-453b-8909-05458d84a69a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434926673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2434926673
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3404268394
Short name T700
Test name
Test status
Simulation time 948011257 ps
CPU time 10.78 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:40 PM PDT 24
Peak memory 233136 kb
Host smart-0b896b00-4d90-4e31-b6cf-8b3e6038bf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404268394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3404268394
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3710996048
Short name T504
Test name
Test status
Simulation time 24254619 ps
CPU time 0.75 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:22 PM PDT 24
Peak memory 207352 kb
Host smart-945e658d-db09-477b-8da6-bb620ead2c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710996048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3710996048
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1095787625
Short name T609
Test name
Test status
Simulation time 8699550788 ps
CPU time 45.21 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:21:14 PM PDT 24
Peak memory 239948 kb
Host smart-e6f907eb-d4b5-44d9-bd28-8c542aa7ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095787625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1095787625
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.239331075
Short name T790
Test name
Test status
Simulation time 47633036411 ps
CPU time 341.49 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:26:10 PM PDT 24
Peak memory 254492 kb
Host smart-411454de-8b72-4f05-8b88-3ad7e42d4078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239331075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.239331075
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3802090612
Short name T763
Test name
Test status
Simulation time 54268849239 ps
CPU time 103.28 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:22:12 PM PDT 24
Peak memory 257836 kb
Host smart-c0da14c5-2f8c-48ef-9fcd-b52b8b79afda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802090612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3802090612
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.301920869
Short name T653
Test name
Test status
Simulation time 5336344268 ps
CPU time 16.78 seconds
Started Jul 19 06:20:30 PM PDT 24
Finished Jul 19 06:20:47 PM PDT 24
Peak memory 233208 kb
Host smart-db351160-9858-41ff-a383-c48c146eb0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301920869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.301920869
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1651546030
Short name T36
Test name
Test status
Simulation time 150016604149 ps
CPU time 441.11 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:27:50 PM PDT 24
Peak memory 249544 kb
Host smart-3435149f-1e31-452d-9500-99a0ddb899e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651546030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1651546030
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3514034995
Short name T764
Test name
Test status
Simulation time 1182144136 ps
CPU time 13.76 seconds
Started Jul 19 06:20:27 PM PDT 24
Finished Jul 19 06:20:42 PM PDT 24
Peak memory 233092 kb
Host smart-06ce8a91-e0c5-4493-9c0d-6b12e3f0bc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514034995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3514034995
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2035821503
Short name T232
Test name
Test status
Simulation time 16509883622 ps
CPU time 40.73 seconds
Started Jul 19 06:20:29 PM PDT 24
Finished Jul 19 06:21:11 PM PDT 24
Peak memory 236600 kb
Host smart-51bdca71-0a71-4e2b-81f6-d9ba574afb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035821503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2035821503
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2577123251
Short name T219
Test name
Test status
Simulation time 1370538395 ps
CPU time 3.21 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:32 PM PDT 24
Peak memory 224848 kb
Host smart-625b888d-6500-4713-ac1f-a100ba6d651b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577123251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2577123251
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.698422996
Short name T405
Test name
Test status
Simulation time 2772105545 ps
CPU time 9.79 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:38 PM PDT 24
Peak memory 233072 kb
Host smart-fc55c6e7-9586-4545-a462-b8ef0446d8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698422996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.698422996
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1479137631
Short name T614
Test name
Test status
Simulation time 299270166 ps
CPU time 4.52 seconds
Started Jul 19 06:20:29 PM PDT 24
Finished Jul 19 06:20:35 PM PDT 24
Peak memory 221824 kb
Host smart-f9c57243-83f9-4220-b4d0-8d3cbe274133
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1479137631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1479137631
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4153406928
Short name T468
Test name
Test status
Simulation time 45514283 ps
CPU time 1 seconds
Started Jul 19 06:20:29 PM PDT 24
Finished Jul 19 06:20:31 PM PDT 24
Peak memory 207444 kb
Host smart-1a9de709-dd2e-489a-8080-0ab47cb00b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153406928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4153406928
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.944757515
Short name T717
Test name
Test status
Simulation time 19500290033 ps
CPU time 8.43 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 216736 kb
Host smart-b43fa79b-091b-4dce-9619-5f6c8c391410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944757515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.944757515
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2900983069
Short name T968
Test name
Test status
Simulation time 2000004921 ps
CPU time 6.27 seconds
Started Jul 19 06:20:21 PM PDT 24
Finished Jul 19 06:20:28 PM PDT 24
Peak memory 216424 kb
Host smart-d4d1e2bc-d68a-4845-b907-cef1d807b3e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900983069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2900983069
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.2188544491
Short name T377
Test name
Test status
Simulation time 591454147 ps
CPU time 1.97 seconds
Started Jul 19 06:20:29 PM PDT 24
Finished Jul 19 06:20:32 PM PDT 24
Peak memory 216668 kb
Host smart-f04bff42-815e-4db2-ad76-b0f3131da2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188544491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2188544491
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3464295744
Short name T369
Test name
Test status
Simulation time 25329415 ps
CPU time 0.69 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 206128 kb
Host smart-2d63683d-f4ff-4167-a75a-0c55f0ca362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464295744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3464295744
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.125967794
Short name T971
Test name
Test status
Simulation time 3640441446 ps
CPU time 7.19 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:36 PM PDT 24
Peak memory 225040 kb
Host smart-f064854c-17a1-41bd-b3d5-3098f234eb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125967794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.125967794
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1540304581
Short name T386
Test name
Test status
Simulation time 13282781 ps
CPU time 0.74 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:41 PM PDT 24
Peak memory 205344 kb
Host smart-e97dc6fe-b18c-411f-80d2-6b670de3fca0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540304581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1540304581
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.864028447
Short name T927
Test name
Test status
Simulation time 14172532538 ps
CPU time 6.37 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:46 PM PDT 24
Peak memory 233164 kb
Host smart-5339e9bc-b93d-49e1-bc1a-8e739ccf791b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864028447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.864028447
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2078946997
Short name T346
Test name
Test status
Simulation time 16752786 ps
CPU time 0.76 seconds
Started Jul 19 06:20:29 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 206080 kb
Host smart-8abd3a64-f2c5-4840-aa0f-2f1fa6bf5b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078946997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2078946997
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2441396316
Short name T484
Test name
Test status
Simulation time 23013532 ps
CPU time 0.79 seconds
Started Jul 19 06:20:42 PM PDT 24
Finished Jul 19 06:20:43 PM PDT 24
Peak memory 216244 kb
Host smart-973573d9-2c28-4ba7-9d02-60e796ecc26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441396316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2441396316
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3873007216
Short name T552
Test name
Test status
Simulation time 200278149629 ps
CPU time 112.09 seconds
Started Jul 19 06:20:45 PM PDT 24
Finished Jul 19 06:22:37 PM PDT 24
Peak memory 241448 kb
Host smart-e2396b7f-5cf7-4630-b853-e5775e60e74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873007216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3873007216
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3877061075
Short name T90
Test name
Test status
Simulation time 9767988728 ps
CPU time 41.36 seconds
Started Jul 19 06:20:42 PM PDT 24
Finished Jul 19 06:21:24 PM PDT 24
Peak memory 252372 kb
Host smart-d97f1f30-c2a5-4ac2-bfbf-28538c67d579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877061075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3877061075
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2806574726
Short name T410
Test name
Test status
Simulation time 898437766 ps
CPU time 15.19 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:54 PM PDT 24
Peak memory 233156 kb
Host smart-6b49474e-0f8c-4743-a40e-6f7e3821d406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806574726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2806574726
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.575986955
Short name T578
Test name
Test status
Simulation time 7219584291 ps
CPU time 42.05 seconds
Started Jul 19 06:20:41 PM PDT 24
Finished Jul 19 06:21:24 PM PDT 24
Peak memory 249612 kb
Host smart-af068796-8f81-40b2-b050-ddc3a6c9aa83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575986955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.575986955
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2467493731
Short name T271
Test name
Test status
Simulation time 1025042760 ps
CPU time 6.25 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:46 PM PDT 24
Peak memory 233108 kb
Host smart-3abfb1d8-1b06-4587-8024-fe183f850e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467493731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2467493731
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2607984327
Short name T487
Test name
Test status
Simulation time 334747068 ps
CPU time 4.57 seconds
Started Jul 19 06:20:36 PM PDT 24
Finished Jul 19 06:20:43 PM PDT 24
Peak memory 224896 kb
Host smart-088381d6-e276-4f09-8ebb-2ee93f96e787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607984327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2607984327
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1895784129
Short name T268
Test name
Test status
Simulation time 2691556048 ps
CPU time 6.29 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:47 PM PDT 24
Peak memory 225032 kb
Host smart-164f53aa-017a-425b-8689-28731e7710d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895784129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1895784129
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3263257775
Short name T445
Test name
Test status
Simulation time 3332928366 ps
CPU time 3.86 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:42 PM PDT 24
Peak memory 225052 kb
Host smart-3aaa0ffa-a4ef-490c-9fea-9f1881ee203a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263257775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3263257775
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.882491363
Short name T612
Test name
Test status
Simulation time 4656187957 ps
CPU time 10.66 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:50 PM PDT 24
Peak memory 219536 kb
Host smart-689e96c7-1cd4-4f8a-a88d-9bdbf81ccc67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=882491363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.882491363
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2259676068
Short name T845
Test name
Test status
Simulation time 38276992310 ps
CPU time 85.96 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:22:04 PM PDT 24
Peak memory 272828 kb
Host smart-2f375d4e-fd6d-48b4-8f34-5435155cd0b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259676068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2259676068
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.211560894
Short name T744
Test name
Test status
Simulation time 8210857986 ps
CPU time 24.78 seconds
Started Jul 19 06:20:31 PM PDT 24
Finished Jul 19 06:20:56 PM PDT 24
Peak memory 217072 kb
Host smart-141b0ee1-ba99-4030-88a6-a5fea7fd6a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211560894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.211560894
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2707160813
Short name T608
Test name
Test status
Simulation time 305222763 ps
CPU time 2.41 seconds
Started Jul 19 06:20:30 PM PDT 24
Finished Jul 19 06:20:33 PM PDT 24
Peak memory 216532 kb
Host smart-00bc98eb-d5c4-411d-96bd-03ee84bdef17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707160813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2707160813
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1272226701
Short name T321
Test name
Test status
Simulation time 128374296 ps
CPU time 1.64 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:31 PM PDT 24
Peak memory 216688 kb
Host smart-65e88172-b439-44de-8277-28fbbc50460b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272226701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1272226701
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1391215501
Short name T382
Test name
Test status
Simulation time 170270761 ps
CPU time 0.78 seconds
Started Jul 19 06:20:28 PM PDT 24
Finished Jul 19 06:20:30 PM PDT 24
Peak memory 206432 kb
Host smart-a1666b79-1436-49d7-86ea-d55ca357f7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391215501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1391215501
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2886974646
Short name T660
Test name
Test status
Simulation time 12635859883 ps
CPU time 37.74 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:21:18 PM PDT 24
Peak memory 249548 kb
Host smart-e7c43ef6-7590-4dd4-96c0-84001820c46a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886974646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2886974646
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3106539039
Short name T420
Test name
Test status
Simulation time 137686796 ps
CPU time 0.73 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:40 PM PDT 24
Peak memory 205328 kb
Host smart-e4824091-c421-4fad-888f-ada91daccc28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106539039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3106539039
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.757600534
Short name T973
Test name
Test status
Simulation time 8093019304 ps
CPU time 16.06 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:56 PM PDT 24
Peak memory 233172 kb
Host smart-a15f5ec8-3eae-4424-ba7f-3ce11bb579cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757600534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.757600534
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2715990251
Short name T337
Test name
Test status
Simulation time 26470938 ps
CPU time 0.76 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:40 PM PDT 24
Peak memory 206032 kb
Host smart-fc668802-003a-416d-b985-e1f2aeb32e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715990251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2715990251
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.26340959
Short name T695
Test name
Test status
Simulation time 1671600354 ps
CPU time 26.07 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:21:06 PM PDT 24
Peak memory 249504 kb
Host smart-9d138283-a748-4554-bb69-59c33a2d3133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26340959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.26340959
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2951427805
Short name T720
Test name
Test status
Simulation time 44504642085 ps
CPU time 215.36 seconds
Started Jul 19 06:20:36 PM PDT 24
Finished Jul 19 06:24:13 PM PDT 24
Peak memory 249664 kb
Host smart-81913246-d8b2-40e3-85e7-f6cc86014d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951427805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2951427805
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.77145705
Short name T9
Test name
Test status
Simulation time 12309014073 ps
CPU time 42.8 seconds
Started Jul 19 06:20:36 PM PDT 24
Finished Jul 19 06:21:21 PM PDT 24
Peak memory 257836 kb
Host smart-5fa5fbb4-bf90-435b-9485-73522e24ab2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77145705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.77145705
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.347069403
Short name T144
Test name
Test status
Simulation time 1747682965 ps
CPU time 20.83 seconds
Started Jul 19 06:20:43 PM PDT 24
Finished Jul 19 06:21:05 PM PDT 24
Peak memory 233048 kb
Host smart-3728240b-3e86-450f-af67-055fafb9a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347069403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.347069403
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.987377457
Short name T51
Test name
Test status
Simulation time 915519352 ps
CPU time 12.01 seconds
Started Jul 19 06:20:36 PM PDT 24
Finished Jul 19 06:20:50 PM PDT 24
Peak memory 234204 kb
Host smart-8798f51f-1b52-495b-a103-f90f2a4861f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987377457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds
.987377457
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3363633346
Short name T848
Test name
Test status
Simulation time 1035418057 ps
CPU time 9.25 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:50 PM PDT 24
Peak memory 233064 kb
Host smart-0a6bd990-e2f0-4687-874e-99a9902771a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363633346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3363633346
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3796396151
Short name T905
Test name
Test status
Simulation time 9642164917 ps
CPU time 28.29 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:21:08 PM PDT 24
Peak memory 228340 kb
Host smart-6c193d80-64cf-49f5-8f2c-45e321827c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796396151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3796396151
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1530266976
Short name T34
Test name
Test status
Simulation time 12636433197 ps
CPU time 37.2 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:21:17 PM PDT 24
Peak memory 240568 kb
Host smart-3b58c908-b1f3-4956-b39f-f1f0ac181be8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530266976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1530266976
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1746031299
Short name T682
Test name
Test status
Simulation time 18342582140 ps
CPU time 15.16 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:55 PM PDT 24
Peak memory 224996 kb
Host smart-4ce225a2-4325-460e-aebd-4854249e526b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746031299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1746031299
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3046815891
Short name T685
Test name
Test status
Simulation time 340594883 ps
CPU time 4.04 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:43 PM PDT 24
Peak memory 220880 kb
Host smart-f82ba22b-a907-4875-ae2f-74bd81507d78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046815891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3046815891
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.406607247
Short name T755
Test name
Test status
Simulation time 79459380266 ps
CPU time 286.93 seconds
Started Jul 19 06:20:43 PM PDT 24
Finished Jul 19 06:25:31 PM PDT 24
Peak memory 250716 kb
Host smart-d1d6a51a-8521-40aa-8382-e5e2fe3ba656
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406607247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.406607247
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.485008047
Short name T310
Test name
Test status
Simulation time 12735302889 ps
CPU time 18.89 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:59 PM PDT 24
Peak memory 220568 kb
Host smart-97362758-783a-46ad-b25e-fe8cc1b32479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485008047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.485008047
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.802960192
Short name T341
Test name
Test status
Simulation time 2119006069 ps
CPU time 2.96 seconds
Started Jul 19 06:20:36 PM PDT 24
Finished Jul 19 06:20:41 PM PDT 24
Peak memory 216624 kb
Host smart-8b8c9a0a-c8c4-4777-b4d4-198dcf82fc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802960192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.802960192
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3279719002
Short name T602
Test name
Test status
Simulation time 16714738 ps
CPU time 0.74 seconds
Started Jul 19 06:20:43 PM PDT 24
Finished Jul 19 06:20:45 PM PDT 24
Peak memory 206432 kb
Host smart-3558780b-6bbf-4811-8c3e-6d5617bb1985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279719002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3279719002
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3208526625
Short name T563
Test name
Test status
Simulation time 111214096 ps
CPU time 1.09 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:40 PM PDT 24
Peak memory 207584 kb
Host smart-b0bb7c99-9442-4a8c-8ad3-24e34f2172ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208526625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3208526625
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3423562535
Short name T17
Test name
Test status
Simulation time 1008624458 ps
CPU time 4.67 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:44 PM PDT 24
Peak memory 224876 kb
Host smart-c4a51f7d-13b6-4e70-bf1b-cfd54570f2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423562535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3423562535
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2851798541
Short name T964
Test name
Test status
Simulation time 106597944 ps
CPU time 0.71 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:51 PM PDT 24
Peak memory 205376 kb
Host smart-f63dfd76-9275-4340-8750-cc1b6271a8e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851798541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2851798541
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3540589516
Short name T250
Test name
Test status
Simulation time 702505417 ps
CPU time 3.48 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:20:48 PM PDT 24
Peak memory 224964 kb
Host smart-7a17378a-5fab-470a-b0d4-ec499504e5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540589516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3540589516
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1239255990
Short name T756
Test name
Test status
Simulation time 31050261 ps
CPU time 0.79 seconds
Started Jul 19 06:20:43 PM PDT 24
Finished Jul 19 06:20:45 PM PDT 24
Peak memory 207324 kb
Host smart-8ba78c8e-43a3-40ee-b28d-23f2c4766ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239255990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1239255990
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3067025741
Short name T628
Test name
Test status
Simulation time 22438212289 ps
CPU time 47.16 seconds
Started Jul 19 06:20:51 PM PDT 24
Finished Jul 19 06:21:39 PM PDT 24
Peak memory 241244 kb
Host smart-80ebf2ea-b53e-4e93-91da-6c9b02fd0d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067025741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3067025741
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2923433771
Short name T898
Test name
Test status
Simulation time 695991655 ps
CPU time 4.67 seconds
Started Jul 19 06:20:42 PM PDT 24
Finished Jul 19 06:20:47 PM PDT 24
Peak memory 218112 kb
Host smart-862d1b6c-d564-4e7a-b832-bca708945ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923433771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2923433771
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.4095269273
Short name T694
Test name
Test status
Simulation time 849008155 ps
CPU time 17.42 seconds
Started Jul 19 06:20:50 PM PDT 24
Finished Jul 19 06:21:10 PM PDT 24
Peak memory 225008 kb
Host smart-134369e4-58f5-4218-8f07-86b0e8b17720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095269273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.4095269273
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3853949466
Short name T299
Test name
Test status
Simulation time 799931535 ps
CPU time 7.16 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:58 PM PDT 24
Peak memory 240700 kb
Host smart-043c79ea-5086-4a04-85f4-bd8bb2c09a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853949466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3853949466
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2716001977
Short name T77
Test name
Test status
Simulation time 49022710622 ps
CPU time 122.92 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:22:48 PM PDT 24
Peak memory 266412 kb
Host smart-e40b9e24-09c2-4b20-ba63-2a855232d9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716001977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2716001977
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3230985243
Short name T371
Test name
Test status
Simulation time 111109818 ps
CPU time 2.1 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:53 PM PDT 24
Peak memory 224292 kb
Host smart-e8a79fc6-4cc3-46b5-8ff7-314b635f2a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230985243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3230985243
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2041554807
Short name T572
Test name
Test status
Simulation time 1149199608 ps
CPU time 14.88 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:21:05 PM PDT 24
Peak memory 233108 kb
Host smart-71f9a2f4-eb43-4458-bc77-e8dac4f99811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041554807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2041554807
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2122174216
Short name T657
Test name
Test status
Simulation time 1741832852 ps
CPU time 3.88 seconds
Started Jul 19 06:20:46 PM PDT 24
Finished Jul 19 06:20:50 PM PDT 24
Peak memory 224924 kb
Host smart-28ff8094-e792-4a4f-8a73-ec192d07e70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122174216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2122174216
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1093873186
Short name T463
Test name
Test status
Simulation time 1986059461 ps
CPU time 10.44 seconds
Started Jul 19 06:20:42 PM PDT 24
Finished Jul 19 06:20:53 PM PDT 24
Peak memory 233116 kb
Host smart-a0a459ba-a70c-4f0d-95eb-c9121fc6c522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093873186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1093873186
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2156859139
Short name T12
Test name
Test status
Simulation time 1126872540 ps
CPU time 7.54 seconds
Started Jul 19 06:20:45 PM PDT 24
Finished Jul 19 06:20:54 PM PDT 24
Peak memory 222816 kb
Host smart-8d8b9a46-0835-4015-8d88-b2490c014f74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2156859139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2156859139
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.123524607
Short name T133
Test name
Test status
Simulation time 14442129731 ps
CPU time 124.06 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:22:49 PM PDT 24
Peak memory 255208 kb
Host smart-40188426-590a-4587-a7f2-580e06c0b759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123524607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.123524607
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2865427453
Short name T823
Test name
Test status
Simulation time 14565951 ps
CPU time 0.75 seconds
Started Jul 19 06:20:35 PM PDT 24
Finished Jul 19 06:20:36 PM PDT 24
Peak memory 206200 kb
Host smart-86f6f7a5-1bc5-4ae3-b89a-93d9609e7749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865427453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2865427453
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.28929399
Short name T670
Test name
Test status
Simulation time 9221142354 ps
CPU time 8.6 seconds
Started Jul 19 06:20:38 PM PDT 24
Finished Jul 19 06:20:49 PM PDT 24
Peak memory 216672 kb
Host smart-a8f64dfa-8fe6-4d49-8e10-26a9f26ba085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28929399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.28929399
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.327296193
Short name T659
Test name
Test status
Simulation time 216367904 ps
CPU time 3.07 seconds
Started Jul 19 06:20:37 PM PDT 24
Finished Jul 19 06:20:43 PM PDT 24
Peak memory 216616 kb
Host smart-c42bece9-d5fc-436a-a8e1-9337809e26d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327296193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.327296193
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3914415165
Short name T891
Test name
Test status
Simulation time 48032355 ps
CPU time 0.8 seconds
Started Jul 19 06:20:40 PM PDT 24
Finished Jul 19 06:20:41 PM PDT 24
Peak memory 206408 kb
Host smart-6ce132c8-3128-4d99-8587-8d59ecea5508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914415165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3914415165
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1990587716
Short name T494
Test name
Test status
Simulation time 62902224 ps
CPU time 2.23 seconds
Started Jul 19 06:20:43 PM PDT 24
Finished Jul 19 06:20:46 PM PDT 24
Peak memory 232780 kb
Host smart-d96f559e-93ef-40c6-a30f-a6e04fb0aa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990587716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1990587716
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.975998419
Short name T368
Test name
Test status
Simulation time 50036199 ps
CPU time 0.73 seconds
Started Jul 19 06:16:10 PM PDT 24
Finished Jul 19 06:16:11 PM PDT 24
Peak memory 205920 kb
Host smart-d7dc25a7-9216-4917-a718-c7c59cefe5c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975998419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.975998419
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1321449664
Short name T495
Test name
Test status
Simulation time 1512572292 ps
CPU time 4.1 seconds
Started Jul 19 06:16:02 PM PDT 24
Finished Jul 19 06:16:07 PM PDT 24
Peak memory 224868 kb
Host smart-a3cdb230-e108-4e67-848c-a9313b41ffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321449664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1321449664
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.655943314
Short name T966
Test name
Test status
Simulation time 18763431 ps
CPU time 0.79 seconds
Started Jul 19 06:15:54 PM PDT 24
Finished Jul 19 06:15:55 PM PDT 24
Peak memory 206060 kb
Host smart-0e1e46bd-1082-4c93-a05b-b0ad0fb1180f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655943314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.655943314
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.801503927
Short name T376
Test name
Test status
Simulation time 7216935401 ps
CPU time 49.84 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:17:00 PM PDT 24
Peak memory 239532 kb
Host smart-ad34d6f5-912d-4544-883a-7bb75b7b7883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801503927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.801503927
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.4133727351
Short name T315
Test name
Test status
Simulation time 108459648669 ps
CPU time 47.8 seconds
Started Jul 19 06:16:10 PM PDT 24
Finished Jul 19 06:16:58 PM PDT 24
Peak memory 219840 kb
Host smart-ca326919-3333-4475-8485-76fea08d36b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133727351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4133727351
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1311857527
Short name T43
Test name
Test status
Simulation time 14001875707 ps
CPU time 61.49 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:17:11 PM PDT 24
Peak memory 252048 kb
Host smart-ae98bafa-dab1-49c2-b544-dc720a7258ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311857527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1311857527
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3720671112
Short name T454
Test name
Test status
Simulation time 305500909 ps
CPU time 5.66 seconds
Started Jul 19 06:16:01 PM PDT 24
Finished Jul 19 06:16:08 PM PDT 24
Peak memory 236284 kb
Host smart-c37aef45-0e2c-4f8f-b242-f1645aad5eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720671112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3720671112
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.113969112
Short name T478
Test name
Test status
Simulation time 7977550285 ps
CPU time 30.94 seconds
Started Jul 19 06:16:02 PM PDT 24
Finished Jul 19 06:16:34 PM PDT 24
Peak memory 237620 kb
Host smart-49d833cf-b91b-40e1-8705-7108596c0e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113969112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
113969112
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2193611461
Short name T5
Test name
Test status
Simulation time 28865641 ps
CPU time 2.13 seconds
Started Jul 19 06:15:57 PM PDT 24
Finished Jul 19 06:16:00 PM PDT 24
Peak memory 224292 kb
Host smart-dca50102-5fe0-472d-a1f2-34543b9c5e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193611461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2193611461
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2833505031
Short name T531
Test name
Test status
Simulation time 299742203 ps
CPU time 8.23 seconds
Started Jul 19 06:16:04 PM PDT 24
Finished Jul 19 06:16:13 PM PDT 24
Peak memory 236304 kb
Host smart-3d82ce98-b1e7-4eba-86cf-e2dfd64f6c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833505031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2833505031
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4166607649
Short name T263
Test name
Test status
Simulation time 3732493912 ps
CPU time 14.11 seconds
Started Jul 19 06:15:55 PM PDT 24
Finished Jul 19 06:16:10 PM PDT 24
Peak memory 233212 kb
Host smart-af84d474-6223-4333-bbf7-7638a317a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166607649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4166607649
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2614388855
Short name T488
Test name
Test status
Simulation time 1552020792 ps
CPU time 7.23 seconds
Started Jul 19 06:15:56 PM PDT 24
Finished Jul 19 06:16:04 PM PDT 24
Peak memory 224888 kb
Host smart-0bdb16bb-163f-49a5-b4f3-cea037ff9930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614388855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2614388855
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3104618650
Short name T742
Test name
Test status
Simulation time 197467245 ps
CPU time 5.3 seconds
Started Jul 19 06:16:10 PM PDT 24
Finished Jul 19 06:16:16 PM PDT 24
Peak memory 223416 kb
Host smart-eeb08c1a-7545-40f4-bd64-71a829bc1f60
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3104618650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3104618650
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4235963786
Short name T60
Test name
Test status
Simulation time 39517881 ps
CPU time 1.02 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:16:11 PM PDT 24
Peak memory 236580 kb
Host smart-8b1921ec-4a41-4751-b863-c592b4d637a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235963786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4235963786
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1441828901
Short name T184
Test name
Test status
Simulation time 38656784962 ps
CPU time 114.93 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:18:05 PM PDT 24
Peak memory 256156 kb
Host smart-eabab2d4-226c-4fae-b901-1ada92f87e42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441828901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1441828901
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2360498550
Short name T26
Test name
Test status
Simulation time 541800415 ps
CPU time 8.63 seconds
Started Jul 19 06:15:56 PM PDT 24
Finished Jul 19 06:16:05 PM PDT 24
Peak memory 219048 kb
Host smart-239c6c6b-5897-4901-b8f2-cb8e0839b78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360498550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2360498550
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3911728974
Short name T355
Test name
Test status
Simulation time 378485492 ps
CPU time 1.35 seconds
Started Jul 19 06:15:55 PM PDT 24
Finished Jul 19 06:15:57 PM PDT 24
Peak memory 208348 kb
Host smart-6ab05b47-fe02-4da1-8fca-80c99476e703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911728974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3911728974
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.270483892
Short name T91
Test name
Test status
Simulation time 23191186 ps
CPU time 1.62 seconds
Started Jul 19 06:15:55 PM PDT 24
Finished Jul 19 06:15:57 PM PDT 24
Peak memory 216640 kb
Host smart-cf78e434-6ae4-4ea5-8fd5-270d53c83444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270483892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.270483892
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3355125275
Short name T396
Test name
Test status
Simulation time 125968841 ps
CPU time 0.81 seconds
Started Jul 19 06:15:58 PM PDT 24
Finished Jul 19 06:16:00 PM PDT 24
Peak memory 206428 kb
Host smart-ce20b7e8-e674-4522-ab72-36ff3a71bae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355125275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3355125275
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2202877580
Short name T576
Test name
Test status
Simulation time 4431161149 ps
CPU time 16.94 seconds
Started Jul 19 06:16:01 PM PDT 24
Finished Jul 19 06:16:19 PM PDT 24
Peak memory 241248 kb
Host smart-1e73bf25-1116-4c5c-b8bf-249ab45dabc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202877580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2202877580
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.702990700
Short name T347
Test name
Test status
Simulation time 22422050 ps
CPU time 0.76 seconds
Started Jul 19 06:20:53 PM PDT 24
Finished Jul 19 06:20:55 PM PDT 24
Peak memory 205940 kb
Host smart-688dcf21-c7af-40f5-9474-ef8e8a89e5db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702990700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.702990700
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3930305928
Short name T894
Test name
Test status
Simulation time 220351998 ps
CPU time 2.5 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:53 PM PDT 24
Peak memory 224928 kb
Host smart-54613f19-0667-48ee-b5c6-3ff8505cbfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930305928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3930305928
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2626259687
Short name T333
Test name
Test status
Simulation time 44580094 ps
CPU time 0.76 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:20:46 PM PDT 24
Peak memory 206332 kb
Host smart-72cb50bb-8437-4743-ad32-afc9bafaf6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626259687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2626259687
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3014537929
Short name T636
Test name
Test status
Simulation time 562355150 ps
CPU time 6.23 seconds
Started Jul 19 06:20:50 PM PDT 24
Finished Jul 19 06:20:58 PM PDT 24
Peak memory 235456 kb
Host smart-7c0e141e-279e-48c6-b52e-06dec12262bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014537929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3014537929
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3756122165
Short name T189
Test name
Test status
Simulation time 11991513299 ps
CPU time 90.36 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:22:20 PM PDT 24
Peak memory 225068 kb
Host smart-b3ec09da-4222-49aa-abbd-f8b58b15869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756122165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3756122165
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.3585689083
Short name T195
Test name
Test status
Simulation time 35823460979 ps
CPU time 355.91 seconds
Started Jul 19 06:20:52 PM PDT 24
Finished Jul 19 06:26:49 PM PDT 24
Peak memory 251508 kb
Host smart-f779c173-8193-4bb0-8d5b-90a40b99e965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585689083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.3585689083
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.617375180
Short name T298
Test name
Test status
Simulation time 3062646163 ps
CPU time 49.44 seconds
Started Jul 19 06:20:51 PM PDT 24
Finished Jul 19 06:21:42 PM PDT 24
Peak memory 237060 kb
Host smart-ec397352-1e30-4e7c-8f72-dd1325d0eada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617375180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.617375180
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.2656737130
Short name T936
Test name
Test status
Simulation time 11572834 ps
CPU time 0.76 seconds
Started Jul 19 06:20:50 PM PDT 24
Finished Jul 19 06:20:52 PM PDT 24
Peak memory 216260 kb
Host smart-71f21423-6f07-4d8b-a167-c443e00a822b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656737130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.2656737130
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3342399808
Short name T224
Test name
Test status
Simulation time 1804455451 ps
CPU time 18.8 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:21:04 PM PDT 24
Peak memory 233168 kb
Host smart-f9d1b0b7-8132-47fc-b0a9-7b377fbf1714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342399808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3342399808
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.1757266692
Short name T416
Test name
Test status
Simulation time 10449535581 ps
CPU time 40.06 seconds
Started Jul 19 06:20:50 PM PDT 24
Finished Jul 19 06:21:32 PM PDT 24
Peak memory 240248 kb
Host smart-155373f8-f712-45a7-b34b-3ea653cf0f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757266692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1757266692
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3580218186
Short name T264
Test name
Test status
Simulation time 2206184322 ps
CPU time 7.31 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:20:52 PM PDT 24
Peak memory 225004 kb
Host smart-d47941b6-57f5-4f2e-bde3-c58e275c72e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580218186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3580218186
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2305999650
Short name T739
Test name
Test status
Simulation time 3194570513 ps
CPU time 5.73 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:57 PM PDT 24
Peak memory 233156 kb
Host smart-b8ed0f72-7fa7-4e82-870e-51c593bbb09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305999650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2305999650
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2012694149
Short name T797
Test name
Test status
Simulation time 1029063120 ps
CPU time 9.14 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:21:00 PM PDT 24
Peak memory 220608 kb
Host smart-9df1086e-248a-4a8f-80f5-779510f9024e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2012694149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2012694149
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2513268933
Short name T864
Test name
Test status
Simulation time 10041699994 ps
CPU time 97.53 seconds
Started Jul 19 06:20:51 PM PDT 24
Finished Jul 19 06:22:30 PM PDT 24
Peak memory 253180 kb
Host smart-623dd126-7c00-42bd-b769-05fad89c1cfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513268933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2513268933
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2203901427
Short name T553
Test name
Test status
Simulation time 1587457990 ps
CPU time 27.41 seconds
Started Jul 19 06:20:43 PM PDT 24
Finished Jul 19 06:21:11 PM PDT 24
Peak memory 219856 kb
Host smart-ebda904f-daaa-463e-a9cf-fcad219d9005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203901427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2203901427
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.309061764
Short name T935
Test name
Test status
Simulation time 4382725592 ps
CPU time 12.84 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:21:04 PM PDT 24
Peak memory 216712 kb
Host smart-a7a63880-e941-4ff6-a3fb-230f3538e039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309061764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.309061764
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.663332570
Short name T350
Test name
Test status
Simulation time 148906008 ps
CPU time 3.14 seconds
Started Jul 19 06:20:51 PM PDT 24
Finished Jul 19 06:20:55 PM PDT 24
Peak memory 216644 kb
Host smart-59c5c56d-2385-40d8-8320-9b24fa7dc1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663332570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.663332570
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2408186288
Short name T332
Test name
Test status
Simulation time 47384960 ps
CPU time 0.8 seconds
Started Jul 19 06:20:44 PM PDT 24
Finished Jul 19 06:20:46 PM PDT 24
Peak memory 206372 kb
Host smart-c7b1dc9b-a0f3-48a1-9b6e-1638ed2a4aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408186288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2408186288
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.988179841
Short name T599
Test name
Test status
Simulation time 96356960446 ps
CPU time 17.31 seconds
Started Jul 19 06:20:48 PM PDT 24
Finished Jul 19 06:21:05 PM PDT 24
Peak memory 233136 kb
Host smart-cd25c26c-53dd-46a3-9ae0-ae1b6eb57778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988179841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.988179841
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3450519601
Short name T3
Test name
Test status
Simulation time 12380473 ps
CPU time 0.73 seconds
Started Jul 19 06:20:59 PM PDT 24
Finished Jul 19 06:21:00 PM PDT 24
Peak memory 205328 kb
Host smart-74277390-9d20-4b9c-b5e2-e217eb2993dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450519601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3450519601
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1950123181
Short name T228
Test name
Test status
Simulation time 40308451 ps
CPU time 2.59 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:53 PM PDT 24
Peak memory 233052 kb
Host smart-56373da2-3a78-4b0f-8228-451eae28334d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950123181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1950123181
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.98090144
Short name T940
Test name
Test status
Simulation time 52277256 ps
CPU time 0.76 seconds
Started Jul 19 06:20:53 PM PDT 24
Finished Jul 19 06:20:55 PM PDT 24
Peak memory 207060 kb
Host smart-bfd5bcb4-4fee-44d2-953c-f7706d8470af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98090144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.98090144
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2564695063
Short name T882
Test name
Test status
Simulation time 13123634 ps
CPU time 0.75 seconds
Started Jul 19 06:21:02 PM PDT 24
Finished Jul 19 06:21:03 PM PDT 24
Peak memory 216244 kb
Host smart-5786ade4-a143-446b-81bc-efa20d28d869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564695063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2564695063
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3292082702
Short name T227
Test name
Test status
Simulation time 13986443733 ps
CPU time 60.48 seconds
Started Jul 19 06:20:57 PM PDT 24
Finished Jul 19 06:21:58 PM PDT 24
Peak memory 239804 kb
Host smart-aa87f90f-c932-4770-a347-ba79361e13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292082702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3292082702
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2181659535
Short name T172
Test name
Test status
Simulation time 2905216531 ps
CPU time 59.51 seconds
Started Jul 19 06:20:57 PM PDT 24
Finished Jul 19 06:21:57 PM PDT 24
Peak memory 255040 kb
Host smart-7983eae1-8543-4962-9ca1-d67fbe9a0975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181659535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2181659535
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.4032273022
Short name T844
Test name
Test status
Simulation time 1143824547 ps
CPU time 6.79 seconds
Started Jul 19 06:20:48 PM PDT 24
Finished Jul 19 06:20:56 PM PDT 24
Peak memory 225080 kb
Host smart-54916b92-8654-4ecf-bb30-99c380580ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032273022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.4032273022
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2797059120
Short name T287
Test name
Test status
Simulation time 15636886575 ps
CPU time 91.93 seconds
Started Jul 19 06:20:56 PM PDT 24
Finished Jul 19 06:22:28 PM PDT 24
Peak memory 256280 kb
Host smart-8de5edd4-5393-49a2-acc0-d940a485869c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797059120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2797059120
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3503868145
Short name T732
Test name
Test status
Simulation time 109836515 ps
CPU time 2.06 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:53 PM PDT 24
Peak memory 219360 kb
Host smart-91611911-fc81-4fa3-9e4f-c2e33389140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503868145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3503868145
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.1554325096
Short name T209
Test name
Test status
Simulation time 696783614 ps
CPU time 11.79 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:21:03 PM PDT 24
Peak memory 241008 kb
Host smart-c8fcce23-2978-4187-99cb-239beb95ceeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554325096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1554325096
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3807010386
Short name T259
Test name
Test status
Simulation time 910001162 ps
CPU time 3.39 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:54 PM PDT 24
Peak memory 224932 kb
Host smart-45b38cd4-fd04-4ad2-aedd-41a8a99fe2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807010386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3807010386
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.4025212116
Short name T253
Test name
Test status
Simulation time 157744232 ps
CPU time 3.71 seconds
Started Jul 19 06:20:52 PM PDT 24
Finished Jul 19 06:20:58 PM PDT 24
Peak memory 233092 kb
Host smart-21f37204-793c-44a9-b5e3-db3905ed2278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025212116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.4025212116
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2407932807
Short name T593
Test name
Test status
Simulation time 146933490 ps
CPU time 3.5 seconds
Started Jul 19 06:21:00 PM PDT 24
Finished Jul 19 06:21:04 PM PDT 24
Peak memory 220704 kb
Host smart-c602ba30-92b7-4d4a-9436-7336935d9872
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2407932807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2407932807
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3868339898
Short name T414
Test name
Test status
Simulation time 272524013 ps
CPU time 0.94 seconds
Started Jul 19 06:20:57 PM PDT 24
Finished Jul 19 06:20:58 PM PDT 24
Peak memory 208008 kb
Host smart-8e06ecb9-2ebe-4d21-a9cc-b7e9ba818a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868339898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3868339898
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1597947060
Short name T308
Test name
Test status
Simulation time 297877027 ps
CPU time 5.15 seconds
Started Jul 19 06:20:51 PM PDT 24
Finished Jul 19 06:20:58 PM PDT 24
Peak memory 219400 kb
Host smart-22dcc36b-8af4-4746-a278-a02f6127a8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597947060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1597947060
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2227966932
Short name T746
Test name
Test status
Simulation time 178517211 ps
CPU time 1.66 seconds
Started Jul 19 06:20:51 PM PDT 24
Finished Jul 19 06:20:54 PM PDT 24
Peak memory 208336 kb
Host smart-fdf0ccf9-7825-4c15-9111-b8cde5141e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227966932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2227966932
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1231409370
Short name T353
Test name
Test status
Simulation time 366896494 ps
CPU time 1.4 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:20:51 PM PDT 24
Peak memory 216744 kb
Host smart-c67f6a97-f343-44f5-ac22-96f70cc785f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231409370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1231409370
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3020957208
Short name T130
Test name
Test status
Simulation time 15041941 ps
CPU time 0.72 seconds
Started Jul 19 06:20:47 PM PDT 24
Finished Jul 19 06:20:48 PM PDT 24
Peak memory 206440 kb
Host smart-7cc2af81-bb28-470b-bd21-5e7c238c9326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020957208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3020957208
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2231481885
Short name T604
Test name
Test status
Simulation time 10681671612 ps
CPU time 12.52 seconds
Started Jul 19 06:20:49 PM PDT 24
Finished Jul 19 06:21:03 PM PDT 24
Peak memory 249560 kb
Host smart-292204c6-6988-480b-b2a4-114f827f6b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231481885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2231481885
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1857588512
Short name T623
Test name
Test status
Simulation time 19811683 ps
CPU time 0.73 seconds
Started Jul 19 06:21:05 PM PDT 24
Finished Jul 19 06:21:07 PM PDT 24
Peak memory 205916 kb
Host smart-49150dfb-1e2a-4d6c-9dd9-3dd60e4dbca3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857588512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1857588512
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1147556361
Short name T437
Test name
Test status
Simulation time 191324122 ps
CPU time 3.61 seconds
Started Jul 19 06:21:08 PM PDT 24
Finished Jul 19 06:21:12 PM PDT 24
Peak memory 224924 kb
Host smart-412bf71d-3423-497d-af1f-378fd011701d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147556361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1147556361
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3814407152
Short name T418
Test name
Test status
Simulation time 20258355 ps
CPU time 0.79 seconds
Started Jul 19 06:20:58 PM PDT 24
Finished Jul 19 06:21:00 PM PDT 24
Peak memory 207080 kb
Host smart-3b212282-d1cc-41e4-923b-762fe27ed158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814407152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3814407152
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.894108607
Short name T855
Test name
Test status
Simulation time 7265978988 ps
CPU time 58.94 seconds
Started Jul 19 06:21:05 PM PDT 24
Finished Jul 19 06:22:04 PM PDT 24
Peak memory 251884 kb
Host smart-c8b345d3-15b1-4efd-9625-eabb276095fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894108607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.894108607
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3943649170
Short name T611
Test name
Test status
Simulation time 8019973211 ps
CPU time 51.98 seconds
Started Jul 19 06:21:05 PM PDT 24
Finished Jul 19 06:21:58 PM PDT 24
Peak memory 255192 kb
Host smart-18bd2af3-22ba-4aac-8c72-1da24de7e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943649170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3943649170
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1937939903
Short name T122
Test name
Test status
Simulation time 51678750484 ps
CPU time 108.99 seconds
Started Jul 19 06:21:03 PM PDT 24
Finished Jul 19 06:22:53 PM PDT 24
Peak memory 252112 kb
Host smart-0f0e0ff4-9869-44e5-9f98-12c2422907ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937939903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1937939903
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.97499504
Short name T153
Test name
Test status
Simulation time 61984199 ps
CPU time 2.8 seconds
Started Jul 19 06:21:04 PM PDT 24
Finished Jul 19 06:21:07 PM PDT 24
Peak memory 224884 kb
Host smart-6c68e84b-ad44-4602-9aa3-e6d0e2ac8548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97499504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.97499504
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3316591402
Short name T244
Test name
Test status
Simulation time 546746316 ps
CPU time 9.22 seconds
Started Jul 19 06:20:58 PM PDT 24
Finished Jul 19 06:21:08 PM PDT 24
Peak memory 224884 kb
Host smart-e8c7bbce-2a44-4a51-a167-9bfe1d3d2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316591402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3316591402
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4216939452
Short name T378
Test name
Test status
Simulation time 1923919447 ps
CPU time 10.63 seconds
Started Jul 19 06:21:03 PM PDT 24
Finished Jul 19 06:21:14 PM PDT 24
Peak memory 224852 kb
Host smart-9b12c17b-1465-4b7e-b4fb-fbdcf7fa779f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216939452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4216939452
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2997318915
Short name T728
Test name
Test status
Simulation time 75300340738 ps
CPU time 18.11 seconds
Started Jul 19 06:20:55 PM PDT 24
Finished Jul 19 06:21:14 PM PDT 24
Peak memory 224940 kb
Host smart-60195888-b073-416d-b04c-7bb95c9b1ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997318915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2997318915
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1853501212
Short name T247
Test name
Test status
Simulation time 77277770545 ps
CPU time 24.1 seconds
Started Jul 19 06:20:59 PM PDT 24
Finished Jul 19 06:21:24 PM PDT 24
Peak memory 233176 kb
Host smart-a2601e7a-1341-4276-b63f-4c22d939096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853501212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1853501212
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1928327246
Short name T814
Test name
Test status
Simulation time 252372276 ps
CPU time 6.13 seconds
Started Jul 19 06:21:04 PM PDT 24
Finished Jul 19 06:21:11 PM PDT 24
Peak memory 220828 kb
Host smart-4d66bdf5-deeb-4842-aff5-bc33bf707d2d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1928327246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1928327246
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2126968043
Short name T786
Test name
Test status
Simulation time 182323689 ps
CPU time 1.02 seconds
Started Jul 19 06:21:02 PM PDT 24
Finished Jul 19 06:21:04 PM PDT 24
Peak memory 208048 kb
Host smart-e0326529-d39e-46ec-92f8-fa58dfe9523a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126968043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2126968043
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4091126879
Short name T706
Test name
Test status
Simulation time 2594025296 ps
CPU time 26.28 seconds
Started Jul 19 06:20:58 PM PDT 24
Finished Jul 19 06:21:25 PM PDT 24
Peak memory 216740 kb
Host smart-f6e80d41-743a-446b-ab4a-974ffd41db71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091126879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4091126879
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2655174781
Short name T518
Test name
Test status
Simulation time 690673102 ps
CPU time 5.94 seconds
Started Jul 19 06:20:59 PM PDT 24
Finished Jul 19 06:21:06 PM PDT 24
Peak memory 216640 kb
Host smart-cfea5eb0-6655-4afc-b631-fd8304b99cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655174781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2655174781
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2970203548
Short name T805
Test name
Test status
Simulation time 122677594 ps
CPU time 2.01 seconds
Started Jul 19 06:20:58 PM PDT 24
Finished Jul 19 06:21:01 PM PDT 24
Peak memory 216640 kb
Host smart-ffd36a76-3fe7-4ac8-a48f-074d288c9947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970203548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2970203548
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3221191652
Short name T924
Test name
Test status
Simulation time 115280402 ps
CPU time 0.76 seconds
Started Jul 19 06:20:57 PM PDT 24
Finished Jul 19 06:20:59 PM PDT 24
Peak memory 206396 kb
Host smart-79f43296-d06b-41ba-898f-b3c9c0764812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221191652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3221191652
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.176281810
Short name T1010
Test name
Test status
Simulation time 1919166579 ps
CPU time 9.21 seconds
Started Jul 19 06:21:03 PM PDT 24
Finished Jul 19 06:21:13 PM PDT 24
Peak memory 233140 kb
Host smart-d5558f27-1708-40e3-ac16-45c953f93e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176281810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.176281810
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2686064326
Short name T534
Test name
Test status
Simulation time 13254793 ps
CPU time 0.73 seconds
Started Jul 19 06:21:11 PM PDT 24
Finished Jul 19 06:21:12 PM PDT 24
Peak memory 206296 kb
Host smart-9cb3d6b4-4959-427b-89a2-fc794bb2be5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686064326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2686064326
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2487212965
Short name T520
Test name
Test status
Simulation time 1993460269 ps
CPU time 11.19 seconds
Started Jul 19 06:21:14 PM PDT 24
Finished Jul 19 06:21:26 PM PDT 24
Peak memory 232908 kb
Host smart-31ca55a3-0d44-4399-83bc-58ab8e8c222b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487212965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2487212965
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3785275994
Short name T588
Test name
Test status
Simulation time 17541909 ps
CPU time 0.83 seconds
Started Jul 19 06:21:05 PM PDT 24
Finished Jul 19 06:21:07 PM PDT 24
Peak memory 207080 kb
Host smart-a01f703e-2a8b-478f-81c8-ce8ecbf1e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785275994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3785275994
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.295316895
Short name T835
Test name
Test status
Simulation time 16365172320 ps
CPU time 34.74 seconds
Started Jul 19 06:21:10 PM PDT 24
Finished Jul 19 06:21:45 PM PDT 24
Peak memory 236568 kb
Host smart-f2be8c72-ad2a-4660-9d05-59dca35a3380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295316895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.295316895
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2688656239
Short name T942
Test name
Test status
Simulation time 285214860113 ps
CPU time 428.64 seconds
Started Jul 19 06:21:09 PM PDT 24
Finished Jul 19 06:28:18 PM PDT 24
Peak memory 257800 kb
Host smart-f39bb270-de5f-4e4b-b986-20312dd88da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688656239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2688656239
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1807075140
Short name T699
Test name
Test status
Simulation time 10071681252 ps
CPU time 113.37 seconds
Started Jul 19 06:21:12 PM PDT 24
Finished Jul 19 06:23:06 PM PDT 24
Peak memory 256364 kb
Host smart-ff8ccc48-87c5-4efc-aa34-2a24e6298124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807075140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1807075140
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2655544777
Short name T621
Test name
Test status
Simulation time 196216455 ps
CPU time 3.48 seconds
Started Jul 19 06:21:14 PM PDT 24
Finished Jul 19 06:21:18 PM PDT 24
Peak memory 232824 kb
Host smart-db33bf51-b73f-475a-bc30-e28a4245bf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655544777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2655544777
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2103358539
Short name T634
Test name
Test status
Simulation time 35000212206 ps
CPU time 132.11 seconds
Started Jul 19 06:21:09 PM PDT 24
Finished Jul 19 06:23:22 PM PDT 24
Peak memory 249588 kb
Host smart-1d473fa1-1860-48c7-849f-512ea8a7843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103358539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2103358539
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1365333533
Short name T123
Test name
Test status
Simulation time 919245099 ps
CPU time 3.56 seconds
Started Jul 19 06:21:03 PM PDT 24
Finished Jul 19 06:21:08 PM PDT 24
Peak memory 233252 kb
Host smart-4bd292b3-ce68-460e-9193-f7481f7f28b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365333533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1365333533
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.767064266
Short name T725
Test name
Test status
Simulation time 22458431952 ps
CPU time 38.98 seconds
Started Jul 19 06:21:12 PM PDT 24
Finished Jul 19 06:21:52 PM PDT 24
Peak memory 237752 kb
Host smart-2786294c-f3e0-4050-aa7d-ce115a5d5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767064266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.767064266
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1820108935
Short name T178
Test name
Test status
Simulation time 1505679413 ps
CPU time 4.65 seconds
Started Jul 19 06:21:08 PM PDT 24
Finished Jul 19 06:21:13 PM PDT 24
Peak memory 233076 kb
Host smart-3b0c1d0f-5615-451a-88cd-cb71d3910d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820108935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1820108935
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.391645259
Short name T233
Test name
Test status
Simulation time 554637181 ps
CPU time 5.35 seconds
Started Jul 19 06:21:05 PM PDT 24
Finished Jul 19 06:21:11 PM PDT 24
Peak memory 233156 kb
Host smart-f9f5f790-0ebc-4d9a-b724-7debffe35af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391645259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.391645259
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3984055159
Short name T799
Test name
Test status
Simulation time 229914250 ps
CPU time 6.01 seconds
Started Jul 19 06:21:10 PM PDT 24
Finished Jul 19 06:21:17 PM PDT 24
Peak memory 222580 kb
Host smart-34a373a8-3f2d-4989-a9d6-a3e3f366f05f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3984055159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3984055159
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3356379758
Short name T598
Test name
Test status
Simulation time 32712981901 ps
CPU time 118.55 seconds
Started Jul 19 06:21:13 PM PDT 24
Finished Jul 19 06:23:13 PM PDT 24
Peak memory 233744 kb
Host smart-fad5792a-a05e-44a7-a4bb-b2778d28cecb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356379758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3356379758
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1836897768
Short name T692
Test name
Test status
Simulation time 7327202011 ps
CPU time 37.55 seconds
Started Jul 19 06:21:02 PM PDT 24
Finished Jul 19 06:21:40 PM PDT 24
Peak memory 216788 kb
Host smart-3564a169-6957-443a-9a94-c82718259fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836897768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1836897768
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.281871715
Short name T344
Test name
Test status
Simulation time 1437298035 ps
CPU time 6.55 seconds
Started Jul 19 06:21:03 PM PDT 24
Finished Jul 19 06:21:10 PM PDT 24
Peak memory 216656 kb
Host smart-3a62877f-d41e-4421-b028-870c8030eed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281871715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.281871715
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4054355926
Short name T639
Test name
Test status
Simulation time 177051572 ps
CPU time 1.67 seconds
Started Jul 19 06:21:04 PM PDT 24
Finished Jul 19 06:21:06 PM PDT 24
Peak memory 216624 kb
Host smart-4ac4040b-a088-4541-a622-4ae3121fcffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054355926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4054355926
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3980989339
Short name T808
Test name
Test status
Simulation time 54060706 ps
CPU time 0.74 seconds
Started Jul 19 06:21:08 PM PDT 24
Finished Jul 19 06:21:09 PM PDT 24
Peak memory 206412 kb
Host smart-4ccdc096-07a6-4e96-a7aa-6e0ce5d48ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980989339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3980989339
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1538324789
Short name T275
Test name
Test status
Simulation time 463151335 ps
CPU time 3.74 seconds
Started Jul 19 06:21:12 PM PDT 24
Finished Jul 19 06:21:16 PM PDT 24
Peak memory 224956 kb
Host smart-1e337ae9-fce5-4222-88f8-b69a2fa9b514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538324789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1538324789
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2625573638
Short name T777
Test name
Test status
Simulation time 39654360 ps
CPU time 0.74 seconds
Started Jul 19 06:21:18 PM PDT 24
Finished Jul 19 06:21:19 PM PDT 24
Peak memory 205964 kb
Host smart-0966d224-6a08-4ecd-b783-d9836f7cfcaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625573638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2625573638
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2326658230
Short name T388
Test name
Test status
Simulation time 553849720 ps
CPU time 2.92 seconds
Started Jul 19 06:21:12 PM PDT 24
Finished Jul 19 06:21:16 PM PDT 24
Peak memory 224804 kb
Host smart-e107d9ae-bd6d-40b5-a7e8-23f689bd0fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326658230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2326658230
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1081556515
Short name T517
Test name
Test status
Simulation time 29549055 ps
CPU time 0.77 seconds
Started Jul 19 06:21:09 PM PDT 24
Finished Jul 19 06:21:10 PM PDT 24
Peak memory 205988 kb
Host smart-c441ed62-7092-4458-b2c5-64b11598a6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081556515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1081556515
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1316771286
Short name T421
Test name
Test status
Simulation time 128096113 ps
CPU time 0.87 seconds
Started Jul 19 06:21:17 PM PDT 24
Finished Jul 19 06:21:19 PM PDT 24
Peak memory 216344 kb
Host smart-8ff52b65-69af-40fb-966c-2cce79218401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316771286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1316771286
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3581396391
Short name T314
Test name
Test status
Simulation time 3407560142 ps
CPU time 27.14 seconds
Started Jul 19 06:21:17 PM PDT 24
Finished Jul 19 06:21:45 PM PDT 24
Peak memory 217992 kb
Host smart-48050943-3157-427c-8c27-88b0edfe7402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581396391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3581396391
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3919905704
Short name T278
Test name
Test status
Simulation time 83023244991 ps
CPU time 165.2 seconds
Started Jul 19 06:21:16 PM PDT 24
Finished Jul 19 06:24:02 PM PDT 24
Peak memory 267076 kb
Host smart-2cad6d67-97d1-4a04-96b1-aed57de58fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919905704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3919905704
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1582726747
Short name T457
Test name
Test status
Simulation time 1995989365 ps
CPU time 8.82 seconds
Started Jul 19 06:21:11 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 239944 kb
Host smart-9dae4328-f7f1-4350-9fa9-d9fc6ec3bee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582726747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1582726747
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1757830796
Short name T223
Test name
Test status
Simulation time 1930491878 ps
CPU time 17.34 seconds
Started Jul 19 06:21:10 PM PDT 24
Finished Jul 19 06:21:28 PM PDT 24
Peak memory 233044 kb
Host smart-f58599ac-ba2b-429a-92a7-883b5b22a9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757830796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1757830796
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2019839094
Short name T124
Test name
Test status
Simulation time 12559706199 ps
CPU time 36.27 seconds
Started Jul 19 06:21:09 PM PDT 24
Finished Jul 19 06:21:46 PM PDT 24
Peak memory 233228 kb
Host smart-0e90e795-c19e-4878-9458-e5fce99c3771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019839094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2019839094
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2019770860
Short name T210
Test name
Test status
Simulation time 331983058 ps
CPU time 5.1 seconds
Started Jul 19 06:21:12 PM PDT 24
Finished Jul 19 06:21:18 PM PDT 24
Peak memory 224952 kb
Host smart-dc40e02d-4095-4df2-9006-37a439d2c4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019770860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2019770860
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3523004810
Short name T501
Test name
Test status
Simulation time 116793154 ps
CPU time 2.48 seconds
Started Jul 19 06:21:13 PM PDT 24
Finished Jul 19 06:21:16 PM PDT 24
Peak memory 224912 kb
Host smart-b687d3ce-e173-471c-897d-9b1a556d1faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523004810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3523004810
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.240315512
Short name T375
Test name
Test status
Simulation time 1217330753 ps
CPU time 3.58 seconds
Started Jul 19 06:21:18 PM PDT 24
Finished Jul 19 06:21:22 PM PDT 24
Peak memory 219320 kb
Host smart-984cf750-6546-47de-891c-b30980b4d839
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=240315512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.240315512
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1404203497
Short name T455
Test name
Test status
Simulation time 738846637 ps
CPU time 3.48 seconds
Started Jul 19 06:21:12 PM PDT 24
Finished Jul 19 06:21:16 PM PDT 24
Peak memory 216708 kb
Host smart-2c185e7b-540f-4d05-9e74-f2e4089f8ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404203497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1404203497
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2932775083
Short name T709
Test name
Test status
Simulation time 1688282530 ps
CPU time 9.96 seconds
Started Jul 19 06:21:11 PM PDT 24
Finished Jul 19 06:21:21 PM PDT 24
Peak memory 216636 kb
Host smart-c0b45ff4-df76-4024-9760-c4434e212fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932775083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2932775083
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3921578328
Short name T527
Test name
Test status
Simulation time 1194144639 ps
CPU time 2.42 seconds
Started Jul 19 06:21:10 PM PDT 24
Finished Jul 19 06:21:14 PM PDT 24
Peak memory 216644 kb
Host smart-d7da751b-dba0-40b5-9f57-3fc56bbd9b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921578328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3921578328
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.2258452206
Short name T324
Test name
Test status
Simulation time 93707943 ps
CPU time 0.98 seconds
Started Jul 19 06:21:09 PM PDT 24
Finished Jul 19 06:21:11 PM PDT 24
Peak memory 207444 kb
Host smart-6743c9df-8a8d-4ecd-a71a-1a02740ef73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258452206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.2258452206
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3501351181
Short name T486
Test name
Test status
Simulation time 2276337290 ps
CPU time 4.79 seconds
Started Jul 19 06:21:10 PM PDT 24
Finished Jul 19 06:21:16 PM PDT 24
Peak memory 224944 kb
Host smart-d5f99761-4a55-410d-9854-3c2fef1ce0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501351181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3501351181
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3725840877
Short name T493
Test name
Test status
Simulation time 18286183 ps
CPU time 0.72 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:21:27 PM PDT 24
Peak memory 205960 kb
Host smart-3ecab9cf-72c3-4d34-aebe-1b6fddefb202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725840877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3725840877
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2493171421
Short name T548
Test name
Test status
Simulation time 3638133606 ps
CPU time 5.12 seconds
Started Jul 19 06:21:18 PM PDT 24
Finished Jul 19 06:21:24 PM PDT 24
Peak memory 225016 kb
Host smart-adeeefe4-56e5-4a6d-9fb6-9e2c5dd63e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493171421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2493171421
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2046217379
Short name T916
Test name
Test status
Simulation time 93504676 ps
CPU time 0.76 seconds
Started Jul 19 06:21:19 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 206032 kb
Host smart-983390a3-a987-46a9-b5e9-3544b2cabe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046217379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2046217379
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1383976430
Short name T738
Test name
Test status
Simulation time 5746390416 ps
CPU time 74.69 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:22:39 PM PDT 24
Peak memory 253460 kb
Host smart-dc604474-d52f-4281-9fc2-eb6edd0d0958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383976430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1383976430
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.820392898
Short name T934
Test name
Test status
Simulation time 40177939946 ps
CPU time 84.18 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:22:51 PM PDT 24
Peak memory 249656 kb
Host smart-fa859e46-49b5-4adc-8654-6f092eb9309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820392898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.820392898
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.1924971547
Short name T861
Test name
Test status
Simulation time 1277483899 ps
CPU time 16.63 seconds
Started Jul 19 06:21:15 PM PDT 24
Finished Jul 19 06:21:32 PM PDT 24
Peak memory 249496 kb
Host smart-7290dc9b-5f36-4d09-91f2-ab1353be856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924971547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1924971547
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2652490901
Short name T180
Test name
Test status
Simulation time 21237746366 ps
CPU time 141.12 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:23:48 PM PDT 24
Peak memory 255708 kb
Host smart-617ca69e-e5b8-4134-82c7-43ce80b5f22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652490901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2652490901
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.4076752779
Short name T596
Test name
Test status
Simulation time 333730595 ps
CPU time 2.51 seconds
Started Jul 19 06:21:17 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 227136 kb
Host smart-ee8ba1c7-67a9-41ff-a3d1-3c0874717377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076752779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.4076752779
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.826175269
Short name T923
Test name
Test status
Simulation time 3410341258 ps
CPU time 15.51 seconds
Started Jul 19 06:21:16 PM PDT 24
Finished Jul 19 06:21:32 PM PDT 24
Peak memory 241368 kb
Host smart-d049b02e-15b7-4cf2-bc42-d2b625757f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826175269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.826175269
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2417838846
Short name T289
Test name
Test status
Simulation time 706067693 ps
CPU time 5.11 seconds
Started Jul 19 06:21:15 PM PDT 24
Finished Jul 19 06:21:21 PM PDT 24
Peak memory 224888 kb
Host smart-86567cfc-48d0-47f7-b13b-cd1ea4144dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417838846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2417838846
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.716431155
Short name T539
Test name
Test status
Simulation time 2103969383 ps
CPU time 7.29 seconds
Started Jul 19 06:21:15 PM PDT 24
Finished Jul 19 06:21:23 PM PDT 24
Peak memory 224896 kb
Host smart-3c74ad62-43b6-49e0-a163-5e25e6fb12c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716431155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.716431155
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1784291222
Short name T836
Test name
Test status
Simulation time 917483740 ps
CPU time 4.82 seconds
Started Jul 19 06:21:27 PM PDT 24
Finished Jul 19 06:21:33 PM PDT 24
Peak memory 220300 kb
Host smart-51c4d896-0c0a-445a-ab2f-5dc9db1d406e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1784291222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1784291222
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2396012927
Short name T266
Test name
Test status
Simulation time 22297892425 ps
CPU time 124.12 seconds
Started Jul 19 06:21:26 PM PDT 24
Finished Jul 19 06:23:31 PM PDT 24
Peak memory 266012 kb
Host smart-b8565aa9-7632-4f67-bce5-f32975879ee1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396012927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2396012927
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.2794133586
Short name T931
Test name
Test status
Simulation time 833265153 ps
CPU time 13.31 seconds
Started Jul 19 06:21:16 PM PDT 24
Finished Jul 19 06:21:30 PM PDT 24
Peak memory 219708 kb
Host smart-321ab521-ff4c-4b3e-8ac1-533263fa1f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794133586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.2794133586
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2326975847
Short name T72
Test name
Test status
Simulation time 3469424656 ps
CPU time 2.37 seconds
Started Jul 19 06:21:17 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 208416 kb
Host smart-511ee8e0-6465-4471-8024-1ed4f53b4303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326975847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2326975847
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3253504147
Short name T397
Test name
Test status
Simulation time 337799701 ps
CPU time 5.83 seconds
Started Jul 19 06:21:18 PM PDT 24
Finished Jul 19 06:21:25 PM PDT 24
Peak memory 216696 kb
Host smart-da4a99ac-6963-4622-804c-a9b3750ba006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253504147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3253504147
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3100316913
Short name T361
Test name
Test status
Simulation time 41304109 ps
CPU time 0.74 seconds
Started Jul 19 06:21:19 PM PDT 24
Finished Jul 19 06:21:20 PM PDT 24
Peak memory 206416 kb
Host smart-d16b48d8-95f8-4c8f-a68e-906e260f4335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100316913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3100316913
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1745523502
Short name T703
Test name
Test status
Simulation time 81314753880 ps
CPU time 36.48 seconds
Started Jul 19 06:21:16 PM PDT 24
Finished Jul 19 06:21:53 PM PDT 24
Peak memory 233200 kb
Host smart-55e7b6f4-c798-4d34-a072-88d2d98d1554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745523502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1745523502
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2725821105
Short name T438
Test name
Test status
Simulation time 53995080 ps
CPU time 0.8 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:21:35 PM PDT 24
Peak memory 205352 kb
Host smart-c66f635b-c540-49d2-b6a3-f01d29b61ccf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725821105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2725821105
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4119096133
Short name T174
Test name
Test status
Simulation time 116255436 ps
CPU time 2.85 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:21:29 PM PDT 24
Peak memory 233084 kb
Host smart-65fc6af5-be26-4152-80d9-187450ffb457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119096133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4119096133
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2591474169
Short name T972
Test name
Test status
Simulation time 19858771 ps
CPU time 0.73 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:21:25 PM PDT 24
Peak memory 207092 kb
Host smart-2160e37f-5cc3-4c4e-932f-cae06dbc494d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591474169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2591474169
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2341227612
Short name T571
Test name
Test status
Simulation time 24589984742 ps
CPU time 81.74 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:22:47 PM PDT 24
Peak memory 254028 kb
Host smart-add21438-7c5d-444d-93ba-3ba58f60bdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341227612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2341227612
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3191368875
Short name T389
Test name
Test status
Simulation time 21328054188 ps
CPU time 224.78 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:25:11 PM PDT 24
Peak memory 254276 kb
Host smart-464deb97-0325-47e3-be0a-174459d76aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191368875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3191368875
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3209601407
Short name T292
Test name
Test status
Simulation time 4490874518 ps
CPU time 70.43 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:22:45 PM PDT 24
Peak memory 249604 kb
Host smart-165d9841-c278-4e2a-8c28-4f68b9fc465a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209601407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3209601407
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3947371412
Short name T80
Test name
Test status
Simulation time 607952313 ps
CPU time 5.3 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:21:31 PM PDT 24
Peak memory 233132 kb
Host smart-851f7486-6e19-4098-9cd2-dd8c78ae3fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947371412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3947371412
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2595084353
Short name T714
Test name
Test status
Simulation time 45436097961 ps
CPU time 104.16 seconds
Started Jul 19 06:21:26 PM PDT 24
Finished Jul 19 06:23:12 PM PDT 24
Peak memory 249596 kb
Host smart-04e3b449-4a05-488e-afab-b754a0ce9c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595084353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2595084353
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1277462731
Short name T842
Test name
Test status
Simulation time 186356230 ps
CPU time 3.46 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:21:30 PM PDT 24
Peak memory 224836 kb
Host smart-9583271f-80e2-4ea0-a530-0927e9ea43e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277462731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1277462731
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.985192910
Short name T427
Test name
Test status
Simulation time 598128527 ps
CPU time 4.45 seconds
Started Jul 19 06:21:26 PM PDT 24
Finished Jul 19 06:21:32 PM PDT 24
Peak memory 224908 kb
Host smart-097f9d5b-7715-413a-b01b-7c2ff32749b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985192910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.985192910
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1391658328
Short name T979
Test name
Test status
Simulation time 4461979773 ps
CPU time 12.26 seconds
Started Jul 19 06:21:26 PM PDT 24
Finished Jul 19 06:21:40 PM PDT 24
Peak memory 224912 kb
Host smart-98f20525-78e4-47b8-bdbc-676ef35746ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391658328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1391658328
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3296425210
Short name T719
Test name
Test status
Simulation time 642229797 ps
CPU time 4.39 seconds
Started Jul 19 06:21:29 PM PDT 24
Finished Jul 19 06:21:34 PM PDT 24
Peak memory 224940 kb
Host smart-d26697ec-cc91-49ef-ad70-821808c51ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296425210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3296425210
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3326661652
Short name T675
Test name
Test status
Simulation time 650741467 ps
CPU time 4.31 seconds
Started Jul 19 06:21:29 PM PDT 24
Finished Jul 19 06:21:34 PM PDT 24
Peak memory 223000 kb
Host smart-686afd55-e588-42c4-925a-d79c5d5b44f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3326661652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3326661652
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1046701156
Short name T149
Test name
Test status
Simulation time 338840110729 ps
CPU time 420.14 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:28:35 PM PDT 24
Peak memory 255636 kb
Host smart-60e3ad95-f3bd-4178-ab33-495c4fbb58e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046701156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1046701156
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1512578453
Short name T710
Test name
Test status
Simulation time 28098070272 ps
CPU time 38.05 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:22:03 PM PDT 24
Peak memory 216688 kb
Host smart-d7a5fce5-fc16-4b10-a4c6-adaf4b71483a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512578453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1512578453
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3317469973
Short name T411
Test name
Test status
Simulation time 10482596705 ps
CPU time 8.76 seconds
Started Jul 19 06:21:27 PM PDT 24
Finished Jul 19 06:21:37 PM PDT 24
Peak memory 216996 kb
Host smart-c007399c-5211-43e7-a4a5-8072b635e41d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317469973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3317469973
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.741390592
Short name T583
Test name
Test status
Simulation time 30635492 ps
CPU time 0.82 seconds
Started Jul 19 06:21:27 PM PDT 24
Finished Jul 19 06:21:29 PM PDT 24
Peak memory 206440 kb
Host smart-168ed49d-fdee-4557-8dc1-82145df3ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741390592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.741390592
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3744254763
Short name T330
Test name
Test status
Simulation time 39636840 ps
CPU time 0.71 seconds
Started Jul 19 06:21:24 PM PDT 24
Finished Jul 19 06:21:26 PM PDT 24
Peak memory 206116 kb
Host smart-7f722ccb-1005-4f3d-8f57-d2e60c5aa043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744254763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3744254763
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.4014318924
Short name T89
Test name
Test status
Simulation time 27845469064 ps
CPU time 31.97 seconds
Started Jul 19 06:21:25 PM PDT 24
Finished Jul 19 06:21:59 PM PDT 24
Peak memory 233132 kb
Host smart-54c3658e-8213-4cc1-8698-e1780b118d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014318924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.4014318924
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1371512434
Short name T921
Test name
Test status
Simulation time 38281230 ps
CPU time 0.72 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:33 PM PDT 24
Peak memory 205928 kb
Host smart-b0873868-c976-4a2d-87f4-67e2b38723a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371512434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1371512434
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2478711124
Short name T749
Test name
Test status
Simulation time 240207243 ps
CPU time 4.81 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:37 PM PDT 24
Peak memory 233120 kb
Host smart-2d99cec1-a484-4f9e-a267-84e854896143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478711124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2478711124
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4049234902
Short name T510
Test name
Test status
Simulation time 19002880 ps
CPU time 0.82 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:21:35 PM PDT 24
Peak memory 207236 kb
Host smart-1a3a0f5c-542f-4269-816b-ba3667e69fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049234902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4049234902
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1149284723
Short name T664
Test name
Test status
Simulation time 4114922584 ps
CPU time 73.23 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:22:44 PM PDT 24
Peak memory 254748 kb
Host smart-937eeed5-c67a-4e2a-b1de-7f8049940e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149284723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1149284723
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4269582257
Short name T754
Test name
Test status
Simulation time 13290149524 ps
CPU time 156.06 seconds
Started Jul 19 06:21:34 PM PDT 24
Finished Jul 19 06:24:11 PM PDT 24
Peak memory 252852 kb
Host smart-74c266d5-4ccc-450b-b418-bdd8d1d34a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269582257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4269582257
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.924911312
Short name T46
Test name
Test status
Simulation time 30588361886 ps
CPU time 64 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:22:37 PM PDT 24
Peak memory 233180 kb
Host smart-8e18c935-c4cb-4a19-becf-9326f4093d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924911312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.924911312
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.2317491039
Short name T305
Test name
Test status
Simulation time 654152162 ps
CPU time 7.67 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:21:42 PM PDT 24
Peak memory 234576 kb
Host smart-2ebcc3c8-c42d-486d-a0a8-c4c8135988d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317491039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2317491039
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.857482574
Short name T982
Test name
Test status
Simulation time 5320089351 ps
CPU time 21.53 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:21:56 PM PDT 24
Peak memory 236564 kb
Host smart-f8dba197-9391-4f91-bfa9-1e9fc9a7882b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857482574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.857482574
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3090109621
Short name T1008
Test name
Test status
Simulation time 714906908 ps
CPU time 3.26 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:35 PM PDT 24
Peak memory 224956 kb
Host smart-282ec6bc-6339-4967-a4a9-e7cc0b833df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090109621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3090109621
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.105473506
Short name T954
Test name
Test status
Simulation time 5855185863 ps
CPU time 36.85 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:22:10 PM PDT 24
Peak memory 240084 kb
Host smart-8a20aedb-385d-4ebc-8b36-d64ec194136e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105473506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.105473506
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2373884056
Short name T900
Test name
Test status
Simulation time 16391581553 ps
CPU time 24.45 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:56 PM PDT 24
Peak memory 233184 kb
Host smart-8e492fe0-edc7-4ea8-a3cb-158bb8b19742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373884056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2373884056
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.799373060
Short name T873
Test name
Test status
Simulation time 2493324170 ps
CPU time 6.86 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:21:41 PM PDT 24
Peak memory 225000 kb
Host smart-42eebe71-c3e2-4786-9173-58515948bfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799373060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.799373060
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1753192610
Short name T843
Test name
Test status
Simulation time 812948387 ps
CPU time 6.68 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:39 PM PDT 24
Peak memory 220236 kb
Host smart-b43dcebf-5722-45b2-bdd8-cfec97c55795
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753192610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1753192610
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.397497773
Short name T390
Test name
Test status
Simulation time 2726584177 ps
CPU time 32.09 seconds
Started Jul 19 06:21:34 PM PDT 24
Finished Jul 19 06:22:07 PM PDT 24
Peak memory 216912 kb
Host smart-f0eabe45-71b4-46f4-897b-cdd79833d4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397497773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.397497773
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2173183295
Short name T521
Test name
Test status
Simulation time 5200882724 ps
CPU time 15.5 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:21:50 PM PDT 24
Peak memory 216688 kb
Host smart-a28681b0-b3d4-4acb-9ae8-0c84d5ead988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173183295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2173183295
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1853508161
Short name T403
Test name
Test status
Simulation time 31799148 ps
CPU time 0.7 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:21:34 PM PDT 24
Peak memory 206132 kb
Host smart-235aa9d3-c5c3-4fe5-a70d-19203798b550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853508161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1853508161
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4012202390
Short name T793
Test name
Test status
Simulation time 46707328 ps
CPU time 0.91 seconds
Started Jul 19 06:21:33 PM PDT 24
Finished Jul 19 06:21:35 PM PDT 24
Peak memory 206664 kb
Host smart-e2a20871-0d74-4b34-be2c-5ce1879d4af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012202390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4012202390
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.524049721
Short name T505
Test name
Test status
Simulation time 1084856428 ps
CPU time 7.36 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:21:41 PM PDT 24
Peak memory 233120 kb
Host smart-076ab26a-8ac7-4348-9245-e609bdf52032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524049721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.524049721
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1061777550
Short name T926
Test name
Test status
Simulation time 12447254 ps
CPU time 0.72 seconds
Started Jul 19 06:21:35 PM PDT 24
Finished Jul 19 06:21:36 PM PDT 24
Peak memory 205908 kb
Host smart-ced26cf2-2612-424f-bd4d-d1777dae1f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061777550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1061777550
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.91844839
Short name T704
Test name
Test status
Simulation time 216329904 ps
CPU time 2.13 seconds
Started Jul 19 06:21:37 PM PDT 24
Finished Jul 19 06:21:40 PM PDT 24
Peak memory 223596 kb
Host smart-65c19a05-365e-4f4c-97d4-d765cf7d104b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91844839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.91844839
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1820382206
Short name T53
Test name
Test status
Simulation time 15147036 ps
CPU time 0.81 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:21:34 PM PDT 24
Peak memory 207056 kb
Host smart-1dd69eea-0a34-4870-a973-fa3242e0ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820382206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1820382206
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3260713028
Short name T187
Test name
Test status
Simulation time 28044168612 ps
CPU time 70.64 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:22:50 PM PDT 24
Peak memory 256132 kb
Host smart-3d3cc085-1607-407e-9a7f-da2a4f76756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260713028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3260713028
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2786181482
Short name T260
Test name
Test status
Simulation time 9237544113 ps
CPU time 103.33 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:23:23 PM PDT 24
Peak memory 261932 kb
Host smart-87c317df-237d-4a17-b25c-0d41b2134bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786181482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2786181482
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2116156105
Short name T626
Test name
Test status
Simulation time 539158501 ps
CPU time 3.64 seconds
Started Jul 19 06:21:39 PM PDT 24
Finished Jul 19 06:21:43 PM PDT 24
Peak memory 224968 kb
Host smart-0eebbd71-6a98-45a4-bf81-346da12823c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116156105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2116156105
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1397147145
Short name T524
Test name
Test status
Simulation time 45753077814 ps
CPU time 87.63 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:23:07 PM PDT 24
Peak memory 241800 kb
Host smart-1a47f6d4-8b30-4b94-bb2e-f2c4d14e2cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397147145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1397147145
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2917329871
Short name T645
Test name
Test status
Simulation time 1066481391 ps
CPU time 5.38 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:37 PM PDT 24
Peak memory 224808 kb
Host smart-02ea726d-cbcc-4b1a-ac8e-ff4ae385be91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917329871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2917329871
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2968872301
Short name T500
Test name
Test status
Simulation time 318243336 ps
CPU time 3.54 seconds
Started Jul 19 06:21:30 PM PDT 24
Finished Jul 19 06:21:34 PM PDT 24
Peak memory 233100 kb
Host smart-56bf5f81-b1f3-4a4d-9cdc-14175967f0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968872301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2968872301
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2621872441
Short name T295
Test name
Test status
Simulation time 3210579105 ps
CPU time 7.65 seconds
Started Jul 19 06:21:34 PM PDT 24
Finished Jul 19 06:21:43 PM PDT 24
Peak memory 234252 kb
Host smart-3559fecf-ebe5-4693-9516-9a22a609aa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621872441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2621872441
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2064964370
Short name T914
Test name
Test status
Simulation time 5735968152 ps
CPU time 6.56 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:21:39 PM PDT 24
Peak memory 225132 kb
Host smart-766f8d09-88ad-4a00-9c60-670abeb45363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064964370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2064964370
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1387000758
Short name T896
Test name
Test status
Simulation time 1410995482 ps
CPU time 5.4 seconds
Started Jul 19 06:21:41 PM PDT 24
Finished Jul 19 06:21:47 PM PDT 24
Peak memory 222072 kb
Host smart-e84d6e04-c000-44e2-b33b-15bd0102b725
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1387000758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1387000758
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.458879198
Short name T958
Test name
Test status
Simulation time 7221679213 ps
CPU time 132.47 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:23:51 PM PDT 24
Peak memory 266024 kb
Host smart-305e6883-c708-44a6-b8a8-bb012e10dfd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458879198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.458879198
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3560493965
Short name T708
Test name
Test status
Simulation time 14415726075 ps
CPU time 39.05 seconds
Started Jul 19 06:21:32 PM PDT 24
Finished Jul 19 06:22:12 PM PDT 24
Peak memory 216672 kb
Host smart-17ae0e5a-b554-48f6-ae2b-c7bceb07544d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560493965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3560493965
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1580308012
Short name T649
Test name
Test status
Simulation time 16180139773 ps
CPU time 13.71 seconds
Started Jul 19 06:21:30 PM PDT 24
Finished Jul 19 06:21:45 PM PDT 24
Peak memory 216716 kb
Host smart-8ea0a838-c5e1-4ee1-b361-5bebdfbf2045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580308012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1580308012
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2129059360
Short name T402
Test name
Test status
Simulation time 136138260 ps
CPU time 0.98 seconds
Started Jul 19 06:21:34 PM PDT 24
Finished Jul 19 06:21:36 PM PDT 24
Peak memory 207476 kb
Host smart-280e615c-465b-41b7-be29-c59d3d6b4dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129059360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2129059360
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3512601330
Short name T915
Test name
Test status
Simulation time 168811284 ps
CPU time 0.84 seconds
Started Jul 19 06:21:31 PM PDT 24
Finished Jul 19 06:21:33 PM PDT 24
Peak memory 206460 kb
Host smart-cb5f6738-037d-49cd-9260-a286cbd62cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512601330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3512601330
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3749610664
Short name T519
Test name
Test status
Simulation time 910240090 ps
CPU time 9.71 seconds
Started Jul 19 06:21:34 PM PDT 24
Finished Jul 19 06:21:45 PM PDT 24
Peak memory 240536 kb
Host smart-4aec1ad8-08b3-4fe3-a2b1-57e6be2e4942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749610664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3749610664
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1341228088
Short name T883
Test name
Test status
Simulation time 19169071 ps
CPU time 0.72 seconds
Started Jul 19 06:21:45 PM PDT 24
Finished Jul 19 06:21:47 PM PDT 24
Peak memory 205912 kb
Host smart-569f78f1-0f97-49b9-9b9b-b0ab420a967f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341228088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1341228088
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3426084403
Short name T401
Test name
Test status
Simulation time 776646456 ps
CPU time 3.25 seconds
Started Jul 19 06:21:37 PM PDT 24
Finished Jul 19 06:21:41 PM PDT 24
Peak memory 224864 kb
Host smart-1bff4c81-1832-4196-8f2d-d0c4b7492657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426084403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3426084403
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1139346677
Short name T960
Test name
Test status
Simulation time 65190260 ps
CPU time 0.8 seconds
Started Jul 19 06:21:37 PM PDT 24
Finished Jul 19 06:21:38 PM PDT 24
Peak memory 207068 kb
Host smart-cabd116a-663e-4667-9def-386a78eb4891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139346677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1139346677
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3510626725
Short name T387
Test name
Test status
Simulation time 6988059233 ps
CPU time 36.49 seconds
Started Jul 19 06:21:43 PM PDT 24
Finished Jul 19 06:22:21 PM PDT 24
Peak memory 240180 kb
Host smart-b04ed2e0-a940-4d6a-8e8e-6ca83b0da19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510626725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3510626725
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.3814368714
Short name T740
Test name
Test status
Simulation time 20068153727 ps
CPU time 146 seconds
Started Jul 19 06:21:43 PM PDT 24
Finished Jul 19 06:24:10 PM PDT 24
Peak memory 249784 kb
Host smart-9accc6d1-2609-4c9f-89e6-ebf3f689063b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814368714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.3814368714
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.4033941866
Short name T31
Test name
Test status
Simulation time 56753208623 ps
CPU time 510.41 seconds
Started Jul 19 06:21:43 PM PDT 24
Finished Jul 19 06:30:13 PM PDT 24
Peak memory 257840 kb
Host smart-978eb4d7-d066-4edd-a55f-e9276648251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033941866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.4033941866
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3974066030
Short name T837
Test name
Test status
Simulation time 3048674281 ps
CPU time 17.66 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:21:57 PM PDT 24
Peak memory 235456 kb
Host smart-e6be4724-9800-4a1f-ae60-dc2159d8c980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974066030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3974066030
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.2640020118
Short name T360
Test name
Test status
Simulation time 69964423 ps
CPU time 0.73 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:21:40 PM PDT 24
Peak memory 216248 kb
Host smart-a850bcc9-8d45-46af-858d-8f4c2b734d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640020118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.2640020118
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2571023136
Short name T533
Test name
Test status
Simulation time 1282808389 ps
CPU time 5.45 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:21:44 PM PDT 24
Peak memory 224860 kb
Host smart-d24b6244-f844-44ee-a7ea-fd5891a80c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571023136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2571023136
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1444291246
Short name T751
Test name
Test status
Simulation time 722665513 ps
CPU time 12.07 seconds
Started Jul 19 06:21:40 PM PDT 24
Finished Jul 19 06:21:53 PM PDT 24
Peak memory 241080 kb
Host smart-9b719ab2-0050-41c2-8db1-23748aad189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444291246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1444291246
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1996267016
Short name T182
Test name
Test status
Simulation time 924112595 ps
CPU time 4.97 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:21:44 PM PDT 24
Peak memory 233140 kb
Host smart-96fb9028-5d83-4a7b-ad57-fe86bafaf6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996267016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1996267016
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1838329314
Short name T249
Test name
Test status
Simulation time 2072910321 ps
CPU time 9.38 seconds
Started Jul 19 06:21:37 PM PDT 24
Finished Jul 19 06:21:48 PM PDT 24
Peak memory 233164 kb
Host smart-684b9d83-38dd-4946-be8e-f2ee4392420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838329314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1838329314
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4047294086
Short name T721
Test name
Test status
Simulation time 380472516 ps
CPU time 4.17 seconds
Started Jul 19 06:21:46 PM PDT 24
Finished Jul 19 06:21:50 PM PDT 24
Peak memory 223412 kb
Host smart-e0018e1b-d0c1-4a45-84aa-6b9cbad3e309
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4047294086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4047294086
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2982989318
Short name T976
Test name
Test status
Simulation time 40945095119 ps
CPU time 281.4 seconds
Started Jul 19 06:21:46 PM PDT 24
Finished Jul 19 06:26:28 PM PDT 24
Peak memory 257824 kb
Host smart-56b2655e-1d53-4916-8f8c-0b7340774d0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982989318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2982989318
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.554533448
Short name T391
Test name
Test status
Simulation time 20378996240 ps
CPU time 33.28 seconds
Started Jul 19 06:21:38 PM PDT 24
Finished Jul 19 06:22:12 PM PDT 24
Peak memory 216716 kb
Host smart-e7d5993c-c8f1-46b1-95ae-5f3330aa53ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554533448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.554533448
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3867524731
Short name T503
Test name
Test status
Simulation time 1081733461 ps
CPU time 2.37 seconds
Started Jul 19 06:21:41 PM PDT 24
Finished Jul 19 06:21:44 PM PDT 24
Peak memory 216716 kb
Host smart-83930a41-06d7-431a-9887-7cc31e8387c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867524731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3867524731
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2140388640
Short name T491
Test name
Test status
Simulation time 68098825 ps
CPU time 2.18 seconds
Started Jul 19 06:21:40 PM PDT 24
Finished Jul 19 06:21:43 PM PDT 24
Peak memory 216724 kb
Host smart-8c5aab11-2c88-422a-bf16-bfcfbf9a78bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140388640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2140388640
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3268524076
Short name T778
Test name
Test status
Simulation time 154678424 ps
CPU time 0.94 seconds
Started Jul 19 06:21:36 PM PDT 24
Finished Jul 19 06:21:38 PM PDT 24
Peak memory 206364 kb
Host smart-f650a079-c2ca-4a03-8b9f-9c885f425e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268524076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3268524076
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3139916785
Short name T475
Test name
Test status
Simulation time 2311739049 ps
CPU time 10.36 seconds
Started Jul 19 06:21:41 PM PDT 24
Finished Jul 19 06:21:52 PM PDT 24
Peak memory 225028 kb
Host smart-2b055fa5-9d02-467b-85f5-b4d5ee7d051e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139916785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3139916785
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.1658755040
Short name T783
Test name
Test status
Simulation time 15101530 ps
CPU time 0.75 seconds
Started Jul 19 06:16:22 PM PDT 24
Finished Jul 19 06:16:23 PM PDT 24
Peak memory 205912 kb
Host smart-86866c5a-084f-48a7-8ee1-737001674515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658755040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.1
658755040
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3139836228
Short name T170
Test name
Test status
Simulation time 32766667 ps
CPU time 2.16 seconds
Started Jul 19 06:16:21 PM PDT 24
Finished Jul 19 06:16:24 PM PDT 24
Peak memory 224904 kb
Host smart-e14f2473-e74d-439f-b90f-64d5cbb90f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139836228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3139836228
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2064011565
Short name T329
Test name
Test status
Simulation time 22543226 ps
CPU time 0.75 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:16:10 PM PDT 24
Peak memory 207084 kb
Host smart-187995b6-212c-413f-b653-f41aa101d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064011565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2064011565
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.217177253
Short name T630
Test name
Test status
Simulation time 75443380038 ps
CPU time 251.45 seconds
Started Jul 19 06:16:22 PM PDT 24
Finished Jul 19 06:20:34 PM PDT 24
Peak memory 241564 kb
Host smart-f0f78039-0316-4bc1-b507-890851d59735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217177253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.217177253
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2327602249
Short name T281
Test name
Test status
Simulation time 355171977296 ps
CPU time 781.96 seconds
Started Jul 19 06:16:23 PM PDT 24
Finished Jul 19 06:29:26 PM PDT 24
Peak memory 257208 kb
Host smart-8a1a8d3a-db98-42b4-b644-b041fdb96907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327602249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2327602249
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3989750907
Short name T789
Test name
Test status
Simulation time 198975370 ps
CPU time 3.5 seconds
Started Jul 19 06:16:21 PM PDT 24
Finished Jul 19 06:16:25 PM PDT 24
Peak memory 241284 kb
Host smart-b5459624-76c5-4a85-90a5-57d2105b7179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989750907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3989750907
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2914937163
Short name T989
Test name
Test status
Simulation time 1916862372 ps
CPU time 12.34 seconds
Started Jul 19 06:16:21 PM PDT 24
Finished Jul 19 06:16:34 PM PDT 24
Peak memory 238152 kb
Host smart-2bff03e3-4fc0-4bbf-88e6-98ecdc6d2be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914937163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2914937163
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.332025021
Short name T33
Test name
Test status
Simulation time 110203734 ps
CPU time 4.08 seconds
Started Jul 19 06:16:23 PM PDT 24
Finished Jul 19 06:16:27 PM PDT 24
Peak memory 233116 kb
Host smart-bf7a4da5-689c-4516-9db6-21ed2964af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332025021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.332025021
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1885867681
Short name T550
Test name
Test status
Simulation time 436974287 ps
CPU time 2.96 seconds
Started Jul 19 06:16:22 PM PDT 24
Finished Jul 19 06:16:25 PM PDT 24
Peak memory 233120 kb
Host smart-8c623e43-7dbe-4742-a7b9-1fcb7a7ad0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885867681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1885867681
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.139634150
Short name T997
Test name
Test status
Simulation time 5581588398 ps
CPU time 6.31 seconds
Started Jul 19 06:16:24 PM PDT 24
Finished Jul 19 06:16:31 PM PDT 24
Peak memory 225020 kb
Host smart-510bbb19-675b-4983-92f9-6a953a69cd4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139634150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
139634150
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.341040875
Short name T990
Test name
Test status
Simulation time 2286180726 ps
CPU time 17.15 seconds
Started Jul 19 06:16:11 PM PDT 24
Finished Jul 19 06:16:29 PM PDT 24
Peak memory 234508 kb
Host smart-d1d4faa9-bc84-4b30-a4b8-d933614f3222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341040875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.341040875
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1189198542
Short name T858
Test name
Test status
Simulation time 1533183685 ps
CPU time 6.39 seconds
Started Jul 19 06:16:25 PM PDT 24
Finished Jul 19 06:16:32 PM PDT 24
Peak memory 223620 kb
Host smart-0e3708e4-50c7-4966-bc82-199fe235ca83
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1189198542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1189198542
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2706126082
Short name T465
Test name
Test status
Simulation time 19128600067 ps
CPU time 25.68 seconds
Started Jul 19 06:16:22 PM PDT 24
Finished Jul 19 06:16:48 PM PDT 24
Peak memory 241476 kb
Host smart-fd1a686c-b2fb-448e-9a08-0a7bd4e3cb8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706126082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2706126082
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.512530556
Short name T904
Test name
Test status
Simulation time 18823844568 ps
CPU time 26.33 seconds
Started Jul 19 06:16:10 PM PDT 24
Finished Jul 19 06:16:37 PM PDT 24
Peak memory 216780 kb
Host smart-ea938947-3bc3-4973-b727-2b2bac47525d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512530556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.512530556
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2005529630
Short name T325
Test name
Test status
Simulation time 20271546457 ps
CPU time 14.17 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:16:24 PM PDT 24
Peak memory 216760 kb
Host smart-7f1c88d1-bb9c-4372-9268-ee4783dba797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005529630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2005529630
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.56466584
Short name T380
Test name
Test status
Simulation time 29594077 ps
CPU time 1.44 seconds
Started Jul 19 06:16:08 PM PDT 24
Finished Jul 19 06:16:10 PM PDT 24
Peak memory 216624 kb
Host smart-ef125187-45ba-44f0-bad1-3bbb2c09c670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56466584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.56466584
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1801400470
Short name T469
Test name
Test status
Simulation time 18681771 ps
CPU time 0.71 seconds
Started Jul 19 06:16:09 PM PDT 24
Finished Jul 19 06:16:10 PM PDT 24
Peak memory 206132 kb
Host smart-7aaccb4d-6f6b-4ba0-b62a-1c694b35f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801400470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1801400470
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1804620990
Short name T722
Test name
Test status
Simulation time 18085328329 ps
CPU time 16.86 seconds
Started Jul 19 06:16:23 PM PDT 24
Finished Jul 19 06:16:40 PM PDT 24
Peak memory 233172 kb
Host smart-4d0b968e-ba00-433f-a162-e3cd97167074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804620990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1804620990
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.552853277
Short name T753
Test name
Test status
Simulation time 35856293 ps
CPU time 0.7 seconds
Started Jul 19 06:16:27 PM PDT 24
Finished Jul 19 06:16:28 PM PDT 24
Peak memory 205952 kb
Host smart-924ad0a7-b603-4ddf-b84e-1a412063d1a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552853277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.552853277
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1648703146
Short name T127
Test name
Test status
Simulation time 58349576 ps
CPU time 2.51 seconds
Started Jul 19 06:16:30 PM PDT 24
Finished Jul 19 06:16:33 PM PDT 24
Peak memory 233136 kb
Host smart-9d8ec13c-fa0a-44b9-99c8-e2e386196b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648703146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1648703146
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2664296148
Short name T335
Test name
Test status
Simulation time 18970621 ps
CPU time 0.8 seconds
Started Jul 19 06:16:21 PM PDT 24
Finished Jul 19 06:16:22 PM PDT 24
Peak memory 207356 kb
Host smart-78da637d-a7cc-4420-b142-b2ca4d19edc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664296148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2664296148
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2219160831
Short name T860
Test name
Test status
Simulation time 1309596428 ps
CPU time 29.26 seconds
Started Jul 19 06:16:34 PM PDT 24
Finished Jul 19 06:17:04 PM PDT 24
Peak memory 255228 kb
Host smart-852b9721-4dc5-4869-885f-cd67013fb886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219160831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2219160831
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3612706975
Short name T906
Test name
Test status
Simulation time 59644596583 ps
CPU time 104.72 seconds
Started Jul 19 06:16:29 PM PDT 24
Finished Jul 19 06:18:15 PM PDT 24
Peak memory 241432 kb
Host smart-ddc83762-06f1-49fc-9790-6db1c9c96525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612706975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3612706975
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2465563537
Short name T306
Test name
Test status
Simulation time 1003497194 ps
CPU time 7.84 seconds
Started Jul 19 06:16:28 PM PDT 24
Finished Jul 19 06:16:36 PM PDT 24
Peak memory 249544 kb
Host smart-4ab8de3a-b0cd-4669-9e17-dadfbaff813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465563537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2465563537
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2789570226
Short name T176
Test name
Test status
Simulation time 43220344087 ps
CPU time 149.93 seconds
Started Jul 19 06:16:28 PM PDT 24
Finished Jul 19 06:18:59 PM PDT 24
Peak memory 269620 kb
Host smart-762fd3ce-d0ad-4bb1-8045-dcb7a1303704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789570226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2789570226
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2088009765
Short name T998
Test name
Test status
Simulation time 4185957970 ps
CPU time 25.11 seconds
Started Jul 19 06:16:32 PM PDT 24
Finished Jul 19 06:16:57 PM PDT 24
Peak memory 225016 kb
Host smart-6226ce76-c675-497a-858d-e03c79677567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088009765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2088009765
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1973456160
Short name T697
Test name
Test status
Simulation time 11811816640 ps
CPU time 32.02 seconds
Started Jul 19 06:16:30 PM PDT 24
Finished Jul 19 06:17:02 PM PDT 24
Peak memory 224936 kb
Host smart-0f93595a-652a-4a65-a5e1-c26a85ecc8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973456160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1973456160
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.391306097
Short name T770
Test name
Test status
Simulation time 966675203 ps
CPU time 4.96 seconds
Started Jul 19 06:16:27 PM PDT 24
Finished Jul 19 06:16:33 PM PDT 24
Peak memory 233132 kb
Host smart-d9913138-edb4-46d6-b885-7ccd816f9aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391306097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
391306097
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.426601534
Short name T255
Test name
Test status
Simulation time 1607699111 ps
CPU time 12.5 seconds
Started Jul 19 06:16:28 PM PDT 24
Finished Jul 19 06:16:41 PM PDT 24
Peak memory 249512 kb
Host smart-45f02c39-ee1f-4db4-aa7a-5f7d43573820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426601534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.426601534
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2774384195
Short name T522
Test name
Test status
Simulation time 562519067 ps
CPU time 9.13 seconds
Started Jul 19 06:16:30 PM PDT 24
Finished Jul 19 06:16:39 PM PDT 24
Peak memory 219492 kb
Host smart-95eeafd9-f471-4078-a0ba-d5f526d05ef0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2774384195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2774384195
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.2422425380
Short name T21
Test name
Test status
Simulation time 4381003503 ps
CPU time 63.03 seconds
Started Jul 19 06:16:27 PM PDT 24
Finished Jul 19 06:17:31 PM PDT 24
Peak memory 254000 kb
Host smart-dd13aa7f-f84c-4893-9b70-a1cf69d1001c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422425380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.2422425380
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3838416202
Short name T752
Test name
Test status
Simulation time 3982488561 ps
CPU time 21.27 seconds
Started Jul 19 06:16:25 PM PDT 24
Finished Jul 19 06:16:47 PM PDT 24
Peak memory 216716 kb
Host smart-0c5d0f53-5ab9-4f1c-8b9f-f4e235019454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838416202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3838416202
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.196131562
Short name T877
Test name
Test status
Simulation time 4015815715 ps
CPU time 8.36 seconds
Started Jul 19 06:16:24 PM PDT 24
Finished Jul 19 06:16:33 PM PDT 24
Peak memory 216772 kb
Host smart-5a209391-0f14-4b98-bd76-4bff57c429d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196131562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.196131562
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1595646205
Short name T962
Test name
Test status
Simulation time 77542038 ps
CPU time 1.27 seconds
Started Jul 19 06:16:21 PM PDT 24
Finished Jul 19 06:16:23 PM PDT 24
Peak memory 216708 kb
Host smart-428266aa-285f-463d-8b42-39c135476cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595646205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1595646205
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.907615621
Short name T547
Test name
Test status
Simulation time 77809272 ps
CPU time 0.97 seconds
Started Jul 19 06:16:23 PM PDT 24
Finished Jul 19 06:16:25 PM PDT 24
Peak memory 207460 kb
Host smart-5db665b8-255e-4883-84be-f59754400f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907615621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.907615621
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2244785296
Short name T241
Test name
Test status
Simulation time 17134543147 ps
CPU time 20.17 seconds
Started Jul 19 06:16:35 PM PDT 24
Finished Jul 19 06:16:56 PM PDT 24
Peak memory 233244 kb
Host smart-10f79206-2a27-4ed5-b97d-ddb86aa0f1ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244785296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2244785296
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3403513041
Short name T760
Test name
Test status
Simulation time 38584186 ps
CPU time 0.7 seconds
Started Jul 19 06:16:38 PM PDT 24
Finished Jul 19 06:16:39 PM PDT 24
Peak memory 205360 kb
Host smart-7fc9f0be-17db-48e9-909c-27bc121be4e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403513041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
403513041
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3168873263
Short name T79
Test name
Test status
Simulation time 2263011289 ps
CPU time 7.46 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:16:45 PM PDT 24
Peak memory 233196 kb
Host smart-ba828808-c860-4d10-a9b7-966024235035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168873263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3168873263
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2773294619
Short name T502
Test name
Test status
Simulation time 74390539 ps
CPU time 0.81 seconds
Started Jul 19 06:16:31 PM PDT 24
Finished Jul 19 06:16:32 PM PDT 24
Peak memory 207344 kb
Host smart-30bd2420-64e8-4454-bb87-9ff7270c729b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773294619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2773294619
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1496870734
Short name T448
Test name
Test status
Simulation time 4202946721 ps
CPU time 39.36 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:17:17 PM PDT 24
Peak memory 257260 kb
Host smart-c7b10851-e916-4825-93c4-a14ffcaf3a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496870734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1496870734
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2652821773
Short name T320
Test name
Test status
Simulation time 3175890512 ps
CPU time 9.26 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:16:47 PM PDT 24
Peak memory 224944 kb
Host smart-675ea76e-dd79-4526-9899-583a52ac3bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652821773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2652821773
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2823992971
Short name T984
Test name
Test status
Simulation time 29521466419 ps
CPU time 78.34 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:17:56 PM PDT 24
Peak memory 252068 kb
Host smart-801affb6-91bc-4d6f-8364-858f260b6164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823992971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2823992971
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3314978588
Short name T680
Test name
Test status
Simulation time 4295535751 ps
CPU time 66.87 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:17:45 PM PDT 24
Peak memory 252020 kb
Host smart-ef7a011e-266c-4825-8bca-e899c60f7cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314978588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3314978588
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2811169675
Short name T541
Test name
Test status
Simulation time 98769685512 ps
CPU time 193.89 seconds
Started Jul 19 06:16:38 PM PDT 24
Finished Jul 19 06:19:53 PM PDT 24
Peak memory 250688 kb
Host smart-71c342c3-fd92-4b09-a385-4c4e982e931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811169675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2811169675
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.115711313
Short name T537
Test name
Test status
Simulation time 3399351471 ps
CPU time 14.36 seconds
Started Jul 19 06:16:40 PM PDT 24
Finished Jul 19 06:16:55 PM PDT 24
Peak memory 224920 kb
Host smart-39725ef8-8d1f-4c3a-a9ea-6d368b4ac844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115711313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.115711313
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2205662914
Short name T658
Test name
Test status
Simulation time 1422488019 ps
CPU time 21.94 seconds
Started Jul 19 06:16:40 PM PDT 24
Finished Jul 19 06:17:03 PM PDT 24
Peak memory 233056 kb
Host smart-ed4ba489-3ead-4c3d-bc86-0f79eac8075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205662914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2205662914
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.1042819525
Short name T128
Test name
Test status
Simulation time 494173702 ps
CPU time 2.66 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:16:41 PM PDT 24
Peak memory 232844 kb
Host smart-fc2033fc-2405-45e4-b9fa-e46a8cbdf734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042819525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.1042819525
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2001706613
Short name T179
Test name
Test status
Simulation time 45275071689 ps
CPU time 11.94 seconds
Started Jul 19 06:16:36 PM PDT 24
Finished Jul 19 06:16:50 PM PDT 24
Peak memory 224976 kb
Host smart-e245c2fe-fc4e-4b63-86b1-dcf876d8f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001706613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2001706613
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.886769804
Short name T690
Test name
Test status
Simulation time 561356546 ps
CPU time 8.8 seconds
Started Jul 19 06:16:40 PM PDT 24
Finished Jul 19 06:16:49 PM PDT 24
Peak memory 223068 kb
Host smart-2acc174d-52e2-4e57-bab3-0315c2d5bb5a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=886769804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.886769804
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1690159350
Short name T994
Test name
Test status
Simulation time 2500586614 ps
CPU time 13.82 seconds
Started Jul 19 06:16:36 PM PDT 24
Finished Jul 19 06:16:51 PM PDT 24
Peak memory 216828 kb
Host smart-db0ca9ba-3ef9-4e82-b1db-c40fbcbf0214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690159350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1690159350
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2356800345
Short name T677
Test name
Test status
Simulation time 24681599773 ps
CPU time 6.63 seconds
Started Jul 19 06:16:28 PM PDT 24
Finished Jul 19 06:16:35 PM PDT 24
Peak memory 216748 kb
Host smart-08e0e0fc-f265-4718-ae88-2ebe5d68587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356800345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2356800345
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1743047035
Short name T768
Test name
Test status
Simulation time 115316624 ps
CPU time 0.92 seconds
Started Jul 19 06:16:30 PM PDT 24
Finished Jul 19 06:16:31 PM PDT 24
Peak memory 207256 kb
Host smart-e911d83f-6a07-4fa0-b5a3-598b59898278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743047035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1743047035
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2580408604
Short name T731
Test name
Test status
Simulation time 32284087 ps
CPU time 0.8 seconds
Started Jul 19 06:16:35 PM PDT 24
Finished Jul 19 06:16:36 PM PDT 24
Peak memory 206556 kb
Host smart-4044695e-84a1-495b-b365-ee58c58694ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580408604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2580408604
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.865398007
Short name T229
Test name
Test status
Simulation time 4071914447 ps
CPU time 15.42 seconds
Started Jul 19 06:16:37 PM PDT 24
Finished Jul 19 06:16:53 PM PDT 24
Peak memory 233192 kb
Host smart-0e633ae5-7561-48dc-8600-e98b9dc9770a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865398007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.865398007
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.960073028
Short name T444
Test name
Test status
Simulation time 14055767 ps
CPU time 0.74 seconds
Started Jul 19 06:16:51 PM PDT 24
Finished Jul 19 06:16:53 PM PDT 24
Peak memory 205352 kb
Host smart-563223a5-2699-4dc4-b3a2-53925030bb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960073028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.960073028
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.987894175
Short name T442
Test name
Test status
Simulation time 424021582 ps
CPU time 4 seconds
Started Jul 19 06:16:43 PM PDT 24
Finished Jul 19 06:16:48 PM PDT 24
Peak memory 233088 kb
Host smart-b146af46-00b7-405f-9a25-7c6cb128197a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987894175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.987894175
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.999460426
Short name T716
Test name
Test status
Simulation time 60575426 ps
CPU time 0.74 seconds
Started Jul 19 06:16:38 PM PDT 24
Finished Jul 19 06:16:40 PM PDT 24
Peak memory 206356 kb
Host smart-fdd3a713-804c-403a-b17f-ffcebab9f4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999460426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.999460426
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1685194804
Short name T810
Test name
Test status
Simulation time 3822007630 ps
CPU time 83.38 seconds
Started Jul 19 06:16:50 PM PDT 24
Finished Jul 19 06:18:14 PM PDT 24
Peak memory 249624 kb
Host smart-ebe459ad-9bf2-4bf2-a74a-bdc99b27bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685194804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1685194804
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1500746387
Short name T817
Test name
Test status
Simulation time 11773044837 ps
CPU time 104.76 seconds
Started Jul 19 06:16:50 PM PDT 24
Finished Jul 19 06:18:36 PM PDT 24
Peak memory 234500 kb
Host smart-d66d9a79-d9f8-4575-ad1d-5b9c43a3a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500746387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1500746387
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3973893024
Short name T294
Test name
Test status
Simulation time 20218370029 ps
CPU time 73.3 seconds
Started Jul 19 06:16:51 PM PDT 24
Finished Jul 19 06:18:05 PM PDT 24
Peak memory 249672 kb
Host smart-5ca0b12a-3663-4ab1-9ffc-b6617c3ebf66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973893024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3973893024
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2089621359
Short name T542
Test name
Test status
Simulation time 217541124 ps
CPU time 6.05 seconds
Started Jul 19 06:16:52 PM PDT 24
Finished Jul 19 06:16:58 PM PDT 24
Peak memory 233116 kb
Host smart-5f98a1e2-7824-435d-b121-c908406927b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089621359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2089621359
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.116114722
Short name T536
Test name
Test status
Simulation time 1269159227 ps
CPU time 19.37 seconds
Started Jul 19 06:16:53 PM PDT 24
Finished Jul 19 06:17:13 PM PDT 24
Peak memory 249520 kb
Host smart-b861b3fe-d395-4d6d-b623-1065e29f0516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116114722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
116114722
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1331524641
Short name T713
Test name
Test status
Simulation time 3033109946 ps
CPU time 27.7 seconds
Started Jul 19 06:16:45 PM PDT 24
Finished Jul 19 06:17:13 PM PDT 24
Peak memory 233224 kb
Host smart-5bba5fc4-1c99-49e7-83f6-ff66a3c66ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331524641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1331524641
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2577458036
Short name T974
Test name
Test status
Simulation time 11866837975 ps
CPU time 13.87 seconds
Started Jul 19 06:16:43 PM PDT 24
Finished Jul 19 06:16:58 PM PDT 24
Peak memory 224948 kb
Host smart-274709b8-dd68-4309-b8de-59442a19b135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577458036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2577458036
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3248870455
Short name T666
Test name
Test status
Simulation time 1196901865 ps
CPU time 3.12 seconds
Started Jul 19 06:16:44 PM PDT 24
Finished Jul 19 06:16:48 PM PDT 24
Peak memory 224884 kb
Host smart-fd8241c5-a268-42fb-bb61-70eef2083d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248870455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3248870455
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4230712796
Short name T795
Test name
Test status
Simulation time 9663244777 ps
CPU time 9.61 seconds
Started Jul 19 06:16:46 PM PDT 24
Finished Jul 19 06:16:56 PM PDT 24
Peak memory 225020 kb
Host smart-a3e83a04-18d2-484d-ad2f-4ea831d3c82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230712796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4230712796
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.893821158
Short name T456
Test name
Test status
Simulation time 740129778 ps
CPU time 6.28 seconds
Started Jul 19 06:16:52 PM PDT 24
Finished Jul 19 06:16:59 PM PDT 24
Peak memory 219164 kb
Host smart-ad189eab-69b1-4fae-8403-3af1ceb6b4ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=893821158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.893821158
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3823906457
Short name T820
Test name
Test status
Simulation time 19659551596 ps
CPU time 243.77 seconds
Started Jul 19 06:16:51 PM PDT 24
Finished Jul 19 06:20:56 PM PDT 24
Peak memory 266100 kb
Host smart-fd7b9ab3-d23e-4987-a57a-61f4a457d2ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823906457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3823906457
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2376977656
Short name T821
Test name
Test status
Simulation time 8155858952 ps
CPU time 40.31 seconds
Started Jul 19 06:16:43 PM PDT 24
Finished Jul 19 06:17:24 PM PDT 24
Peak memory 216704 kb
Host smart-b70b9d25-51e6-476e-a7fc-8aeb88524025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376977656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2376977656
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1048109024
Short name T412
Test name
Test status
Simulation time 1608416263 ps
CPU time 4.17 seconds
Started Jul 19 06:16:45 PM PDT 24
Finished Jul 19 06:16:50 PM PDT 24
Peak memory 216672 kb
Host smart-3e34e193-6f96-45be-bea6-56e155ba253d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048109024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1048109024
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2999099426
Short name T323
Test name
Test status
Simulation time 174603005 ps
CPU time 4.34 seconds
Started Jul 19 06:16:45 PM PDT 24
Finished Jul 19 06:16:50 PM PDT 24
Peak memory 216712 kb
Host smart-ea7eaab2-1524-4110-a454-8ed672735cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999099426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2999099426
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2004408908
Short name T625
Test name
Test status
Simulation time 41060956 ps
CPU time 0.8 seconds
Started Jul 19 06:16:43 PM PDT 24
Finished Jul 19 06:16:45 PM PDT 24
Peak memory 206360 kb
Host smart-ef4f3ec8-d323-4886-bb41-3ad4f2bf2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004408908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2004408908
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.158450403
Short name T477
Test name
Test status
Simulation time 688882461 ps
CPU time 4.59 seconds
Started Jul 19 06:16:45 PM PDT 24
Finished Jul 19 06:16:51 PM PDT 24
Peak memory 233172 kb
Host smart-3c84f284-8967-476c-9e9e-1fba3948f90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158450403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.158450403
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2377675255
Short name T339
Test name
Test status
Simulation time 24024925 ps
CPU time 0.72 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:06 PM PDT 24
Peak memory 205392 kb
Host smart-80b263d7-8e55-4cc1-b172-a4b1cf905d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377675255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
377675255
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.377222666
Short name T258
Test name
Test status
Simulation time 486093555 ps
CPU time 4.96 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:10 PM PDT 24
Peak memory 224948 kb
Host smart-18a67165-bcb5-4e4e-b002-94d51195a6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377222666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.377222666
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.869841779
Short name T729
Test name
Test status
Simulation time 27183193 ps
CPU time 0.76 seconds
Started Jul 19 06:16:52 PM PDT 24
Finished Jul 19 06:16:53 PM PDT 24
Peak memory 206064 kb
Host smart-52605e77-bdf8-4fe1-89cb-aa4864ad2dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869841779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.869841779
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.901114675
Short name T561
Test name
Test status
Simulation time 17412742660 ps
CPU time 43.13 seconds
Started Jul 19 06:17:06 PM PDT 24
Finished Jul 19 06:17:49 PM PDT 24
Peak memory 233240 kb
Host smart-ac9d39c0-e5bf-46a9-9a95-ba9288aaca02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901114675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.901114675
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.621574806
Short name T978
Test name
Test status
Simulation time 139610591624 ps
CPU time 341.05 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:22:45 PM PDT 24
Peak memory 257860 kb
Host smart-3e615bef-5b60-43f4-b0e2-7ef615a2de44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621574806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.621574806
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3173038770
Short name T10
Test name
Test status
Simulation time 19508033607 ps
CPU time 52.59 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:58 PM PDT 24
Peak memory 235552 kb
Host smart-7f874645-feb6-4af5-aeea-fafc86071ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173038770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3173038770
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3429014353
Short name T351
Test name
Test status
Simulation time 882216005 ps
CPU time 5.8 seconds
Started Jul 19 06:17:07 PM PDT 24
Finished Jul 19 06:17:13 PM PDT 24
Peak memory 224880 kb
Host smart-b8b0c0d2-b3e1-4198-bf08-97de61d51c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429014353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3429014353
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1789358979
Short name T129
Test name
Test status
Simulation time 31826330 ps
CPU time 0.74 seconds
Started Jul 19 06:17:05 PM PDT 24
Finished Jul 19 06:17:06 PM PDT 24
Peak memory 216248 kb
Host smart-eee49dd5-afde-4058-9b25-cb43e84c5404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789358979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1789358979
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.452892682
Short name T747
Test name
Test status
Simulation time 6042113587 ps
CPU time 18.13 seconds
Started Jul 19 06:17:01 PM PDT 24
Finished Jul 19 06:17:20 PM PDT 24
Peak memory 233208 kb
Host smart-6e44f4b8-4888-44be-b58a-2073aaa65069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452892682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.452892682
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1116866170
Short name T875
Test name
Test status
Simulation time 1133720850 ps
CPU time 14.98 seconds
Started Jul 19 06:16:59 PM PDT 24
Finished Jul 19 06:17:14 PM PDT 24
Peak memory 240944 kb
Host smart-5987a403-005e-493f-b012-201418adaecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116866170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1116866170
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.472527340
Short name T827
Test name
Test status
Simulation time 295866182 ps
CPU time 3.37 seconds
Started Jul 19 06:16:58 PM PDT 24
Finished Jul 19 06:17:02 PM PDT 24
Peak memory 233052 kb
Host smart-a7326074-b6f9-43e0-bc44-b913be086d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472527340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
472527340
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3410470903
Short name T727
Test name
Test status
Simulation time 373867327 ps
CPU time 7.35 seconds
Started Jul 19 06:17:00 PM PDT 24
Finished Jul 19 06:17:08 PM PDT 24
Peak memory 233080 kb
Host smart-7f6d3010-92b8-4da2-a587-05b33fc107d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410470903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3410470903
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3734051998
Short name T651
Test name
Test status
Simulation time 217652452 ps
CPU time 5.02 seconds
Started Jul 19 06:17:04 PM PDT 24
Finished Jul 19 06:17:09 PM PDT 24
Peak memory 223608 kb
Host smart-122d12c0-d85c-43ea-8c06-3e15cde5ae10
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3734051998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3734051998
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2410066005
Short name T20
Test name
Test status
Simulation time 44106769 ps
CPU time 1.01 seconds
Started Jul 19 06:17:07 PM PDT 24
Finished Jul 19 06:17:09 PM PDT 24
Peak memory 207944 kb
Host smart-df0c6fcc-92a1-4443-a88f-99aaadf8f4db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410066005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2410066005
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.431789584
Short name T374
Test name
Test status
Simulation time 2002497787 ps
CPU time 3.41 seconds
Started Jul 19 06:16:58 PM PDT 24
Finished Jul 19 06:17:02 PM PDT 24
Peak memory 216716 kb
Host smart-44c986cd-257d-41d7-a91d-9884a332ce62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431789584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.431789584
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3333386303
Short name T853
Test name
Test status
Simulation time 16787080569 ps
CPU time 14.71 seconds
Started Jul 19 06:16:50 PM PDT 24
Finished Jul 19 06:17:06 PM PDT 24
Peak memory 216704 kb
Host smart-d7da12de-acd0-4c8f-af7d-e1f9b27dd04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333386303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3333386303
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2178520695
Short name T785
Test name
Test status
Simulation time 170862306 ps
CPU time 1.09 seconds
Started Jul 19 06:16:58 PM PDT 24
Finished Jul 19 06:17:00 PM PDT 24
Peak memory 207720 kb
Host smart-3d070a6e-2ea1-4964-b4dc-ca06b764af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178520695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2178520695
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.200355377
Short name T597
Test name
Test status
Simulation time 49513273 ps
CPU time 0.8 seconds
Started Jul 19 06:16:59 PM PDT 24
Finished Jul 19 06:17:00 PM PDT 24
Peak memory 206444 kb
Host smart-dd07160c-01dd-439b-a235-8a1cef11e732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200355377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.200355377
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3682563977
Short name T920
Test name
Test status
Simulation time 88361895731 ps
CPU time 38.36 seconds
Started Jul 19 06:16:59 PM PDT 24
Finished Jul 19 06:17:39 PM PDT 24
Peak memory 233128 kb
Host smart-9d6fd19a-601b-4a91-9554-5e4a40bdfe8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682563977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3682563977
Directory /workspace/9.spi_device_upload/latest
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