Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2243683	1			T1	1		T2	10381		T5	1
all_values[1]	2243683	1			T1	1		T2	10381		T5	1
all_values[2]	2243683	1			T1	1		T2	10381		T5	1
all_values[3]	2243683	1			T1	1		T2	10381		T5	1
all_values[4]	2243683	1			T1	1		T2	10381		T5	1
all_values[5]	2243683	1			T1	1		T2	10381		T5	1
all_values[6]	2243683	1			T1	1		T2	10381		T5	1
all_values[7]	2243683	1			T1	1		T2	10381		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17271522

1

T1

8

T2

83048

T5

8

auto[1]

677942

1

T15

70

T16

54

T17

1041

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17925491

1

T1

8

T2

82566

T5

8

auto[1]

23973

1

T2

482

T15

71

T25

157

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2140262	1			T1	1		T2	10158		T5	1
all_values[0]	auto[0]	auto[1]	11044	1			T2	223		T15	8		T25	77
all_values[0]	auto[1]	auto[0]	91814	1			T15	3		T16	2		T17	5
all_values[0]	auto[1]	auto[1]	563	1			T15	2		T16	5		T17	5
all_values[1]	auto[0]	auto[0]	2174096	1			T1	1		T2	10206		T5	1
all_values[1]	auto[0]	auto[1]	6880	1			T2	175		T15	2		T25	62
all_values[1]	auto[1]	auto[0]	62298	1			T15	5		T16	4		T17	243
all_values[1]	auto[1]	auto[1]	409	1			T15	8		T16	4		T17	7
all_values[2]	auto[0]	auto[0]	2153656	1			T1	1		T2	10297		T5	1
all_values[2]	auto[0]	auto[1]	2934	1			T2	84		T15	5		T25	18
all_values[2]	auto[1]	auto[0]	86859	1			T15	4		T16	5		T17	6
all_values[2]	auto[1]	auto[1]	234	1			T15	2		T16	2		T17	2
all_values[3]	auto[0]	auto[0]	2134501	1			T1	1		T2	10381		T5	1
all_values[3]	auto[0]	auto[1]	178	1			T15	5		T16	3		T19	2
all_values[3]	auto[1]	auto[0]	108791	1			T15	3		T16	4		T17	256
all_values[3]	auto[1]	auto[1]	213	1			T15	4		T16	1		T18	4
all_values[4]	auto[0]	auto[0]	2146937	1			T1	1		T2	10381		T5	1
all_values[4]	auto[0]	auto[1]	177	1			T15	8		T16	1		T18	3
all_values[4]	auto[1]	auto[0]	96350	1			T15	10		T16	6		T17	248
all_values[4]	auto[1]	auto[1]	219	1			T15	3		T16	4		T17	4
all_values[5]	auto[0]	auto[0]	2182237	1			T1	1		T2	10381		T5	1
all_values[5]	auto[0]	auto[1]	155	1			T15	6		T16	1		T17	1
all_values[5]	auto[1]	auto[0]	61092	1			T15	4		T16	1		T17	4
all_values[5]	auto[1]	auto[1]	199	1			T15	2		T16	3		T17	4
all_values[6]	auto[0]	auto[0]	2183586	1			T1	1		T2	10381		T5	1
all_values[6]	auto[0]	auto[1]	182	1			T15	1		T16	6		T17	4
all_values[6]	auto[1]	auto[0]	59734	1			T15	5		T16	1		T17	5
all_values[6]	auto[1]	auto[1]	181	1			T15	3		T16	3		T17	2
all_values[7]	auto[0]	auto[0]	2134517	1			T1	1		T2	10381		T5	1
all_values[7]	auto[0]	auto[1]	180	1			T15	5		T16	1		T17	3
all_values[7]	auto[1]	auto[0]	108761	1			T15	5		T16	4		T17	247
all_values[7]	auto[1]	auto[1]	225	1			T15	7		T16	5		T17	3