Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35753	1			T1	2		T2	61		T9	142
auto[SpiFlashAddrCfg]	7456	1			T1	6		T2	19		T5	2
auto[SpiFlashAddr3b]	9078	1			T1	2		T2	36		T5	6
auto[SpiFlashAddr4b]	7518	1			T1	4		T2	23		T5	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33147

1

T1

14

T2

84

T5

14

auto[1]

26658

1

T2

55

T9

69

T10

46

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31244

1

T1

6

T2

88

T5

6

auto[1]

28561

1

T1

8

T2

51

T5

8

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	40408	1			T1	6		T2	91		T9	151
values[1]	1056	1			T9	3		T10	1		T43	2
values[2]	1439	1			T2	6		T5	6		T9	1
values[3]	1431	1			T2	1		T9	1		T10	8
values[4]	1496	1			T2	7		T9	4		T10	4
values[5]	1418	1			T2	5		T9	5		T10	4
values[6]	1425	1			T2	6		T9	1		T10	9
values[7]	1316	1			T2	4		T9	3		T10	1
values[8]	9816	1			T1	8		T2	19		T5	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28767

1

T1

14

T5

14

T9

206

auto[1]

31038

1

T2

139

T12

4

T14

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56571

1

T1

10

T2

127

T5

14

write

3234

1

T1

4

T2

12

T9

7

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18903

1

T1

8

T2

55

T5

8

valids[0x1]

40902

1

T1

6

T2

84

T5

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1543	1			T2	7		T9	6		T10	6
internal_process_ops[0x5a]	1601	1			T2	4		T9	2		T10	4
internal_process_ops[0x05]	22028	1			T1	2		T2	24		T9	93
internal_process_ops[0x35]	1568	1			T2	5		T9	3		T10	3
internal_process_ops[0x15]	1568	1			T2	5		T9	4		T10	3
internal_process_ops[0x03]	946	1			T2	3		T5	6		T9	6
internal_process_ops[0x0b]	1070	1			T2	1		T9	3		T10	4
internal_process_ops[0x3b]	1011	1			T1	4		T2	1		T5	2
internal_process_ops[0x6b]	1030	1			T2	1		T9	3		T10	4
internal_process_ops[0xbb]	972	1			T2	4		T5	2		T9	9
internal_process_ops[0xeb]	990	1			T2	1		T5	4		T9	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58166

1

T1

14

T2

135

T5

14

auto[1]

1639

1

T2

4

T9

4

T10

4

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57518

1

T1

14

T2

132

T5

14

auto[1]

2287

1

T2

7

T9

2

T10

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9735

1

T1

2

T9

116

T10

153

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6288

1

T9

23

T10

7

T25

34

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1829

1

T1

4

T5

2

T9

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1629

1

T9

13

T10

13

T25

22

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2329

1

T5

6

T9

6

T10

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1964

1

T9

21

T10

9

T25

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1881

1

T1

4

T5

6

T9

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1653

1

T9

6

T10

12

T25

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

108

1

T10

3

T27

1

T47

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

60

1

T9

1

T25

1

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

52

1

T9

1

T10

2

T27

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T9

1

T10

2

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T1

2

T10

1

T25

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

66

1

T27

2

T41

1

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

91

1

T9

2

T27

1

T16

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

105

1

T41

2

T44

1

T20

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

112

1

T1

2

T27

1

T47

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

89

1

T25

2

T16

2

T44

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

85

1

T44

2

T45

1

T20

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

88

1

T16

1

T41

1

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

93

1

T25

3

T27

1

T16

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

104

1

T10

2

T25

1

T45

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

88

1

T10

1

T25

1

T27

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T9

2

T27

2

T16

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10673

1

T2

37

T16

22

T17

27

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8290

1

T2

23

T16

8

T17

102

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1580

1

T2

15

T14

3

T16

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1601

1

T16

3

T17

12

T18

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1955

1

T2

13

T12

3

T14

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2060

1

T2

18

T16

3

T17

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1547

1

T2

14

T12

1

T14

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1557

1

T2

7

T16

1

T17

7

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T46

1

T74

3

T157

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

108

1

T17

1

T18

3

T80

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

118

1

T2

1

T16

2

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

116

1

T16

1

T18

1

T74

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

108

1

T2

1

T17

2

T18

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

124

1

T18

1

T80

3

T158

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

118

1

T2

3

T80

5

T22

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

97

1

T18

4

T23

3

T48

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

79

1

T80

5

T74

2

T22

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

117

1

T2

2

T16

3

T80

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

87

1

T2

1

T17

1

T18

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

113

1

T2

2

T74

4

T81

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

124

1

T2

2

T74

6

T22

8

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

115

1

T16

2

T80

1

T74

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

121

1

T17

3

T18

1

T80

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

127

1

T80

3

T22

5

T23

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3527	1			T9	29		T10	19		T25	24
auto[0]	values[0]	valids[0x1]	15044	1			T1	6		T9	122		T10	154
auto[0]	values[1]	valids[0x1]	537	1			T9	3		T10	1		T43	2
auto[0]	values[2]	valids[0x0]	476	1			T10	1		T25	1		T27	3
auto[0]	values[2]	valids[0x1]	314	1			T5	6		T9	1		T10	6
auto[0]	values[3]	valids[0x0]	500	1			T9	1		T10	6		T25	9
auto[0]	values[3]	valids[0x1]	248	1			T10	2		T25	2		T27	1
auto[0]	values[4]	valids[0x0]	504	1			T9	2		T10	4		T25	3
auto[0]	values[4]	valids[0x1]	279	1			T9	2		T25	3		T27	2
auto[0]	values[5]	valids[0x0]	477	1			T9	5		T10	3		T25	7
auto[0]	values[5]	valids[0x1]	269	1			T10	1		T27	7		T16	1
auto[0]	values[6]	valids[0x0]	490	1			T9	1		T10	4		T27	4
auto[0]	values[6]	valids[0x1]	280	1			T10	5		T25	2		T27	1
auto[0]	values[7]	valids[0x0]	473	1			T9	3		T10	1		T27	2
auto[0]	values[7]	valids[0x1]	233	1			T41	5		T44	7		T18	1
auto[0]	values[8]	valids[0x0]	3196	1			T1	8		T5	8		T9	21
auto[0]	values[8]	valids[0x1]	1920	1			T9	16		T10	17		T43	2
auto[1]	values[0]	valids[0x0]	4090	1			T2	23		T16	12		T17	13
auto[1]	values[0]	valids[0x1]	17747	1			T2	68		T14	1		T16	29
auto[1]	values[1]	valids[0x1]	519	1			T17	2		T18	6		T46	3
auto[1]	values[2]	valids[0x0]	370	1			T2	2		T17	2		T18	12
auto[1]	values[2]	valids[0x1]	279	1			T2	4		T16	1		T17	2
auto[1]	values[3]	valids[0x0]	421	1			T16	1		T17	3		T18	3
auto[1]	values[3]	valids[0x1]	262	1			T2	1		T17	2		T18	1
auto[1]	values[4]	valids[0x0]	439	1			T2	7		T16	2		T17	2
auto[1]	values[4]	valids[0x1]	274	1			T12	1		T18	1		T80	6
auto[1]	values[5]	valids[0x0]	385	1			T2	2		T12	3		T18	2
auto[1]	values[5]	valids[0x1]	287	1			T2	3		T46	2		T80	1
auto[1]	values[6]	valids[0x0]	416	1			T2	4		T18	4		T80	4
auto[1]	values[6]	valids[0x1]	239	1			T2	2		T16	1		T17	1
auto[1]	values[7]	valids[0x0]	366	1			T2	4		T14	3		T17	4
auto[1]	values[7]	valids[0x1]	244	1			T16	1		T18	4		T80	1
auto[1]	values[8]	valids[0x0]	2773	1			T2	13		T14	1		T17	23
auto[1]	values[8]	valids[0x1]	1927	1			T2	6		T16	4		T17	3