Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3218457

1

T1

1

T2

9090

T5

7864

auto[1]

30542

1

T2

19

T9

86

T10

119

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

937429

1

T1

1

T2

37

T5

7864

auto[1]

2311570

1

T2

9072

T9

4223

T10

14359

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	671439	1			T1	1		T2	261		T5	2048
auto[524288:1048575]	330669	1			T2	3175		T9	265		T10	5915
auto[1048576:1572863]	398607	1			T2	5		T5	131		T9	134
auto[1572864:2097151]	419318	1			T2	1538		T5	1590		T9	1833
auto[2097152:2621439]	366044	1			T5	1679		T10	43		T25	5191
auto[2621440:3145727]	334155	1			T2	521		T5	1047		T9	519
auto[3145728:3670015]	355926	1			T2	535		T5	335		T9	1432
auto[3670016:4194303]	372841	1			T2	3074		T5	1034		T9	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2345386

1

T1

1

T2

9109

T5

22

auto[1]

903613

1

T5

7842

T10

8

T12

320

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2824159

1

T1

1

T2

6038

T5

7864

auto[1]

424840

1

T2

3071

T9

1555

T10

144

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	241959	1			T1	1		T2	5		T5	2048
auto[0]	auto[0]	auto[0:524287]	auto[1]	359202	1			T2	256		T9	1		T27	257
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	78195	1			T2	9		T9	4		T10	2
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	190978	1			T2	3151		T10	5912		T25	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103492	1			T2	3		T5	131		T10	7
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	227330	1			T2	2		T10	515		T25	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97414	1			T2	2		T5	1590		T9	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	260118	1			T2	1024		T9	1828		T10	2791
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	116677	1			T5	1679		T10	5		T25	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	205339	1			T10	13		T25	5163		T27	513
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	91767	1			T2	5		T5	1047		T9	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	197874	1			T2	513		T9	512		T10	2738
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	86515	1			T2	1		T5	335		T9	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	229164	1			T2	534		T9	257		T10	2141
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105370	1			T2	3		T5	1034		T9	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	207616	1			T2	512		T25	129		T16	2993
auto[0]	auto[1]	auto[0:524287]	auto[0]	1684	1			T10	2		T27	3		T16	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	63487	1			T16	402		T18	1024		T20	3442
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	595	1			T9	5		T10	1		T25	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	58059	1			T9	256		T25	2		T27	609
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1545	1			T9	6		T10	1		T25	5
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	62091	1			T9	128		T10	138		T25	1548
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	2029	1			T27	1		T44	4		T45	37
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	55561	1			T2	512		T44	512		T122	1024
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	813	1			T27	6		T16	1		T18	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	39806	1			T27	1410		T16	1		T44	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	2386	1			T25	1		T16	1		T18	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	39253	1			T16	512		T18	3		T45	261
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1389	1			T9	3		T10	1		T16	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	34211	1			T9	1157		T16	2		T18	411
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1903	1			T2	2		T10	1		T27	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	54635	1			T2	2556		T22	2424		T23	684
auto[1]	auto[0]	auto[0:524287]	auto[0]	480	1			T9	1		T27	1		T28	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	4000	1			T9	71		T27	3		T28	9
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	390	1			T2	5		T25	2		T16	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2122	1			T2	10		T25	6		T33	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	432	1			T10	3		T25	1		T16	5
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2856	1			T10	36		T25	3		T16	5
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	352	1			T25	1		T41	1		T17	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2608	1			T25	3		T41	18		T17	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	408	1			T10	3		T25	5		T27	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2626	1			T10	22		T25	14		T27	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	366	1			T2	1		T10	1		T27	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1986	1			T2	2		T10	20		T27	17
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	291	1			T9	1		T10	1		T27	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	3517	1			T9	13		T10	33		T27	52
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	286	1			T25	1		T17	1		T44	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2429	1			T25	1		T17	6		T44	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	95	1			T16	1		T45	3		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	532	1			T16	1		T20	5		T81	19
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	51	1			T25	2		T27	3		T18	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	279	1			T25	6		T27	32		T74	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	129	1			T16	1		T20	1		T74	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	732	1			T20	5		T158	1		T195	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	90	1			T45	3		T222	4		T239	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1146	1			T222	5		T194	47		T240	17
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	57	1			T27	2		T16	1		T18	3
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	318	1			T27	9		T18	1		T80	13
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	84	1			T18	1		T74	2		T81	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	439	1			T74	14		T81	5		T158	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	109	1			T16	2		T18	2		T74	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	730	1			T16	3		T81	10		T203	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	76	1			T2	1		T22	1		T59	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	526	1			T22	4		T59	43		T200	7

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1903142	1			T1	1		T2	6020		T5	22
auto[0]	auto[0]	auto[1]	895868	1			T5	7842		T10	5		T12	320
auto[0]	auto[1]	auto[0]	412299	1			T2	3070		T9	1555		T10	144
auto[0]	auto[1]	auto[1]	7148	1			T27	4		T20	1		T241	293
auto[1]	auto[0]	auto[0]	24664	1			T2	18		T9	86		T10	116
auto[1]	auto[0]	auto[1]	485	1			T10	3		T27	2		T28	2
auto[1]	auto[1]	auto[0]	5281	1			T2	1		T25	8		T27	44
auto[1]	auto[1]	auto[1]	112	1			T27	2		T45	2		T80	1