Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2243683	1			T1	1		T2	10381		T5	1
all_pins[1]	2243683	1			T1	1		T2	10381		T5	1
all_pins[2]	2243683	1			T1	1		T2	10381		T5	1
all_pins[3]	2243683	1			T1	1		T2	10381		T5	1
all_pins[4]	2243683	1			T1	1		T2	10381		T5	1
all_pins[5]	2243683	1			T1	1		T2	10381		T5	1
all_pins[6]	2243683	1			T1	1		T2	10381		T5	1
all_pins[7]	2243683	1			T1	1		T2	10381		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17886706	1			T1	8		T2	83048		T5	8
values[0x1]	62758	1			T15	31		T16	27		T17	31
transitions[0x0=>0x1]	61720	1			T15	25		T16	14		T17	29
transitions[0x1=>0x0]	61737	1			T15	25		T16	14		T17	29

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2243069	1			T1	1		T2	10381		T5	1
all_pins[0]	values[0x1]	614	1			T15	2		T16	5		T17	5
all_pins[0]	transitions[0x0=>0x1]	411	1			T15	1		T16	2		T17	4
all_pins[0]	transitions[0x1=>0x0]	228	1			T15	7		T16	1		T17	10
all_pins[1]	values[0x0]	2243252	1			T1	1		T2	10381		T5	1
all_pins[1]	values[0x1]	431	1			T15	8		T16	4		T17	11
all_pins[1]	transitions[0x0=>0x1]	354	1			T15	8		T16	2		T17	10
all_pins[1]	transitions[0x1=>0x0]	163	1			T15	2		T17	1		T18	2
all_pins[2]	values[0x0]	2243443	1			T1	1		T2	10381		T5	1
all_pins[2]	values[0x1]	240	1			T15	2		T16	2		T17	2
all_pins[2]	transitions[0x0=>0x1]	179	1			T15	2		T16	2		T17	2
all_pins[2]	transitions[0x1=>0x0]	152	1			T15	4		T16	1		T18	4
all_pins[3]	values[0x0]	2243470	1			T1	1		T2	10381		T5	1
all_pins[3]	values[0x1]	213	1			T15	4		T16	1		T18	4
all_pins[3]	transitions[0x0=>0x1]	146	1			T15	3		T18	2		T19	4
all_pins[3]	transitions[0x1=>0x0]	152	1			T15	2		T16	3		T17	4
all_pins[4]	values[0x0]	2243464	1			T1	1		T2	10381		T5	1
all_pins[4]	values[0x1]	219	1			T15	3		T16	4		T17	4
all_pins[4]	transitions[0x0=>0x1]	167	1			T15	3		T16	2		T17	4
all_pins[4]	transitions[0x1=>0x0]	1222	1			T15	2		T16	1		T17	4
all_pins[5]	values[0x0]	2242409	1			T1	1		T2	10381		T5	1
all_pins[5]	values[0x1]	1274	1			T15	2		T16	3		T17	4
all_pins[5]	transitions[0x0=>0x1]	808	1			T15	1		T16	2		T17	4
all_pins[5]	transitions[0x1=>0x0]	59076	1			T15	2		T16	2		T17	2
all_pins[6]	values[0x0]	2184141	1			T1	1		T2	10381		T5	1
all_pins[6]	values[0x1]	59542	1			T15	3		T16	3		T17	2
all_pins[6]	transitions[0x0=>0x1]	59495	1			T15	1		T16	2		T17	2
all_pins[6]	transitions[0x1=>0x0]	178	1			T15	5		T16	4		T17	3
all_pins[7]	values[0x0]	2243458	1			T1	1		T2	10381		T5	1
all_pins[7]	values[0x1]	225	1			T15	7		T16	5		T17	3
all_pins[7]	transitions[0x0=>0x1]	160	1			T15	6		T16	2		T17	3
all_pins[7]	transitions[0x1=>0x0]	566	1			T15	1		T16	2		T17	5