Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16514

1

T1

14

T5

14

T9

137

auto[1]

12253

1

T9

69

T10

46

T25

77

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3596	1			T1	14		T9	92		T27	95
values[1]	3519	1			T9	54		T27	118		T16	22
values[2]	3909	1			T43	6		T25	46		T16	52
values[3]	4016	1			T9	20		T10	65		T25	20
values[4]	3736	1			T9	20		T25	54		T16	23
values[5]	3361	1			T25	45		T27	31		T41	36
values[6]	3015	1			T10	61		T16	21		T44	22
values[7]	3615	1			T5	14		T9	20		T10	113

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3444	1			T1	14		T25	22		T27	73
values[1]	3968	1			T9	20		T25	22		T27	20
values[2]	3421	1			T9	20		T10	79		T27	76
values[3]	3691	1			T43	6		T16	21		T41	95
values[4]	3534	1			T5	14		T10	54		T25	23
values[5]	3415	1			T10	45		T25	32		T37	6
values[6]	3967	1			T9	20		T10	61		T25	66
values[7]	3327	1			T9	146		T27	20		T16	70

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	212	1			T1	14		T195	5		T208	14
auto[0]	values[0]	values[1]	252	1			T20	2		T203	11		T191	17
auto[0]	values[0]	values[2]	202	1			T87	13		T227	14		T242	14
auto[0]	values[0]	values[3]	263	1			T205	16		T88	9		T169	8
auto[0]	values[0]	values[4]	137	1			T28	21		T59	13		T196	14
auto[0]	values[0]	values[5]	232	1			T20	11		T243	22		T190	13
auto[0]	values[0]	values[6]	339	1			T27	29		T72	7		T215	12
auto[0]	values[0]	values[7]	325	1			T9	81		T27	13		T41	12
auto[0]	values[1]	values[0]	189	1			T27	13		T44	17		T173	12
auto[0]	values[1]	values[1]	277	1			T20	19		T190	13		T244	8
auto[0]	values[1]	values[2]	462	1			T9	12		T27	69		T153	20
auto[0]	values[1]	values[3]	348	1			T245	22		T246	26		T247	10
auto[0]	values[1]	values[4]	261	1			T45	6		T248	16		T249	8
auto[0]	values[1]	values[5]	222	1			T44	17		T169	9		T218	4
auto[0]	values[1]	values[6]	175	1			T88	14		T194	15		T228	22
auto[0]	values[1]	values[7]	245	1			T9	12		T16	13		T45	12
auto[0]	values[2]	values[0]	174	1			T195	13		T185	30		T39	19
auto[0]	values[2]	values[1]	333	1			T250	2		T190	14		T251	4
auto[0]	values[2]	values[2]	254	1			T33	7		T252	6		T72	12
auto[0]	values[2]	values[3]	286	1			T43	6		T41	19		T253	6
auto[0]	values[2]	values[4]	199	1			T16	11		T41	14		T59	19
auto[0]	values[2]	values[5]	193	1			T87	14		T204	6		T254	6
auto[0]	values[2]	values[6]	282	1			T25	15		T44	15		T20	43
auto[0]	values[2]	values[7]	397	1			T16	20		T45	22		T241	6
auto[0]	values[3]	values[0]	422	1			T16	10		T203	8		T239	10
auto[0]	values[3]	values[1]	305	1			T9	13		T229	12		T173	16
auto[0]	values[3]	values[2]	163	1			T10	11		T226	16		T203	25
auto[0]	values[3]	values[3]	334	1			T47	59		T202	11		T183	10
auto[0]	values[3]	values[4]	331	1			T255	18		T203	12		T183	6
auto[0]	values[3]	values[5]	294	1			T10	37		T45	7		T199	18
auto[0]	values[3]	values[6]	239	1			T25	12		T20	14		T203	25
auto[0]	values[3]	values[7]	268	1			T16	11		T18	11		T45	11
auto[0]	values[4]	values[0]	270	1			T20	16		T203	6		T256	20
auto[0]	values[4]	values[1]	391	1			T25	10		T20	8		T173	6
auto[0]	values[4]	values[2]	246	1			T16	11		T257	6		T191	10
auto[0]	values[4]	values[3]	281	1			T183	10		T258	12		T184	7
auto[0]	values[4]	values[4]	221	1			T259	6		T190	10		T239	9
auto[0]	values[4]	values[5]	210	1			T25	24		T203	12		T200	19
auto[0]	values[4]	values[6]	263	1			T260	12		T194	19		T204	12
auto[0]	values[4]	values[7]	133	1			T9	7		T45	15		T219	4
auto[0]	values[5]	values[0]	292	1			T25	13		T27	11		T217	10
auto[0]	values[5]	values[1]	201	1			T215	12		T177	12		T194	8
auto[0]	values[5]	values[2]	302	1			T41	11		T89	6		T44	27
auto[0]	values[5]	values[3]	183	1			T203	21		T59	14		T186	13
auto[0]	values[5]	values[4]	327	1			T25	14		T20	11		T227	12
auto[0]	values[5]	values[5]	202	1			T90	18		T261	14		T206	10
auto[0]	values[5]	values[6]	242	1			T190	12		T191	32		T169	13
auto[0]	values[5]	values[7]	267	1			T192	10		T20	15		T200	27
auto[0]	values[6]	values[0]	162	1			T231	10		T183	12		T212	8
auto[0]	values[6]	values[1]	197	1			T262	11		T208	8		T263	8
auto[0]	values[6]	values[2]	230	1			T20	28		T214	8		T236	17
auto[0]	values[6]	values[3]	333	1			T16	14		T215	10		T88	15
auto[0]	values[6]	values[4]	213	1			T264	4		T169	9		T193	13
auto[0]	values[6]	values[5]	92	1			T203	14		T239	8		T186	11
auto[0]	values[6]	values[6]	321	1			T10	47		T44	16		T195	13
auto[0]	values[6]	values[7]	94	1			T95	8		T203	7		T183	14
auto[0]	values[7]	values[0]	139	1			T18	12		T38	30		T225	9
auto[0]	values[7]	values[1]	330	1			T27	8		T41	39		T265	11
auto[0]	values[7]	values[2]	221	1			T10	50		T127	4		T215	10
auto[0]	values[7]	values[3]	350	1			T41	17		T18	12		T202	11
auto[0]	values[7]	values[4]	276	1			T5	14		T10	48		T220	6
auto[0]	values[7]	values[5]	358	1			T124	12		T176	2		T200	16
auto[0]	values[7]	values[6]	279	1			T9	12		T44	14		T266	10
auto[0]	values[7]	values[7]	273	1			T45	17		T200	18		T194	7
auto[1]	values[0]	values[0]	236	1			T195	20		T208	14		T218	109
auto[1]	values[0]	values[1]	224	1			T20	19		T203	9		T191	3
auto[1]	values[0]	values[2]	158	1			T87	7		T227	19		T172	10
auto[1]	values[0]	values[3]	146	1			T88	11		T169	12		T208	11
auto[1]	values[0]	values[4]	274	1			T59	7		T267	20		T236	14
auto[1]	values[0]	values[5]	191	1			T37	6		T20	15		T190	7
auto[1]	values[0]	values[6]	198	1			T27	46		T72	14		T215	8
auto[1]	values[0]	values[7]	207	1			T9	11		T27	7		T41	8
auto[1]	values[1]	values[0]	148	1			T27	29		T44	6		T173	8
auto[1]	values[1]	values[1]	124	1			T20	1		T190	7		T244	12
auto[1]	values[1]	values[2]	220	1			T9	8		T27	7		T44	11
auto[1]	values[1]	values[3]	102	1			T247	10		T182	9		T268	7
auto[1]	values[1]	values[4]	139	1			T45	14		T269	6		T72	8
auto[1]	values[1]	values[5]	179	1			T44	6		T169	11		T270	10
auto[1]	values[1]	values[6]	177	1			T88	6		T194	5		T228	10
auto[1]	values[1]	values[7]	251	1			T9	22		T16	9		T45	8
auto[1]	values[2]	values[0]	234	1			T195	12		T185	11		T39	9
auto[1]	values[2]	values[1]	179	1			T190	6		T204	12		T212	8
auto[1]	values[2]	values[2]	173	1			T33	18		T72	10		T228	8
auto[1]	values[2]	values[3]	113	1			T41	56		T169	5		T184	4
auto[1]	values[2]	values[4]	224	1			T16	14		T41	39		T59	7
auto[1]	values[2]	values[5]	370	1			T87	6		T204	14		T254	88
auto[1]	values[2]	values[6]	312	1			T25	31		T44	5		T20	14
auto[1]	values[2]	values[7]	186	1			T16	7		T45	18		T169	11
auto[1]	values[3]	values[0]	157	1			T16	12		T203	12		T239	10
auto[1]	values[3]	values[1]	277	1			T9	7		T173	4		T72	5
auto[1]	values[3]	values[2]	67	1			T10	9		T203	9		T186	12
auto[1]	values[3]	values[3]	95	1			T202	9		T183	16		T218	9
auto[1]	values[3]	values[4]	292	1			T203	8		T183	114		T38	10
auto[1]	values[3]	values[5]	125	1			T10	8		T45	13		T59	9
auto[1]	values[3]	values[6]	459	1			T25	8		T20	30		T271	2
auto[1]	values[3]	values[7]	188	1			T16	10		T18	14		T45	9
auto[1]	values[4]	values[0]	281	1			T20	4		T203	18		T194	114
auto[1]	values[4]	values[1]	400	1			T25	12		T20	52		T173	14
auto[1]	values[4]	values[2]	212	1			T16	12		T191	79		T193	4
auto[1]	values[4]	values[3]	109	1			T183	21		T184	36		T272	9
auto[1]	values[4]	values[4]	166	1			T190	10		T239	11		T215	26
auto[1]	values[4]	values[5]	299	1			T25	8		T203	11		T200	9
auto[1]	values[4]	values[6]	121	1			T194	12		T204	11		T180	23
auto[1]	values[4]	values[7]	133	1			T9	13		T45	5		T185	17
auto[1]	values[5]	values[0]	245	1			T25	9		T27	20		T191	65
auto[1]	values[5]	values[1]	148	1			T215	8		T177	15		T194	12
auto[1]	values[5]	values[2]	171	1			T41	25		T44	21		T18	9
auto[1]	values[5]	values[3]	264	1			T203	21		T59	89		T186	7
auto[1]	values[5]	values[4]	202	1			T25	9		T20	9		T227	8
auto[1]	values[5]	values[5]	69	1			T262	10		T185	12		T38	10
auto[1]	values[5]	values[6]	63	1			T190	8		T191	9		T169	7
auto[1]	values[5]	values[7]	183	1			T20	5		T200	9		T227	10
auto[1]	values[6]	values[0]	145	1			T183	8		T212	14		T207	9
auto[1]	values[6]	values[1]	176	1			T262	12		T208	20		T193	26
auto[1]	values[6]	values[2]	148	1			T20	6		T236	6		T181	6
auto[1]	values[6]	values[3]	223	1			T16	7		T215	10		T88	5
auto[1]	values[6]	values[4]	128	1			T273	4		T169	11		T193	9
auto[1]	values[6]	values[5]	144	1			T203	6		T239	12		T186	9
auto[1]	values[6]	values[6]	356	1			T10	14		T44	6		T195	40
auto[1]	values[6]	values[7]	53	1			T203	13		T183	6		T228	11
auto[1]	values[7]	values[0]	138	1			T18	8		T274	24		T38	7
auto[1]	values[7]	values[1]	154	1			T27	12		T41	17		T265	9
auto[1]	values[7]	values[2]	192	1			T10	9		T230	18		T215	14
auto[1]	values[7]	values[3]	261	1			T41	3		T18	8		T202	9
auto[1]	values[7]	values[4]	144	1			T10	6		T203	14		T72	7
auto[1]	values[7]	values[5]	235	1			T200	4		T87	26		T216	13
auto[1]	values[7]	values[6]	141	1			T9	8		T44	6		T72	8
auto[1]	values[7]	values[7]	124	1			T45	3		T200	10		T194	24