Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	355	1			T5	2		T9	1		T10	1
auto[ReadAddrCrossIntoMailbox]	280	1			T5	2		T9	2		T10	2
auto[ReadAddrCrossOutOfMailbox]	296	1			T9	4		T10	1		T25	2
auto[ReadAddrCrossAllMailbox]	187	1			T5	4		T9	1		T25	1
auto[ReadAddrOutsideMailbox]	3210	1			T1	4		T5	6		T9	17

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2111

1

T1

2

T5

7

T9

13

auto[1]

2217

1

T1

2

T5

7

T9

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	651	1			T5	6		T9	6		T10	3
read_ops[0x0b]	776	1			T9	3		T10	4		T43	2
read_ops[0x3b]	744	1			T1	4		T5	2		T9	2
read_ops[0x6b]	751	1			T9	3		T10	4		T25	1
read_ops[0xbb]	701	1			T5	2		T9	9		T10	2
read_ops[0xeb]	705	1			T5	4		T9	2		T10	4

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T27	1		T41	1		T173	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T25	1		T45	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T45	1		T239	1		T215	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T41	1		T18	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T10	1		T45	1		T20	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T202	1		T211	1		T265	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T5	1		T9	1		T72	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T5	1		T18	1		T195	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	220	1			T5	2		T9	4		T10	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T5	2		T9	1		T10	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T41	1		T20	1		T202	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T27	1		T16	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T9	1		T220	2		T88	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T27	1		T16	2		T45	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T25	2		T20	1		T195	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T9	1		T16	1		T41	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T41	1		T20	1		T211	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T16	1		T44	2		T211	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	279	1			T10	1		T43	1		T27	4
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	315	1			T9	1		T10	3		T43	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T9	1		T25	1		T44	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T45	2		T20	1		T124	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T5	1		T25	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T5	1		T10	1		T41	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T9	1		T88	1		T177	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T45	1		T20	1		T203	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T44	1		T203	2		T72	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T208	1		T194	1		T38	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T1	2		T10	3		T25	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T1	2		T25	3		T27	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T16	1		T195	1		T196	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T10	1		T18	1		T203	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T261	1		T252	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T20	1		T261	1		T252	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T45	1		T20	1		T195	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	35	1			T9	1		T44	1		T202	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T261	1		T252	1		T225	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T25	1		T44	1		T261	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	271	1			T10	3		T27	1		T16	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T9	2		T27	5		T41	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T45	1		T202	1		T173	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T235	1		T190	2		T201	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T9	1		T45	1		T123	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T10	1		T45	1		T173	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T9	1		T44	1		T72	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T16	1		T44	1		T45	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T195	1		T203	1		T227	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T45	1		T20	1		T190	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T5	1		T9	3		T25	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T5	1		T9	4		T10	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T5	1		T16	1		T44	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T5	1		T25	2		T16	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T44	1		T202	1		T211	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T25	1		T45	2		T20	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T41	1		T18	1		T195	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T44	1		T202	1		T203	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T5	1		T203	2		T72	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T5	1		T27	1		T256	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	247	1			T10	3		T25	3		T27	4
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	268	1			T9	2		T10	1		T16	1