Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1754

1

T30

15

T25

8

T16

18

auto[1]

1654

1

T2

5

T30

15

T25

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1815

1

T2

5

T25

13

T16

28

auto[1]

1593

1

T30

30

T25

5

T16

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2686

1

T2

2

T30

30

T25

13

auto[1]

722

1

T2

3

T25

5

T16

14

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	713	1			T2	2		T30	3		T25	6
valid[1]	674	1			T2	2		T30	10		T25	3
valid[2]	681	1			T30	5		T25	2		T16	8
valid[3]	663	1			T2	1		T30	5		T25	4
valid[4]	677	1			T30	7		T25	3		T16	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	132	1			T25	2		T16	1		T44	1
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T30	2		T31	1		T34	2
auto[0]	auto[0]	valid[1]	auto[0]	101	1			T16	3		T33	1		T334	1
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T30	4		T25	1		T31	2
auto[0]	auto[0]	valid[2]	auto[0]	115	1			T16	4		T46	1		T328	2
auto[0]	auto[0]	valid[2]	auto[1]	161	1			T30	2		T31	1		T34	1
auto[0]	auto[0]	valid[3]	auto[0]	101	1			T25	1		T46	1		T80	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T30	4		T25	2		T16	2
auto[0]	auto[0]	valid[4]	auto[0]	113	1			T16	1		T79	2		T80	1
auto[0]	auto[0]	valid[4]	auto[1]	155	1			T30	3		T16	1		T31	1
auto[0]	auto[1]	valid[0]	auto[0]	99	1			T2	1		T25	1		T16	1
auto[0]	auto[1]	valid[0]	auto[1]	167	1			T30	1		T25	1		T16	1
auto[0]	auto[1]	valid[1]	auto[0]	117	1			T25	1		T16	1		T33	1
auto[0]	auto[1]	valid[1]	auto[1]	138	1			T30	6		T25	1		T32	1
auto[0]	auto[1]	valid[2]	auto[0]	102	1			T25	1		T16	2		T18	1
auto[0]	auto[1]	valid[2]	auto[1]	173	1			T30	3		T16	1		T31	2
auto[0]	auto[1]	valid[3]	auto[0]	109	1			T2	1		T16	1		T44	1
auto[0]	auto[1]	valid[3]	auto[1]	140	1			T30	1		T31	2		T32	1
auto[0]	auto[1]	valid[4]	auto[0]	104	1			T25	2		T18	2		T328	1
auto[0]	auto[1]	valid[4]	auto[1]	160	1			T30	4		T31	1		T34	2
auto[1]	auto[0]	valid[0]	auto[0]	78	1			T16	3		T33	1		T17	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T17	1		T44	1		T46	1
auto[1]	auto[0]	valid[2]	auto[0]	74	1			T25	1		T33	1		T18	1
auto[1]	auto[0]	valid[3]	auto[0]	72	1			T44	1		T340	1		T334	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T25	1		T16	3		T328	1
auto[1]	auto[1]	valid[0]	auto[0]	64	1			T2	1		T25	2		T16	1
auto[1]	auto[1]	valid[1]	auto[0]	78	1			T2	2		T16	3		T334	1
auto[1]	auto[1]	valid[2]	auto[0]	56	1			T16	1		T17	1		T18	2
auto[1]	auto[1]	valid[3]	auto[0]	81	1			T25	1		T16	3		T44	1
auto[1]	auto[1]	valid[4]	auto[0]	66	1			T44	1		T81	2		T158	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal