Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45576

1

T2

86

T6

6

T11

10

auto[1]

16652

1

T2

8

T30

352

T25

78

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45368

1

T2

61

T6

2

T11

7

auto[1]

16860

1

T2

33

T6

4

T11

3

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31727	1			T2	42		T6	6		T11	4
others[1]	5346	1			T2	4		T11	1		T30	29
others[2]	5331	1			T2	11		T11	1		T30	37
others[3]	5964	1			T2	13		T11	1		T30	38
interest[1]	3419	1			T2	8		T11	1		T30	17
interest[4]	20738	1			T2	30		T6	4		T11	3
interest[64]	10441	1			T2	16		T11	2		T30	72

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14562	1			T2	24		T6	2		T11	2
auto[0]	auto[0]	others[1]	2487	1			T2	3		T11	1		T25	21
auto[0]	auto[0]	others[2]	2509	1			T2	5		T11	1		T25	19
auto[0]	auto[0]	others[3]	2786	1			T2	8		T11	1		T25	26
auto[0]	auto[0]	interest[1]	1538	1			T2	5		T25	11		T16	25
auto[0]	auto[0]	interest[4]	9456	1			T2	17		T6	2		T11	1
auto[0]	auto[0]	interest[64]	4834	1			T2	8		T11	2		T25	43
auto[0]	auto[1]	others[0]	8595	1			T2	5		T30	159		T25	41
auto[0]	auto[1]	others[1]	1385	1			T30	29		T25	6		T16	14
auto[0]	auto[1]	others[2]	1427	1			T30	37		T25	4		T16	18
auto[0]	auto[1]	others[3]	1564	1			T30	38		T25	6		T16	23
auto[0]	auto[1]	interest[1]	925	1			T2	1		T30	17		T25	5
auto[0]	auto[1]	interest[4]	5701	1			T2	5		T30	115		T25	26
auto[0]	auto[1]	interest[64]	2756	1			T2	2		T30	72		T25	16
auto[1]	auto[0]	others[0]	8570	1			T2	13		T6	4		T11	2
auto[1]	auto[0]	others[1]	1474	1			T2	1		T25	13		T16	24
auto[1]	auto[0]	others[2]	1395	1			T2	6		T25	13		T16	25
auto[1]	auto[0]	others[3]	1614	1			T2	5		T25	9		T16	42
auto[1]	auto[0]	interest[1]	956	1			T2	2		T11	1		T25	7
auto[1]	auto[0]	interest[4]	5581	1			T2	8		T6	2		T11	2
auto[1]	auto[0]	interest[64]	2851	1			T2	6		T25	29		T16	50

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal