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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1029 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3460335881 Jul 20 05:54:14 PM PDT 24 Jul 20 05:54:16 PM PDT 24 41049179 ps
T101 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1783685993 Jul 20 05:53:47 PM PDT 24 Jul 20 05:53:51 PM PDT 24 165457938 ps
T1030 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3151691678 Jul 20 05:54:20 PM PDT 24 Jul 20 05:54:22 PM PDT 24 49013104 ps
T1031 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3923287687 Jul 20 05:54:07 PM PDT 24 Jul 20 05:54:09 PM PDT 24 20149204 ps
T100 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2913664363 Jul 20 05:53:58 PM PDT 24 Jul 20 05:54:03 PM PDT 24 1129054671 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1135194386 Jul 20 05:53:52 PM PDT 24 Jul 20 05:53:56 PM PDT 24 260317347 ps
T114 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3778234517 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:38 PM PDT 24 1116720127 ps
T104 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1565308495 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:09 PM PDT 24 138447426 ps
T1033 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2001183442 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:11 PM PDT 24 12456886 ps
T115 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3947594756 Jul 20 05:54:01 PM PDT 24 Jul 20 05:54:04 PM PDT 24 292717058 ps
T1034 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.585668610 Jul 20 05:54:19 PM PDT 24 Jul 20 05:54:22 PM PDT 24 19475078 ps
T116 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1602895516 Jul 20 05:54:08 PM PDT 24 Jul 20 05:54:12 PM PDT 24 69107997 ps
T1035 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2973210228 Jul 20 05:54:18 PM PDT 24 Jul 20 05:54:20 PM PDT 24 65325763 ps
T165 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2831629237 Jul 20 05:54:21 PM PDT 24 Jul 20 05:54:29 PM PDT 24 441178920 ps
T1036 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.713239975 Jul 20 05:53:52 PM PDT 24 Jul 20 05:53:56 PM PDT 24 172580180 ps
T1037 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2660462662 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:07 PM PDT 24 111881135 ps
T1038 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.833911534 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:06 PM PDT 24 43127409 ps
T1039 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.285896719 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:07 PM PDT 24 164043735 ps
T1040 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2535914386 Jul 20 05:53:44 PM PDT 24 Jul 20 05:53:46 PM PDT 24 25583253 ps
T1041 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2483830392 Jul 20 05:54:19 PM PDT 24 Jul 20 05:54:21 PM PDT 24 27433903 ps
T145 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2088035869 Jul 20 05:54:07 PM PDT 24 Jul 20 05:54:11 PM PDT 24 260330983 ps
T162 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.444642723 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:22 PM PDT 24 208740470 ps
T76 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1225211698 Jul 20 05:54:01 PM PDT 24 Jul 20 05:54:03 PM PDT 24 74711528 ps
T146 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3962819262 Jul 20 05:54:02 PM PDT 24 Jul 20 05:54:06 PM PDT 24 134677734 ps
T1042 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2551688127 Jul 20 05:54:22 PM PDT 24 Jul 20 05:54:24 PM PDT 24 13964083 ps
T117 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2149640933 Jul 20 05:54:05 PM PDT 24 Jul 20 05:54:08 PM PDT 24 55904171 ps
T156 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.102304318 Jul 20 05:54:12 PM PDT 24 Jul 20 05:54:14 PM PDT 24 48687780 ps
T1043 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2848234907 Jul 20 05:54:17 PM PDT 24 Jul 20 05:54:19 PM PDT 24 27360665 ps
T102 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1880097068 Jul 20 05:54:00 PM PDT 24 Jul 20 05:54:04 PM PDT 24 144115616 ps
T118 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2215301911 Jul 20 05:53:54 PM PDT 24 Jul 20 05:53:57 PM PDT 24 17214921 ps
T1044 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.191089129 Jul 20 05:54:07 PM PDT 24 Jul 20 05:54:08 PM PDT 24 38160240 ps
T168 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4094621048 Jul 20 05:54:05 PM PDT 24 Jul 20 05:54:29 PM PDT 24 4253624034 ps
T1045 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.777934852 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:14 PM PDT 24 223452028 ps
T1046 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3335144112 Jul 20 05:54:01 PM PDT 24 Jul 20 05:54:05 PM PDT 24 77709913 ps
T1047 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1551439824 Jul 20 05:54:12 PM PDT 24 Jul 20 05:54:15 PM PDT 24 65326690 ps
T163 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.387591584 Jul 20 05:53:55 PM PDT 24 Jul 20 05:54:13 PM PDT 24 666735163 ps
T1048 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.834454207 Jul 20 05:53:59 PM PDT 24 Jul 20 05:54:09 PM PDT 24 1725819840 ps
T1049 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3729860626 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:18 PM PDT 24 534292708 ps
T1050 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.980713988 Jul 20 05:54:20 PM PDT 24 Jul 20 05:54:23 PM PDT 24 52139941 ps
T1051 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.947099941 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:06 PM PDT 24 82201830 ps
T1052 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3414544003 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:55 PM PDT 24 134536270 ps
T159 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.235310783 Jul 20 05:54:13 PM PDT 24 Jul 20 05:54:28 PM PDT 24 595305998 ps
T1053 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2936805629 Jul 20 05:54:21 PM PDT 24 Jul 20 05:54:23 PM PDT 24 18930647 ps
T119 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4261595906 Jul 20 05:54:12 PM PDT 24 Jul 20 05:54:15 PM PDT 24 34018464 ps
T160 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3412375186 Jul 20 05:54:16 PM PDT 24 Jul 20 05:54:41 PM PDT 24 1987630999 ps
T1054 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.329535630 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:55 PM PDT 24 35320297 ps
T1055 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3161083865 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:07 PM PDT 24 75541039 ps
T1056 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4282543286 Jul 20 05:53:52 PM PDT 24 Jul 20 05:53:56 PM PDT 24 103511947 ps
T1057 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3080987301 Jul 20 05:54:05 PM PDT 24 Jul 20 05:54:09 PM PDT 24 495797142 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.101332458 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:55 PM PDT 24 18449341 ps
T1058 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.574946719 Jul 20 05:53:47 PM PDT 24 Jul 20 05:53:49 PM PDT 24 12604718 ps
T1059 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2273709091 Jul 20 05:53:55 PM PDT 24 Jul 20 05:54:05 PM PDT 24 322111289 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.989922649 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:58 PM PDT 24 768123824 ps
T1061 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1010163517 Jul 20 05:54:24 PM PDT 24 Jul 20 05:54:25 PM PDT 24 44674932 ps
T1062 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.626411628 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:55 PM PDT 24 13542034 ps
T1063 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1576784244 Jul 20 05:53:47 PM PDT 24 Jul 20 05:54:03 PM PDT 24 1881984982 ps
T1064 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1156410137 Jul 20 05:53:52 PM PDT 24 Jul 20 05:53:55 PM PDT 24 48830244 ps
T1065 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3582181078 Jul 20 05:54:11 PM PDT 24 Jul 20 05:54:16 PM PDT 24 1024924240 ps
T1066 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1300771446 Jul 20 05:54:13 PM PDT 24 Jul 20 05:54:18 PM PDT 24 991895580 ps
T1067 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2161432032 Jul 20 05:54:08 PM PDT 24 Jul 20 05:54:17 PM PDT 24 324517194 ps
T1068 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1893942177 Jul 20 05:54:26 PM PDT 24 Jul 20 05:54:27 PM PDT 24 14106738 ps
T1069 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.239656181 Jul 20 05:54:13 PM PDT 24 Jul 20 05:54:19 PM PDT 24 306222400 ps
T1070 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1594352799 Jul 20 05:53:54 PM PDT 24 Jul 20 05:54:00 PM PDT 24 374137857 ps
T1071 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3670162753 Jul 20 05:54:23 PM PDT 24 Jul 20 05:54:25 PM PDT 24 54041780 ps
T1072 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1899925305 Jul 20 05:53:53 PM PDT 24 Jul 20 05:54:10 PM PDT 24 11789160529 ps
T1073 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.254776733 Jul 20 05:54:15 PM PDT 24 Jul 20 05:54:23 PM PDT 24 378658652 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3606113661 Jul 20 05:54:01 PM PDT 24 Jul 20 05:54:02 PM PDT 24 34688937 ps
T1075 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1803323993 Jul 20 05:54:24 PM PDT 24 Jul 20 05:54:25 PM PDT 24 12198877 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1797625003 Jul 20 05:54:01 PM PDT 24 Jul 20 05:54:06 PM PDT 24 231151912 ps
T1077 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.900852750 Jul 20 05:53:50 PM PDT 24 Jul 20 05:54:05 PM PDT 24 642455938 ps
T121 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2058108035 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:12 PM PDT 24 102231723 ps
T167 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1306585744 Jul 20 05:53:46 PM PDT 24 Jul 20 05:53:54 PM PDT 24 275236759 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1234008052 Jul 20 05:54:04 PM PDT 24 Jul 20 05:54:08 PM PDT 24 100280782 ps
T1079 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2158645748 Jul 20 05:54:21 PM PDT 24 Jul 20 05:54:23 PM PDT 24 18621942 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1701652586 Jul 20 05:53:52 PM PDT 24 Jul 20 05:53:56 PM PDT 24 136133436 ps
T164 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2360515950 Jul 20 05:54:01 PM PDT 24 Jul 20 05:54:17 PM PDT 24 2383053362 ps
T1081 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2270946125 Jul 20 05:54:18 PM PDT 24 Jul 20 05:54:22 PM PDT 24 207198484 ps
T1082 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3278885414 Jul 20 05:53:43 PM PDT 24 Jul 20 05:53:46 PM PDT 24 392120288 ps
T1083 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3974028413 Jul 20 05:53:51 PM PDT 24 Jul 20 05:54:27 PM PDT 24 1635404071 ps
T77 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3267787455 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:56 PM PDT 24 45259995 ps
T78 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3090037726 Jul 20 05:53:54 PM PDT 24 Jul 20 05:53:57 PM PDT 24 26517968 ps
T1084 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.872209678 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:06 PM PDT 24 173086969 ps
T1085 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4245421909 Jul 20 05:54:18 PM PDT 24 Jul 20 05:54:20 PM PDT 24 57387154 ps
T1086 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4053430290 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:30 PM PDT 24 297565161 ps
T1087 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1327878227 Jul 20 05:54:08 PM PDT 24 Jul 20 05:54:09 PM PDT 24 33738744 ps
T1088 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1114068357 Jul 20 05:54:15 PM PDT 24 Jul 20 05:54:19 PM PDT 24 2118913586 ps
T1089 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2952032125 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:12 PM PDT 24 37931080 ps
T1090 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1528812129 Jul 20 05:54:00 PM PDT 24 Jul 20 05:54:05 PM PDT 24 205280496 ps
T1091 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3730732240 Jul 20 05:54:04 PM PDT 24 Jul 20 05:54:07 PM PDT 24 51075572 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.188090372 Jul 20 05:54:12 PM PDT 24 Jul 20 05:54:14 PM PDT 24 28580853 ps
T1093 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3227983309 Jul 20 05:53:51 PM PDT 24 Jul 20 05:54:00 PM PDT 24 698370781 ps
T1094 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1377506252 Jul 20 05:53:55 PM PDT 24 Jul 20 05:53:59 PM PDT 24 37468809 ps
T1095 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2868995608 Jul 20 05:54:16 PM PDT 24 Jul 20 05:54:20 PM PDT 24 878240089 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1746232941 Jul 20 05:53:55 PM PDT 24 Jul 20 05:54:05 PM PDT 24 445540421 ps
T1097 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.561115908 Jul 20 05:54:26 PM PDT 24 Jul 20 05:54:28 PM PDT 24 15784629 ps
T1098 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3030999821 Jul 20 05:54:13 PM PDT 24 Jul 20 05:54:18 PM PDT 24 311609593 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.607388512 Jul 20 05:54:10 PM PDT 24 Jul 20 05:54:15 PM PDT 24 63325298 ps
T1100 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2172082254 Jul 20 05:54:18 PM PDT 24 Jul 20 05:54:20 PM PDT 24 51683775 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2539043145 Jul 20 05:53:54 PM PDT 24 Jul 20 05:53:56 PM PDT 24 170640494 ps
T1102 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1423392796 Jul 20 05:54:20 PM PDT 24 Jul 20 05:54:22 PM PDT 24 16247151 ps
T1103 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3847932820 Jul 20 05:53:54 PM PDT 24 Jul 20 05:53:56 PM PDT 24 36111061 ps
T161 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3665145941 Jul 20 05:54:16 PM PDT 24 Jul 20 05:54:38 PM PDT 24 3333813914 ps
T1104 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3492722850 Jul 20 05:54:03 PM PDT 24 Jul 20 05:54:07 PM PDT 24 340558784 ps
T1105 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3222456585 Jul 20 05:54:08 PM PDT 24 Jul 20 05:54:09 PM PDT 24 17454679 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3111266330 Jul 20 05:54:09 PM PDT 24 Jul 20 05:54:12 PM PDT 24 88489875 ps
T1107 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4214362261 Jul 20 05:54:05 PM PDT 24 Jul 20 05:54:07 PM PDT 24 73576959 ps
T166 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1173042950 Jul 20 05:53:51 PM PDT 24 Jul 20 05:53:59 PM PDT 24 1300623894 ps
T1108 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3695298833 Jul 20 05:54:12 PM PDT 24 Jul 20 05:54:14 PM PDT 24 25837607 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2951693671 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:56 PM PDT 24 88200338 ps
T1110 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2703564186 Jul 20 05:54:08 PM PDT 24 Jul 20 05:54:11 PM PDT 24 154421749 ps
T1111 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.433262328 Jul 20 05:54:05 PM PDT 24 Jul 20 05:54:08 PM PDT 24 109573551 ps
T1112 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3574860545 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:56 PM PDT 24 182313220 ps
T1113 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4010655912 Jul 20 05:54:22 PM PDT 24 Jul 20 05:54:24 PM PDT 24 171864661 ps
T1114 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1162794391 Jul 20 05:54:14 PM PDT 24 Jul 20 05:54:17 PM PDT 24 105951221 ps
T1115 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2890943247 Jul 20 05:54:21 PM PDT 24 Jul 20 05:54:23 PM PDT 24 13456033 ps
T1116 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2818530162 Jul 20 05:54:12 PM PDT 24 Jul 20 05:54:13 PM PDT 24 16564069 ps
T1117 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1007530207 Jul 20 05:54:20 PM PDT 24 Jul 20 05:54:22 PM PDT 24 44379000 ps
T1118 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3977838102 Jul 20 05:54:13 PM PDT 24 Jul 20 05:54:16 PM PDT 24 307090822 ps
T1119 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3955032078 Jul 20 05:54:02 PM PDT 24 Jul 20 05:54:05 PM PDT 24 96811702 ps
T1120 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.183296255 Jul 20 05:53:55 PM PDT 24 Jul 20 05:53:57 PM PDT 24 44864547 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3589229873 Jul 20 05:54:06 PM PDT 24 Jul 20 05:54:07 PM PDT 24 51659091 ps
T1122 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1766004655 Jul 20 05:53:53 PM PDT 24 Jul 20 05:53:59 PM PDT 24 153144720 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3157095084 Jul 20 05:53:47 PM PDT 24 Jul 20 05:53:50 PM PDT 24 430965951 ps
T1124 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.910448952 Jul 20 05:54:07 PM PDT 24 Jul 20 05:54:10 PM PDT 24 118472019 ps
T1125 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1161016798 Jul 20 05:54:07 PM PDT 24 Jul 20 05:54:09 PM PDT 24 20756596 ps
T1126 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.603082843 Jul 20 05:54:28 PM PDT 24 Jul 20 05:54:30 PM PDT 24 29900079 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3649775434 Jul 20 05:53:55 PM PDT 24 Jul 20 05:54:33 PM PDT 24 9417326130 ps
T1128 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3582400908 Jul 20 05:54:10 PM PDT 24 Jul 20 05:54:11 PM PDT 24 61318659 ps
T1129 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.438409097 Jul 20 05:54:19 PM PDT 24 Jul 20 05:54:21 PM PDT 24 14900706 ps
T1130 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2138512680 Jul 20 05:53:52 PM PDT 24 Jul 20 05:53:55 PM PDT 24 461217782 ps
T1131 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4239515657 Jul 20 05:54:18 PM PDT 24 Jul 20 05:54:21 PM PDT 24 105990100 ps

Test location /workspace/coverage/default/5.spi_device_flash_all.275541415
Short name T10
Test name
Test status
Simulation time 59966054466 ps
CPU time 233.33 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:56:07 PM PDT 24
Peak memory 252116 kb
Host smart-73b64d48-8575-45a1-8366-dc6e217574a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275541415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.275541415
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3580336542
Short name T16
Test name
Test status
Simulation time 75327430885 ps
CPU time 643.04 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 07:04:56 PM PDT 24
Peak memory 266052 kb
Host smart-86470a04-37b3-48bb-81d7-3b40ff8591d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580336542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3580336542
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3755076720
Short name T23
Test name
Test status
Simulation time 39299203267 ps
CPU time 379.95 seconds
Started Jul 20 06:54:28 PM PDT 24
Finished Jul 20 07:00:49 PM PDT 24
Peak memory 257804 kb
Host smart-d0fae6c4-5215-46ac-b459-555d85d7997b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755076720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3755076720
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1107967948
Short name T98
Test name
Test status
Simulation time 876092502 ps
CPU time 3.85 seconds
Started Jul 20 05:54:14 PM PDT 24
Finished Jul 20 05:54:19 PM PDT 24
Peak memory 218084 kb
Host smart-d4f4c614-2a55-4894-b585-3bef155a2d61
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107967948 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1107967948
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.1673709128
Short name T20
Test name
Test status
Simulation time 198056420468 ps
CPU time 398.52 seconds
Started Jul 20 06:51:53 PM PDT 24
Finished Jul 20 06:58:32 PM PDT 24
Peak memory 269460 kb
Host smart-6d3815d4-5e2e-4444-8223-49317019978c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673709128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.1673709128
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2966571659
Short name T67
Test name
Test status
Simulation time 16448472 ps
CPU time 0.76 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 216516 kb
Host smart-be562c98-dadc-4326-b7f2-c0440ae8bb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966571659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2966571659
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.969316179
Short name T185
Test name
Test status
Simulation time 137667180406 ps
CPU time 360.38 seconds
Started Jul 20 06:53:41 PM PDT 24
Finished Jul 20 06:59:49 PM PDT 24
Peak memory 269976 kb
Host smart-9f22874b-0fc1-4e72-a444-2b9ebe0297cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969316179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.969316179
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.3263067682
Short name T194
Test name
Test status
Simulation time 18756403278 ps
CPU time 136.12 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:56:45 PM PDT 24
Peak memory 268360 kb
Host smart-6839601d-0fe8-4b5d-9d89-32824ae9abc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263067682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.3263067682
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3300416411
Short name T18
Test name
Test status
Simulation time 140836059310 ps
CPU time 505.95 seconds
Started Jul 20 06:54:54 PM PDT 24
Finished Jul 20 07:03:21 PM PDT 24
Peak memory 274084 kb
Host smart-ad18def8-ee5d-4773-b378-8f17bd5c5861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300416411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3300416411
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.402021136
Short name T35
Test name
Test status
Simulation time 232865170 ps
CPU time 1.24 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:14 PM PDT 24
Peak memory 236240 kb
Host smart-72950361-e53b-4dd9-be5c-ee2af382312c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402021136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.402021136
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.1904961576
Short name T203
Test name
Test status
Simulation time 293225719106 ps
CPU time 525.4 seconds
Started Jul 20 06:53:40 PM PDT 24
Finished Jul 20 07:02:34 PM PDT 24
Peak memory 268516 kb
Host smart-305bca22-4005-4e69-9dfe-a3857268cbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904961576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1904961576
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.3150369886
Short name T169
Test name
Test status
Simulation time 21559899175 ps
CPU time 140.21 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:57:26 PM PDT 24
Peak memory 265996 kb
Host smart-721b83af-20e1-4186-a417-2793c4a65b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150369886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.3150369886
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2188364434
Short name T12
Test name
Test status
Simulation time 135474664 ps
CPU time 6.5 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:52:03 PM PDT 24
Peak memory 234396 kb
Host smart-4b964e8d-23cb-460d-981e-46dfa6d9a37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188364434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2188364434
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.951262955
Short name T22
Test name
Test status
Simulation time 159359110884 ps
CPU time 356.02 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:59:23 PM PDT 24
Peak memory 266080 kb
Host smart-dc280a1e-27ac-4303-bbb3-3c2a14bd25b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951262955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.951262955
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3089148371
Short name T144
Test name
Test status
Simulation time 13498792841 ps
CPU time 14.39 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 215276 kb
Host smart-410f72f6-25e7-465e-8c1a-84bf4863b6b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089148371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3089148371
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2824387631
Short name T180
Test name
Test status
Simulation time 71200140090 ps
CPU time 328.22 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:58:43 PM PDT 24
Peak memory 274184 kb
Host smart-fd2d63d5-0908-48df-9939-923213a639af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824387631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2824387631
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2939174647
Short name T48
Test name
Test status
Simulation time 104584222697 ps
CPU time 170.69 seconds
Started Jul 20 06:52:57 PM PDT 24
Finished Jul 20 06:55:48 PM PDT 24
Peak memory 249656 kb
Host smart-b29fdd56-9970-4ae7-9894-9bc739a557ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939174647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2939174647
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2927092559
Short name T113
Test name
Test status
Simulation time 142233682 ps
CPU time 2.56 seconds
Started Jul 20 05:54:15 PM PDT 24
Finished Jul 20 05:54:18 PM PDT 24
Peak memory 207140 kb
Host smart-16de9b03-f3ca-4732-9554-652a17d00939
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927092559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2927092559
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1872295417
Short name T268
Test name
Test status
Simulation time 6955748147 ps
CPU time 91.89 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:53:39 PM PDT 24
Peak memory 249612 kb
Host smart-a3563197-2d71-4179-8020-569ea9c90b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872295417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1872295417
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2943537033
Short name T96
Test name
Test status
Simulation time 207418030 ps
CPU time 3.11 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 219292 kb
Host smart-4263944b-d8c4-48fb-bbb4-9e99f3eb6a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943537033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2943537033
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1336057617
Short name T38
Test name
Test status
Simulation time 290561028658 ps
CPU time 414.5 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:59:23 PM PDT 24
Peak memory 268804 kb
Host smart-47971dc1-0bab-46ab-ad14-c842bafc910a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336057617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1336057617
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2540886527
Short name T39
Test name
Test status
Simulation time 7997968796 ps
CPU time 117.52 seconds
Started Jul 20 06:53:02 PM PDT 24
Finished Jul 20 06:55:00 PM PDT 24
Peak memory 268824 kb
Host smart-3874b2d9-bd54-48f4-a074-ce3454b4718e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540886527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2540886527
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.535094520
Short name T183
Test name
Test status
Simulation time 9692982508 ps
CPU time 69.92 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:56:04 PM PDT 24
Peak memory 255836 kb
Host smart-56b3957f-805e-4578-aaa8-5a0490033683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535094520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.535094520
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1828250319
Short name T88
Test name
Test status
Simulation time 16656850015 ps
CPU time 111.5 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:55:37 PM PDT 24
Peak memory 267504 kb
Host smart-54cd4025-d30b-4bb5-922e-5a030f19616c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828250319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1828250319
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.376513473
Short name T44
Test name
Test status
Simulation time 45573043358 ps
CPU time 455.85 seconds
Started Jul 20 06:51:50 PM PDT 24
Finished Jul 20 06:59:26 PM PDT 24
Peak memory 267240 kb
Host smart-3dcc927c-4286-4cbb-be0a-6c3682c4ca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376513473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.
376513473
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2263224827
Short name T45
Test name
Test status
Simulation time 922942353836 ps
CPU time 319.6 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 07:00:20 PM PDT 24
Peak memory 265960 kb
Host smart-3f2b2910-e770-42d9-853c-c6ec3bfb4405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263224827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2263224827
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1849213240
Short name T289
Test name
Test status
Simulation time 10928286074 ps
CPU time 98.1 seconds
Started Jul 20 06:52:14 PM PDT 24
Finished Jul 20 06:53:55 PM PDT 24
Peak memory 255964 kb
Host smart-0f74d81f-6d67-4120-a4d6-2547c8527240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849213240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1849213240
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1481755010
Short name T349
Test name
Test status
Simulation time 184056399 ps
CPU time 0.73 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 205368 kb
Host smart-b1db08c9-f5c8-4bec-a18e-ebe535586a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481755010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1481755010
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.436496412
Short name T25
Test name
Test status
Simulation time 15148283165 ps
CPU time 123.38 seconds
Started Jul 20 06:54:18 PM PDT 24
Finished Jul 20 06:56:23 PM PDT 24
Peak memory 253808 kb
Host smart-0f4f0615-78b1-4ad2-9587-05b03195f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436496412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.436496412
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2913664363
Short name T100
Test name
Test status
Simulation time 1129054671 ps
CPU time 4.44 seconds
Started Jul 20 05:53:58 PM PDT 24
Finished Jul 20 05:54:03 PM PDT 24
Peak memory 215664 kb
Host smart-196e671c-4fe0-4027-a410-3a4b9560adf1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913664363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
913664363
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3652222234
Short name T904
Test name
Test status
Simulation time 161493222330 ps
CPU time 387.99 seconds
Started Jul 20 06:52:04 PM PDT 24
Finished Jul 20 06:58:33 PM PDT 24
Peak memory 254092 kb
Host smart-0b2f894a-d02a-4237-abe9-2f3adeb3999c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652222234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3652222234
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.324206739
Short name T228
Test name
Test status
Simulation time 50753991309 ps
CPU time 196.71 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:55:30 PM PDT 24
Peak memory 256188 kb
Host smart-c6dcfc23-47b5-44d2-9d9a-8c78cc86b476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324206739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.324206739
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1029047516
Short name T83
Test name
Test status
Simulation time 196484864 ps
CPU time 8.58 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 249408 kb
Host smart-bd3a006c-1a82-4783-abcf-e2c40608dda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029047516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1029047516
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3412375186
Short name T160
Test name
Test status
Simulation time 1987630999 ps
CPU time 23.91 seconds
Started Jul 20 05:54:16 PM PDT 24
Finished Jul 20 05:54:41 PM PDT 24
Peak memory 215876 kb
Host smart-268357b7-d156-4257-9f81-fb2b0e7828f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412375186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3412375186
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3710603596
Short name T204
Test name
Test status
Simulation time 55176885226 ps
CPU time 395.73 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:59:07 PM PDT 24
Peak memory 253080 kb
Host smart-9afe873e-c7c4-426f-a31d-9f617d003061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710603596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3710603596
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3007095202
Short name T41
Test name
Test status
Simulation time 79006538298 ps
CPU time 179.46 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:57:02 PM PDT 24
Peak memory 249584 kb
Host smart-62b115ab-c954-46f2-a8bc-385a3f33b8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007095202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3007095202
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.918366744
Short name T334
Test name
Test status
Simulation time 5247209545 ps
CPU time 19.8 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:49 PM PDT 24
Peak memory 220484 kb
Host smart-89f0379b-da9e-4182-bdf5-ef1e2f490366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918366744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.918366744
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2360515950
Short name T164
Test name
Test status
Simulation time 2383053362 ps
CPU time 15.81 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 215424 kb
Host smart-2ffa1436-77ec-47f5-8618-a2b6eec8e198
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360515950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2360515950
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2903560511
Short name T197
Test name
Test status
Simulation time 3412319543 ps
CPU time 83.49 seconds
Started Jul 20 06:52:43 PM PDT 24
Finished Jul 20 06:54:07 PM PDT 24
Peak memory 266220 kb
Host smart-96261557-4a74-4797-a6b7-4e93e8648a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903560511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2903560511
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.812268114
Short name T297
Test name
Test status
Simulation time 15108802967 ps
CPU time 92.86 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:53:29 PM PDT 24
Peak memory 257232 kb
Host smart-bff0e739-00f0-4f85-a577-f70c154d1454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812268114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
812268114
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2204772888
Short name T323
Test name
Test status
Simulation time 3074932209 ps
CPU time 9.98 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:24 PM PDT 24
Peak memory 225020 kb
Host smart-c84b0a7b-59c5-435a-b73d-46e0ccaef689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204772888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2204772888
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3048008786
Short name T107
Test name
Test status
Simulation time 216903747 ps
CPU time 7.52 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 215320 kb
Host smart-0ab38787-247f-47f4-8478-ab47774a3618
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048008786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3048008786
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.361593110
Short name T56
Test name
Test status
Simulation time 91596864726 ps
CPU time 146.19 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 249668 kb
Host smart-697cd159-0f21-4c03-8d97-ec98d81f722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361593110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.361593110
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1741742354
Short name T233
Test name
Test status
Simulation time 148334696467 ps
CPU time 447.29 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:59:58 PM PDT 24
Peak memory 281736 kb
Host smart-723a562a-2f1f-44e2-8d4d-120328799f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741742354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1741742354
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1620611468
Short name T418
Test name
Test status
Simulation time 101747851 ps
CPU time 2.34 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:39 PM PDT 24
Peak memory 224864 kb
Host smart-2d8e70d0-7ef1-46e2-a9e3-49cd426c45d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620611468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1620611468
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3884658211
Short name T525
Test name
Test status
Simulation time 3736570907 ps
CPU time 29.83 seconds
Started Jul 20 06:52:38 PM PDT 24
Finished Jul 20 06:53:09 PM PDT 24
Peak memory 233216 kb
Host smart-aac5a608-5dc1-4665-b87a-8cdf9aa0bbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884658211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3884658211
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3335859025
Short name T188
Test name
Test status
Simulation time 73918486631 ps
CPU time 226.07 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:56:35 PM PDT 24
Peak memory 273532 kb
Host smart-b7d5f1bb-f00a-4e09-86b8-9bd26a77d572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335859025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3335859025
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1545305293
Short name T313
Test name
Test status
Simulation time 38108117783 ps
CPU time 267.33 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:57:26 PM PDT 24
Peak memory 252804 kb
Host smart-abb887bf-3eeb-483c-8176-eaf4b2d0f000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545305293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1545305293
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.204989141
Short name T324
Test name
Test status
Simulation time 1756472128 ps
CPU time 24.27 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:54:11 PM PDT 24
Peak memory 241208 kb
Host smart-67067932-9123-4fac-96af-bfbc5b6c399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204989141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.204989141
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.180661556
Short name T225
Test name
Test status
Simulation time 47222038753 ps
CPU time 206.75 seconds
Started Jul 20 06:54:46 PM PDT 24
Finished Jul 20 06:58:13 PM PDT 24
Peak memory 254880 kb
Host smart-f0b63b5a-eca1-402c-a2d0-7112ab9aeff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180661556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.180661556
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1809718028
Short name T231
Test name
Test status
Simulation time 281322791 ps
CPU time 3.13 seconds
Started Jul 20 06:51:58 PM PDT 24
Finished Jul 20 06:52:02 PM PDT 24
Peak memory 224804 kb
Host smart-beb413f4-dd36-41a5-94bb-6b9a6340f3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809718028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1809718028
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3157095084
Short name T1123
Test name
Test status
Simulation time 430965951 ps
CPU time 1.42 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:53:50 PM PDT 24
Peak memory 207072 kb
Host smart-c9b6096e-2ac5-4c2d-820b-f6eaad74376b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157095084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3157095084
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.688908783
Short name T91
Test name
Test status
Simulation time 571973299 ps
CPU time 3.8 seconds
Started Jul 20 05:54:11 PM PDT 24
Finished Jul 20 05:54:16 PM PDT 24
Peak memory 215388 kb
Host smart-90d37761-4b4a-4d8f-9d4f-3640e5ce8a0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688908783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.688908783
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1746232941
Short name T1096
Test name
Test status
Simulation time 445540421 ps
CPU time 8.38 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 207132 kb
Host smart-fb1034f0-fff8-40be-a321-ddfdc46d0332
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746232941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1746232941
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1576784244
Short name T1063
Test name
Test status
Simulation time 1881984982 ps
CPU time 14.08 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:54:03 PM PDT 24
Peak memory 207144 kb
Host smart-38132363-18eb-48fe-a7a8-5cb0a291da1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576784244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1576784244
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1377506252
Short name T1094
Test name
Test status
Simulation time 37468809 ps
CPU time 2.57 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 216632 kb
Host smart-ce8ed45b-641b-4f57-b59e-4f5e12fb7e54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377506252 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1377506252
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2252960293
Short name T142
Test name
Test status
Simulation time 273044985 ps
CPU time 1.83 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 207044 kb
Host smart-7ec3bb38-ef7f-483b-990d-6b5616827769
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252960293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
252960293
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.574946719
Short name T1058
Test name
Test status
Simulation time 12604718 ps
CPU time 0.75 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:53:49 PM PDT 24
Peak memory 204060 kb
Host smart-8b384a95-6af2-4022-a889-8d70aa490704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574946719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.574946719
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3278885414
Short name T1082
Test name
Test status
Simulation time 392120288 ps
CPU time 1.38 seconds
Started Jul 20 05:53:43 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 215368 kb
Host smart-bf987292-21e6-40e6-b1a5-dafb944fda44
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278885414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3278885414
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2535914386
Short name T1040
Test name
Test status
Simulation time 25583253 ps
CPU time 0.68 seconds
Started Jul 20 05:53:44 PM PDT 24
Finished Jul 20 05:53:46 PM PDT 24
Peak memory 203672 kb
Host smart-95475954-d3d1-4c48-b906-cf8b7fd6104d
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535914386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2535914386
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.989922649
Short name T1060
Test name
Test status
Simulation time 768123824 ps
CPU time 3.18 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:58 PM PDT 24
Peak memory 215172 kb
Host smart-525e151a-211e-4c9b-a093-0e5550583215
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989922649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.989922649
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1783685993
Short name T101
Test name
Test status
Simulation time 165457938 ps
CPU time 2.35 seconds
Started Jul 20 05:53:47 PM PDT 24
Finished Jul 20 05:53:51 PM PDT 24
Peak memory 215488 kb
Host smart-de1a2163-d9e4-432e-9e52-5a08dd55df96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783685993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
783685993
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1306585744
Short name T167
Test name
Test status
Simulation time 275236759 ps
CPU time 7.07 seconds
Started Jul 20 05:53:46 PM PDT 24
Finished Jul 20 05:53:54 PM PDT 24
Peak memory 215316 kb
Host smart-c47b2f0e-1bb0-4b93-9296-282a168b6561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306585744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1306585744
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1899925305
Short name T1072
Test name
Test status
Simulation time 11789160529 ps
CPU time 15.95 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:54:10 PM PDT 24
Peak memory 215232 kb
Host smart-73fbf946-12d6-43da-aeee-aa2bbd9fa6c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899925305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1899925305
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.900852750
Short name T1077
Test name
Test status
Simulation time 642455938 ps
CPU time 14.47 seconds
Started Jul 20 05:53:50 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 207140 kb
Host smart-68ca29b2-0055-45a5-acee-9d3e59a75989
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900852750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_bit_bash.900852750
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3090037726
Short name T78
Test name
Test status
Simulation time 26517968 ps
CPU time 1.34 seconds
Started Jul 20 05:53:54 PM PDT 24
Finished Jul 20 05:53:57 PM PDT 24
Peak memory 216276 kb
Host smart-892de669-9ba1-4912-9055-72d5f604af53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090037726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3090037726
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4282543286
Short name T1056
Test name
Test status
Simulation time 103511947 ps
CPU time 3.75 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 217232 kb
Host smart-6d8f94a4-75ee-4def-8b5b-c6b5d40316cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282543286 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4282543286
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2215301911
Short name T118
Test name
Test status
Simulation time 17214921 ps
CPU time 1.33 seconds
Started Jul 20 05:53:54 PM PDT 24
Finished Jul 20 05:53:57 PM PDT 24
Peak memory 207036 kb
Host smart-e9fb5833-216b-425b-8ba5-9b546db36c6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215301911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
215301911
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1816550314
Short name T1027
Test name
Test status
Simulation time 17392497 ps
CPU time 0.77 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:53:57 PM PDT 24
Peak memory 204136 kb
Host smart-11406849-3371-4005-b6b2-359304ff7d44
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816550314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
816550314
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1156410137
Short name T1064
Test name
Test status
Simulation time 48830244 ps
CPU time 1.97 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 215388 kb
Host smart-de1615a4-a3b6-4ee0-99b0-228b55ffc0a6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156410137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1156410137
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2539043145
Short name T1101
Test name
Test status
Simulation time 170640494 ps
CPU time 0.73 seconds
Started Jul 20 05:53:54 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 204032 kb
Host smart-a65e5677-f7ac-4a73-83d9-9db4ed160629
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539043145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2539043145
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.713239975
Short name T1036
Test name
Test status
Simulation time 172580180 ps
CPU time 4.08 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 215308 kb
Host smart-bc3d8a14-2c48-4630-b07b-8dcae16fe979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713239975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.713239975
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1173042950
Short name T166
Test name
Test status
Simulation time 1300623894 ps
CPU time 7.7 seconds
Started Jul 20 05:53:51 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 215244 kb
Host smart-d0941c71-e821-4c2d-a5c8-a7ff5a0b34c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173042950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1173042950
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2088035869
Short name T145
Test name
Test status
Simulation time 260330983 ps
CPU time 3.68 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:11 PM PDT 24
Peak memory 218640 kb
Host smart-16d435ab-7caf-4d1d-b7e1-235b20d7b58c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088035869 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2088035869
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.4214362261
Short name T1107
Test name
Test status
Simulation time 73576959 ps
CPU time 1.51 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 215244 kb
Host smart-5af94299-02ac-446c-8f1d-654e468d41dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214362261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
4214362261
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1161016798
Short name T1125
Test name
Test status
Simulation time 20756596 ps
CPU time 0.71 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 203828 kb
Host smart-1f467abc-a796-4bbf-8b55-c1f9c99c77a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161016798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1161016798
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.285896719
Short name T1039
Test name
Test status
Simulation time 164043735 ps
CPU time 3.06 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 215212 kb
Host smart-d584c1c1-57f5-436d-8b76-53f62be6c4cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285896719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.285896719
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3730732240
Short name T1091
Test name
Test status
Simulation time 51075572 ps
CPU time 1.75 seconds
Started Jul 20 05:54:04 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 215292 kb
Host smart-81d47cc1-b5ba-4be8-80be-a3ef54af0cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730732240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3730732240
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3786661454
Short name T66
Test name
Test status
Simulation time 114615670 ps
CPU time 6.98 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:13 PM PDT 24
Peak memory 215244 kb
Host smart-b08536e1-1b8f-40f9-ad85-b414a4240626
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786661454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3786661454
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.947099941
Short name T1051
Test name
Test status
Simulation time 82201830 ps
CPU time 2.51 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 216432 kb
Host smart-378ab7bf-b612-42f8-9069-3be880bca28a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947099941 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.947099941
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3955032078
Short name T1119
Test name
Test status
Simulation time 96811702 ps
CPU time 2.63 seconds
Started Jul 20 05:54:02 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 215304 kb
Host smart-4934b9e0-acfe-4037-9992-d4d4fce5986c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955032078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3955032078
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2542851833
Short name T1018
Test name
Test status
Simulation time 14643465 ps
CPU time 0.74 seconds
Started Jul 20 05:54:08 PM PDT 24
Finished Jul 20 05:54:10 PM PDT 24
Peak memory 204076 kb
Host smart-806be454-d0fd-4058-aad8-002fec16d2cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542851833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2542851833
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1797625003
Short name T1076
Test name
Test status
Simulation time 231151912 ps
CPU time 4.96 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215140 kb
Host smart-ee4544bf-0a0d-4d6f-a4ea-8d731e4f533b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797625003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1797625003
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1234008052
Short name T1078
Test name
Test status
Simulation time 100280782 ps
CPU time 3.21 seconds
Started Jul 20 05:54:04 PM PDT 24
Finished Jul 20 05:54:08 PM PDT 24
Peak memory 215452 kb
Host smart-6c4918bb-cfb6-4fe6-af55-4bcae90c3a9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234008052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1234008052
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.2161432032
Short name T1067
Test name
Test status
Simulation time 324517194 ps
CPU time 7.84 seconds
Started Jul 20 05:54:08 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 215240 kb
Host smart-8f2adfd9-049c-4d2a-ac93-ca04c6bfbdda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161432032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.2161432032
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.910448952
Short name T1124
Test name
Test status
Simulation time 118472019 ps
CPU time 2.82 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:10 PM PDT 24
Peak memory 216744 kb
Host smart-c5dd5545-2737-4027-99d6-c746ab5c304f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910448952 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.910448952
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3606113661
Short name T1074
Test name
Test status
Simulation time 34688937 ps
CPU time 1.26 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:02 PM PDT 24
Peak memory 215372 kb
Host smart-986dbd06-9b47-43c5-b041-c61056342a6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606113661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3606113661
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3589229873
Short name T1121
Test name
Test status
Simulation time 51659091 ps
CPU time 0.75 seconds
Started Jul 20 05:54:06 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 203788 kb
Host smart-6eda7962-2afd-4fd9-8a0e-5861f6bb3caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589229873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3589229873
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2703564186
Short name T1110
Test name
Test status
Simulation time 154421749 ps
CPU time 2.65 seconds
Started Jul 20 05:54:08 PM PDT 24
Finished Jul 20 05:54:11 PM PDT 24
Peak memory 215236 kb
Host smart-1e0b2a76-2eaf-4d21-b6f3-6e3b156a703e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703564186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.2703564186
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3161083865
Short name T1055
Test name
Test status
Simulation time 75541039 ps
CPU time 2.51 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 215480 kb
Host smart-6412f421-e60d-45c9-87a4-bda6fff85737
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161083865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3161083865
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3977838102
Short name T1118
Test name
Test status
Simulation time 307090822 ps
CPU time 2.53 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:16 PM PDT 24
Peak memory 217764 kb
Host smart-88ecd446-b341-44d4-85b2-d194c8ecb03c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977838102 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3977838102
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1162794391
Short name T1114
Test name
Test status
Simulation time 105951221 ps
CPU time 1.83 seconds
Started Jul 20 05:54:14 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 207008 kb
Host smart-f71221d6-c10b-438e-91b2-ae010e93a773
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162794391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1162794391
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2535652096
Short name T151
Test name
Test status
Simulation time 13222007 ps
CPU time 0.71 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 203816 kb
Host smart-8070b9ae-5a73-4897-8cd2-c497e0cb0d7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535652096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2535652096
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.239656181
Short name T1069
Test name
Test status
Simulation time 306222400 ps
CPU time 4.5 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:19 PM PDT 24
Peak memory 215284 kb
Host smart-ed249fa3-fe60-49b3-a648-15df29d60357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239656181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.239656181
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.4239515657
Short name T1131
Test name
Test status
Simulation time 105990100 ps
CPU time 2.24 seconds
Started Jul 20 05:54:18 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 215452 kb
Host smart-861428a7-39ad-4524-a37f-f6319bc0814e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239515657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
4239515657
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.235310783
Short name T159
Test name
Test status
Simulation time 595305998 ps
CPU time 13.64 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:28 PM PDT 24
Peak memory 215232 kb
Host smart-a2e510cf-dbfe-44a7-8cfb-80e51809d50e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235310783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.235310783
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.102304318
Short name T156
Test name
Test status
Simulation time 48687780 ps
CPU time 1.52 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:14 PM PDT 24
Peak memory 207116 kb
Host smart-831b0f8f-ee74-4e0d-9cf1-f4ac45ec21f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102304318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.102304318
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2818530162
Short name T1116
Test name
Test status
Simulation time 16564069 ps
CPU time 0.8 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:13 PM PDT 24
Peak memory 204100 kb
Host smart-5c2d2186-d8b5-4d9f-9cca-628d38739ded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818530162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2818530162
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1699840000
Short name T1019
Test name
Test status
Simulation time 76628944 ps
CPU time 2.79 seconds
Started Jul 20 05:54:14 PM PDT 24
Finished Jul 20 05:54:17 PM PDT 24
Peak memory 215248 kb
Host smart-bb8dfcbe-ab7b-4f41-bb36-43437ab2a3f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699840000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.1699840000
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3798448482
Short name T65
Test name
Test status
Simulation time 147237072 ps
CPU time 5.5 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 216408 kb
Host smart-6eb25785-8d8b-4251-b92a-11a04e13c6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798448482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3798448482
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.949482197
Short name T93
Test name
Test status
Simulation time 302986112 ps
CPU time 19.66 seconds
Started Jul 20 05:54:10 PM PDT 24
Finished Jul 20 05:54:30 PM PDT 24
Peak memory 215232 kb
Host smart-b3aa087e-f094-444f-97d5-ed8e4488eaf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949482197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.949482197
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1114068357
Short name T1088
Test name
Test status
Simulation time 2118913586 ps
CPU time 2.98 seconds
Started Jul 20 05:54:15 PM PDT 24
Finished Jul 20 05:54:19 PM PDT 24
Peak memory 217128 kb
Host smart-cbc5e657-0baf-404d-99d4-0a176a1bfa74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114068357 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1114068357
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.188090372
Short name T1092
Test name
Test status
Simulation time 28580853 ps
CPU time 0.74 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:14 PM PDT 24
Peak memory 203836 kb
Host smart-ff980a41-e175-4233-9fe4-f063f2437855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188090372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.188090372
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2314688947
Short name T141
Test name
Test status
Simulation time 727016463 ps
CPU time 4.1 seconds
Started Jul 20 05:54:16 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 215220 kb
Host smart-0c43b925-e364-4567-81eb-affcc472ad01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314688947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2314688947
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.254776733
Short name T1073
Test name
Test status
Simulation time 378658652 ps
CPU time 6.7 seconds
Started Jul 20 05:54:15 PM PDT 24
Finished Jul 20 05:54:23 PM PDT 24
Peak memory 215460 kb
Host smart-ff9e658a-7e06-47d7-bc6a-352c87132ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254776733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.254776733
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3030999821
Short name T1098
Test name
Test status
Simulation time 311609593 ps
CPU time 3.84 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:18 PM PDT 24
Peak memory 218596 kb
Host smart-e380622b-1f21-4ecf-b8be-6cfce50335ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030999821 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3030999821
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.4261595906
Short name T119
Test name
Test status
Simulation time 34018464 ps
CPU time 2.34 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 215212 kb
Host smart-2585eb5b-5cdc-43ce-9b57-7572b23e7f20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261595906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
4261595906
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3460335881
Short name T1029
Test name
Test status
Simulation time 41049179 ps
CPU time 0.75 seconds
Started Jul 20 05:54:14 PM PDT 24
Finished Jul 20 05:54:16 PM PDT 24
Peak memory 203820 kb
Host smart-f044ddc1-dc50-4ceb-9caa-24fbf5f6337b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460335881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3460335881
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.98166190
Short name T135
Test name
Test status
Simulation time 313366865 ps
CPU time 4.09 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 215320 kb
Host smart-789003f1-f1a1-4e89-85d5-f64a58d6cc89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98166190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp
i_device_same_csr_outstanding.98166190
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3070404697
Short name T94
Test name
Test status
Simulation time 213093992 ps
CPU time 1.75 seconds
Started Jul 20 05:54:18 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 215480 kb
Host smart-0baea7d8-0c26-4faa-8dcf-2cd6b65d9656
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070404697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3070404697
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3582181078
Short name T1065
Test name
Test status
Simulation time 1024924240 ps
CPU time 3.99 seconds
Started Jul 20 05:54:11 PM PDT 24
Finished Jul 20 05:54:16 PM PDT 24
Peak memory 218588 kb
Host smart-e77c1a43-07aa-406a-89d5-c79b3416733f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582181078 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3582181078
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2868995608
Short name T1095
Test name
Test status
Simulation time 878240089 ps
CPU time 2.73 seconds
Started Jul 20 05:54:16 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 215320 kb
Host smart-89936aac-6a2a-4ff2-84ca-139c73e482fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868995608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2868995608
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3923287687
Short name T1031
Test name
Test status
Simulation time 20149204 ps
CPU time 0.68 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 203740 kb
Host smart-cab79d89-635f-4cc2-9a36-c7acd9b927cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923287687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3923287687
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1300771446
Short name T1066
Test name
Test status
Simulation time 991895580 ps
CPU time 4.1 seconds
Started Jul 20 05:54:13 PM PDT 24
Finished Jul 20 05:54:18 PM PDT 24
Peak memory 215256 kb
Host smart-a672207b-2bdc-479f-b542-e405575ce5c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300771446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1300771446
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3665145941
Short name T161
Test name
Test status
Simulation time 3333813914 ps
CPU time 20.84 seconds
Started Jul 20 05:54:16 PM PDT 24
Finished Jul 20 05:54:38 PM PDT 24
Peak memory 215404 kb
Host smart-9b5b1184-fb47-4c21-93dc-321ab1b3330b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665145941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3665145941
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2270946125
Short name T1081
Test name
Test status
Simulation time 207198484 ps
CPU time 2.77 seconds
Started Jul 20 05:54:18 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 217156 kb
Host smart-7227661e-98ac-4373-a263-31e3a92ea033
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270946125 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2270946125
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.530461500
Short name T112
Test name
Test status
Simulation time 691133217 ps
CPU time 1.31 seconds
Started Jul 20 05:54:21 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 206968 kb
Host smart-181f060c-b2dc-4b90-a9a3-b0c8f072f6a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530461500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.530461500
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3695298833
Short name T1108
Test name
Test status
Simulation time 25837607 ps
CPU time 0.71 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:14 PM PDT 24
Peak memory 204136 kb
Host smart-6266cf9e-c1ad-46e8-b5e1-ade2ebbbee27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695298833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3695298833
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2587130585
Short name T137
Test name
Test status
Simulation time 134366013 ps
CPU time 3.2 seconds
Started Jul 20 05:54:15 PM PDT 24
Finished Jul 20 05:54:19 PM PDT 24
Peak memory 214680 kb
Host smart-0ac1dc7f-2243-4de0-8867-7911176be228
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587130585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2587130585
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1551439824
Short name T1047
Test name
Test status
Simulation time 65326690 ps
CPU time 2.31 seconds
Started Jul 20 05:54:12 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 215336 kb
Host smart-153c0e99-2f0b-4d00-a09c-e416e846cac9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551439824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1551439824
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4053430290
Short name T1086
Test name
Test status
Simulation time 297565161 ps
CPU time 19.88 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:30 PM PDT 24
Peak memory 215316 kb
Host smart-046553c1-c47d-4c7c-83c7-39e9c074e119
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053430290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4053430290
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3111266330
Short name T1106
Test name
Test status
Simulation time 88489875 ps
CPU time 1.83 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:12 PM PDT 24
Peak memory 216452 kb
Host smart-af4b32c8-098b-4904-a727-2751daa21e94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111266330 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3111266330
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1602895516
Short name T116
Test name
Test status
Simulation time 69107997 ps
CPU time 2.67 seconds
Started Jul 20 05:54:08 PM PDT 24
Finished Jul 20 05:54:12 PM PDT 24
Peak memory 207072 kb
Host smart-b6ddacd2-2e4a-4edc-b8f7-4a59b275ae08
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602895516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1602895516
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.585668610
Short name T1034
Test name
Test status
Simulation time 19475078 ps
CPU time 0.81 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 203828 kb
Host smart-bc95c174-b84f-4aaa-b11e-a37352c32755
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585668610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.585668610
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.607388512
Short name T1099
Test name
Test status
Simulation time 63325298 ps
CPU time 3.93 seconds
Started Jul 20 05:54:10 PM PDT 24
Finished Jul 20 05:54:15 PM PDT 24
Peak memory 215268 kb
Host smart-974b3947-1349-4061-86a5-413e82bd7515
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607388512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.607388512
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4126351981
Short name T106
Test name
Test status
Simulation time 185262317 ps
CPU time 1.52 seconds
Started Jul 20 05:54:11 PM PDT 24
Finished Jul 20 05:54:13 PM PDT 24
Peak memory 215408 kb
Host smart-da77b6dd-9e21-4eb6-ac44-cfe4d8b24c6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126351981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4126351981
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2831629237
Short name T165
Test name
Test status
Simulation time 441178920 ps
CPU time 6.83 seconds
Started Jul 20 05:54:21 PM PDT 24
Finished Jul 20 05:54:29 PM PDT 24
Peak memory 215560 kb
Host smart-2d0e942c-5869-4a7e-ac3a-20b90a32a261
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831629237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2831629237
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2273709091
Short name T1059
Test name
Test status
Simulation time 322111289 ps
CPU time 8.4 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 215272 kb
Host smart-198985c4-5b83-4ba9-bdc4-e4404b00066e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273709091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2273709091
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3974028413
Short name T1083
Test name
Test status
Simulation time 1635404071 ps
CPU time 35.32 seconds
Started Jul 20 05:53:51 PM PDT 24
Finished Jul 20 05:54:27 PM PDT 24
Peak memory 215208 kb
Host smart-e0797492-52c5-4861-adbb-c30b4cc848d2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974028413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3974028413
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3482577251
Short name T75
Test name
Test status
Simulation time 121506043 ps
CPU time 1.14 seconds
Started Jul 20 05:53:58 PM PDT 24
Finished Jul 20 05:54:00 PM PDT 24
Peak memory 216228 kb
Host smart-a9607017-bf93-4c4f-bc7b-1849881dfcc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482577251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3482577251
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2727739134
Short name T103
Test name
Test status
Simulation time 43560636 ps
CPU time 1.71 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:53:58 PM PDT 24
Peak memory 215368 kb
Host smart-551df5a9-e305-4ec7-bda2-6ad1fd63743a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727739134 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2727739134
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3414544003
Short name T1052
Test name
Test status
Simulation time 134536270 ps
CPU time 1.27 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 207048 kb
Host smart-87a3cc65-e303-4a57-9835-6195d027e9df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414544003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
414544003
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2125847107
Short name T1020
Test name
Test status
Simulation time 66392348 ps
CPU time 0.68 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:54 PM PDT 24
Peak memory 204140 kb
Host smart-dc08ee6c-c9c0-4fc1-82fd-a1efedd2ab1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125847107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
125847107
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.101332458
Short name T120
Test name
Test status
Simulation time 18449341 ps
CPU time 1.18 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 215396 kb
Host smart-71f246a6-771d-408b-a846-9ef550ea8d6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101332458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_
device_mem_partial_access.101332458
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.626411628
Short name T1062
Test name
Test status
Simulation time 13542034 ps
CPU time 0.69 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 203704 kb
Host smart-a596a220-f92a-4493-9a1b-69fb62e2774c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626411628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.626411628
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1766004655
Short name T1122
Test name
Test status
Simulation time 153144720 ps
CPU time 4.28 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:59 PM PDT 24
Peak memory 215148 kb
Host smart-f1b3a822-7854-410d-add9-f55cc1c1071b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766004655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1766004655
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1701652586
Short name T1080
Test name
Test status
Simulation time 136133436 ps
CPU time 3.49 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 215396 kb
Host smart-6f272a4d-f275-4607-a1d8-eae666610a07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701652586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
701652586
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.577912405
Short name T64
Test name
Test status
Simulation time 862087015 ps
CPU time 8.06 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:54:00 PM PDT 24
Peak memory 222496 kb
Host smart-c8de271d-2f86-4c81-a894-b2f96032f21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577912405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.577912405
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2001183442
Short name T1033
Test name
Test status
Simulation time 12456886 ps
CPU time 0.75 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:11 PM PDT 24
Peak memory 203820 kb
Host smart-02f61690-0fc9-432e-9122-602fe9026415
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001183442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2001183442
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3582400908
Short name T1128
Test name
Test status
Simulation time 61318659 ps
CPU time 0.79 seconds
Started Jul 20 05:54:10 PM PDT 24
Finished Jul 20 05:54:11 PM PDT 24
Peak memory 203740 kb
Host smart-390f063b-44cd-4724-85ff-556baf20c2ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582400908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3582400908
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2764636398
Short name T1022
Test name
Test status
Simulation time 22918784 ps
CPU time 0.73 seconds
Started Jul 20 05:54:22 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 203820 kb
Host smart-19bc5fe6-4c59-456d-92e7-beb4881770dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764636398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2764636398
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.4010655912
Short name T1113
Test name
Test status
Simulation time 171864661 ps
CPU time 0.71 seconds
Started Jul 20 05:54:22 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 203728 kb
Host smart-0f4c1749-7f29-49be-b506-f024d2a754ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010655912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
4010655912
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2551688127
Short name T1042
Test name
Test status
Simulation time 13964083 ps
CPU time 0.77 seconds
Started Jul 20 05:54:22 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 204136 kb
Host smart-126a9f58-3561-4d80-9c57-8fe2e634a422
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551688127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2551688127
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.603082843
Short name T1126
Test name
Test status
Simulation time 29900079 ps
CPU time 0.73 seconds
Started Jul 20 05:54:28 PM PDT 24
Finished Jul 20 05:54:30 PM PDT 24
Peak memory 203832 kb
Host smart-e50b166c-9510-422e-82ed-4cad7c19ac16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603082843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.603082843
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.561115908
Short name T1097
Test name
Test status
Simulation time 15784629 ps
CPU time 0.75 seconds
Started Jul 20 05:54:26 PM PDT 24
Finished Jul 20 05:54:28 PM PDT 24
Peak memory 203840 kb
Host smart-fc47969c-fb31-418f-9d88-526cffe2609e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561115908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.561115908
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.4027336316
Short name T1026
Test name
Test status
Simulation time 12680404 ps
CPU time 0.77 seconds
Started Jul 20 05:54:22 PM PDT 24
Finished Jul 20 05:54:24 PM PDT 24
Peak memory 203800 kb
Host smart-9e1d9b09-c249-4cd1-b495-109266a11b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027336316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
4027336316
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4245421909
Short name T1085
Test name
Test status
Simulation time 57387154 ps
CPU time 0.74 seconds
Started Jul 20 05:54:18 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 203736 kb
Host smart-d9325246-159b-441f-b39d-7d8667233c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245421909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4245421909
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1423392796
Short name T1102
Test name
Test status
Simulation time 16247151 ps
CPU time 0.78 seconds
Started Jul 20 05:54:20 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 203820 kb
Host smart-8a978b16-2b2a-494c-8e4e-7f3ccf86efab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423392796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1423392796
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3831490496
Short name T1021
Test name
Test status
Simulation time 1240019491 ps
CPU time 16.15 seconds
Started Jul 20 05:53:50 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 207104 kb
Host smart-cc0f8b6b-bd3b-4e73-aaf8-7b92a362488f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831490496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3831490496
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3649775434
Short name T1127
Test name
Test status
Simulation time 9417326130 ps
CPU time 36.72 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:54:33 PM PDT 24
Peak memory 207052 kb
Host smart-ad4384f7-3354-4471-8d8c-3d22a398b396
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649775434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3649775434
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3267787455
Short name T77
Test name
Test status
Simulation time 45259995 ps
CPU time 1.03 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 206696 kb
Host smart-c15de7ae-a5b2-48f9-b5ee-4e0192e6b42d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267787455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3267787455
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3574860545
Short name T1112
Test name
Test status
Simulation time 182313220 ps
CPU time 1.96 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 216452 kb
Host smart-7a7b2ccf-025f-430d-a5ad-34cb3ef8962c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574860545 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.3574860545
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3826278290
Short name T110
Test name
Test status
Simulation time 57734324 ps
CPU time 1.23 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 215320 kb
Host smart-e78a10a9-2463-49f5-ae16-82b4c7ee9950
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826278290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
826278290
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3847932820
Short name T1103
Test name
Test status
Simulation time 36111061 ps
CPU time 0.69 seconds
Started Jul 20 05:53:54 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 204136 kb
Host smart-21cea4c6-28e7-4fcb-894b-46371406b962
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847932820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
847932820
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2138512680
Short name T1130
Test name
Test status
Simulation time 461217782 ps
CPU time 1.72 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 215372 kb
Host smart-44804e9f-5bd5-43d8-aae0-1aba51158602
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138512680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2138512680
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4002765907
Short name T1014
Test name
Test status
Simulation time 11698632 ps
CPU time 0.69 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 204028 kb
Host smart-d3385df1-8b91-40f4-a4aa-b2ac32bba9a5
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002765907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4002765907
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1135194386
Short name T1032
Test name
Test status
Simulation time 260317347 ps
CPU time 2.93 seconds
Started Jul 20 05:53:52 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 215232 kb
Host smart-8ac05079-a576-4f64-b507-f7c4753cf55c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135194386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1135194386
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2951693671
Short name T1109
Test name
Test status
Simulation time 88200338 ps
CPU time 2.99 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:56 PM PDT 24
Peak memory 215380 kb
Host smart-acad88cf-6e09-43b5-8636-55c6a55b4a81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951693671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
951693671
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.387591584
Short name T163
Test name
Test status
Simulation time 666735163 ps
CPU time 16.52 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:54:13 PM PDT 24
Peak memory 215236 kb
Host smart-08489770-6ea6-4af1-ae45-0e13c23ce24f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387591584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.387591584
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.2848234907
Short name T1043
Test name
Test status
Simulation time 27360665 ps
CPU time 0.7 seconds
Started Jul 20 05:54:17 PM PDT 24
Finished Jul 20 05:54:19 PM PDT 24
Peak memory 204156 kb
Host smart-ae353226-4c76-46d0-a91c-462b614f4d07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848234907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
2848234907
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.606196157
Short name T1016
Test name
Test status
Simulation time 31452200 ps
CPU time 0.75 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 203764 kb
Host smart-4ecb0859-fbe4-4a9c-b929-6fbda229662e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606196157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.606196157
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3670162753
Short name T1071
Test name
Test status
Simulation time 54041780 ps
CPU time 0.76 seconds
Started Jul 20 05:54:23 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 204040 kb
Host smart-43f4f271-4ae3-4663-ae75-c7dfafea90c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670162753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3670162753
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.1803323993
Short name T1075
Test name
Test status
Simulation time 12198877 ps
CPU time 0.81 seconds
Started Jul 20 05:54:24 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 203804 kb
Host smart-323e7925-b21c-463b-88e9-4c4f02d72eb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803323993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
1803323993
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.2973210228
Short name T1035
Test name
Test status
Simulation time 65325763 ps
CPU time 0.7 seconds
Started Jul 20 05:54:18 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 204120 kb
Host smart-4be11b5a-a8c3-4736-9166-634761caac1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973210228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
2973210228
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1572555129
Short name T1024
Test name
Test status
Simulation time 14924116 ps
CPU time 0.75 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 204136 kb
Host smart-1685a865-3a04-44e2-ba2b-5196455de94f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572555129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1572555129
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2172082254
Short name T1100
Test name
Test status
Simulation time 51683775 ps
CPU time 0.74 seconds
Started Jul 20 05:54:18 PM PDT 24
Finished Jul 20 05:54:20 PM PDT 24
Peak memory 204064 kb
Host smart-1ad8b16b-07ce-4b12-8df1-3ab01bd3b6c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172082254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2172082254
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.980713988
Short name T1050
Test name
Test status
Simulation time 52139941 ps
CPU time 0.77 seconds
Started Jul 20 05:54:20 PM PDT 24
Finished Jul 20 05:54:23 PM PDT 24
Peak memory 204084 kb
Host smart-2c581118-0bd1-4430-83f7-de0d47fa6e5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980713988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.980713988
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2483830392
Short name T1041
Test name
Test status
Simulation time 27433903 ps
CPU time 0.7 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 203820 kb
Host smart-aed6c227-f2b1-415c-9e7c-8360b8d23a27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483830392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2483830392
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1893942177
Short name T1068
Test name
Test status
Simulation time 14106738 ps
CPU time 0.78 seconds
Started Jul 20 05:54:26 PM PDT 24
Finished Jul 20 05:54:27 PM PDT 24
Peak memory 203820 kb
Host smart-c21df59a-e948-43bd-bd43-b06f9dc65a45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893942177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1893942177
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.834454207
Short name T1048
Test name
Test status
Simulation time 1725819840 ps
CPU time 9.61 seconds
Started Jul 20 05:53:59 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 207032 kb
Host smart-c874b993-2257-4550-ad41-e10318c1b39e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834454207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.834454207
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3778234517
Short name T114
Test name
Test status
Simulation time 1116720127 ps
CPU time 33.58 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:38 PM PDT 24
Peak memory 215312 kb
Host smart-249ad2e9-879e-438a-91fa-b6f85ebd1c38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778234517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3778234517
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1225211698
Short name T76
Test name
Test status
Simulation time 74711528 ps
CPU time 1.45 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:03 PM PDT 24
Peak memory 206900 kb
Host smart-516faedc-1a3a-4641-852f-cee49da1c18a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225211698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1225211698
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.833911534
Short name T1038
Test name
Test status
Simulation time 43127409 ps
CPU time 1.62 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215400 kb
Host smart-edef631b-5c51-4274-ad1b-1dc923652198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833911534 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.833911534
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.872209678
Short name T1084
Test name
Test status
Simulation time 173086969 ps
CPU time 1.46 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215248 kb
Host smart-7f5f8816-0ab4-4ff0-a65b-93ad8381c499
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872209678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.872209678
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.183296255
Short name T1120
Test name
Test status
Simulation time 44864547 ps
CPU time 0.72 seconds
Started Jul 20 05:53:55 PM PDT 24
Finished Jul 20 05:53:57 PM PDT 24
Peak memory 204136 kb
Host smart-a4164164-699b-4139-b964-5cf0e33b51a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183296255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.183296255
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3947594756
Short name T115
Test name
Test status
Simulation time 292717058 ps
CPU time 2.13 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:04 PM PDT 24
Peak memory 215304 kb
Host smart-27177719-1a2d-4701-a6cc-650d8f9730d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947594756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3947594756
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.329535630
Short name T1054
Test name
Test status
Simulation time 35320297 ps
CPU time 0.69 seconds
Started Jul 20 05:53:53 PM PDT 24
Finished Jul 20 05:53:55 PM PDT 24
Peak memory 203720 kb
Host smart-cf08fd4e-6770-4cbd-ab5b-c42ea5b0a19e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329535630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.329535630
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1496790365
Short name T136
Test name
Test status
Simulation time 80842446 ps
CPU time 3.91 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215316 kb
Host smart-ac923e19-8503-40db-ae9a-27d755cba357
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496790365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1496790365
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.1594352799
Short name T1070
Test name
Test status
Simulation time 374137857 ps
CPU time 4.69 seconds
Started Jul 20 05:53:54 PM PDT 24
Finished Jul 20 05:54:00 PM PDT 24
Peak memory 215436 kb
Host smart-31484508-2213-4d08-886f-654ef3537d70
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594352799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.1
594352799
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3227983309
Short name T1093
Test name
Test status
Simulation time 698370781 ps
CPU time 7.76 seconds
Started Jul 20 05:53:51 PM PDT 24
Finished Jul 20 05:54:00 PM PDT 24
Peak memory 215416 kb
Host smart-42371332-802a-4ff5-8f6a-c5e716b7abf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227983309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3227983309
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2936805629
Short name T1053
Test name
Test status
Simulation time 18930647 ps
CPU time 0.74 seconds
Started Jul 20 05:54:21 PM PDT 24
Finished Jul 20 05:54:23 PM PDT 24
Peak memory 204140 kb
Host smart-9b65336f-893e-4d2d-beba-efbbab3a997f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936805629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2936805629
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2780663099
Short name T1025
Test name
Test status
Simulation time 88909626 ps
CPU time 0.73 seconds
Started Jul 20 05:54:27 PM PDT 24
Finished Jul 20 05:54:29 PM PDT 24
Peak memory 203836 kb
Host smart-78bd4cd4-5a9c-45a6-a363-750d9b0833e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780663099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2780663099
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.438409097
Short name T1129
Test name
Test status
Simulation time 14900706 ps
CPU time 0.72 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 203816 kb
Host smart-c2f0f42c-5663-47b8-a688-8c60937c1235
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438409097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.438409097
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2158645748
Short name T1079
Test name
Test status
Simulation time 18621942 ps
CPU time 0.77 seconds
Started Jul 20 05:54:21 PM PDT 24
Finished Jul 20 05:54:23 PM PDT 24
Peak memory 203816 kb
Host smart-c0ba3550-e896-43f1-85fc-53a1acca3cac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158645748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2158645748
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2890943247
Short name T1115
Test name
Test status
Simulation time 13456033 ps
CPU time 0.77 seconds
Started Jul 20 05:54:21 PM PDT 24
Finished Jul 20 05:54:23 PM PDT 24
Peak memory 204124 kb
Host smart-4fde56a4-ba56-4b33-82ae-f9a744919fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890943247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2890943247
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3151691678
Short name T1030
Test name
Test status
Simulation time 49013104 ps
CPU time 0.74 seconds
Started Jul 20 05:54:20 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 203772 kb
Host smart-7b5cacff-2067-4b78-87a1-912df6f006e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151691678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3151691678
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1346375436
Short name T1023
Test name
Test status
Simulation time 37967223 ps
CPU time 0.74 seconds
Started Jul 20 05:54:26 PM PDT 24
Finished Jul 20 05:54:27 PM PDT 24
Peak memory 203812 kb
Host smart-513ace41-1b9e-4dd3-acef-27180093aa32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346375436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1346375436
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1010163517
Short name T1061
Test name
Test status
Simulation time 44674932 ps
CPU time 0.71 seconds
Started Jul 20 05:54:24 PM PDT 24
Finished Jul 20 05:54:25 PM PDT 24
Peak memory 203756 kb
Host smart-c9a636a3-7476-46cc-805b-aabb8777e7bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010163517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1010163517
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3071969180
Short name T1015
Test name
Test status
Simulation time 103474086 ps
CPU time 0.76 seconds
Started Jul 20 05:54:19 PM PDT 24
Finished Jul 20 05:54:21 PM PDT 24
Peak memory 204132 kb
Host smart-5528df96-7aec-4a4b-9fb8-1265c3c5fae5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071969180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3071969180
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1007530207
Short name T1117
Test name
Test status
Simulation time 44379000 ps
CPU time 0.8 seconds
Started Jul 20 05:54:20 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 203816 kb
Host smart-40db6a5d-2cf1-4572-899d-41af62bfb7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007530207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1007530207
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1884954126
Short name T105
Test name
Test status
Simulation time 139740067 ps
CPU time 3.54 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:08 PM PDT 24
Peak memory 217144 kb
Host smart-f03f278d-7f2c-41c5-b04c-9303f9b2e520
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884954126 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1884954126
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.2058108035
Short name T121
Test name
Test status
Simulation time 102231723 ps
CPU time 1.88 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:12 PM PDT 24
Peak memory 207132 kb
Host smart-2ae6e6f4-bb12-46ff-962f-1eb9af700dc7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058108035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2
058108035
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3222456585
Short name T1105
Test name
Test status
Simulation time 17454679 ps
CPU time 0.78 seconds
Started Jul 20 05:54:08 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 203760 kb
Host smart-a979883a-f83f-436a-91fb-3e0b0fdfcf0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222456585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
222456585
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3962819262
Short name T146
Test name
Test status
Simulation time 134677734 ps
CPU time 2.94 seconds
Started Jul 20 05:54:02 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215224 kb
Host smart-341a2b38-4c3b-4c45-9a61-f544689178cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962819262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3962819262
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3792805405
Short name T99
Test name
Test status
Simulation time 115105285 ps
CPU time 2.01 seconds
Started Jul 20 05:54:02 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 215460 kb
Host smart-10633f41-3036-43d5-87a5-cfaea36a82eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792805405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
792805405
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2784313020
Short name T92
Test name
Test status
Simulation time 56598829 ps
CPU time 2.09 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215356 kb
Host smart-bdb5623f-48a1-4669-86b8-ed993e20a3d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784313020 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2784313020
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2952032125
Short name T1089
Test name
Test status
Simulation time 37931080 ps
CPU time 2.49 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:12 PM PDT 24
Peak memory 207052 kb
Host smart-aaa8b0f4-4c9c-4334-a816-8f283adeadde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952032125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
952032125
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1327878227
Short name T1087
Test name
Test status
Simulation time 33738744 ps
CPU time 0.72 seconds
Started Jul 20 05:54:08 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 204072 kb
Host smart-fd0a01d7-55cd-4461-b8a4-e340220334e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327878227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
327878227
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.777934852
Short name T1045
Test name
Test status
Simulation time 223452028 ps
CPU time 3.83 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:14 PM PDT 24
Peak memory 215156 kb
Host smart-58facee9-48aa-4666-a6e1-59c9d70b227e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777934852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.777934852
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1397053312
Short name T97
Test name
Test status
Simulation time 967768090 ps
CPU time 3.33 seconds
Started Jul 20 05:54:00 PM PDT 24
Finished Jul 20 05:54:04 PM PDT 24
Peak memory 215380 kb
Host smart-a2fb99ff-e61b-43ae-8504-863a9c1c180e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397053312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
397053312
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.444642723
Short name T162
Test name
Test status
Simulation time 208740470 ps
CPU time 12.09 seconds
Started Jul 20 05:54:09 PM PDT 24
Finished Jul 20 05:54:22 PM PDT 24
Peak memory 215112 kb
Host smart-fab571ba-b9ea-4307-9353-43b2ebe8d492
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444642723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.444642723
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3492722850
Short name T1104
Test name
Test status
Simulation time 340558784 ps
CPU time 2.58 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 217164 kb
Host smart-9c91927f-0b5a-4b97-a9cf-820cff8e44d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492722850 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3492722850
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2149640933
Short name T117
Test name
Test status
Simulation time 55904171 ps
CPU time 1.93 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:08 PM PDT 24
Peak memory 215304 kb
Host smart-c96bad0d-3c37-4bd8-917b-25c75242ea4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149640933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
149640933
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.191089129
Short name T1044
Test name
Test status
Simulation time 38160240 ps
CPU time 0.72 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:08 PM PDT 24
Peak memory 203832 kb
Host smart-aa52cf2e-beb7-467c-8a34-f192fe06b380
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191089129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.191089129
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.2660462662
Short name T1037
Test name
Test status
Simulation time 111881135 ps
CPU time 3.13 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:07 PM PDT 24
Peak memory 215164 kb
Host smart-ec881319-34fe-4b23-9b39-b0291215aa8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660462662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.2660462662
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3335144112
Short name T1046
Test name
Test status
Simulation time 77709913 ps
CPU time 2.79 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 215448 kb
Host smart-4eda968f-cdad-4e58-a659-ee5a9f1b2ce7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335144112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
335144112
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.433262328
Short name T1111
Test name
Test status
Simulation time 109573551 ps
CPU time 2.82 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:08 PM PDT 24
Peak memory 217848 kb
Host smart-6b04b875-a38e-4f52-93e8-cbc7e1ff6df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433262328 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.433262328
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.715637696
Short name T143
Test name
Test status
Simulation time 191841674 ps
CPU time 2.27 seconds
Started Jul 20 05:54:07 PM PDT 24
Finished Jul 20 05:54:10 PM PDT 24
Peak memory 215244 kb
Host smart-edef02bc-2e23-49a5-8a94-ddb73bfa6a0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715637696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.715637696
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3998999181
Short name T1017
Test name
Test status
Simulation time 14292586 ps
CPU time 0.79 seconds
Started Jul 20 05:54:01 PM PDT 24
Finished Jul 20 05:54:02 PM PDT 24
Peak memory 203756 kb
Host smart-9c5cbac2-b9a6-4718-8fe5-7a9687346baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998999181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
998999181
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1528812129
Short name T1090
Test name
Test status
Simulation time 205280496 ps
CPU time 4.52 seconds
Started Jul 20 05:54:00 PM PDT 24
Finished Jul 20 05:54:05 PM PDT 24
Peak memory 215304 kb
Host smart-798390dd-41db-4f2b-9ae6-adc35b29fb44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528812129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1528812129
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.1880097068
Short name T102
Test name
Test status
Simulation time 144115616 ps
CPU time 3.33 seconds
Started Jul 20 05:54:00 PM PDT 24
Finished Jul 20 05:54:04 PM PDT 24
Peak memory 215440 kb
Host smart-c17798fe-02e3-48cf-b723-0ea2730e6b48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880097068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.1
880097068
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.4094621048
Short name T168
Test name
Test status
Simulation time 4253624034 ps
CPU time 22.81 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:29 PM PDT 24
Peak memory 215936 kb
Host smart-c8d327e4-58f4-4b3d-b54c-e1f6e0ce1a85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094621048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.4094621048
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2285330941
Short name T1028
Test name
Test status
Simulation time 132777411 ps
CPU time 3.76 seconds
Started Jul 20 05:54:04 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 217028 kb
Host smart-a4695ed5-e86a-43b6-86b6-adb058b4b9e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285330941 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2285330941
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.1403518786
Short name T111
Test name
Test status
Simulation time 124499307 ps
CPU time 2.46 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:06 PM PDT 24
Peak memory 215272 kb
Host smart-fcc7a366-4ac8-4c8b-8d14-d8073c549e85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403518786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1
403518786
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.351893665
Short name T150
Test name
Test status
Simulation time 15039045 ps
CPU time 0.76 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:04 PM PDT 24
Peak memory 204120 kb
Host smart-0f12c33d-4019-46a2-99c0-cbc3782273d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351893665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.351893665
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3080987301
Short name T1057
Test name
Test status
Simulation time 495797142 ps
CPU time 3.17 seconds
Started Jul 20 05:54:05 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 215324 kb
Host smart-d9658963-9df0-43b9-bce5-c251d7e10f41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080987301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3080987301
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1565308495
Short name T104
Test name
Test status
Simulation time 138447426 ps
CPU time 4.27 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:09 PM PDT 24
Peak memory 215496 kb
Host smart-48672884-5ae5-42db-8d09-7dd7c1003c5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565308495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
565308495
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3729860626
Short name T1049
Test name
Test status
Simulation time 534292708 ps
CPU time 15.18 seconds
Started Jul 20 05:54:03 PM PDT 24
Finished Jul 20 05:54:18 PM PDT 24
Peak memory 215268 kb
Host smart-74147ae2-7b9a-4720-871c-ce092d478d57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729860626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3729860626
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3984603327
Short name T756
Test name
Test status
Simulation time 29288099 ps
CPU time 0.77 seconds
Started Jul 20 06:51:56 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 205368 kb
Host smart-26c478b8-3230-4dbf-9c65-65e4087b0ae3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984603327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
984603327
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1508884917
Short name T546
Test name
Test status
Simulation time 1092694766 ps
CPU time 12.2 seconds
Started Jul 20 06:51:42 PM PDT 24
Finished Jul 20 06:51:56 PM PDT 24
Peak memory 233128 kb
Host smart-8635b59d-7c07-4709-bc4c-fb4f50a87ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508884917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1508884917
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.2572952479
Short name T483
Test name
Test status
Simulation time 47588521 ps
CPU time 0.8 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 207516 kb
Host smart-f83120c7-310b-4afe-ae06-430e16957b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572952479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.2572952479
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1488346044
Short name T982
Test name
Test status
Simulation time 13795812860 ps
CPU time 106.32 seconds
Started Jul 20 06:51:45 PM PDT 24
Finished Jul 20 06:53:32 PM PDT 24
Peak memory 252764 kb
Host smart-81a646b4-e7a9-4194-8e0c-5291430a0db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488346044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1488346044
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2412483614
Short name T743
Test name
Test status
Simulation time 49282792673 ps
CPU time 170.54 seconds
Started Jul 20 06:51:43 PM PDT 24
Finished Jul 20 06:54:35 PM PDT 24
Peak memory 264212 kb
Host smart-290bc729-5452-44f4-b746-f5738963a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412483614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2412483614
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3403313268
Short name T321
Test name
Test status
Simulation time 465779998 ps
CPU time 10.57 seconds
Started Jul 20 06:51:47 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 233132 kb
Host smart-30dc7bf2-fb0c-4c64-a036-2705c3b31019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403313268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3403313268
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.163616103
Short name T190
Test name
Test status
Simulation time 22989328801 ps
CPU time 182.58 seconds
Started Jul 20 06:51:44 PM PDT 24
Finished Jul 20 06:54:48 PM PDT 24
Peak memory 249600 kb
Host smart-deeead55-50e3-4b00-b4cd-ca8781c48b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163616103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
163616103
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3124944658
Short name T355
Test name
Test status
Simulation time 127131692 ps
CPU time 2.64 seconds
Started Jul 20 06:51:47 PM PDT 24
Finished Jul 20 06:51:50 PM PDT 24
Peak memory 232780 kb
Host smart-9594efa3-bd60-4e8a-823d-77668977661a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124944658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3124944658
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3042903932
Short name T477
Test name
Test status
Simulation time 20447436597 ps
CPU time 33.3 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:52:17 PM PDT 24
Peak memory 248720 kb
Host smart-6cd3b70f-857b-4d3b-ab33-d19423aedc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042903932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3042903932
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2486526174
Short name T389
Test name
Test status
Simulation time 2740220084 ps
CPU time 13.34 seconds
Started Jul 20 06:51:40 PM PDT 24
Finished Jul 20 06:51:56 PM PDT 24
Peak memory 239664 kb
Host smart-b4d7bf94-d389-4b79-bd05-3889dc79892c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486526174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2486526174
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2081116698
Short name T612
Test name
Test status
Simulation time 3233959727 ps
CPU time 11.31 seconds
Started Jul 20 06:51:45 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 225044 kb
Host smart-9954689e-61d2-44b4-b4ab-9c5db1eabc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081116698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2081116698
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.218360677
Short name T655
Test name
Test status
Simulation time 84148765 ps
CPU time 4.19 seconds
Started Jul 20 06:51:42 PM PDT 24
Finished Jul 20 06:51:49 PM PDT 24
Peak memory 223540 kb
Host smart-5efb52f1-0c5a-4aaf-ad12-697f9e8cab18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=218360677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direc
t.218360677
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3883617040
Short name T69
Test name
Test status
Simulation time 31592368 ps
CPU time 1.01 seconds
Started Jul 20 06:51:56 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 235940 kb
Host smart-47b0e995-22cc-413e-b025-979cc7f65af1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883617040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3883617040
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.58930266
Short name T504
Test name
Test status
Simulation time 3365135196 ps
CPU time 7.25 seconds
Started Jul 20 06:51:44 PM PDT 24
Finished Jul 20 06:51:53 PM PDT 24
Peak memory 219716 kb
Host smart-244d8f36-4b65-4687-bbbf-9108ee69f651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58930266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.58930266
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3612983798
Short name T492
Test name
Test status
Simulation time 1332759414 ps
CPU time 6.01 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:49 PM PDT 24
Peak memory 216644 kb
Host smart-756ccb93-03b3-450d-a74e-bc876a1f0a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612983798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3612983798
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.693196721
Short name T398
Test name
Test status
Simulation time 74376057 ps
CPU time 0.92 seconds
Started Jul 20 06:51:41 PM PDT 24
Finished Jul 20 06:51:44 PM PDT 24
Peak memory 207096 kb
Host smart-ee940f10-2052-40b4-8fed-85acce46ed5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693196721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.693196721
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.366516412
Short name T659
Test name
Test status
Simulation time 13631143 ps
CPU time 0.71 seconds
Started Jul 20 06:51:47 PM PDT 24
Finished Jul 20 06:51:48 PM PDT 24
Peak memory 206120 kb
Host smart-0c6e88cf-8b94-47b3-8a62-74eb9b6ccf7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366516412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.366516412
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3857244861
Short name T245
Test name
Test status
Simulation time 58726874447 ps
CPU time 48.13 seconds
Started Jul 20 06:51:44 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 233160 kb
Host smart-15c7646c-eadc-4af3-95ec-4d0e4e9f6159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857244861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3857244861
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2262376888
Short name T531
Test name
Test status
Simulation time 47193307 ps
CPU time 0.73 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:51:56 PM PDT 24
Peak memory 205348 kb
Host smart-22dc31db-e886-4268-82b5-ba12c008878a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262376888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
262376888
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2488969558
Short name T257
Test name
Test status
Simulation time 397718560 ps
CPU time 7.55 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:52:03 PM PDT 24
Peak memory 233076 kb
Host smart-dd9dc3bb-9430-423a-baa9-14b742e39566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488969558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2488969558
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2702926541
Short name T723
Test name
Test status
Simulation time 33728355 ps
CPU time 0.81 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:51:56 PM PDT 24
Peak memory 207072 kb
Host smart-ba41ec6f-5c58-4a4e-aaca-254ce716627c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702926541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2702926541
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3587803420
Short name T294
Test name
Test status
Simulation time 104030944922 ps
CPU time 381.61 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:58:20 PM PDT 24
Peak memory 256336 kb
Host smart-99466079-264b-44f7-ad9d-f65ae9c6c22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587803420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3587803420
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1472685386
Short name T301
Test name
Test status
Simulation time 22116040543 ps
CPU time 116.01 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:53:51 PM PDT 24
Peak memory 249676 kb
Host smart-51eb8c8c-3d65-4476-9184-f5c0d7ecc760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472685386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1472685386
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1769832238
Short name T207
Test name
Test status
Simulation time 14034587209 ps
CPU time 88.3 seconds
Started Jul 20 06:51:58 PM PDT 24
Finished Jul 20 06:53:27 PM PDT 24
Peak memory 264948 kb
Host smart-d7b7df05-d737-43d3-9fcf-9ef6bdd45c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769832238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1769832238
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.4040003167
Short name T799
Test name
Test status
Simulation time 2527858452 ps
CPU time 33.4 seconds
Started Jul 20 06:51:59 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 233208 kb
Host smart-dfbdf1fa-0c50-471b-be8c-496a5b229dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040003167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.4040003167
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.4021367216
Short name T172
Test name
Test status
Simulation time 799202470 ps
CPU time 16.43 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:52:11 PM PDT 24
Peak memory 235160 kb
Host smart-bc43a64d-660e-4d9c-baad-296355167e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021367216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.4021367216
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2832071923
Short name T769
Test name
Test status
Simulation time 293532102 ps
CPU time 6.05 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:52:02 PM PDT 24
Peak memory 233076 kb
Host smart-9c6e8bd1-3d80-4ce0-9e18-66daebb6f6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832071923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2832071923
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.2177161466
Short name T256
Test name
Test status
Simulation time 12009591059 ps
CPU time 34.34 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 241128 kb
Host smart-f50c2281-6c85-482c-a2ad-a36f4fefbdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177161466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2177161466
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.771551777
Short name T269
Test name
Test status
Simulation time 1262290355 ps
CPU time 5.76 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:52:00 PM PDT 24
Peak memory 233164 kb
Host smart-a1860594-0034-4a50-80ca-6b9c0ff623a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771551777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
771551777
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1681758374
Short name T1011
Test name
Test status
Simulation time 889072441 ps
CPU time 11.29 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:52:09 PM PDT 24
Peak memory 220692 kb
Host smart-fde18505-c19b-4c3f-97a9-3d22ed3b64fc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1681758374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1681758374
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2349309721
Short name T71
Test name
Test status
Simulation time 271590434 ps
CPU time 1.16 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:51:56 PM PDT 24
Peak memory 236020 kb
Host smart-04bb8661-2900-48f0-807e-1e34993ca3ae
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349309721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2349309721
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1544151829
Short name T548
Test name
Test status
Simulation time 37176193 ps
CPU time 0.98 seconds
Started Jul 20 06:51:56 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 206244 kb
Host smart-29ff247b-bb3d-486d-8064-a158deccc21e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544151829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1544151829
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1653358581
Short name T877
Test name
Test status
Simulation time 4272480216 ps
CPU time 8.13 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:52:03 PM PDT 24
Peak memory 216764 kb
Host smart-be10e5a3-900f-444a-93ed-ce7bb2166a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653358581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1653358581
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3389071484
Short name T942
Test name
Test status
Simulation time 1214315605 ps
CPU time 8.34 seconds
Started Jul 20 06:51:59 PM PDT 24
Finished Jul 20 06:52:08 PM PDT 24
Peak memory 216624 kb
Host smart-144b8d43-787b-407b-b7bf-708ca0c9bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389071484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3389071484
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.429878894
Short name T336
Test name
Test status
Simulation time 245777972 ps
CPU time 0.94 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:51:59 PM PDT 24
Peak memory 207468 kb
Host smart-a6c5029e-a8e1-45d3-8cf4-23eddcacab67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429878894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.429878894
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.778599314
Short name T785
Test name
Test status
Simulation time 62064899 ps
CPU time 0.99 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:51:57 PM PDT 24
Peak memory 206424 kb
Host smart-4f183cc6-0f93-4617-9adb-a129cae9eb17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778599314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.778599314
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.138938967
Short name T288
Test name
Test status
Simulation time 442670544 ps
CPU time 2.92 seconds
Started Jul 20 06:51:58 PM PDT 24
Finished Jul 20 06:52:02 PM PDT 24
Peak memory 233168 kb
Host smart-92025333-be72-4e94-a73a-ba3211925905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138938967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.138938967
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1484608496
Short name T969
Test name
Test status
Simulation time 50346658 ps
CPU time 0.72 seconds
Started Jul 20 06:52:20 PM PDT 24
Finished Jul 20 06:52:22 PM PDT 24
Peak memory 206068 kb
Host smart-2a7579c0-315d-4979-9331-63cf80a65b7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484608496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1484608496
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3462530134
Short name T353
Test name
Test status
Simulation time 4806447295 ps
CPU time 11.97 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:34 PM PDT 24
Peak memory 225020 kb
Host smart-226c7340-de59-40b0-840d-7ec8a4fdeb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462530134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3462530134
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.4194881600
Short name T24
Test name
Test status
Simulation time 65770524 ps
CPU time 0.82 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 207048 kb
Host smart-c8f2ac3d-5f1c-468f-8cf8-cd8ace5963bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194881600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.4194881600
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1959805535
Short name T783
Test name
Test status
Simulation time 115544985103 ps
CPU time 267.64 seconds
Started Jul 20 06:52:23 PM PDT 24
Finished Jul 20 06:56:53 PM PDT 24
Peak memory 255176 kb
Host smart-50f5f3fe-92a8-4296-8614-82f19f9179f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959805535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1959805535
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.608871982
Short name T216
Test name
Test status
Simulation time 290284858545 ps
CPU time 204.09 seconds
Started Jul 20 06:52:20 PM PDT 24
Finished Jul 20 06:55:45 PM PDT 24
Peak memory 251860 kb
Host smart-56d0965e-c69a-468b-a6c0-31df3c3ccc39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608871982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.608871982
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.2127674945
Short name T628
Test name
Test status
Simulation time 46818629263 ps
CPU time 494.55 seconds
Started Jul 20 06:52:17 PM PDT 24
Finished Jul 20 07:00:32 PM PDT 24
Peak memory 267912 kb
Host smart-9a9f60e9-f1fd-4eef-beb2-9850a4fab31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127674945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.2127674945
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.4131887051
Short name T413
Test name
Test status
Simulation time 1860341466 ps
CPU time 12.98 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 241320 kb
Host smart-a4303439-1062-4e18-9339-4f5a131948d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131887051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.4131887051
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1521371830
Short name T816
Test name
Test status
Simulation time 696935325 ps
CPU time 5.62 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 224892 kb
Host smart-4e4a8998-86de-49cf-be7b-6c539062787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521371830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1521371830
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1342325824
Short name T205
Test name
Test status
Simulation time 3259533522 ps
CPU time 10.75 seconds
Started Jul 20 06:52:20 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 225012 kb
Host smart-4dbb4f28-d779-4de0-a409-06495fd2b3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342325824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1342325824
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1768977825
Short name T770
Test name
Test status
Simulation time 5087011027 ps
CPU time 58.2 seconds
Started Jul 20 06:52:16 PM PDT 24
Finished Jul 20 06:53:15 PM PDT 24
Peak memory 233232 kb
Host smart-f1bed4d9-0203-4821-9eec-18e477cd7d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768977825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1768977825
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.658542884
Short name T771
Test name
Test status
Simulation time 566232186 ps
CPU time 4.16 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 233160 kb
Host smart-9453f161-4f39-428d-92f2-a8f8ccc03d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658542884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.658542884
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2164992637
Short name T924
Test name
Test status
Simulation time 2310425815 ps
CPU time 5.67 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:34 PM PDT 24
Peak memory 224988 kb
Host smart-a634adf1-e4cb-4fc6-b3ef-beae89d93d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164992637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2164992637
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3433306940
Short name T427
Test name
Test status
Simulation time 1563116220 ps
CPU time 11.79 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 221996 kb
Host smart-317cd8fa-fb39-4c73-b89d-8c765ab9d4bf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3433306940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3433306940
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.241161518
Short name T907
Test name
Test status
Simulation time 15857812230 ps
CPU time 227.53 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:56:07 PM PDT 24
Peak memory 274244 kb
Host smart-b74cdfda-8669-4aaf-9a03-7a40fb310aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241161518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.241161518
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2690122681
Short name T478
Test name
Test status
Simulation time 10656895930 ps
CPU time 20.32 seconds
Started Jul 20 06:52:23 PM PDT 24
Finished Jul 20 06:52:46 PM PDT 24
Peak memory 216756 kb
Host smart-20d508e2-6840-4868-8bd3-c528f2e4cb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690122681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2690122681
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.710421150
Short name T372
Test name
Test status
Simulation time 2562172731 ps
CPU time 8.09 seconds
Started Jul 20 06:52:17 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 216744 kb
Host smart-3236e159-8e26-4ad1-822e-4bbcc306da6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710421150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.710421150
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.3514719823
Short name T559
Test name
Test status
Simulation time 593369312 ps
CPU time 2.17 seconds
Started Jul 20 06:52:23 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 216656 kb
Host smart-00736dc3-cf60-44de-b239-39c476447eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514719823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.3514719823
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.576440899
Short name T646
Test name
Test status
Simulation time 96160299 ps
CPU time 0.78 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 206444 kb
Host smart-b6523415-3b74-4d41-85c0-0cbbaa146031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576440899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.576440899
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1775579051
Short name T560
Test name
Test status
Simulation time 2202807788 ps
CPU time 6.55 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:30 PM PDT 24
Peak memory 225020 kb
Host smart-ae6424e6-7411-45a0-80e4-f54b20cb0843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775579051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1775579051
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.488982431
Short name T396
Test name
Test status
Simulation time 14450903 ps
CPU time 0.74 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:23 PM PDT 24
Peak memory 206284 kb
Host smart-fbbfe883-a621-4832-9eed-0e138772910a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488982431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.488982431
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3674968588
Short name T825
Test name
Test status
Simulation time 3271317334 ps
CPU time 9.49 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 224940 kb
Host smart-cbea49f0-34ae-474f-a5b7-7ef8c3a20e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674968588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3674968588
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3379189014
Short name T450
Test name
Test status
Simulation time 66151796 ps
CPU time 0.79 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 207380 kb
Host smart-c76f5720-5180-42ae-97b9-5738d60090e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379189014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3379189014
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1611666099
Short name T728
Test name
Test status
Simulation time 34831741886 ps
CPU time 63.38 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:53:25 PM PDT 24
Peak memory 266012 kb
Host smart-8cdded2a-dc69-422a-bb1a-eedc004f8b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611666099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1611666099
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2669263469
Short name T600
Test name
Test status
Simulation time 83456876866 ps
CPU time 196.67 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:55:40 PM PDT 24
Peak memory 252584 kb
Host smart-084526f5-6c7e-46cd-8a77-d35c79c72b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669263469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2669263469
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3645638435
Short name T959
Test name
Test status
Simulation time 45444771448 ps
CPU time 60.77 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:53:29 PM PDT 24
Peak memory 241444 kb
Host smart-e12b2fbf-725d-4199-a144-cc8c8d58091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645638435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3645638435
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.4254301760
Short name T746
Test name
Test status
Simulation time 2047081614 ps
CPU time 9.23 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 225020 kb
Host smart-d0c6f0d9-4af8-4495-a5d2-86bbde599795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254301760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.4254301760
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1821470932
Short name T295
Test name
Test status
Simulation time 88023499914 ps
CPU time 294.59 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:57:14 PM PDT 24
Peak memory 273824 kb
Host smart-40626ccf-e3ae-4f56-ab71-223d351887b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821470932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1821470932
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3632335914
Short name T214
Test name
Test status
Simulation time 740865360 ps
CPU time 6.68 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 224948 kb
Host smart-65696f03-977d-4f51-b74f-aa887612a15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632335914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3632335914
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2210159898
Short name T192
Test name
Test status
Simulation time 322856890 ps
CPU time 7.67 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 224892 kb
Host smart-c52fd6d2-4844-43ee-b430-2c1dc6179dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210159898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2210159898
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2423063128
Short name T902
Test name
Test status
Simulation time 205415385 ps
CPU time 3.53 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 233036 kb
Host smart-41b64b97-8bec-4082-ba09-723899c9d0ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423063128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2423063128
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2676995420
Short name T127
Test name
Test status
Simulation time 5555022195 ps
CPU time 18.32 seconds
Started Jul 20 06:52:20 PM PDT 24
Finished Jul 20 06:52:39 PM PDT 24
Peak memory 233220 kb
Host smart-463bd162-3ee6-4689-b369-2a1f5df1814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676995420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2676995420
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.539653730
Short name T594
Test name
Test status
Simulation time 1839048149 ps
CPU time 7.7 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 220112 kb
Host smart-b4e0cea5-1b3c-4af5-b045-47863f814ac2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539653730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.539653730
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2949863167
Short name T15
Test name
Test status
Simulation time 191206862 ps
CPU time 1.26 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:24 PM PDT 24
Peak memory 207404 kb
Host smart-433d6a6c-ddaf-49f8-9946-44b0f1eeae38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949863167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2949863167
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.628253648
Short name T1008
Test name
Test status
Simulation time 8279258078 ps
CPU time 19.36 seconds
Started Jul 20 06:52:23 PM PDT 24
Finished Jul 20 06:52:45 PM PDT 24
Peak memory 216712 kb
Host smart-bb260adf-b581-48ec-bc6f-0c76f3428888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628253648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.628253648
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4138429214
Short name T977
Test name
Test status
Simulation time 13744498 ps
CPU time 0.72 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 206164 kb
Host smart-6b033f9a-e565-4498-9398-b9293093d0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138429214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4138429214
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.657665681
Short name T6
Test name
Test status
Simulation time 58593170 ps
CPU time 1.38 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:26 PM PDT 24
Peak memory 208492 kb
Host smart-72978554-dcf6-4201-9b17-330a21b37db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657665681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.657665681
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2265339860
Short name T954
Test name
Test status
Simulation time 25575896 ps
CPU time 0.86 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:22 PM PDT 24
Peak memory 206428 kb
Host smart-6698b1ec-9ca2-42a2-ac51-89af939a620e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265339860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2265339860
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.592331542
Short name T763
Test name
Test status
Simulation time 2813561831 ps
CPU time 4.25 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:29 PM PDT 24
Peak memory 233164 kb
Host smart-5845643d-13ff-4ccd-8dbf-e4fb813a6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592331542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.592331542
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.789718983
Short name T866
Test name
Test status
Simulation time 201278490 ps
CPU time 3.88 seconds
Started Jul 20 06:52:33 PM PDT 24
Finished Jul 20 06:52:37 PM PDT 24
Peak memory 225104 kb
Host smart-a1660121-b928-4ebc-990c-a1bafa0f754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789718983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.789718983
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1827095142
Short name T364
Test name
Test status
Simulation time 16988094 ps
CPU time 0.83 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 207188 kb
Host smart-685dea45-0c9c-4b16-9b0a-d0cc5ee6767a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827095142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1827095142
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2304851594
Short name T901
Test name
Test status
Simulation time 4936383017 ps
CPU time 87.67 seconds
Started Jul 20 06:52:37 PM PDT 24
Finished Jul 20 06:54:05 PM PDT 24
Peak memory 250688 kb
Host smart-4909ccc5-98d3-482b-a8f8-d9ca9d148ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304851594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2304851594
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.687520243
Short name T40
Test name
Test status
Simulation time 40893524732 ps
CPU time 122.58 seconds
Started Jul 20 06:52:32 PM PDT 24
Finished Jul 20 06:54:35 PM PDT 24
Peak memory 253144 kb
Host smart-3dc06386-4e80-4ece-b85b-aad6d64466fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687520243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.687520243
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4109260704
Short name T1012
Test name
Test status
Simulation time 521371773 ps
CPU time 7.88 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:39 PM PDT 24
Peak memory 237620 kb
Host smart-fb55bbed-b3f5-4924-8d42-8024acb2081a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109260704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4109260704
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4272150940
Short name T865
Test name
Test status
Simulation time 1862170964 ps
CPU time 27.55 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:58 PM PDT 24
Peak memory 234800 kb
Host smart-5249954a-5d4f-421a-93af-22cbc5872b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272150940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4272150940
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.548254490
Short name T258
Test name
Test status
Simulation time 457747898 ps
CPU time 4.88 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 224868 kb
Host smart-7ef6c504-1105-43e2-ae63-aed391638b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548254490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.548254490
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.646914971
Short name T670
Test name
Test status
Simulation time 58999111 ps
CPU time 2.45 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 232844 kb
Host smart-fadebfde-6d84-4ca2-a82c-e16d0e4d3960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646914971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.646914971
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2674867695
Short name T457
Test name
Test status
Simulation time 483608231 ps
CPU time 3.28 seconds
Started Jul 20 06:52:26 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 224924 kb
Host smart-aea0dd28-e240-4c46-a292-176d20a8bfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674867695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2674867695
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3306223294
Short name T753
Test name
Test status
Simulation time 3171697417 ps
CPU time 14.51 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:41 PM PDT 24
Peak memory 249120 kb
Host smart-f4dc8adc-fa71-489a-9952-7ff6d0abbe2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306223294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3306223294
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1718000182
Short name T363
Test name
Test status
Simulation time 150654137 ps
CPU time 4.65 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 223072 kb
Host smart-177f8251-8b0a-42a2-bb82-6c62d4236ec1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1718000182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1718000182
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.541289253
Short name T721
Test name
Test status
Simulation time 91668118654 ps
CPU time 238.72 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:56:29 PM PDT 24
Peak memory 265684 kb
Host smart-b5a0d1ba-7175-4134-b2aa-6938339d6bb8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541289253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.541289253
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.113336294
Short name T740
Test name
Test status
Simulation time 6728370549 ps
CPU time 40.93 seconds
Started Jul 20 06:52:26 PM PDT 24
Finished Jul 20 06:53:08 PM PDT 24
Peak memory 216984 kb
Host smart-308eb336-17df-4ed5-8ed8-ec1c92d45622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113336294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.113336294
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3141578194
Short name T643
Test name
Test status
Simulation time 1192419906 ps
CPU time 8 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:30 PM PDT 24
Peak memory 216828 kb
Host smart-1bd92094-0e2a-431d-9fb3-0dd9e88bd15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141578194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3141578194
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1757100593
Short name T439
Test name
Test status
Simulation time 28631246 ps
CPU time 1.25 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 216664 kb
Host smart-71ee3936-efcf-46d7-8098-259ef8d050fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757100593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1757100593
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3116685447
Short name T1007
Test name
Test status
Simulation time 848740251 ps
CPU time 0.96 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 206104 kb
Host smart-47edbdfb-a709-4daf-9083-98bd037e8d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116685447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3116685447
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4056554638
Short name T620
Test name
Test status
Simulation time 104990053 ps
CPU time 2.56 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:22 PM PDT 24
Peak memory 233136 kb
Host smart-a42d0b9f-fdb8-4b2a-8535-e7a7b737808b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056554638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4056554638
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4215676216
Short name T997
Test name
Test status
Simulation time 14486060 ps
CPU time 0.72 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 205372 kb
Host smart-de025f0f-3416-45da-b5d5-7ffcb60f0093
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215676216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4215676216
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1809554707
Short name T586
Test name
Test status
Simulation time 933412973 ps
CPU time 5.57 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 233124 kb
Host smart-bb40d28c-edf2-48b9-bd85-9912842b656a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809554707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1809554707
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1602608684
Short name T937
Test name
Test status
Simulation time 23317728 ps
CPU time 0.75 seconds
Started Jul 20 06:52:30 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 206332 kb
Host smart-a0c53912-f8c0-4532-8ad0-07dd98f4423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602608684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1602608684
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1346214218
Short name T368
Test name
Test status
Simulation time 21537123 ps
CPU time 0.81 seconds
Started Jul 20 06:52:28 PM PDT 24
Finished Jul 20 06:52:30 PM PDT 24
Peak memory 216072 kb
Host smart-7e737a5f-60c2-4311-975f-fd4200e3f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346214218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1346214218
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2983269316
Short name T629
Test name
Test status
Simulation time 1289270472 ps
CPU time 15.46 seconds
Started Jul 20 06:52:28 PM PDT 24
Finished Jul 20 06:52:45 PM PDT 24
Peak memory 233132 kb
Host smart-408a0a1b-20dc-469f-b630-65b2c59d4913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983269316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2983269316
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2829407791
Short name T822
Test name
Test status
Simulation time 21111591653 ps
CPU time 168.83 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:55:18 PM PDT 24
Peak memory 254824 kb
Host smart-a0d9146c-839c-42fc-aa68-c1eb247d0d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829407791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2829407791
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3757173870
Short name T912
Test name
Test status
Simulation time 3249827967 ps
CPU time 6.35 seconds
Started Jul 20 06:52:33 PM PDT 24
Finished Jul 20 06:52:40 PM PDT 24
Peak memory 224996 kb
Host smart-46f25481-758c-4263-874a-d7559326e37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757173870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3757173870
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3448184998
Short name T871
Test name
Test status
Simulation time 207562782 ps
CPU time 2.5 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 233140 kb
Host smart-e5255afb-d754-4e80-a683-3d36e02640b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448184998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3448184998
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.98520891
Short name T284
Test name
Test status
Simulation time 1873836534 ps
CPU time 7.25 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 233120 kb
Host smart-11048a90-96e4-4087-9ba7-69d8ee93f172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98520891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.98520891
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.4143042928
Short name T90
Test name
Test status
Simulation time 6783774126 ps
CPU time 12.99 seconds
Started Jul 20 06:52:28 PM PDT 24
Finished Jul 20 06:52:43 PM PDT 24
Peak memory 224972 kb
Host smart-0ccc8d2b-16ef-474e-8861-5105a8e8a45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143042928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.4143042928
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3701185989
Short name T614
Test name
Test status
Simulation time 392987938 ps
CPU time 3.82 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:35 PM PDT 24
Peak memory 223660 kb
Host smart-403927dd-69bc-4770-abb5-2085485d35ec
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3701185989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3701185989
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1734692314
Short name T758
Test name
Test status
Simulation time 6258127985 ps
CPU time 23.93 seconds
Started Jul 20 06:52:30 PM PDT 24
Finished Jul 20 06:52:55 PM PDT 24
Peak memory 217052 kb
Host smart-c6db7061-c1f7-4489-abc1-880239640ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734692314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1734692314
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3450255999
Short name T82
Test name
Test status
Simulation time 10083929931 ps
CPU time 8.07 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:52:39 PM PDT 24
Peak memory 216680 kb
Host smart-3b68292e-fb2c-40e8-9b48-bce68e74fbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450255999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3450255999
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3974106214
Short name T573
Test name
Test status
Simulation time 202443042 ps
CPU time 3.84 seconds
Started Jul 20 06:52:33 PM PDT 24
Finished Jul 20 06:52:38 PM PDT 24
Peak memory 216704 kb
Host smart-dd49cdc6-1bea-4e53-8660-892379d6a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974106214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3974106214
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.645554145
Short name T611
Test name
Test status
Simulation time 28573770 ps
CPU time 0.82 seconds
Started Jul 20 06:52:30 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 206452 kb
Host smart-547502fb-45a7-4e21-92be-e6023935ea21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645554145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.645554145
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3127419935
Short name T465
Test name
Test status
Simulation time 3968351213 ps
CPU time 4.34 seconds
Started Jul 20 06:52:30 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 225020 kb
Host smart-232d3224-fa6b-4b11-a845-b521db533348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127419935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3127419935
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2241213659
Short name T4
Test name
Test status
Simulation time 14487245 ps
CPU time 0.69 seconds
Started Jul 20 06:52:36 PM PDT 24
Finished Jul 20 06:52:38 PM PDT 24
Peak memory 205344 kb
Host smart-342d3865-dd07-4164-943d-42b15a8c6cf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241213659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2241213659
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3276810719
Short name T616
Test name
Test status
Simulation time 74304236 ps
CPU time 2.27 seconds
Started Jul 20 06:52:36 PM PDT 24
Finished Jul 20 06:52:40 PM PDT 24
Peak memory 224508 kb
Host smart-b5ac10f3-eb42-48d4-9764-0500d13e08f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276810719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3276810719
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3882680268
Short name T961
Test name
Test status
Simulation time 63237535 ps
CPU time 0.79 seconds
Started Jul 20 06:52:31 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 207520 kb
Host smart-b090c155-0e6a-4ad8-80c7-7fc1e10e8bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882680268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3882680268
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.945089127
Short name T290
Test name
Test status
Simulation time 2910730075 ps
CPU time 66.04 seconds
Started Jul 20 06:52:42 PM PDT 24
Finished Jul 20 06:53:49 PM PDT 24
Peak memory 273920 kb
Host smart-cb18e9a4-f128-42cf-8247-43cc6b258414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945089127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.945089127
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.513779841
Short name T656
Test name
Test status
Simulation time 38924643871 ps
CPU time 398.05 seconds
Started Jul 20 06:52:40 PM PDT 24
Finished Jul 20 06:59:19 PM PDT 24
Peak memory 257844 kb
Host smart-01aeca83-7150-4dfc-82b4-0dffe7f806a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513779841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.513779841
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1958154647
Short name T2
Test name
Test status
Simulation time 20771718929 ps
CPU time 121.66 seconds
Started Jul 20 06:52:38 PM PDT 24
Finished Jul 20 06:54:40 PM PDT 24
Peak memory 249628 kb
Host smart-c9862cbc-640d-4f66-b43b-b5d5be39279a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958154647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1958154647
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1833291820
Short name T664
Test name
Test status
Simulation time 1774154546 ps
CPU time 29.22 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 224952 kb
Host smart-3b56dcee-a2ea-470f-8fb4-062cdb42c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833291820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1833291820
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.311071921
Short name T818
Test name
Test status
Simulation time 2862999514 ps
CPU time 58.45 seconds
Started Jul 20 06:52:34 PM PDT 24
Finished Jul 20 06:53:34 PM PDT 24
Peak memory 255964 kb
Host smart-afe97383-c8bb-4eab-b53e-6bf68def345a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311071921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.311071921
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.1766796027
Short name T579
Test name
Test status
Simulation time 538517813 ps
CPU time 3.73 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 224924 kb
Host smart-33aad5f4-c54e-4a38-81e4-fe254b1a2f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766796027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.1766796027
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1395636247
Short name T571
Test name
Test status
Simulation time 3245142060 ps
CPU time 19.8 seconds
Started Jul 20 06:52:34 PM PDT 24
Finished Jul 20 06:52:54 PM PDT 24
Peak memory 224988 kb
Host smart-fb32f353-6b7c-4b60-8aeb-2a900f5544ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395636247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1395636247
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.529326282
Short name T314
Test name
Test status
Simulation time 902158072 ps
CPU time 4.74 seconds
Started Jul 20 06:52:30 PM PDT 24
Finished Jul 20 06:52:36 PM PDT 24
Peak memory 224884 kb
Host smart-8e25e814-fe16-41d8-b89d-cdf8aae4e814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529326282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.529326282
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3944462985
Short name T43
Test name
Test status
Simulation time 957980628 ps
CPU time 5.46 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:34 PM PDT 24
Peak memory 241040 kb
Host smart-3b638635-53a9-4b08-b9da-2fefacee0d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944462985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3944462985
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.4056300604
Short name T109
Test name
Test status
Simulation time 79695544 ps
CPU time 3.55 seconds
Started Jul 20 06:52:38 PM PDT 24
Finished Jul 20 06:52:42 PM PDT 24
Peak memory 223676 kb
Host smart-ef44d6f5-5ab1-4b95-8664-90624aa8da6d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056300604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.4056300604
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1402367925
Short name T131
Test name
Test status
Simulation time 4054274769 ps
CPU time 111.85 seconds
Started Jul 20 06:52:37 PM PDT 24
Finished Jul 20 06:54:29 PM PDT 24
Peak memory 264352 kb
Host smart-5a59d847-a474-45b8-870c-409acc560f46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402367925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1402367925
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3741740920
Short name T647
Test name
Test status
Simulation time 15823866570 ps
CPU time 45.5 seconds
Started Jul 20 06:52:29 PM PDT 24
Finished Jul 20 06:53:16 PM PDT 24
Peak memory 216820 kb
Host smart-fc9266e9-2dcd-4f4d-bfe1-510737912122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741740920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3741740920
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.4032734839
Short name T432
Test name
Test status
Simulation time 28969864248 ps
CPU time 19.45 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:55 PM PDT 24
Peak memory 217028 kb
Host smart-e4af7fee-519f-4295-9c26-d18239326d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032734839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.4032734839
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3545053422
Short name T130
Test name
Test status
Simulation time 57974094 ps
CPU time 0.84 seconds
Started Jul 20 06:52:30 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 207120 kb
Host smart-c33d7ae2-5f00-43cf-9062-36819cd088ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545053422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3545053422
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.2324943688
Short name T896
Test name
Test status
Simulation time 13034367 ps
CPU time 0.72 seconds
Started Jul 20 06:52:27 PM PDT 24
Finished Jul 20 06:52:30 PM PDT 24
Peak memory 206444 kb
Host smart-422c9218-beca-44b5-b83a-5a2268615196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324943688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.2324943688
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1507193485
Short name T47
Test name
Test status
Simulation time 30155373047 ps
CPU time 52.01 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:53:27 PM PDT 24
Peak memory 241424 kb
Host smart-f2846636-e696-48f5-8f39-77ee0557192a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507193485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1507193485
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3850813806
Short name T366
Test name
Test status
Simulation time 25658528 ps
CPU time 0.74 seconds
Started Jul 20 06:52:44 PM PDT 24
Finished Jul 20 06:52:46 PM PDT 24
Peak memory 205368 kb
Host smart-ac6ed992-b7c1-4542-80a5-f03dcbbc0d49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850813806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3850813806
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.549026679
Short name T514
Test name
Test status
Simulation time 112571669 ps
CPU time 0.78 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:37 PM PDT 24
Peak memory 207068 kb
Host smart-9bb0c6d2-c40a-46fb-a02b-cf1d22e78a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549026679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.549026679
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2910543961
Short name T428
Test name
Test status
Simulation time 23680378 ps
CPU time 0.75 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:52:42 PM PDT 24
Peak memory 216232 kb
Host smart-4b919b8f-0591-4575-9e0f-c878e107ce06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910543961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2910543961
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1096284459
Short name T342
Test name
Test status
Simulation time 3136792033 ps
CPU time 10.38 seconds
Started Jul 20 06:52:44 PM PDT 24
Finished Jul 20 06:52:55 PM PDT 24
Peak memory 217868 kb
Host smart-f2ab55f1-5fd3-485b-8f5a-accd179ec210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096284459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1096284459
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1942765745
Short name T506
Test name
Test status
Simulation time 17098436909 ps
CPU time 143.56 seconds
Started Jul 20 06:52:38 PM PDT 24
Finished Jul 20 06:55:02 PM PDT 24
Peak memory 256352 kb
Host smart-6cc56ce2-b82e-419f-9d61-add5089a74fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942765745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1942765745
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.499930148
Short name T249
Test name
Test status
Simulation time 489290990 ps
CPU time 5.91 seconds
Started Jul 20 06:52:36 PM PDT 24
Finished Jul 20 06:52:43 PM PDT 24
Peak memory 233164 kb
Host smart-44bfb960-662f-4dd0-8615-28366e9b03a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499930148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.499930148
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1773115643
Short name T575
Test name
Test status
Simulation time 2448105628 ps
CPU time 6.84 seconds
Started Jul 20 06:52:40 PM PDT 24
Finished Jul 20 06:52:48 PM PDT 24
Peak memory 224956 kb
Host smart-c8ff8b9f-55af-49d2-8b01-a469a0a945c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773115643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1773115643
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.595852659
Short name T700
Test name
Test status
Simulation time 4442165464 ps
CPU time 4.18 seconds
Started Jul 20 06:52:37 PM PDT 24
Finished Jul 20 06:52:42 PM PDT 24
Peak memory 233168 kb
Host smart-c0e85f5c-1247-4657-acbb-4fc6d6f37444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595852659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap
.595852659
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1662744470
Short name T421
Test name
Test status
Simulation time 720010428 ps
CPU time 12.45 seconds
Started Jul 20 06:52:34 PM PDT 24
Finished Jul 20 06:52:47 PM PDT 24
Peak memory 235640 kb
Host smart-9c9295a6-09a4-4954-9ffc-0bc389b52760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662744470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1662744470
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3865740172
Short name T983
Test name
Test status
Simulation time 75606672 ps
CPU time 3.71 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:40 PM PDT 24
Peak memory 220240 kb
Host smart-74d4b071-cf00-4851-a064-3b81812a354b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3865740172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3865740172
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.773815545
Short name T613
Test name
Test status
Simulation time 90782233 ps
CPU time 1.05 seconds
Started Jul 20 06:52:40 PM PDT 24
Finished Jul 20 06:52:42 PM PDT 24
Peak memory 208204 kb
Host smart-6fe2ce6d-0ad9-4422-8789-52d64bfcb9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773815545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.773815545
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.612436880
Short name T921
Test name
Test status
Simulation time 2968538710 ps
CPU time 18.79 seconds
Started Jul 20 06:52:37 PM PDT 24
Finished Jul 20 06:52:57 PM PDT 24
Peak memory 216804 kb
Host smart-cc6dfb8a-0399-4447-9f39-ab1c502d2e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612436880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.612436880
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2144262314
Short name T831
Test name
Test status
Simulation time 3701649509 ps
CPU time 3.26 seconds
Started Jul 20 06:52:38 PM PDT 24
Finished Jul 20 06:52:42 PM PDT 24
Peak memory 216708 kb
Host smart-487605e0-5fad-4a99-8ebe-353fb0ee0d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144262314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2144262314
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4266204495
Short name T393
Test name
Test status
Simulation time 88642403 ps
CPU time 1.1 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:37 PM PDT 24
Peak memory 208216 kb
Host smart-8603034e-09dd-4d7f-8e77-5339d699e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266204495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4266204495
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3236253538
Short name T963
Test name
Test status
Simulation time 32308512 ps
CPU time 0.91 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:37 PM PDT 24
Peak memory 207464 kb
Host smart-d558fd3c-1d19-4511-bb7d-554df74256bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236253538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3236253538
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1897826728
Short name T471
Test name
Test status
Simulation time 2965517541 ps
CPU time 6.03 seconds
Started Jul 20 06:52:35 PM PDT 24
Finished Jul 20 06:52:43 PM PDT 24
Peak memory 229628 kb
Host smart-de96532e-a574-4f06-a893-1cf380752034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897826728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1897826728
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1518708611
Short name T472
Test name
Test status
Simulation time 42252385 ps
CPU time 0.75 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:52:49 PM PDT 24
Peak memory 205364 kb
Host smart-91b3b1d5-0834-4e74-b2dc-8154cff8fb44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518708611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1518708611
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.550879425
Short name T266
Test name
Test status
Simulation time 460401846 ps
CPU time 7.54 seconds
Started Jul 20 06:52:40 PM PDT 24
Finished Jul 20 06:52:48 PM PDT 24
Peak memory 233160 kb
Host smart-e9caceb5-c2ac-4e17-97ba-1f8e3ff19ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550879425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.550879425
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.193427610
Short name T835
Test name
Test status
Simulation time 19810726 ps
CPU time 0.74 seconds
Started Jul 20 06:52:39 PM PDT 24
Finished Jul 20 06:52:41 PM PDT 24
Peak memory 207392 kb
Host smart-56e49525-f678-43d3-944f-6f430a33a174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193427610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.193427610
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.745099057
Short name T451
Test name
Test status
Simulation time 7202423871 ps
CPU time 88.35 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:54:11 PM PDT 24
Peak memory 250460 kb
Host smart-98986ff7-19cd-42ca-8a8a-50d4f2713638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745099057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.745099057
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3569868630
Short name T299
Test name
Test status
Simulation time 48957929531 ps
CPU time 128.65 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:54:50 PM PDT 24
Peak memory 252428 kb
Host smart-41332eca-ac7d-43e7-aee2-c0af44700a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569868630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3569868630
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3311473268
Short name T14
Test name
Test status
Simulation time 677885248 ps
CPU time 4.27 seconds
Started Jul 20 06:52:43 PM PDT 24
Finished Jul 20 06:52:48 PM PDT 24
Peak memory 224924 kb
Host smart-66e28ec9-dc40-4895-b86e-8c8289fa6e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311473268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3311473268
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2884263878
Short name T202
Test name
Test status
Simulation time 15580241513 ps
CPU time 39.86 seconds
Started Jul 20 06:52:44 PM PDT 24
Finished Jul 20 06:53:24 PM PDT 24
Peak memory 241416 kb
Host smart-b79bd84c-551f-4e87-9382-864cfb0eb785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884263878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2884263878
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.4103695428
Short name T974
Test name
Test status
Simulation time 872548091 ps
CPU time 11.42 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 233092 kb
Host smart-9cb083d5-be16-4a82-bede-7b30dcdaba3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103695428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.4103695428
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4199164773
Short name T657
Test name
Test status
Simulation time 17595969988 ps
CPU time 38.83 seconds
Started Jul 20 06:52:43 PM PDT 24
Finished Jul 20 06:53:22 PM PDT 24
Peak memory 233152 kb
Host smart-b6916de6-ddac-47f6-a651-5ea71703fe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199164773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4199164773
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3516448429
Short name T726
Test name
Test status
Simulation time 2962585972 ps
CPU time 15.6 seconds
Started Jul 20 06:52:44 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 225024 kb
Host smart-651d113a-6661-4a38-9387-f5abff293bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516448429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3516448429
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2669951456
Short name T54
Test name
Test status
Simulation time 716470693 ps
CPU time 8.52 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:52:50 PM PDT 24
Peak memory 233092 kb
Host smart-f5a92799-e45a-4cb1-9a43-252f313e6031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669951456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2669951456
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4056684486
Short name T431
Test name
Test status
Simulation time 188381457 ps
CPU time 4.32 seconds
Started Jul 20 06:52:39 PM PDT 24
Finished Jul 20 06:52:44 PM PDT 24
Peak memory 219264 kb
Host smart-686d15b6-cd00-4c51-91e0-2575c44bf5e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4056684486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4056684486
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2787894031
Short name T21
Test name
Test status
Simulation time 78117074 ps
CPU time 1.21 seconds
Started Jul 20 06:52:39 PM PDT 24
Finished Jul 20 06:52:41 PM PDT 24
Peak memory 207300 kb
Host smart-3c6c8654-45d1-4973-a2af-af1d23387d3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787894031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2787894031
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1420104115
Short name T455
Test name
Test status
Simulation time 7011536171 ps
CPU time 19.46 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:53:02 PM PDT 24
Peak memory 216528 kb
Host smart-b8a1060b-de84-4fb5-b8eb-b9468a941d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420104115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1420104115
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.771119795
Short name T696
Test name
Test status
Simulation time 1566723231 ps
CPU time 4.47 seconds
Started Jul 20 06:52:40 PM PDT 24
Finished Jul 20 06:52:45 PM PDT 24
Peak memory 216636 kb
Host smart-e014173d-ce1b-4807-abde-24747bf9f27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771119795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.771119795
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1845321597
Short name T400
Test name
Test status
Simulation time 66625826 ps
CPU time 1.09 seconds
Started Jul 20 06:52:44 PM PDT 24
Finished Jul 20 06:52:45 PM PDT 24
Peak memory 208364 kb
Host smart-54e5a1f8-9cf7-4162-802b-b9264d2e4733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845321597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1845321597
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.631259190
Short name T442
Test name
Test status
Simulation time 170074044 ps
CPU time 0.74 seconds
Started Jul 20 06:52:44 PM PDT 24
Finished Jul 20 06:52:45 PM PDT 24
Peak memory 206412 kb
Host smart-ecd9ed1a-3ecc-4063-8657-0da05a8d058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631259190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.631259190
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3820335033
Short name T838
Test name
Test status
Simulation time 142742389 ps
CPU time 4.9 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:52:47 PM PDT 24
Peak memory 235188 kb
Host smart-c214c5b0-5a20-41c4-86e2-1b03265e27a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820335033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3820335033
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.206764219
Short name T63
Test name
Test status
Simulation time 11835064 ps
CPU time 0.76 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:51 PM PDT 24
Peak memory 205928 kb
Host smart-55f50846-9318-4c62-9940-8658d5280260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206764219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.206764219
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.1017935849
Short name T278
Test name
Test status
Simulation time 5040130998 ps
CPU time 32.15 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:53:23 PM PDT 24
Peak memory 224996 kb
Host smart-3dc33a2f-5157-4ed4-a391-03d78496d2f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017935849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1017935849
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1811043159
Short name T971
Test name
Test status
Simulation time 15771652 ps
CPU time 0.76 seconds
Started Jul 20 06:52:41 PM PDT 24
Finished Jul 20 06:52:43 PM PDT 24
Peak memory 206344 kb
Host smart-8349ff57-9dd5-4bd0-b3c3-4225b9db9c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811043159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1811043159
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3136349667
Short name T218
Test name
Test status
Simulation time 7679967954 ps
CPU time 75.04 seconds
Started Jul 20 06:52:47 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 256036 kb
Host smart-705db3b7-4a8d-4088-9c54-cba258d8e7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136349667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3136349667
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.538147613
Short name T208
Test name
Test status
Simulation time 3213818185 ps
CPU time 87.44 seconds
Started Jul 20 06:52:47 PM PDT 24
Finished Jul 20 06:54:15 PM PDT 24
Peak memory 257516 kb
Host smart-8903da18-93cd-4eec-8699-4e974f74b1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538147613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.538147613
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2365998222
Short name T553
Test name
Test status
Simulation time 7917393405 ps
CPU time 56.29 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:53:45 PM PDT 24
Peak memory 250544 kb
Host smart-aa0c8108-a9ca-4866-93da-26eca08b047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365998222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2365998222
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.2583919009
Short name T918
Test name
Test status
Simulation time 77036355 ps
CPU time 2.58 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:53 PM PDT 24
Peak memory 224872 kb
Host smart-67fefb7e-2eb2-480f-9bad-1bfe12e05740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583919009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.2583919009
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.430248418
Short name T544
Test name
Test status
Simulation time 1757351358 ps
CPU time 37.7 seconds
Started Jul 20 06:52:50 PM PDT 24
Finished Jul 20 06:53:29 PM PDT 24
Peak memory 249540 kb
Host smart-2f06f41a-ca54-47e5-906a-d3bc370782cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430248418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.430248418
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1241637661
Short name T623
Test name
Test status
Simulation time 11535747039 ps
CPU time 20.1 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:53:10 PM PDT 24
Peak memory 233152 kb
Host smart-bd8894a7-ab36-4ab4-b832-c1bc315c5c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241637661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1241637661
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1809753907
Short name T827
Test name
Test status
Simulation time 2473532273 ps
CPU time 9.81 seconds
Started Jul 20 06:52:47 PM PDT 24
Finished Jul 20 06:52:57 PM PDT 24
Peak memory 233136 kb
Host smart-2fce55b1-af01-4a45-b925-061e39f1fced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809753907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1809753907
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.441363382
Short name T270
Test name
Test status
Simulation time 3340155330 ps
CPU time 15.3 seconds
Started Jul 20 06:52:52 PM PDT 24
Finished Jul 20 06:53:07 PM PDT 24
Peak memory 239664 kb
Host smart-34c35f13-df68-4586-b7ac-c839349274eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441363382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.441363382
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.702335200
Short name T852
Test name
Test status
Simulation time 541070967 ps
CPU time 6.03 seconds
Started Jul 20 06:52:51 PM PDT 24
Finished Jul 20 06:52:57 PM PDT 24
Peak memory 241276 kb
Host smart-a790bab9-dbce-4957-9014-05ee2998a960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702335200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.702335200
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.831803636
Short name T108
Test name
Test status
Simulation time 5672363769 ps
CPU time 7.04 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:52:56 PM PDT 24
Peak memory 219732 kb
Host smart-7f998019-b2cc-425f-a323-c3727af8c896
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=831803636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.831803636
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.322318924
Short name T149
Test name
Test status
Simulation time 32917080535 ps
CPU time 60.68 seconds
Started Jul 20 06:52:52 PM PDT 24
Finished Jul 20 06:53:53 PM PDT 24
Peak memory 251672 kb
Host smart-c4f15cc0-054e-48fb-a011-3d9dc1b4400e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322318924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.322318924
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3911375786
Short name T486
Test name
Test status
Simulation time 28660178965 ps
CPU time 14.5 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:53:05 PM PDT 24
Peak memory 216880 kb
Host smart-6704c7a6-e499-483f-98b2-7bced914deb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911375786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3911375786
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3374622842
Short name T842
Test name
Test status
Simulation time 18808808805 ps
CPU time 8.4 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:58 PM PDT 24
Peak memory 216820 kb
Host smart-8a329046-3150-45f3-8feb-907cf30c186d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374622842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3374622842
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2477118176
Short name T369
Test name
Test status
Simulation time 72660278 ps
CPU time 1.97 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:52:51 PM PDT 24
Peak memory 216624 kb
Host smart-835b376b-f3f8-4e95-8748-0dcb973116ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477118176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2477118176
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3279428935
Short name T582
Test name
Test status
Simulation time 16862913 ps
CPU time 0.76 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:52:50 PM PDT 24
Peak memory 206452 kb
Host smart-d0de3e91-21c5-4af8-9d0f-845caa9f32c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279428935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3279428935
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.537197256
Short name T671
Test name
Test status
Simulation time 385487537 ps
CPU time 4.36 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:52:54 PM PDT 24
Peak memory 224964 kb
Host smart-3283bd6d-c783-4d67-bfea-856c8247b3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537197256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.537197256
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2535453885
Short name T1013
Test name
Test status
Simulation time 20777562 ps
CPU time 0.76 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 205336 kb
Host smart-7e19eba8-fedb-4d42-a6ae-edd34b2ec51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535453885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2535453885
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2021832221
Short name T496
Test name
Test status
Simulation time 852160094 ps
CPU time 2.79 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:53 PM PDT 24
Peak memory 233144 kb
Host smart-90a542eb-ec5a-46b9-8bd7-62132d8db839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021832221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2021832221
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3218843974
Short name T379
Test name
Test status
Simulation time 18526389 ps
CPU time 0.75 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:51 PM PDT 24
Peak memory 206044 kb
Host smart-1ffc7423-f578-434d-a868-ba2cc5d2623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218843974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3218843974
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3748563103
Short name T254
Test name
Test status
Simulation time 856633202 ps
CPU time 20.84 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:21 PM PDT 24
Peak memory 249576 kb
Host smart-f7086275-f041-4440-b2d3-2dbecd8d5e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748563103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3748563103
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2864769500
Short name T786
Test name
Test status
Simulation time 1935876402 ps
CPU time 34.9 seconds
Started Jul 20 06:52:57 PM PDT 24
Finished Jul 20 06:53:33 PM PDT 24
Peak memory 225000 kb
Host smart-9d417656-80f8-4b98-910b-81b9a2fc374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864769500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2864769500
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2422365573
Short name T929
Test name
Test status
Simulation time 1319468840 ps
CPU time 18.4 seconds
Started Jul 20 06:52:57 PM PDT 24
Finished Jul 20 06:53:17 PM PDT 24
Peak memory 233028 kb
Host smart-874db5a5-90ca-4c78-a7e3-b243e3a86b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422365573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2422365573
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.29418318
Short name T500
Test name
Test status
Simulation time 58353984 ps
CPU time 3.39 seconds
Started Jul 20 06:52:50 PM PDT 24
Finished Jul 20 06:52:54 PM PDT 24
Peak memory 233168 kb
Host smart-12a9a1c0-88ec-4284-8b5f-52de8a14f844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29418318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.29418318
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3661364613
Short name T688
Test name
Test status
Simulation time 6576959086 ps
CPU time 16.93 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:53:07 PM PDT 24
Peak memory 241132 kb
Host smart-95c83f86-7769-4a74-9025-7cf54ae39b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661364613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3661364613
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.1613650026
Short name T837
Test name
Test status
Simulation time 222953788 ps
CPU time 3.14 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:54 PM PDT 24
Peak memory 224888 kb
Host smart-ed58d05c-e5a3-4d89-bc4e-6193416d4c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613650026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.1613650026
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3304300703
Short name T238
Test name
Test status
Simulation time 4913371404 ps
CPU time 10.9 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 225020 kb
Host smart-a998ff40-55db-40d9-9be9-f2ba62bb5ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304300703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3304300703
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1858452806
Short name T3
Test name
Test status
Simulation time 151069745 ps
CPU time 4.91 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:04 PM PDT 24
Peak memory 224372 kb
Host smart-cc23b149-0c0a-42f9-b9da-79b3c9041a80
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1858452806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1858452806
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1605102890
Short name T757
Test name
Test status
Simulation time 37744616952 ps
CPU time 335.41 seconds
Started Jul 20 06:53:03 PM PDT 24
Finished Jul 20 06:58:38 PM PDT 24
Peak memory 251728 kb
Host smart-ba906b6c-2797-485b-9d18-49a3a3e8856f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605102890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1605102890
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1361608520
Short name T684
Test name
Test status
Simulation time 2035225730 ps
CPU time 21.65 seconds
Started Jul 20 06:52:50 PM PDT 24
Finished Jul 20 06:53:13 PM PDT 24
Peak memory 216800 kb
Host smart-d653c85c-273c-421d-a03a-935f8e2a046b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361608520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1361608520
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3548607526
Short name T576
Test name
Test status
Simulation time 30306868 ps
CPU time 0.75 seconds
Started Jul 20 06:52:47 PM PDT 24
Finished Jul 20 06:52:48 PM PDT 24
Peak memory 206140 kb
Host smart-e6a175ee-2ca8-4940-a1e1-1b12eb143ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548607526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3548607526
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.684667917
Short name T925
Test name
Test status
Simulation time 801444266 ps
CPU time 2.85 seconds
Started Jul 20 06:52:49 PM PDT 24
Finished Jul 20 06:52:53 PM PDT 24
Peak memory 216644 kb
Host smart-94d2631d-0273-415c-a327-dd0fd5c6f757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684667917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.684667917
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.684288839
Short name T351
Test name
Test status
Simulation time 19636859 ps
CPU time 0.77 seconds
Started Jul 20 06:52:48 PM PDT 24
Finished Jul 20 06:52:50 PM PDT 24
Peak memory 206444 kb
Host smart-b15a5e68-3130-4061-b2bd-d026d4747e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684288839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.684288839
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1205001299
Short name T415
Test name
Test status
Simulation time 628819094 ps
CPU time 3.76 seconds
Started Jul 20 06:52:50 PM PDT 24
Finished Jul 20 06:52:54 PM PDT 24
Peak memory 224924 kb
Host smart-a2a80f38-9a23-49bd-b32a-b5447b60a120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205001299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1205001299
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3125936175
Short name T371
Test name
Test status
Simulation time 19641617 ps
CPU time 0.77 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 205368 kb
Host smart-b25500d5-90a0-4210-947b-5d6d06283f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125936175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3125936175
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3880667777
Short name T446
Test name
Test status
Simulation time 102765902 ps
CPU time 2.67 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:03 PM PDT 24
Peak memory 224972 kb
Host smart-44041528-20e1-49ba-ba64-59c3193e9944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880667777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3880667777
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.550039556
Short name T781
Test name
Test status
Simulation time 46527709 ps
CPU time 0.76 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:00 PM PDT 24
Peak memory 206364 kb
Host smart-7b6eefe1-1c2d-4efb-8f75-8e6e86b3d0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550039556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.550039556
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.10672811
Short name T540
Test name
Test status
Simulation time 54166097569 ps
CPU time 92.5 seconds
Started Jul 20 06:52:57 PM PDT 24
Finished Jul 20 06:54:31 PM PDT 24
Peak memory 249740 kb
Host smart-064c762c-0370-4d00-8eee-08f07fa89971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10672811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.10672811
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.707058246
Short name T892
Test name
Test status
Simulation time 43026216975 ps
CPU time 94.16 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:54:34 PM PDT 24
Peak memory 249488 kb
Host smart-81ddc10a-6a5e-44a6-8c92-ebed5bcea460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707058246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.707058246
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.119555582
Short name T704
Test name
Test status
Simulation time 2630177727 ps
CPU time 31.26 seconds
Started Jul 20 06:53:01 PM PDT 24
Finished Jul 20 06:53:33 PM PDT 24
Peak memory 218076 kb
Host smart-0540c243-0667-41a7-85db-318eaead02c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119555582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle
.119555582
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2817311526
Short name T563
Test name
Test status
Simulation time 2586471884 ps
CPU time 15.73 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:17 PM PDT 24
Peak memory 249916 kb
Host smart-defbd4bb-b767-4dab-b780-75910a9031c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817311526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2817311526
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3735120017
Short name T846
Test name
Test status
Simulation time 54078759022 ps
CPU time 61.12 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 224912 kb
Host smart-66319a86-9ef7-4ac8-a059-73c52dfc7187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735120017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3735120017
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3787287228
Short name T392
Test name
Test status
Simulation time 1343743482 ps
CPU time 5.73 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 224896 kb
Host smart-8f5c6214-b836-439d-b6c2-e4dd203b0d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787287228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3787287228
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2990422902
Short name T381
Test name
Test status
Simulation time 1672855426 ps
CPU time 22.12 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:22 PM PDT 24
Peak memory 224952 kb
Host smart-b173da2a-8854-4dac-8317-9a28eb54a071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990422902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2990422902
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3080922080
Short name T267
Test name
Test status
Simulation time 6954895217 ps
CPU time 21.53 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:20 PM PDT 24
Peak memory 229968 kb
Host smart-a61c6df8-cd7b-4497-a736-763216a06803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080922080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3080922080
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3697639966
Short name T1
Test name
Test status
Simulation time 776852073 ps
CPU time 5.06 seconds
Started Jul 20 06:53:04 PM PDT 24
Finished Jul 20 06:53:09 PM PDT 24
Peak memory 224672 kb
Host smart-b1de6fb0-3f35-4594-af49-a39d792803d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697639966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3697639966
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2722790792
Short name T140
Test name
Test status
Simulation time 130268516 ps
CPU time 3.63 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:04 PM PDT 24
Peak memory 223612 kb
Host smart-62f3e839-14b4-4c2d-b8f7-8a72582d451c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722790792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2722790792
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.560401344
Short name T79
Test name
Test status
Simulation time 713331711 ps
CPU time 6.53 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:07 PM PDT 24
Peak memory 218904 kb
Host smart-4428ede4-d880-44e5-abfb-85df3a5bfda6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560401344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.560401344
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1294978021
Short name T456
Test name
Test status
Simulation time 453752771 ps
CPU time 1.82 seconds
Started Jul 20 06:53:04 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 208136 kb
Host smart-09ce2a17-09aa-449f-9a61-77f8ad220c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294978021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1294978021
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.360709232
Short name T808
Test name
Test status
Simulation time 221820857 ps
CPU time 1.39 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:01 PM PDT 24
Peak memory 216628 kb
Host smart-06f209c7-32c3-4cf5-81d0-b54a58aa24f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360709232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.360709232
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1836376977
Short name T638
Test name
Test status
Simulation time 30173933 ps
CPU time 0.7 seconds
Started Jul 20 06:53:00 PM PDT 24
Finished Jul 20 06:53:02 PM PDT 24
Peak memory 206120 kb
Host smart-9a8ef82a-d4cb-4b6f-8a5f-2ad9c3db8434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836376977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1836376977
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1069712528
Short name T868
Test name
Test status
Simulation time 3180910581 ps
CPU time 7.7 seconds
Started Jul 20 06:53:01 PM PDT 24
Finished Jul 20 06:53:09 PM PDT 24
Peak memory 233216 kb
Host smart-751a3eea-96c0-45d0-bfc2-99ea12ae1543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069712528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1069712528
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.787936787
Short name T449
Test name
Test status
Simulation time 19254436 ps
CPU time 0.77 seconds
Started Jul 20 06:52:04 PM PDT 24
Finished Jul 20 06:52:06 PM PDT 24
Peak memory 205344 kb
Host smart-8e679f70-14ea-4253-abbe-d1c55bea9a3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787936787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.787936787
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2634584655
Short name T1003
Test name
Test status
Simulation time 831819687 ps
CPU time 4.85 seconds
Started Jul 20 06:51:56 PM PDT 24
Finished Jul 20 06:52:02 PM PDT 24
Peak memory 233088 kb
Host smart-4e6553ad-8425-4c35-9aaa-c9d173c1857f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634584655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2634584655
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2208167532
Short name T58
Test name
Test status
Simulation time 85588416 ps
CPU time 0.83 seconds
Started Jul 20 06:51:59 PM PDT 24
Finished Jul 20 06:52:00 PM PDT 24
Peak memory 207060 kb
Host smart-9729407f-ddb6-4ce9-9c7b-df8ee289f475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208167532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2208167532
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.156161900
Short name T1002
Test name
Test status
Simulation time 14477555224 ps
CPU time 128.21 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 249608 kb
Host smart-58cb3579-86b2-464e-9cdc-53ef83198e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156161900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.156161900
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2411732815
Short name T122
Test name
Test status
Simulation time 6963242453 ps
CPU time 45.45 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:52:40 PM PDT 24
Peak memory 241524 kb
Host smart-4783d8f3-f5ff-4f7b-8d19-a31533496dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411732815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2411732815
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.277702649
Short name T86
Test name
Test status
Simulation time 40559735632 ps
CPU time 270.09 seconds
Started Jul 20 06:52:01 PM PDT 24
Finished Jul 20 06:56:31 PM PDT 24
Peak memory 251908 kb
Host smart-9ce8c932-afbc-43f1-bd46-5eefc9cc0cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277702649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
277702649
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.707024911
Short name T596
Test name
Test status
Simulation time 282219877 ps
CPU time 3.1 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 233072 kb
Host smart-68556428-888b-4a3c-9fed-4dfba2a2a080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707024911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.707024911
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3457982167
Short name T123
Test name
Test status
Simulation time 8595194559 ps
CPU time 32.31 seconds
Started Jul 20 06:51:53 PM PDT 24
Finished Jul 20 06:52:26 PM PDT 24
Peak memory 233136 kb
Host smart-3b0e7fe1-d821-4cfe-9558-e4b9c29c7cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3457982167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3457982167
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2486449352
Short name T237
Test name
Test status
Simulation time 1110410945 ps
CPU time 5.68 seconds
Started Jul 20 06:51:58 PM PDT 24
Finished Jul 20 06:52:05 PM PDT 24
Peak memory 225052 kb
Host smart-855ff5a4-8328-4b21-9414-8cf40a054102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486449352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2486449352
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2688034140
Short name T717
Test name
Test status
Simulation time 12770603223 ps
CPU time 10.53 seconds
Started Jul 20 06:52:00 PM PDT 24
Finished Jul 20 06:52:11 PM PDT 24
Peak memory 225036 kb
Host smart-02dbb90c-887f-408e-9f45-28a41270f61b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688034140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2688034140
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1988218244
Short name T806
Test name
Test status
Simulation time 1295157594 ps
CPU time 10.42 seconds
Started Jul 20 06:51:55 PM PDT 24
Finished Jul 20 06:52:07 PM PDT 24
Peak memory 223624 kb
Host smart-84d74288-d3d5-4167-bc0d-a71be97100a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1988218244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1988218244
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.584115616
Short name T68
Test name
Test status
Simulation time 119538147 ps
CPU time 0.96 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:51:59 PM PDT 24
Peak memory 235588 kb
Host smart-84e7c616-140a-4661-bd65-f4d03ce50aee
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584115616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.584115616
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1987249528
Short name T775
Test name
Test status
Simulation time 27462994147 ps
CPU time 160.65 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:54:38 PM PDT 24
Peak memory 264644 kb
Host smart-ee83d6fd-b6dc-447e-a9b2-0c94642a86f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987249528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1987249528
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3795672829
Short name T515
Test name
Test status
Simulation time 4419447747 ps
CPU time 7.24 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:52:03 PM PDT 24
Peak memory 216756 kb
Host smart-c03fff67-e8b8-43f1-a3b3-b27e3334621a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795672829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3795672829
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2676382728
Short name T981
Test name
Test status
Simulation time 38327895 ps
CPU time 1.03 seconds
Started Jul 20 06:51:56 PM PDT 24
Finished Jul 20 06:51:58 PM PDT 24
Peak memory 207508 kb
Host smart-441c0028-7be3-434c-9248-dac475670046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676382728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2676382728
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2288702697
Short name T409
Test name
Test status
Simulation time 51377982 ps
CPU time 0.84 seconds
Started Jul 20 06:51:57 PM PDT 24
Finished Jul 20 06:51:59 PM PDT 24
Peak memory 207236 kb
Host smart-703c3911-cade-4e69-8887-45ef121bf9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288702697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2288702697
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3678592819
Short name T377
Test name
Test status
Simulation time 75036533 ps
CPU time 0.96 seconds
Started Jul 20 06:51:54 PM PDT 24
Finished Jul 20 06:51:56 PM PDT 24
Peak memory 206448 kb
Host smart-bdb22568-c56c-4e6e-8cbe-ba6a70002113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678592819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3678592819
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3917292536
Short name T995
Test name
Test status
Simulation time 590380184 ps
CPU time 8.27 seconds
Started Jul 20 06:51:53 PM PDT 24
Finished Jul 20 06:52:02 PM PDT 24
Peak memory 233168 kb
Host smart-8666e969-d95f-43be-ae05-1f83526b7953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917292536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3917292536
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2521919240
Short name T580
Test name
Test status
Simulation time 12090800 ps
CPU time 0.75 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:12 PM PDT 24
Peak memory 205256 kb
Host smart-b548bdff-3730-4df2-b078-df529fc9dab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521919240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2521919240
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3503931870
Short name T699
Test name
Test status
Simulation time 4153321140 ps
CPU time 7.9 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:07 PM PDT 24
Peak memory 224956 kb
Host smart-962c92a9-9b93-45f8-9ebb-abea256ed5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503931870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3503931870
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.797981735
Short name T850
Test name
Test status
Simulation time 54745623 ps
CPU time 0.76 seconds
Started Jul 20 06:53:01 PM PDT 24
Finished Jul 20 06:53:02 PM PDT 24
Peak memory 207376 kb
Host smart-6ff413e2-ed71-4e2c-981f-04c3618dd7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797981735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.797981735
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1878617289
Short name T182
Test name
Test status
Simulation time 110880038973 ps
CPU time 228.22 seconds
Started Jul 20 06:53:05 PM PDT 24
Finished Jul 20 06:56:54 PM PDT 24
Peak memory 262868 kb
Host smart-e07981c7-4396-4a3c-b209-2d10696c3437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878617289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1878617289
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3272553603
Short name T81
Test name
Test status
Simulation time 9851940596 ps
CPU time 75.48 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 255912 kb
Host smart-41cdbfbd-7e84-4371-aad8-301f4d161ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272553603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3272553603
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1849339865
Short name T201
Test name
Test status
Simulation time 153958447271 ps
CPU time 98.68 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:54:50 PM PDT 24
Peak memory 225012 kb
Host smart-8fac4447-5b60-4ce7-8798-d93f7070183c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849339865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1849339865
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.928878286
Short name T317
Test name
Test status
Simulation time 473134813 ps
CPU time 7.38 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:53:16 PM PDT 24
Peak memory 236808 kb
Host smart-c3b4b060-d7aa-4597-8a31-e08568aa36c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928878286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.928878286
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.4284739172
Short name T511
Test name
Test status
Simulation time 10213041824 ps
CPU time 51.47 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 250724 kb
Host smart-67cc287b-99ee-49db-91a5-cea76c47b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284739172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.4284739172
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.635581494
Short name T685
Test name
Test status
Simulation time 31475233 ps
CPU time 2.78 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:04 PM PDT 24
Peak memory 232820 kb
Host smart-58048f91-1a2b-4c8c-92e5-0aa6f5296806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635581494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.635581494
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1157471499
Short name T873
Test name
Test status
Simulation time 10945543327 ps
CPU time 95.75 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:54:36 PM PDT 24
Peak memory 249556 kb
Host smart-ac7fed3e-3ebf-417e-a8bd-5fd475b62252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157471499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1157471499
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.4256134625
Short name T791
Test name
Test status
Simulation time 4943632125 ps
CPU time 15.92 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:15 PM PDT 24
Peak memory 233152 kb
Host smart-95063061-d47b-4b80-a9d9-6fa33fe41919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256134625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.4256134625
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3282896731
Short name T881
Test name
Test status
Simulation time 24845990051 ps
CPU time 16.14 seconds
Started Jul 20 06:53:01 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 233176 kb
Host smart-9fefbc62-f7f4-4e19-b87c-6e6e558e6465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282896731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3282896731
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3088536028
Short name T411
Test name
Test status
Simulation time 325992425 ps
CPU time 5.27 seconds
Started Jul 20 06:53:05 PM PDT 24
Finished Jul 20 06:53:10 PM PDT 24
Peak memory 223572 kb
Host smart-94e1c4cf-1b8c-4dbd-80ea-a279c987970e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3088536028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3088536028
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3281264953
Short name T886
Test name
Test status
Simulation time 29018253377 ps
CPU time 62.94 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:54:10 PM PDT 24
Peak memory 237496 kb
Host smart-ad2ceae0-4f41-400f-b26d-46360f6fd65e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281264953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3281264953
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2271078372
Short name T552
Test name
Test status
Simulation time 564831201 ps
CPU time 2.69 seconds
Started Jul 20 06:52:57 PM PDT 24
Finished Jul 20 06:53:01 PM PDT 24
Peak memory 216704 kb
Host smart-077fd1cf-57c8-4468-8401-9d9bc0dc49d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271078372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2271078372
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.183401678
Short name T748
Test name
Test status
Simulation time 5568955815 ps
CPU time 6.8 seconds
Started Jul 20 06:52:56 PM PDT 24
Finished Jul 20 06:53:04 PM PDT 24
Peak memory 216708 kb
Host smart-d8e6650c-e779-4c7d-be35-b4a45313ab57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183401678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.183401678
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1434101015
Short name T460
Test name
Test status
Simulation time 597822293 ps
CPU time 2.28 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:01 PM PDT 24
Peak memory 216700 kb
Host smart-61832161-02e8-4ce2-83ec-ceecfbd49836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434101015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1434101015
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1989564928
Short name T567
Test name
Test status
Simulation time 113489242 ps
CPU time 0.83 seconds
Started Jul 20 06:52:58 PM PDT 24
Finished Jul 20 06:53:01 PM PDT 24
Peak memory 206416 kb
Host smart-2980ef9f-942c-4dcf-910c-00b325efdf64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989564928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1989564928
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.389889949
Short name T951
Test name
Test status
Simulation time 157306491 ps
CPU time 3.52 seconds
Started Jul 20 06:52:59 PM PDT 24
Finished Jul 20 06:53:04 PM PDT 24
Peak memory 229068 kb
Host smart-cb8a27b5-69c8-4495-9053-5041d271a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389889949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.389889949
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1701117089
Short name T441
Test name
Test status
Simulation time 21220417 ps
CPU time 0.77 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:11 PM PDT 24
Peak memory 205920 kb
Host smart-2f661d88-7bdc-4419-9026-3a54eea55c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701117089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1701117089
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.903094528
Short name T438
Test name
Test status
Simulation time 2237505999 ps
CPU time 14.12 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:53:21 PM PDT 24
Peak memory 233148 kb
Host smart-e612a919-57c1-40a9-9701-0f130466f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903094528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.903094528
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3667133426
Short name T473
Test name
Test status
Simulation time 35404429 ps
CPU time 0.8 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:53:08 PM PDT 24
Peak memory 207064 kb
Host smart-2793007c-e852-4023-a658-59d66f8e63c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667133426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3667133426
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2361978299
Short name T304
Test name
Test status
Simulation time 31650652540 ps
CPU time 159.85 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:55:49 PM PDT 24
Peak memory 255368 kb
Host smart-ba94ab1c-1d9a-41d8-9aba-f2ac133ed905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361978299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2361978299
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3769889564
Short name T499
Test name
Test status
Simulation time 16339548902 ps
CPU time 73.1 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 250684 kb
Host smart-7af08c0e-fc8c-48bf-a663-68d809e45fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769889564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3769889564
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3871482868
Short name T885
Test name
Test status
Simulation time 2076088697 ps
CPU time 31.1 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:47 PM PDT 24
Peak memory 240992 kb
Host smart-a231780d-fbb7-4a4d-9ad2-070ba07b48df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871482868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3871482868
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2468077863
Short name T361
Test name
Test status
Simulation time 340797456 ps
CPU time 6.57 seconds
Started Jul 20 06:53:09 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 234924 kb
Host smart-2a8c6a32-cf7c-4087-a375-1935918dcca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468077863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2468077863
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.977009105
Short name T654
Test name
Test status
Simulation time 33997560510 ps
CPU time 142.38 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:55:30 PM PDT 24
Peak memory 249608 kb
Host smart-062cdd9a-1c06-4220-859d-74c33a481a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977009105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.977009105
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2904132857
Short name T932
Test name
Test status
Simulation time 347671008 ps
CPU time 3.27 seconds
Started Jul 20 06:53:05 PM PDT 24
Finished Jul 20 06:53:08 PM PDT 24
Peak memory 224864 kb
Host smart-e44d637e-b0c1-4192-814a-fb3283784ad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904132857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2904132857
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1803746312
Short name T206
Test name
Test status
Simulation time 6170992299 ps
CPU time 60.03 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:54:09 PM PDT 24
Peak memory 233140 kb
Host smart-3efd2ca2-ad11-404f-b55c-6cd8439efb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803746312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1803746312
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2944296342
Short name T597
Test name
Test status
Simulation time 313940727 ps
CPU time 3.61 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:19 PM PDT 24
Peak memory 224932 kb
Host smart-149046b7-9efd-4160-bda4-6fc36f13dae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944296342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2944296342
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.4213397785
Short name T916
Test name
Test status
Simulation time 2756779071 ps
CPU time 12.53 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:25 PM PDT 24
Peak memory 241036 kb
Host smart-783449cc-a54c-4570-bce0-baac8b0e831f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213397785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.4213397785
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.949987681
Short name T374
Test name
Test status
Simulation time 1211688511 ps
CPU time 3.84 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:53:13 PM PDT 24
Peak memory 223600 kb
Host smart-bebc8455-7c3a-4bef-9722-4b988b3795e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=949987681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.949987681
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2954997039
Short name T678
Test name
Test status
Simulation time 52028744460 ps
CPU time 206.47 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:56:38 PM PDT 24
Peak memory 268916 kb
Host smart-fd6355d9-01e7-4dae-8e5b-e62e6ceb36f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954997039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2954997039
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3413665941
Short name T345
Test name
Test status
Simulation time 45238176890 ps
CPU time 19.99 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:32 PM PDT 24
Peak memory 216904 kb
Host smart-bf078257-b7b5-4807-a73a-4027160b2898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413665941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3413665941
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.1888737145
Short name T956
Test name
Test status
Simulation time 15278665458 ps
CPU time 11.44 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:53:20 PM PDT 24
Peak memory 217884 kb
Host smart-d7cda727-b77f-4df0-91f8-e7bb570a66e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888737145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1888737145
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2375757012
Short name T617
Test name
Test status
Simulation time 77373635 ps
CPU time 0.93 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:53:10 PM PDT 24
Peak memory 207700 kb
Host smart-a258cf39-1505-4ee7-bb4c-cb459e3cf0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375757012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2375757012
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1565119463
Short name T430
Test name
Test status
Simulation time 47160394 ps
CPU time 0.75 seconds
Started Jul 20 06:53:05 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 206428 kb
Host smart-a7dec66f-1eef-4f39-ba46-4a630b7b4aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565119463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1565119463
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3882802469
Short name T577
Test name
Test status
Simulation time 3870026377 ps
CPU time 6.64 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:19 PM PDT 24
Peak memory 233160 kb
Host smart-8d29e781-aad3-4154-a671-1c5f4193839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882802469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3882802469
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1833460228
Short name T844
Test name
Test status
Simulation time 186207373 ps
CPU time 0.71 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:13 PM PDT 24
Peak memory 205376 kb
Host smart-e28ae86a-6971-4e5a-9199-b68339ba7284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833460228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1833460228
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3278450608
Short name T264
Test name
Test status
Simulation time 280058421 ps
CPU time 5.54 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 224892 kb
Host smart-265a1e62-a1bc-4cc2-95c7-37f843f1d79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278450608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3278450608
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1372169099
Short name T346
Test name
Test status
Simulation time 15929655 ps
CPU time 0.8 seconds
Started Jul 20 06:53:09 PM PDT 24
Finished Jul 20 06:53:12 PM PDT 24
Peak memory 207380 kb
Host smart-a9c1fe51-67a6-4a29-b7fb-cf5e80ced933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372169099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1372169099
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3982646251
Short name T74
Test name
Test status
Simulation time 84333123260 ps
CPU time 168.86 seconds
Started Jul 20 06:53:09 PM PDT 24
Finished Jul 20 06:56:00 PM PDT 24
Peak memory 249496 kb
Host smart-93563b5b-5372-46c3-a935-8bfa85b8fa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982646251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3982646251
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.641445863
Short name T72
Test name
Test status
Simulation time 38909658164 ps
CPU time 389.47 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:59:40 PM PDT 24
Peak memory 252116 kb
Host smart-30f5b6e5-ac67-4f5d-abec-7b892c9f84dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641445863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.641445863
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.812655238
Short name T830
Test name
Test status
Simulation time 11501080487 ps
CPU time 108.29 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:54:55 PM PDT 24
Peak memory 249552 kb
Host smart-21c2cfbf-c228-4e5b-9db0-108612d176be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812655238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.812655238
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3987103846
Short name T545
Test name
Test status
Simulation time 94222667 ps
CPU time 4.51 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:53:14 PM PDT 24
Peak memory 233064 kb
Host smart-983e9a9a-595f-435a-bc43-1931635cfbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987103846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3987103846
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.2968316626
Short name T760
Test name
Test status
Simulation time 19100712 ps
CPU time 0.76 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:53:08 PM PDT 24
Peak memory 216140 kb
Host smart-ebef73c8-8da9-47c3-a59a-1c263e206d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968316626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.2968316626
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1453688656
Short name T687
Test name
Test status
Simulation time 404513081 ps
CPU time 4.68 seconds
Started Jul 20 06:53:09 PM PDT 24
Finished Jul 20 06:53:16 PM PDT 24
Peak memory 233100 kb
Host smart-316860d4-4f5c-4049-a4ee-071a20b8eaf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453688656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1453688656
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1866046500
Short name T856
Test name
Test status
Simulation time 492219526 ps
CPU time 2.18 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:53:10 PM PDT 24
Peak memory 224540 kb
Host smart-b1598e51-54ba-4dbd-a12c-8d1800e1069a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866046500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1866046500
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.396722604
Short name T273
Test name
Test status
Simulation time 939493603 ps
CPU time 3.95 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:14 PM PDT 24
Peak memory 224944 kb
Host smart-d896bc11-3ab4-482b-ae13-b77044c863b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396722604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap
.396722604
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4253335126
Short name T765
Test name
Test status
Simulation time 1544767378 ps
CPU time 8.77 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 233088 kb
Host smart-02290bc9-9ce8-4e51-8830-6bdd279867b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253335126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4253335126
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3418051863
Short name T412
Test name
Test status
Simulation time 7429271914 ps
CPU time 7.32 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:17 PM PDT 24
Peak memory 219412 kb
Host smart-10db2767-259d-4d5c-89fa-df37869228c9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3418051863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3418051863
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1698185315
Short name T293
Test name
Test status
Simulation time 17064689475 ps
CPU time 234.98 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:57:05 PM PDT 24
Peak memory 266060 kb
Host smart-7f46b17b-1e95-47a2-9949-fefcb33eb583
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698185315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1698185315
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3881889682
Short name T529
Test name
Test status
Simulation time 2544472067 ps
CPU time 31.71 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:53:39 PM PDT 24
Peak memory 216892 kb
Host smart-a9b84ba2-5bf5-459c-9bbe-f660fc5f8a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881889682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3881889682
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1929264354
Short name T789
Test name
Test status
Simulation time 1328754021 ps
CPU time 1.94 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:16 PM PDT 24
Peak memory 216596 kb
Host smart-2bc0bbce-3cbc-4467-9603-546aee8cb0f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929264354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1929264354
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.386935296
Short name T542
Test name
Test status
Simulation time 174768078 ps
CPU time 3.77 seconds
Started Jul 20 06:53:05 PM PDT 24
Finished Jul 20 06:53:10 PM PDT 24
Peak memory 216632 kb
Host smart-1b076b99-89e4-4d57-bc4b-22737a85b874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386935296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.386935296
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2860307634
Short name T878
Test name
Test status
Simulation time 15442498 ps
CPU time 0.71 seconds
Started Jul 20 06:53:05 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 206436 kb
Host smart-a4691815-c174-451b-9a2a-960843410322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860307634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2860307634
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1563970431
Short name T839
Test name
Test status
Simulation time 575792668 ps
CPU time 5.94 seconds
Started Jul 20 06:53:07 PM PDT 24
Finished Jul 20 06:53:14 PM PDT 24
Peak memory 237028 kb
Host smart-bb310067-b336-40f4-8e15-0e52cfcb2314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563970431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1563970431
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3353980170
Short name T777
Test name
Test status
Simulation time 10314662 ps
CPU time 0.7 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:16 PM PDT 24
Peak memory 205940 kb
Host smart-aa508923-5feb-4634-86e0-742e76fa3163
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353980170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3353980170
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2083070325
Short name T572
Test name
Test status
Simulation time 364409342 ps
CPU time 5.59 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:21 PM PDT 24
Peak memory 224912 kb
Host smart-52dcf07a-742b-4a49-916e-74c1874c664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083070325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2083070325
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.530754010
Short name T73
Test name
Test status
Simulation time 56393360 ps
CPU time 0.78 seconds
Started Jul 20 06:53:09 PM PDT 24
Finished Jul 20 06:53:12 PM PDT 24
Peak memory 207384 kb
Host smart-34e6b9bb-5307-40b7-b681-d09e883602d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530754010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.530754010
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1177758117
Short name T275
Test name
Test status
Simulation time 35742686163 ps
CPU time 52.92 seconds
Started Jul 20 06:53:12 PM PDT 24
Finished Jul 20 06:54:06 PM PDT 24
Peak memory 249608 kb
Host smart-c28a119a-6f0f-4425-a79e-6eb5ae5901c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177758117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1177758117
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1724354892
Short name T906
Test name
Test status
Simulation time 14978892762 ps
CPU time 130.55 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:55:25 PM PDT 24
Peak memory 249668 kb
Host smart-094a2278-14ad-4c51-b1d3-0682eaa55680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724354892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1724354892
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.615315697
Short name T315
Test name
Test status
Simulation time 33619024880 ps
CPU time 60.89 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:54:15 PM PDT 24
Peak memory 249516 kb
Host smart-963d474c-ebfd-46aa-b722-fcb622924723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615315697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.615315697
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3076979492
Short name T247
Test name
Test status
Simulation time 8564253561 ps
CPU time 49.59 seconds
Started Jul 20 06:53:16 PM PDT 24
Finished Jul 20 06:54:09 PM PDT 24
Peak memory 241524 kb
Host smart-66fe6e3f-e1cb-4504-b5c5-990fa3a2a50d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076979492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3076979492
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2890303875
Short name T435
Test name
Test status
Simulation time 734724756 ps
CPU time 5.18 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:15 PM PDT 24
Peak memory 233180 kb
Host smart-137d8498-5f67-4766-b397-5b015658e986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890303875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2890303875
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.1723250665
Short name T840
Test name
Test status
Simulation time 162830607 ps
CPU time 3.41 seconds
Started Jul 20 06:53:06 PM PDT 24
Finished Jul 20 06:53:11 PM PDT 24
Peak memory 224916 kb
Host smart-09f91e13-cd39-497c-a2f9-c7a2b6d17881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723250665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1723250665
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1291567310
Short name T554
Test name
Test status
Simulation time 121584321 ps
CPU time 2.09 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:12 PM PDT 24
Peak memory 223520 kb
Host smart-3d8c2704-67ab-4912-9286-eacb594d0cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291567310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1291567310
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3364637992
Short name T679
Test name
Test status
Simulation time 2503447139 ps
CPU time 8.32 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:23 PM PDT 24
Peak memory 233212 kb
Host smart-44cce885-782b-414b-ac89-1760ce77ddc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364637992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3364637992
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3617013280
Short name T768
Test name
Test status
Simulation time 162984356 ps
CPU time 4.52 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:20 PM PDT 24
Peak memory 223552 kb
Host smart-fc4f6d17-fea6-4b18-aa9b-4c6e5b58497e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3617013280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3617013280
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.413768853
Short name T147
Test name
Test status
Simulation time 184692430 ps
CPU time 1.01 seconds
Started Jul 20 06:53:17 PM PDT 24
Finished Jul 20 06:53:22 PM PDT 24
Peak memory 207412 kb
Host smart-b21d780e-2a5d-4752-9c80-fb9e4e530574
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413768853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.413768853
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3277930903
Short name T790
Test name
Test status
Simulation time 23795831410 ps
CPU time 10.54 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:23 PM PDT 24
Peak memory 216716 kb
Host smart-a13c1c80-e606-4efd-b972-3daaa7cf1dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277930903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3277930903
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1594976590
Short name T352
Test name
Test status
Simulation time 32075504629 ps
CPU time 24.01 seconds
Started Jul 20 06:53:10 PM PDT 24
Finished Jul 20 06:53:36 PM PDT 24
Peak memory 217768 kb
Host smart-05cba401-14ef-4b46-9b4f-5beebfb994e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594976590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1594976590
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1848651698
Short name T710
Test name
Test status
Simulation time 41935632 ps
CPU time 0.88 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:11 PM PDT 24
Peak memory 207152 kb
Host smart-cd1b5334-0897-4f7f-b895-1333c0400d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848651698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1848651698
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.248240889
Short name T999
Test name
Test status
Simulation time 69692977 ps
CPU time 0.7 seconds
Started Jul 20 06:53:08 PM PDT 24
Finished Jul 20 06:53:12 PM PDT 24
Peak memory 206088 kb
Host smart-c0566ffc-a4ed-4ea5-8a2d-93eec1cd8326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248240889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.248240889
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3563353986
Short name T28
Test name
Test status
Simulation time 8905361873 ps
CPU time 16.75 seconds
Started Jul 20 06:53:15 PM PDT 24
Finished Jul 20 06:53:35 PM PDT 24
Peak memory 225016 kb
Host smart-0709dc87-af0f-4fc1-8718-681debb608bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563353986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3563353986
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3148407749
Short name T485
Test name
Test status
Simulation time 11831887 ps
CPU time 0.72 seconds
Started Jul 20 06:53:12 PM PDT 24
Finished Jul 20 06:53:14 PM PDT 24
Peak memory 205956 kb
Host smart-bc20c67f-fa7a-4089-ad5f-49b8d46a4329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148407749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3148407749
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.682832501
Short name T276
Test name
Test status
Simulation time 708705140 ps
CPU time 8.15 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:25 PM PDT 24
Peak memory 224892 kb
Host smart-9d22200c-3d55-4097-ae09-329c04c6c238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682832501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.682832501
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.2475241419
Short name T858
Test name
Test status
Simulation time 266232484 ps
CPU time 0.77 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:17 PM PDT 24
Peak memory 207068 kb
Host smart-33a98d1c-662b-4eda-8257-fb3c84c408bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475241419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2475241419
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2824874356
Short name T461
Test name
Test status
Simulation time 78782469367 ps
CPU time 163.36 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:55:59 PM PDT 24
Peak memory 253240 kb
Host smart-b934197e-5703-415f-8b31-95ae7f38dcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824874356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2824874356
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4217153483
Short name T433
Test name
Test status
Simulation time 13924147299 ps
CPU time 72.84 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:54:30 PM PDT 24
Peak memory 249556 kb
Host smart-27e1587a-1fd0-41e2-bd4d-2df6e998afe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217153483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4217153483
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1560207903
Short name T426
Test name
Test status
Simulation time 55652321820 ps
CPU time 138.56 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:55:41 PM PDT 24
Peak memory 250068 kb
Host smart-6ffd404b-c05f-4a96-8d9e-6ac62809171f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560207903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1560207903
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1379289752
Short name T738
Test name
Test status
Simulation time 6048967771 ps
CPU time 25.06 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:48 PM PDT 24
Peak memory 233248 kb
Host smart-da21aed8-5d33-412e-b635-8b37515e881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379289752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1379289752
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.210011180
Short name T715
Test name
Test status
Simulation time 97841210 ps
CPU time 0.82 seconds
Started Jul 20 06:53:12 PM PDT 24
Finished Jul 20 06:53:14 PM PDT 24
Peak memory 216248 kb
Host smart-33d6f227-5e84-4d85-989c-823fb8162df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210011180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.210011180
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.4191981299
Short name T259
Test name
Test status
Simulation time 443711110 ps
CPU time 5.04 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:20 PM PDT 24
Peak memory 224944 kb
Host smart-ce1341ac-10c4-47cc-995f-16fc0f038172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191981299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.4191981299
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.238817146
Short name T220
Test name
Test status
Simulation time 4138238037 ps
CPU time 41.77 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:58 PM PDT 24
Peak memory 233144 kb
Host smart-c0ad5b29-51e3-43fe-9f09-09bd90c84aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238817146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.238817146
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2062947946
Short name T891
Test name
Test status
Simulation time 405111587 ps
CPU time 8.35 seconds
Started Jul 20 06:53:15 PM PDT 24
Finished Jul 20 06:53:26 PM PDT 24
Peak memory 238608 kb
Host smart-aeb5b5ae-0a62-485e-aa99-d24def8e6bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062947946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2062947946
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.579441883
Short name T917
Test name
Test status
Simulation time 4955686003 ps
CPU time 18.09 seconds
Started Jul 20 06:53:15 PM PDT 24
Finished Jul 20 06:53:36 PM PDT 24
Peak memory 233236 kb
Host smart-0ba5999a-c958-4267-ab33-ce4477bd44d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579441883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.579441883
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3410332982
Short name T707
Test name
Test status
Simulation time 1329470469 ps
CPU time 15.55 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:32 PM PDT 24
Peak memory 220532 kb
Host smart-42f66655-fbd6-4fd0-84e4-56027817b8bb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3410332982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3410332982
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3739210802
Short name T50
Test name
Test status
Simulation time 35621200449 ps
CPU time 131.5 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:55:35 PM PDT 24
Peak memory 254164 kb
Host smart-474aeb1c-160f-45d4-8ba9-991deabde93f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739210802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3739210802
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.4041894148
Short name T945
Test name
Test status
Simulation time 1255416614 ps
CPU time 4.36 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:19 PM PDT 24
Peak memory 216792 kb
Host smart-7e79bb75-d07d-4768-ac02-f7660eed3676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041894148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.4041894148
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1223276907
Short name T34
Test name
Test status
Simulation time 417933366 ps
CPU time 3.51 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 216692 kb
Host smart-ca67784f-5a03-47ca-9738-6477f2fc2942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223276907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1223276907
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1276200935
Short name T734
Test name
Test status
Simulation time 46138513 ps
CPU time 1.42 seconds
Started Jul 20 06:53:16 PM PDT 24
Finished Jul 20 06:53:20 PM PDT 24
Peak memory 216796 kb
Host smart-54385b15-2588-4ec1-ad62-e13995073f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276200935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1276200935
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3652702458
Short name T555
Test name
Test status
Simulation time 80296695 ps
CPU time 0.92 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:15 PM PDT 24
Peak memory 206408 kb
Host smart-d22ce725-05f1-4f96-a51f-78f5dcd8cabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652702458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3652702458
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3426830864
Short name T125
Test name
Test status
Simulation time 1131421798 ps
CPU time 3.67 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:28 PM PDT 24
Peak memory 224896 kb
Host smart-4d92f944-f6a2-4e57-bf2b-6fa37f52dbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426830864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3426830864
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3599575811
Short name T476
Test name
Test status
Simulation time 35521771 ps
CPU time 0.71 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:29 PM PDT 24
Peak memory 205376 kb
Host smart-b05e4125-7262-4330-bf9e-8ebd76814858
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599575811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3599575811
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2198877878
Short name T826
Test name
Test status
Simulation time 1570078768 ps
CPU time 6.73 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:21 PM PDT 24
Peak memory 224896 kb
Host smart-c6ad1d01-a16e-45bf-a962-5d0d6947e8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198877878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2198877878
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.39819738
Short name T362
Test name
Test status
Simulation time 27552738 ps
CPU time 0.8 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 207376 kb
Host smart-74af6b0c-e09d-4212-adcd-95e70d547912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39819738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.39819738
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2067740772
Short name T566
Test name
Test status
Simulation time 2981284450 ps
CPU time 64.76 seconds
Started Jul 20 06:53:16 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 252068 kb
Host smart-1bdb852b-600b-4cf6-a84f-b820a70ad29e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067740772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2067740772
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1880254578
Short name T308
Test name
Test status
Simulation time 48967325641 ps
CPU time 182.61 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:56:27 PM PDT 24
Peak memory 254848 kb
Host smart-b555f61a-7444-4426-91b2-3db02b54cfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880254578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1880254578
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.627441844
Short name T380
Test name
Test status
Simulation time 24706698893 ps
CPU time 62.71 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 241412 kb
Host smart-985b8ca5-6fcd-45ae-a54f-32aff8c9434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627441844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.627441844
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.318039861
Short name T911
Test name
Test status
Simulation time 456474801 ps
CPU time 6.54 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:21 PM PDT 24
Peak memory 233168 kb
Host smart-0ad88a6f-f4d8-4f6a-90b8-a23e6e223a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318039861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.318039861
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3281283895
Short name T365
Test name
Test status
Simulation time 45315542 ps
CPU time 0.73 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:25 PM PDT 24
Peak memory 216244 kb
Host smart-fcae7e4e-bd0d-4390-81d5-1bc8ac07d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281283895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3281283895
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3889763829
Short name T497
Test name
Test status
Simulation time 570796868 ps
CPU time 5.26 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:29 PM PDT 24
Peak memory 233100 kb
Host smart-652f8f52-3ea5-4836-a21f-87bcb05374b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889763829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3889763829
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2274474268
Short name T235
Test name
Test status
Simulation time 575914998 ps
CPU time 3.96 seconds
Started Jul 20 06:53:16 PM PDT 24
Finished Jul 20 06:53:23 PM PDT 24
Peak memory 234112 kb
Host smart-5cc89bc8-a066-449d-b279-f6e4692cbe10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274474268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2274474268
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.1738639505
Short name T223
Test name
Test status
Simulation time 40074386866 ps
CPU time 11.39 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:27 PM PDT 24
Peak memory 224960 kb
Host smart-9989aa81-3dad-4bac-9b77-a0f5ebe0e576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738639505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.1738639505
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.725653447
Short name T248
Test name
Test status
Simulation time 650935161 ps
CPU time 4.04 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:27 PM PDT 24
Peak memory 233116 kb
Host smart-89042531-e80f-4249-8a7e-02b51cee1aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725653447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.725653447
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1468951676
Short name T767
Test name
Test status
Simulation time 1259588593 ps
CPU time 8.54 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:25 PM PDT 24
Peak memory 219212 kb
Host smart-72c0167b-c9a0-454d-9625-6a4f774128f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1468951676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1468951676
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2362842498
Short name T80
Test name
Test status
Simulation time 91677026276 ps
CPU time 200.59 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:56:50 PM PDT 24
Peak memory 256948 kb
Host smart-563345c7-03ac-4c05-a006-70663c6a7fa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362842498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2362842498
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.1538205403
Short name T328
Test name
Test status
Simulation time 20456943920 ps
CPU time 25.8 seconds
Started Jul 20 06:53:17 PM PDT 24
Finished Jul 20 06:53:46 PM PDT 24
Peak memory 216908 kb
Host smart-c2a96836-9f1a-4674-b47e-13d2386670bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538205403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.1538205403
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3618162813
Short name T697
Test name
Test status
Simulation time 3421998625 ps
CPU time 8.66 seconds
Started Jul 20 06:53:16 PM PDT 24
Finished Jul 20 06:53:27 PM PDT 24
Peak memory 216704 kb
Host smart-cff62276-ff21-4269-ad4f-848c4f7399cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618162813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3618162813
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.979509090
Short name T343
Test name
Test status
Simulation time 52536590 ps
CPU time 0.99 seconds
Started Jul 20 06:53:15 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 208352 kb
Host smart-6176034f-6532-496d-91b8-fd621d31ce17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979509090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.979509090
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.1916724471
Short name T387
Test name
Test status
Simulation time 67277901 ps
CPU time 0.97 seconds
Started Jul 20 06:53:14 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 207448 kb
Host smart-9c407376-4412-4f2a-80b9-5c5625632765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916724471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1916724471
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1825440394
Short name T870
Test name
Test status
Simulation time 26191893442 ps
CPU time 18.64 seconds
Started Jul 20 06:53:13 PM PDT 24
Finished Jul 20 06:53:33 PM PDT 24
Peak memory 233028 kb
Host smart-ce1fccfd-acea-491e-b9b6-e6740e28a3d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825440394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1825440394
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3977788940
Short name T523
Test name
Test status
Simulation time 37502708 ps
CPU time 0.71 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 205872 kb
Host smart-5f4bc08f-aac7-42f6-86ee-c3ced2b70a61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977788940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3977788940
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1536850557
Short name T243
Test name
Test status
Simulation time 606815391 ps
CPU time 8.47 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:32 PM PDT 24
Peak memory 224944 kb
Host smart-9fb75abc-54e2-4b6a-acf5-3f01b43bc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536850557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1536850557
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.4202107268
Short name T663
Test name
Test status
Simulation time 56121477 ps
CPU time 0.85 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 207400 kb
Host smart-456755d8-572c-4f29-ab29-696c3ad1425e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202107268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.4202107268
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.437074907
Short name T750
Test name
Test status
Simulation time 13424003569 ps
CPU time 73.21 seconds
Started Jul 20 06:53:23 PM PDT 24
Finished Jul 20 06:54:44 PM PDT 24
Peak memory 253236 kb
Host smart-1987e360-47ec-4c70-9d93-58c995a7bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437074907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.437074907
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3577393870
Short name T394
Test name
Test status
Simulation time 17861283361 ps
CPU time 60.43 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:54:28 PM PDT 24
Peak memory 257832 kb
Host smart-69e16198-a3a1-429f-aa25-56c8ebb6f1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577393870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3577393870
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1556510340
Short name T864
Test name
Test status
Simulation time 9217492937 ps
CPU time 79.65 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:54:49 PM PDT 24
Peak memory 241428 kb
Host smart-70ae0c17-d148-469c-b295-b71d6fcec6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556510340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1556510340
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.489185917
Short name T968
Test name
Test status
Simulation time 5711769794 ps
CPU time 74.35 seconds
Started Jul 20 06:53:20 PM PDT 24
Finished Jul 20 06:54:41 PM PDT 24
Peak memory 240040 kb
Host smart-7b8fba0d-d714-4fe4-8ec0-2e59d543498f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489185917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.489185917
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3798919810
Short name T855
Test name
Test status
Simulation time 3600009788 ps
CPU time 18.9 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:48 PM PDT 24
Peak memory 249608 kb
Host smart-511408db-2188-4c02-aaef-984b84ffaca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798919810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3798919810
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3225819611
Short name T615
Test name
Test status
Simulation time 29146108 ps
CPU time 2.38 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:31 PM PDT 24
Peak memory 232844 kb
Host smart-bd6ed62f-cb24-4f0e-8fa5-16ea4501825a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225819611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3225819611
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2036454356
Short name T283
Test name
Test status
Simulation time 5552569511 ps
CPU time 43.82 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:54:12 PM PDT 24
Peak memory 224960 kb
Host smart-a8738519-a2e9-4959-a378-2ed89236db07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036454356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2036454356
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.4272396305
Short name T271
Test name
Test status
Simulation time 420220712 ps
CPU time 2.73 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 233112 kb
Host smart-fba3b506-e9a4-4eb1-bdf2-6ae4ade4972b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272396305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.4272396305
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3728366832
Short name T57
Test name
Test status
Simulation time 2524620549 ps
CPU time 6.21 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:36 PM PDT 24
Peak memory 233160 kb
Host smart-9c2a6886-4326-4f10-a946-4ac38e60d5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728366832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3728366832
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1955433477
Short name T509
Test name
Test status
Simulation time 4278275782 ps
CPU time 11.55 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:41 PM PDT 24
Peak memory 222664 kb
Host smart-13dcc41d-2b33-4a3c-aa37-94e3cfba0966
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1955433477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1955433477
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2252385210
Short name T722
Test name
Test status
Simulation time 125760873391 ps
CPU time 181.05 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:56:29 PM PDT 24
Peak memory 256908 kb
Host smart-185f4cba-9ed5-458f-bb36-6a271d8e2afc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252385210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2252385210
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1020161209
Short name T898
Test name
Test status
Simulation time 4948324775 ps
CPU time 16.01 seconds
Started Jul 20 06:53:20 PM PDT 24
Finished Jul 20 06:53:42 PM PDT 24
Peak memory 216712 kb
Host smart-f14b8472-c81d-4d60-a728-adef9bf3299a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020161209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1020161209
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2890407488
Short name T337
Test name
Test status
Simulation time 70751881 ps
CPU time 1.41 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 216704 kb
Host smart-4f08e113-f8c7-42ac-a682-c7a297472031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890407488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2890407488
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1613765863
Short name T510
Test name
Test status
Simulation time 27180029 ps
CPU time 0.73 seconds
Started Jul 20 06:53:23 PM PDT 24
Finished Jul 20 06:53:31 PM PDT 24
Peak memory 206428 kb
Host smart-e47c97a2-ad27-4845-b743-69cf28a78fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613765863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1613765863
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1748440809
Short name T495
Test name
Test status
Simulation time 4277361317 ps
CPU time 17.39 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:47 PM PDT 24
Peak memory 225000 kb
Host smart-c62272a9-1229-4b2a-82dc-282fbe60eecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748440809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1748440809
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.672120527
Short name T490
Test name
Test status
Simulation time 80241055 ps
CPU time 0.73 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 205368 kb
Host smart-1a3ea366-6647-47d0-9b60-95ba2c330fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672120527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.672120527
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.328490818
Short name T420
Test name
Test status
Simulation time 126105804 ps
CPU time 3.38 seconds
Started Jul 20 06:53:24 PM PDT 24
Finished Jul 20 06:53:34 PM PDT 24
Peak memory 224960 kb
Host smart-006b522e-4a28-4d6b-83e5-5367c6b359e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328490818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.328490818
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2374400222
Short name T547
Test name
Test status
Simulation time 21568169 ps
CPU time 0.86 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:29 PM PDT 24
Peak memory 207040 kb
Host smart-831ed519-1d8d-4629-a31d-5f7f3ffbfa92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374400222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2374400222
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3150940004
Short name T244
Test name
Test status
Simulation time 11116245273 ps
CPU time 90.26 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:55:00 PM PDT 24
Peak memory 257124 kb
Host smart-447d141e-7cac-4f80-81d9-25b516e5916d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150940004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3150940004
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1047097948
Short name T910
Test name
Test status
Simulation time 79229990850 ps
CPU time 111.84 seconds
Started Jul 20 06:53:23 PM PDT 24
Finished Jul 20 06:55:22 PM PDT 24
Peak memory 249668 kb
Host smart-cce0237d-500a-47b7-adcc-6214c54edd88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047097948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1047097948
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.4046114692
Short name T847
Test name
Test status
Simulation time 14121086510 ps
CPU time 179.24 seconds
Started Jul 20 06:53:20 PM PDT 24
Finished Jul 20 06:56:25 PM PDT 24
Peak memory 261736 kb
Host smart-f83abb76-55a1-4c8d-8b60-2de740e845fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046114692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.4046114692
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.439312493
Short name T319
Test name
Test status
Simulation time 1210885616 ps
CPU time 15.34 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:43 PM PDT 24
Peak memory 233288 kb
Host smart-8de49078-7b02-4c48-91b4-4685740ca929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439312493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.439312493
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.651609056
Short name T170
Test name
Test status
Simulation time 27559265391 ps
CPU time 56.23 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 249600 kb
Host smart-94c6231b-1d23-40e8-8825-bddf42759e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651609056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds
.651609056
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.39803619
Short name T682
Test name
Test status
Simulation time 3356849361 ps
CPU time 34.6 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:54:02 PM PDT 24
Peak memory 225024 kb
Host smart-78e514c2-0d1f-4816-b2cb-3aa14cefa96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39803619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.39803619
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2180617686
Short name T676
Test name
Test status
Simulation time 13132809097 ps
CPU time 9.58 seconds
Started Jul 20 06:53:19 PM PDT 24
Finished Jul 20 06:53:35 PM PDT 24
Peak memory 224936 kb
Host smart-1cec7fd0-e9ac-4af7-9b40-fd809f0c06e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180617686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2180617686
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.484084965
Short name T843
Test name
Test status
Simulation time 8126041185 ps
CPU time 14.38 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:43 PM PDT 24
Peak memory 240640 kb
Host smart-33b395c3-2941-4f10-b218-92b1a5af8c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484084965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.484084965
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4072178053
Short name T692
Test name
Test status
Simulation time 1028873629 ps
CPU time 5.57 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:35 PM PDT 24
Peak memory 233092 kb
Host smart-bc342b26-edd8-4ba2-a090-aff8a963ccfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072178053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4072178053
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1297132154
Short name T661
Test name
Test status
Simulation time 5916752638 ps
CPU time 5.28 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:34 PM PDT 24
Peak memory 219904 kb
Host smart-c8919e55-4b2e-4eca-adcd-d4f9d3fb6c47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1297132154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1297132154
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3330860833
Short name T604
Test name
Test status
Simulation time 7153585644 ps
CPU time 20.47 seconds
Started Jul 20 06:53:20 PM PDT 24
Finished Jul 20 06:53:47 PM PDT 24
Peak memory 217132 kb
Host smart-010bec5a-1e78-47e4-ab7e-aad1bdce607e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330860833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3330860833
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3661825897
Short name T518
Test name
Test status
Simulation time 15372349913 ps
CPU time 21.78 seconds
Started Jul 20 06:53:20 PM PDT 24
Finished Jul 20 06:53:48 PM PDT 24
Peak memory 216720 kb
Host smart-a2126fef-a29b-4bf8-97f0-fc652fed3c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661825897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3661825897
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1773416006
Short name T447
Test name
Test status
Simulation time 49126954 ps
CPU time 3.02 seconds
Started Jul 20 06:53:22 PM PDT 24
Finished Jul 20 06:53:33 PM PDT 24
Peak memory 216724 kb
Host smart-558a7129-92e9-4351-a1b9-661fab5922fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773416006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1773416006
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.664552698
Short name T988
Test name
Test status
Simulation time 151262969 ps
CPU time 0.83 seconds
Started Jul 20 06:53:21 PM PDT 24
Finished Jul 20 06:53:28 PM PDT 24
Peak memory 206412 kb
Host smart-48a1d570-7c2f-43e9-8e2b-76bb51ff6ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664552698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.664552698
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3224201238
Short name T539
Test name
Test status
Simulation time 751749826 ps
CPU time 3.64 seconds
Started Jul 20 06:53:20 PM PDT 24
Finished Jul 20 06:53:30 PM PDT 24
Peak memory 224964 kb
Host smart-51288f03-f1e7-4900-a3a4-de3e1982e592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224201238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3224201238
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.374474391
Short name T383
Test name
Test status
Simulation time 17531485 ps
CPU time 0.73 seconds
Started Jul 20 06:53:29 PM PDT 24
Finished Jul 20 06:53:36 PM PDT 24
Peak memory 205936 kb
Host smart-757cf27e-f316-43e9-851e-98c316b8fafc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374474391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.374474391
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.2141191791
Short name T861
Test name
Test status
Simulation time 39087432 ps
CPU time 2.46 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:40 PM PDT 24
Peak memory 233144 kb
Host smart-3e2091e4-3c59-4771-a018-103b00da2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141191791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.2141191791
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1705637976
Short name T869
Test name
Test status
Simulation time 15672504 ps
CPU time 0.79 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:38 PM PDT 24
Peak memory 207064 kb
Host smart-bb4937fb-5d66-4169-a22c-9e8b33776358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705637976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1705637976
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.165737754
Short name T448
Test name
Test status
Simulation time 1190194173 ps
CPU time 25.27 seconds
Started Jul 20 06:53:31 PM PDT 24
Finished Jul 20 06:54:04 PM PDT 24
Peak memory 246740 kb
Host smart-3d61fcca-6e5c-413b-b569-a6b58b98b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165737754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.165737754
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3306714966
Short name T642
Test name
Test status
Simulation time 9523573032 ps
CPU time 92.61 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:55:10 PM PDT 24
Peak memory 257700 kb
Host smart-2c2d67f7-3b79-4ced-a0b1-53ca420ea20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306714966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3306714966
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1322471235
Short name T673
Test name
Test status
Simulation time 38243863028 ps
CPU time 94.03 seconds
Started Jul 20 06:53:29 PM PDT 24
Finished Jul 20 06:55:10 PM PDT 24
Peak memory 264728 kb
Host smart-fba2d6ce-1d47-41b2-8765-c69e2dffe965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322471235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1322471235
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3871063703
Short name T755
Test name
Test status
Simulation time 719335161 ps
CPU time 10.39 seconds
Started Jul 20 06:53:33 PM PDT 24
Finished Jul 20 06:53:51 PM PDT 24
Peak memory 224944 kb
Host smart-d8b40ce0-a73f-4394-a84e-36def0c28410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871063703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3871063703
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.3377944056
Short name T538
Test name
Test status
Simulation time 5862422781 ps
CPU time 41.74 seconds
Started Jul 20 06:53:29 PM PDT 24
Finished Jul 20 06:54:18 PM PDT 24
Peak memory 237044 kb
Host smart-6bd8263d-299d-457e-8cf1-bddd3b7a0107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377944056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.3377944056
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2107456055
Short name T556
Test name
Test status
Simulation time 740050319 ps
CPU time 9.27 seconds
Started Jul 20 06:53:28 PM PDT 24
Finished Jul 20 06:53:45 PM PDT 24
Peak memory 233096 kb
Host smart-fae71fbf-a0d8-454c-92b9-5f4a7bfd4b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107456055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2107456055
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3876655519
Short name T232
Test name
Test status
Simulation time 21074824498 ps
CPU time 26.13 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 233220 kb
Host smart-edf43013-687e-48fd-ae73-b298c3b0a2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876655519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3876655519
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1625743915
Short name T37
Test name
Test status
Simulation time 1798763397 ps
CPU time 7.55 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:45 PM PDT 24
Peak memory 224972 kb
Host smart-fdae3551-09bd-491d-8f6b-6b2a9034189d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625743915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1625743915
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.4158026986
Short name T630
Test name
Test status
Simulation time 63267051 ps
CPU time 2.49 seconds
Started Jul 20 06:53:29 PM PDT 24
Finished Jul 20 06:53:38 PM PDT 24
Peak memory 232804 kb
Host smart-e01b4fc0-4d11-4e00-8f90-37e23845c6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158026986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4158026986
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2240165473
Short name T991
Test name
Test status
Simulation time 867745135 ps
CPU time 3.9 seconds
Started Jul 20 06:53:31 PM PDT 24
Finished Jul 20 06:53:43 PM PDT 24
Peak memory 219672 kb
Host smart-69089e4a-2af9-4cc0-91c5-c9067c2dd766
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2240165473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2240165473
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2740318034
Short name T595
Test name
Test status
Simulation time 53990777245 ps
CPU time 322.95 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:59:01 PM PDT 24
Peak memory 274208 kb
Host smart-cbd0733d-a810-43c9-af23-0dac3e43eb40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740318034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2740318034
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1520424841
Short name T61
Test name
Test status
Simulation time 4254377644 ps
CPU time 21.02 seconds
Started Jul 20 06:53:29 PM PDT 24
Finished Jul 20 06:53:56 PM PDT 24
Peak memory 220728 kb
Host smart-a976975c-ae74-4d00-89c9-aeb28fda732c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520424841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1520424841
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2207222984
Short name T401
Test name
Test status
Simulation time 5020889981 ps
CPU time 7.31 seconds
Started Jul 20 06:53:32 PM PDT 24
Finished Jul 20 06:53:47 PM PDT 24
Peak memory 216780 kb
Host smart-f26fdda3-42dd-400a-ae86-32ab6780edcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207222984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2207222984
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1301157559
Short name T521
Test name
Test status
Simulation time 113347108 ps
CPU time 2.37 seconds
Started Jul 20 06:53:31 PM PDT 24
Finished Jul 20 06:53:41 PM PDT 24
Peak memory 216668 kb
Host smart-f86bf4cd-b32f-47ab-923d-1df33f8cc60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301157559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1301157559
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3579432256
Short name T53
Test name
Test status
Simulation time 90108721 ps
CPU time 0.81 seconds
Started Jul 20 06:53:28 PM PDT 24
Finished Jul 20 06:53:36 PM PDT 24
Peak memory 206444 kb
Host smart-c8e136cc-68e9-4cd8-ac89-bacafeb59269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579432256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3579432256
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3478837707
Short name T213
Test name
Test status
Simulation time 3499597897 ps
CPU time 9.84 seconds
Started Jul 20 06:53:32 PM PDT 24
Finished Jul 20 06:53:49 PM PDT 24
Peak memory 248604 kb
Host smart-d6c8f081-5510-48f5-b27f-0324aafce887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478837707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3478837707
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3850770091
Short name T985
Test name
Test status
Simulation time 200047465 ps
CPU time 0.8 seconds
Started Jul 20 06:53:40 PM PDT 24
Finished Jul 20 06:53:49 PM PDT 24
Peak memory 206264 kb
Host smart-04582cda-07b6-419b-aba3-1322f797abf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850770091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3850770091
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1605581278
Short name T585
Test name
Test status
Simulation time 302525160 ps
CPU time 2.91 seconds
Started Jul 20 06:53:38 PM PDT 24
Finished Jul 20 06:53:48 PM PDT 24
Peak memory 224916 kb
Host smart-0d12cd45-5109-4ecb-8e57-6bd070903bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605581278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1605581278
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2325117424
Short name T943
Test name
Test status
Simulation time 21414232 ps
CPU time 0.75 seconds
Started Jul 20 06:53:31 PM PDT 24
Finished Jul 20 06:53:39 PM PDT 24
Peak memory 206048 kb
Host smart-e11bb6c2-e429-4b65-99b8-8e30dbe406eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325117424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2325117424
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.188636916
Short name T292
Test name
Test status
Simulation time 57791837526 ps
CPU time 222.37 seconds
Started Jul 20 06:53:37 PM PDT 24
Finished Jul 20 06:57:27 PM PDT 24
Peak memory 254664 kb
Host smart-99b87d7c-fb50-48cc-a395-2bb44803d718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188636916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.188636916
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1635888450
Short name T675
Test name
Test status
Simulation time 5628594698 ps
CPU time 63.13 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:54:49 PM PDT 24
Peak memory 249984 kb
Host smart-578e60df-f275-439a-b8c3-7f6214694699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635888450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1635888450
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2041345300
Short name T300
Test name
Test status
Simulation time 10802761058 ps
CPU time 50.09 seconds
Started Jul 20 06:53:38 PM PDT 24
Finished Jul 20 06:54:36 PM PDT 24
Peak memory 256608 kb
Host smart-44c8ff29-be11-4b25-ab93-b299a93b95d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041345300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2041345300
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2706999618
Short name T505
Test name
Test status
Simulation time 2240810459 ps
CPU time 10.85 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:57 PM PDT 24
Peak memory 225016 kb
Host smart-e1b0482a-dbc6-4f1d-b0b2-7c544a0a0dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706999618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2706999618
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2239003787
Short name T286
Test name
Test status
Simulation time 5943304248 ps
CPU time 27.44 seconds
Started Jul 20 06:53:40 PM PDT 24
Finished Jul 20 06:54:16 PM PDT 24
Peak memory 233160 kb
Host smart-4bc44be1-2ffc-419a-abfa-79e7047f82e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239003787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2239003787
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3608239843
Short name T807
Test name
Test status
Simulation time 721846496 ps
CPU time 2.53 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:48 PM PDT 24
Peak memory 225032 kb
Host smart-e08523c6-3f19-4c0f-abf4-15b98a153349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608239843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3608239843
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3680508355
Short name T354
Test name
Test status
Simulation time 309325611 ps
CPU time 2.04 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:39 PM PDT 24
Peak memory 223632 kb
Host smart-412b32d7-a28d-4e81-85a7-cebb3ec8995d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680508355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3680508355
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.120623771
Short name T558
Test name
Test status
Simulation time 310598001 ps
CPU time 7.28 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:53 PM PDT 24
Peak memory 219768 kb
Host smart-8a1b990b-e962-45e8-a218-cfea2af2e393
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=120623771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.120623771
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.753393508
Short name T391
Test name
Test status
Simulation time 168828337 ps
CPU time 1.16 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:47 PM PDT 24
Peak memory 207276 kb
Host smart-48927f41-6bd8-4fe6-bb8a-1662fda3dccb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753393508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.753393508
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.108724818
Short name T481
Test name
Test status
Simulation time 4230113178 ps
CPU time 12.88 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:51 PM PDT 24
Peak memory 217020 kb
Host smart-5125ba10-4f9a-4f93-be7d-6844198ffe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108724818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.108724818
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3389881329
Short name T524
Test name
Test status
Simulation time 34980946 ps
CPU time 0.69 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:38 PM PDT 24
Peak memory 206168 kb
Host smart-cd32e779-f8a7-48fc-8a3a-d8301bf77f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389881329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3389881329
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.209848772
Short name T340
Test name
Test status
Simulation time 368293312 ps
CPU time 1.78 seconds
Started Jul 20 06:53:30 PM PDT 24
Finished Jul 20 06:53:40 PM PDT 24
Peak memory 216712 kb
Host smart-d63f6d42-1d91-4e99-bd6d-e7526e2ff665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209848772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.209848772
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2424502937
Short name T889
Test name
Test status
Simulation time 174659342 ps
CPU time 0.9 seconds
Started Jul 20 06:53:29 PM PDT 24
Finished Jul 20 06:53:36 PM PDT 24
Peak memory 206884 kb
Host smart-234ca3b3-a61d-4ba2-b50d-8f00172be2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424502937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2424502937
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1750071960
Short name T940
Test name
Test status
Simulation time 9346598008 ps
CPU time 11.17 seconds
Started Jul 20 06:53:38 PM PDT 24
Finished Jul 20 06:53:56 PM PDT 24
Peak memory 233180 kb
Host smart-0b4268ef-e943-4d37-a7c4-066cae119062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750071960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1750071960
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1885445198
Short name T541
Test name
Test status
Simulation time 48502950 ps
CPU time 0.71 seconds
Started Jul 20 06:52:07 PM PDT 24
Finished Jul 20 06:52:09 PM PDT 24
Peak memory 205364 kb
Host smart-b710415e-0cfa-4786-af81-7cfb4650d4c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885445198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
885445198
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3876552734
Short name T285
Test name
Test status
Simulation time 210568184 ps
CPU time 2.79 seconds
Started Jul 20 06:52:02 PM PDT 24
Finished Jul 20 06:52:06 PM PDT 24
Peak memory 233088 kb
Host smart-eca914b6-a7a3-44e3-8bd8-227d044db535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876552734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3876552734
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.425270131
Short name T561
Test name
Test status
Simulation time 97345066 ps
CPU time 0.76 seconds
Started Jul 20 06:52:03 PM PDT 24
Finished Jul 20 06:52:05 PM PDT 24
Peak memory 207396 kb
Host smart-124a8be9-ee51-482f-a414-a65df5b261cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425270131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.425270131
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1280554864
Short name T603
Test name
Test status
Simulation time 1382342373 ps
CPU time 8.31 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:18 PM PDT 24
Peak memory 235292 kb
Host smart-1710826d-8d7b-4a70-8c07-ec1add7567b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280554864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1280554864
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3481545911
Short name T212
Test name
Test status
Simulation time 68030847095 ps
CPU time 170.6 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 249364 kb
Host smart-a6232cf3-aba0-45bb-a00f-62396d077e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481545911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3481545911
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.591130877
Short name T900
Test name
Test status
Simulation time 176369777267 ps
CPU time 458.23 seconds
Started Jul 20 06:52:07 PM PDT 24
Finished Jul 20 06:59:46 PM PDT 24
Peak memory 263380 kb
Host smart-2ee1503d-1d43-4429-a7f9-5088efa81475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591130877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
591130877
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2739330432
Short name T410
Test name
Test status
Simulation time 457859571 ps
CPU time 6.3 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:16 PM PDT 24
Peak memory 239288 kb
Host smart-7260b601-5b31-42d2-b770-13386b48ffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739330432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2739330432
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1692736175
Short name T535
Test name
Test status
Simulation time 1982565740 ps
CPU time 9.48 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:22 PM PDT 24
Peak memory 235316 kb
Host smart-fc498af4-4966-4d64-8486-10f58c97b6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692736175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1692736175
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1214712506
Short name T824
Test name
Test status
Simulation time 3527908661 ps
CPU time 9.65 seconds
Started Jul 20 06:52:07 PM PDT 24
Finished Jul 20 06:52:18 PM PDT 24
Peak memory 224984 kb
Host smart-0fbb02e3-29db-4245-92fb-9cfa6bcc83d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214712506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1214712506
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.4153404941
Short name T537
Test name
Test status
Simulation time 8485118656 ps
CPU time 97.19 seconds
Started Jul 20 06:52:08 PM PDT 24
Finished Jul 20 06:53:46 PM PDT 24
Peak memory 241396 kb
Host smart-42afa223-0063-469b-b562-c90ccf8f3eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153404941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.4153404941
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1656182389
Short name T296
Test name
Test status
Simulation time 2486277816 ps
CPU time 9.7 seconds
Started Jul 20 06:52:07 PM PDT 24
Finished Jul 20 06:52:18 PM PDT 24
Peak memory 233124 kb
Host smart-c8408f45-8dbe-4340-8a8a-d776fee1cb14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656182389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1656182389
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.460840823
Short name T828
Test name
Test status
Simulation time 4003585407 ps
CPU time 13.27 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:26 PM PDT 24
Peak memory 233172 kb
Host smart-966ea89e-4abb-44aa-80d3-8123119ce0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460840823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.460840823
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3642641350
Short name T407
Test name
Test status
Simulation time 3613397943 ps
CPU time 10.73 seconds
Started Jul 20 06:52:02 PM PDT 24
Finished Jul 20 06:52:13 PM PDT 24
Peak memory 219460 kb
Host smart-de3abd07-8cbb-459b-a23a-0e552fdb3dd7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3642641350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3642641350
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.177533723
Short name T70
Test name
Test status
Simulation time 410527820 ps
CPU time 1.8 seconds
Started Jul 20 06:52:08 PM PDT 24
Finished Jul 20 06:52:11 PM PDT 24
Peak memory 236060 kb
Host smart-cf9ccd97-2087-42f3-82f3-6f4a107f9625
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177533723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.177533723
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3208710468
Short name T17
Test name
Test status
Simulation time 3063440545 ps
CPU time 22.72 seconds
Started Jul 20 06:52:08 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 252852 kb
Host smart-5eeffde8-7a8f-4314-afc3-6041bc50f59f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208710468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3208710468
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1860924477
Short name T487
Test name
Test status
Simulation time 3022149250 ps
CPU time 21.64 seconds
Started Jul 20 06:52:08 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 216716 kb
Host smart-08e81e05-0f21-4765-8ffb-3c21ed30c185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860924477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1860924477
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3997049250
Short name T356
Test name
Test status
Simulation time 31749365 ps
CPU time 0.72 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:52:07 PM PDT 24
Peak memory 206156 kb
Host smart-97a1d74e-9746-43e8-9594-f4dfe137f150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997049250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3997049250
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2108624228
Short name T955
Test name
Test status
Simulation time 537617819 ps
CPU time 1.02 seconds
Started Jul 20 06:52:06 PM PDT 24
Finished Jul 20 06:52:08 PM PDT 24
Peak memory 207544 kb
Host smart-7704f39f-380f-4ad6-848a-620d6b4a016b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108624228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2108624228
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.565216989
Short name T32
Test name
Test status
Simulation time 118533901 ps
CPU time 0.83 seconds
Started Jul 20 06:52:07 PM PDT 24
Finished Jul 20 06:52:08 PM PDT 24
Peak memory 206456 kb
Host smart-5780b590-8c20-470c-81ff-b1bd33d2c7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565216989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.565216989
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.691691810
Short name T253
Test name
Test status
Simulation time 1313068275 ps
CPU time 3.63 seconds
Started Jul 20 06:52:03 PM PDT 24
Finished Jul 20 06:52:08 PM PDT 24
Peak memory 233052 kb
Host smart-d9b70840-3180-4d1f-8020-af0d2ecaa1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691691810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.691691810
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2525393058
Short name T384
Test name
Test status
Simulation time 110104812 ps
CPU time 0.74 seconds
Started Jul 20 06:53:42 PM PDT 24
Finished Jul 20 06:53:51 PM PDT 24
Peak memory 206000 kb
Host smart-c413a2d7-31f1-4cf5-a5a1-7e9d30923015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525393058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2525393058
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2508915841
Short name T458
Test name
Test status
Simulation time 61008440 ps
CPU time 2.62 seconds
Started Jul 20 06:53:40 PM PDT 24
Finished Jul 20 06:53:51 PM PDT 24
Peak memory 232728 kb
Host smart-fd79b8c0-3812-43c3-ae58-8b9f79652713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508915841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2508915841
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.21140576
Short name T1001
Test name
Test status
Simulation time 128096747 ps
CPU time 0.82 seconds
Started Jul 20 06:53:38 PM PDT 24
Finished Jul 20 06:53:46 PM PDT 24
Peak memory 207384 kb
Host smart-3cd78f77-e856-4513-8130-0c2411557b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21140576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.21140576
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1898310777
Short name T215
Test name
Test status
Simulation time 192377909445 ps
CPU time 156.85 seconds
Started Jul 20 06:53:38 PM PDT 24
Finished Jul 20 06:56:23 PM PDT 24
Peak memory 241380 kb
Host smart-a7d8b9a0-489a-4ff5-927d-2fb1f502f97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898310777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1898310777
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1211827080
Short name T609
Test name
Test status
Simulation time 10103004235 ps
CPU time 72.55 seconds
Started Jul 20 06:53:37 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 241360 kb
Host smart-c545ee62-1658-4217-964f-dc5478d2e685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211827080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1211827080
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2879928561
Short name T480
Test name
Test status
Simulation time 1393317004 ps
CPU time 27.55 seconds
Started Jul 20 06:53:40 PM PDT 24
Finished Jul 20 06:54:15 PM PDT 24
Peak memory 241440 kb
Host smart-4036444e-1542-409b-9f6b-d5340a650543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879928561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2879928561
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1902717493
Short name T139
Test name
Test status
Simulation time 1108612769 ps
CPU time 11.36 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:58 PM PDT 24
Peak memory 234568 kb
Host smart-31d82494-4421-4254-96dd-4ca276984ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902717493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1902717493
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1254033206
Short name T927
Test name
Test status
Simulation time 142628310 ps
CPU time 2.63 seconds
Started Jul 20 06:53:36 PM PDT 24
Finished Jul 20 06:53:46 PM PDT 24
Peak memory 232784 kb
Host smart-b336374f-9363-497a-9b77-d47e3b630a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254033206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1254033206
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1112337945
Short name T533
Test name
Test status
Simulation time 52883316073 ps
CPU time 41.31 seconds
Started Jul 20 06:53:37 PM PDT 24
Finished Jul 20 06:54:25 PM PDT 24
Peak memory 233004 kb
Host smart-0d01a62a-aa70-4aaf-a57f-6b1a675a26b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112337945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1112337945
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.286363524
Short name T605
Test name
Test status
Simulation time 234858106 ps
CPU time 5.06 seconds
Started Jul 20 06:53:41 PM PDT 24
Finished Jul 20 06:53:54 PM PDT 24
Peak memory 233116 kb
Host smart-b97f9d7c-e5b7-4320-a628-2e43946dbbec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286363524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.286363524
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1203599162
Short name T557
Test name
Test status
Simulation time 1487873223 ps
CPU time 7.12 seconds
Started Jul 20 06:53:40 PM PDT 24
Finished Jul 20 06:53:55 PM PDT 24
Peak memory 233088 kb
Host smart-7b25a7a5-0989-48cd-9f59-71cbf9beb701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203599162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1203599162
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2976346542
Short name T795
Test name
Test status
Simulation time 206173245 ps
CPU time 5.54 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:52 PM PDT 24
Peak memory 223672 kb
Host smart-c4629e13-11e2-4de1-af69-47367a8652eb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2976346542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2976346542
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2049832119
Short name T333
Test name
Test status
Simulation time 2155958925 ps
CPU time 14.19 seconds
Started Jul 20 06:53:41 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 216720 kb
Host smart-96c7797a-dc16-40d6-841d-370c038292f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049832119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2049832119
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1491472086
Short name T815
Test name
Test status
Simulation time 1520249386 ps
CPU time 6.3 seconds
Started Jul 20 06:53:41 PM PDT 24
Finished Jul 20 06:53:55 PM PDT 24
Peak memory 216688 kb
Host smart-34c41c21-e7f8-4493-933b-905a81ae8c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491472086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1491472086
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.330154018
Short name T424
Test name
Test status
Simulation time 210350436 ps
CPU time 1.52 seconds
Started Jul 20 06:53:39 PM PDT 24
Finished Jul 20 06:53:48 PM PDT 24
Peak memory 216700 kb
Host smart-3eb77b3b-9cfa-45ba-9408-6470fb0a2e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330154018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.330154018
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.227322959
Short name T720
Test name
Test status
Simulation time 48751370 ps
CPU time 0.74 seconds
Started Jul 20 06:53:42 PM PDT 24
Finished Jul 20 06:53:51 PM PDT 24
Peak memory 206256 kb
Host smart-8bc07022-2327-4d85-bf28-fa7e3757ba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227322959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.227322959
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.643866106
Short name T882
Test name
Test status
Simulation time 9335322629 ps
CPU time 28.36 seconds
Started Jul 20 06:53:38 PM PDT 24
Finished Jul 20 06:54:14 PM PDT 24
Peak memory 242148 kb
Host smart-eb7a96c5-a267-409e-9d87-0797d603f06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643866106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.643866106
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.575363141
Short name T619
Test name
Test status
Simulation time 37098341 ps
CPU time 0.76 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:53:57 PM PDT 24
Peak memory 205928 kb
Host smart-0bbcb299-bf45-40b3-be85-2dcc3721db8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575363141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.575363141
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.4203148950
Short name T887
Test name
Test status
Simulation time 3178511981 ps
CPU time 7.26 seconds
Started Jul 20 06:53:45 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 225024 kb
Host smart-ce87dcf8-02ff-4e31-8b44-65978efe6d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203148950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.4203148950
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1621788802
Short name T960
Test name
Test status
Simulation time 16422130 ps
CPU time 0.76 seconds
Started Jul 20 06:53:45 PM PDT 24
Finished Jul 20 06:53:55 PM PDT 24
Peak memory 206364 kb
Host smart-2b5daa42-c66c-4e4e-a71d-f9fc1f80f660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621788802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1621788802
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3873541570
Short name T408
Test name
Test status
Simulation time 28085743649 ps
CPU time 223.23 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:57:39 PM PDT 24
Peak memory 249616 kb
Host smart-c7e36e76-e38e-4311-b07a-380a952d45a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873541570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3873541570
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4016858833
Short name T967
Test name
Test status
Simulation time 3342088456 ps
CPU time 37.07 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 250680 kb
Host smart-585f9074-65e9-4ab4-aa58-fa76b955b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016858833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4016858833
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.2110013962
Short name T972
Test name
Test status
Simulation time 195396357060 ps
CPU time 334.06 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:59:29 PM PDT 24
Peak memory 250204 kb
Host smart-fbc42660-e9d7-4ab4-98e0-60c9380a6f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110013962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.2110013962
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2759376110
Short name T316
Test name
Test status
Simulation time 2088619890 ps
CPU time 33.31 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:29 PM PDT 24
Peak memory 233132 kb
Host smart-6eb3806e-54b1-4e3f-ba8a-7931997a3c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759376110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2759376110
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1263078673
Short name T897
Test name
Test status
Simulation time 1070733968 ps
CPU time 22.26 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:17 PM PDT 24
Peak memory 238812 kb
Host smart-1fdf9fc6-f33a-46e5-9241-9ca53986e9cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263078673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1263078673
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3008213390
Short name T879
Test name
Test status
Simulation time 2633171668 ps
CPU time 9.44 seconds
Started Jul 20 06:53:45 PM PDT 24
Finished Jul 20 06:54:04 PM PDT 24
Peak memory 224844 kb
Host smart-cd7611b6-4cf3-4986-9d45-5184ed6f22da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008213390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3008213390
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.379906388
Short name T95
Test name
Test status
Simulation time 2347322273 ps
CPU time 27.76 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:54:22 PM PDT 24
Peak memory 233220 kb
Host smart-49aff7db-9aee-4795-9d2d-c4d96f6cd0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379906388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.379906388
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3840894198
Short name T422
Test name
Test status
Simulation time 205956728 ps
CPU time 3.22 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:53:58 PM PDT 24
Peak memory 233156 kb
Host smart-514816e6-7dd2-443f-a09d-f532a0dc3033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840894198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3840894198
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3322828102
Short name T260
Test name
Test status
Simulation time 35967226340 ps
CPU time 14.9 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:54:10 PM PDT 24
Peak memory 238660 kb
Host smart-9c9ee000-0045-46a4-8b05-412ac15b0213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322828102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3322828102
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1265085181
Short name T549
Test name
Test status
Simulation time 454686675 ps
CPU time 4.32 seconds
Started Jul 20 06:53:45 PM PDT 24
Finished Jul 20 06:53:58 PM PDT 24
Peak memory 223564 kb
Host smart-613b2b10-de5e-4b2d-9777-cf8e70daac42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1265085181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1265085181
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.4147904778
Short name T272
Test name
Test status
Simulation time 8912721605 ps
CPU time 207.43 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:57:23 PM PDT 24
Peak memory 269220 kb
Host smart-b970224f-725c-4d75-8bb1-56eb3e516d9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147904778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.4147904778
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2027872310
Short name T701
Test name
Test status
Simulation time 2732544723 ps
CPU time 17.82 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:13 PM PDT 24
Peak memory 217064 kb
Host smart-193769e7-79e6-423f-8476-e8d7fd18f767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027872310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2027872310
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.4058865483
Short name T774
Test name
Test status
Simulation time 4982888973 ps
CPU time 4.34 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:53:59 PM PDT 24
Peak memory 216724 kb
Host smart-12698318-dd41-4051-9d57-411a0f123a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058865483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.4058865483
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1392063593
Short name T341
Test name
Test status
Simulation time 137986081 ps
CPU time 0.87 seconds
Started Jul 20 06:53:44 PM PDT 24
Finished Jul 20 06:53:54 PM PDT 24
Peak memory 207868 kb
Host smart-4ce12886-2803-4f11-a3aa-90a71e295443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392063593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1392063593
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1078553285
Short name T658
Test name
Test status
Simulation time 87565429 ps
CPU time 0.83 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:53:56 PM PDT 24
Peak memory 206444 kb
Host smart-6d8e4f3f-397c-4ca7-8b86-486fcb57e6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078553285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1078553285
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3537577004
Short name T859
Test name
Test status
Simulation time 131545493 ps
CPU time 2.74 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:53:58 PM PDT 24
Peak memory 233112 kb
Host smart-e71f0b2f-2fc9-4ab7-9cc9-95a5874ca988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537577004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3537577004
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3297252279
Short name T733
Test name
Test status
Simulation time 50687565 ps
CPU time 0.73 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:05 PM PDT 24
Peak memory 205372 kb
Host smart-c2b67856-c2db-4234-b86c-be444542b46f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297252279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3297252279
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.4082487875
Short name T794
Test name
Test status
Simulation time 259300438 ps
CPU time 5.1 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 233096 kb
Host smart-c6e185a2-ecfb-4710-be9b-42f62de2e96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082487875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.4082487875
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.821259153
Short name T434
Test name
Test status
Simulation time 57065161 ps
CPU time 0.8 seconds
Started Jul 20 06:53:45 PM PDT 24
Finished Jul 20 06:53:55 PM PDT 24
Peak memory 207372 kb
Host smart-0f5ae9b8-7b2e-4987-94da-9b33662c8d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821259153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.821259153
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1018359259
Short name T484
Test name
Test status
Simulation time 5494505474 ps
CPU time 49.23 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:52 PM PDT 24
Peak memory 239000 kb
Host smart-b2d4a7e1-af5f-4ffd-8497-860381f472e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018359259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1018359259
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.727756061
Short name T834
Test name
Test status
Simulation time 10225348454 ps
CPU time 58.49 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:55:00 PM PDT 24
Peak memory 257704 kb
Host smart-04b76ad7-86d9-4857-929e-97f1667cc37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727756061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.727756061
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.430265726
Short name T751
Test name
Test status
Simulation time 1486320875 ps
CPU time 21.22 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:24 PM PDT 24
Peak memory 236200 kb
Host smart-eef2c9db-66a9-43ce-b0a2-0f90b277f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430265726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.430265726
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1258366348
Short name T599
Test name
Test status
Simulation time 32171079 ps
CPU time 2.65 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:53:58 PM PDT 24
Peak memory 233120 kb
Host smart-851385fb-228c-4030-bad3-9c4b2c52bfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258366348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1258366348
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.888728663
Short name T725
Test name
Test status
Simulation time 10294840236 ps
CPU time 78.02 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:55:14 PM PDT 24
Peak memory 233224 kb
Host smart-b75ceaf7-4329-4477-a1e9-1d127a8016fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888728663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.888728663
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1778727432
Short name T880
Test name
Test status
Simulation time 48227884 ps
CPU time 3.11 seconds
Started Jul 20 06:53:45 PM PDT 24
Finished Jul 20 06:53:57 PM PDT 24
Peak memory 233104 kb
Host smart-c3db83ec-b4ca-41dd-84d6-48b621b55dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778727432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1778727432
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2648166857
Short name T709
Test name
Test status
Simulation time 755560456 ps
CPU time 5.21 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 233064 kb
Host smart-40801c74-cca1-42b0-a387-bfb2856e73bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648166857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2648166857
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2724314264
Short name T198
Test name
Test status
Simulation time 1106785434 ps
CPU time 12.23 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:54:08 PM PDT 24
Peak memory 233120 kb
Host smart-a9876e66-4f9e-4313-adb6-7663d04e5594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724314264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2724314264
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3718990623
Short name T8
Test name
Test status
Simulation time 34419354 ps
CPU time 2.55 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:53:57 PM PDT 24
Peak memory 232764 kb
Host smart-78d563f5-bb89-4f89-a8b3-2e2be073f328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718990623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3718990623
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4072468989
Short name T854
Test name
Test status
Simulation time 374287278 ps
CPU time 5.55 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 223516 kb
Host smart-51f7f50e-c93c-46fc-98c4-de3d43aae261
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4072468989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4072468989
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2291256985
Short name T181
Test name
Test status
Simulation time 7839068320 ps
CPU time 85.46 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:55:30 PM PDT 24
Peak memory 257288 kb
Host smart-e53502ce-aacb-46bd-a32b-7cfe4b3fdebf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291256985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2291256985
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.4172149711
Short name T390
Test name
Test status
Simulation time 9191328791 ps
CPU time 14.84 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:54:10 PM PDT 24
Peak memory 216980 kb
Host smart-458e03ea-a58a-4fa2-b7dc-196b0dcd3771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172149711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.4172149711
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3058710233
Short name T712
Test name
Test status
Simulation time 32982605 ps
CPU time 0.72 seconds
Started Jul 20 06:53:47 PM PDT 24
Finished Jul 20 06:53:56 PM PDT 24
Peak memory 206152 kb
Host smart-3ff10b44-1f23-4005-8443-88212e3e2580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058710233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3058710233
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3094408295
Short name T872
Test name
Test status
Simulation time 109885525 ps
CPU time 0.95 seconds
Started Jul 20 06:53:46 PM PDT 24
Finished Jul 20 06:53:55 PM PDT 24
Peak memory 207572 kb
Host smart-f3cf6c1d-f72c-4664-9c6f-ab492a64b6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094408295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3094408295
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.64324690
Short name T851
Test name
Test status
Simulation time 58294226 ps
CPU time 0.9 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:53:57 PM PDT 24
Peak memory 206456 kb
Host smart-2e611004-ff8c-4245-97f7-c4f0e54e3c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64324690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.64324690
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1217511792
Short name T153
Test name
Test status
Simulation time 7174317107 ps
CPU time 23.78 seconds
Started Jul 20 06:53:48 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 241080 kb
Host smart-656ffc53-2bf2-4b6d-afe9-e31c48fdd044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217511792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1217511792
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3511274240
Short name T989
Test name
Test status
Simulation time 16840676 ps
CPU time 0.75 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:06 PM PDT 24
Peak memory 205368 kb
Host smart-6049ac0c-9ca7-4026-997f-59c4fe6df7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511274240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3511274240
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2580845029
Short name T819
Test name
Test status
Simulation time 1728356231 ps
CPU time 16.4 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:17 PM PDT 24
Peak memory 233136 kb
Host smart-a758075f-a1f4-4071-87e6-21a827dfdf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580845029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2580845029
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1273821102
Short name T708
Test name
Test status
Simulation time 32812308 ps
CPU time 0.79 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 207204 kb
Host smart-0dd686fa-ec7c-4a52-8c81-3d43ef98e2fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273821102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1273821102
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1711729991
Short name T762
Test name
Test status
Simulation time 36463181968 ps
CPU time 55.11 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:55 PM PDT 24
Peak memory 249652 kb
Host smart-f61c5051-dd09-434c-875c-a0adc1332205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711729991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1711729991
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1016116111
Short name T236
Test name
Test status
Simulation time 2372072092 ps
CPU time 34.21 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:34 PM PDT 24
Peak memory 253528 kb
Host smart-a7a3d51e-de55-4445-b822-30263c5e365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016116111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1016116111
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.385154971
Short name T829
Test name
Test status
Simulation time 3151969638 ps
CPU time 16.71 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:16 PM PDT 24
Peak memory 233168 kb
Host smart-f6c4892a-5caa-4240-be92-114c57e1c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385154971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.385154971
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.4192668499
Short name T809
Test name
Test status
Simulation time 10824099234 ps
CPU time 73.7 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:55:15 PM PDT 24
Peak memory 256804 kb
Host smart-c978c6a6-eecd-409e-a475-c3e015412462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192668499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.4192668499
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1524543575
Short name T689
Test name
Test status
Simulation time 3879987441 ps
CPU time 10.43 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:15 PM PDT 24
Peak memory 225024 kb
Host smart-89deed22-8670-482c-a5d4-b41e4ac1ee4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524543575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1524543575
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3668536397
Short name T211
Test name
Test status
Simulation time 10370775593 ps
CPU time 25.5 seconds
Started Jul 20 06:54:02 PM PDT 24
Finished Jul 20 06:54:31 PM PDT 24
Peak memory 239372 kb
Host smart-8fc50287-9ea5-415b-9b8d-cbbb25e92417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668536397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3668536397
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.732210401
Short name T311
Test name
Test status
Simulation time 217905001 ps
CPU time 4.91 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:08 PM PDT 24
Peak memory 233172 kb
Host smart-330006b6-413c-4a0f-8696-9783e8c50eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732210401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.732210401
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4066104011
Short name T221
Test name
Test status
Simulation time 302583961 ps
CPU time 4.05 seconds
Started Jul 20 06:53:58 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 224872 kb
Host smart-d9afa54e-7c42-4116-aef4-88ccdda9b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066104011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4066104011
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1018851167
Short name T660
Test name
Test status
Simulation time 1135642244 ps
CPU time 14 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:17 PM PDT 24
Peak memory 222836 kb
Host smart-de1f91b6-75c1-4aac-802f-b725f3d00177
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018851167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1018851167
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.485011585
Short name T913
Test name
Test status
Simulation time 37571910 ps
CPU time 0.89 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:02 PM PDT 24
Peak memory 206168 kb
Host smart-351c1a8e-092c-4e9c-9c09-3affed85b9f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485011585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.485011585
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1242691915
Short name T931
Test name
Test status
Simulation time 5226381653 ps
CPU time 30.68 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 220468 kb
Host smart-03981970-d85a-4b20-8edc-06dfb7995078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242691915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1242691915
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.169409990
Short name T919
Test name
Test status
Simulation time 6026860629 ps
CPU time 3.36 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:08 PM PDT 24
Peak memory 216880 kb
Host smart-aec4032d-b9ce-4c69-860d-686d23c3742a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169409990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.169409990
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3476461637
Short name T833
Test name
Test status
Simulation time 310707129 ps
CPU time 1.2 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:06 PM PDT 24
Peak memory 208376 kb
Host smart-c6e123d5-525d-4e11-9859-888829360cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476461637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3476461637
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.864454833
Short name T804
Test name
Test status
Simulation time 510647411 ps
CPU time 0.9 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:04 PM PDT 24
Peak memory 206456 kb
Host smart-e967636f-5d20-42fd-b9bf-1a222377012d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864454833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.864454833
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3129984909
Short name T470
Test name
Test status
Simulation time 402632296 ps
CPU time 7.67 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:12 PM PDT 24
Peak memory 239740 kb
Host smart-79dc599e-55a2-48ff-b709-54646aa42458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129984909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3129984909
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3466854788
Short name T62
Test name
Test status
Simulation time 11709584 ps
CPU time 0.72 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:05 PM PDT 24
Peak memory 205928 kb
Host smart-5daec76f-dc73-45b6-9845-c85f4e46d92b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466854788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3466854788
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3586575001
Short name T279
Test name
Test status
Simulation time 201820522 ps
CPU time 4.3 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:09 PM PDT 24
Peak memory 233064 kb
Host smart-39fc67bb-5a22-48bf-8110-397baec0ce23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586575001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3586575001
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1363237272
Short name T747
Test name
Test status
Simulation time 29178615 ps
CPU time 0.77 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:06 PM PDT 24
Peak memory 206084 kb
Host smart-1c3f5400-28e0-49cd-8516-af292aecf95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363237272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1363237272
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2571520305
Short name T291
Test name
Test status
Simulation time 37508080902 ps
CPU time 123.05 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:56:06 PM PDT 24
Peak memory 257788 kb
Host smart-20f615f2-4dd4-49b2-bc0e-88a3d4486cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571520305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2571520305
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1231416432
Short name T610
Test name
Test status
Simulation time 94697889203 ps
CPU time 160.71 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:56:41 PM PDT 24
Peak memory 251936 kb
Host smart-579424de-f041-4cd0-9feb-10fd0a7b53a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231416432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1231416432
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.368833838
Short name T132
Test name
Test status
Simulation time 175479236272 ps
CPU time 170.95 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:56:51 PM PDT 24
Peak memory 254480 kb
Host smart-63efe5b2-ecf1-4937-aac2-0ac1d2ca65a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368833838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.368833838
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.195698358
Short name T157
Test name
Test status
Simulation time 4187445930 ps
CPU time 10.55 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:15 PM PDT 24
Peak memory 233260 kb
Host smart-6f6bae11-49ca-4fe8-93a5-68ed9e25fbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195698358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.195698358
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.783367634
Short name T923
Test name
Test status
Simulation time 2264774588 ps
CPU time 56.22 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:55:01 PM PDT 24
Peak memory 262364 kb
Host smart-418c2991-5765-49d9-84bf-f07120d4a7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783367634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.783367634
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.533215060
Short name T234
Test name
Test status
Simulation time 4016438838 ps
CPU time 5.94 seconds
Started Jul 20 06:54:02 PM PDT 24
Finished Jul 20 06:54:11 PM PDT 24
Peak memory 219388 kb
Host smart-7ac7123b-023f-4068-92f1-dcbeef658e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533215060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.533215060
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3104833890
Short name T674
Test name
Test status
Simulation time 975791170 ps
CPU time 15.86 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 249932 kb
Host smart-e13d4b05-5116-49e9-b6fc-349614291a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104833890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3104833890
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3708162366
Short name T274
Test name
Test status
Simulation time 1489054509 ps
CPU time 10.54 seconds
Started Jul 20 06:54:02 PM PDT 24
Finished Jul 20 06:54:16 PM PDT 24
Peak memory 233100 kb
Host smart-fdebf9ea-3330-426f-81c8-6a90c3b079da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708162366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3708162366
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2611056557
Short name T459
Test name
Test status
Simulation time 541452070 ps
CPU time 6.16 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:11 PM PDT 24
Peak memory 233148 kb
Host smart-b5305263-38d5-4d27-a06d-e8dfda7df783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611056557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2611056557
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3244275444
Short name T691
Test name
Test status
Simulation time 2575089550 ps
CPU time 11.72 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:11 PM PDT 24
Peak memory 223504 kb
Host smart-4305442c-fdd6-4d71-a672-151a3e55db8c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3244275444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3244275444
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2558677551
Short name T436
Test name
Test status
Simulation time 9991599046 ps
CPU time 70.98 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:55:11 PM PDT 24
Peak memory 249692 kb
Host smart-4edebcb8-e555-480b-b257-57527f671907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558677551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2558677551
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3151767286
Short name T973
Test name
Test status
Simulation time 3782669075 ps
CPU time 19.79 seconds
Started Jul 20 06:53:58 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 216712 kb
Host smart-e257f757-8c71-4fcb-9871-7d7628108566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151767286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3151767286
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4041288007
Short name T949
Test name
Test status
Simulation time 9707565964 ps
CPU time 27.3 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 216780 kb
Host smart-5a8441ff-8c12-4a20-8a0e-1c0a0cdfce7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041288007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4041288007
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1350389490
Short name T602
Test name
Test status
Simulation time 13849290 ps
CPU time 0.77 seconds
Started Jul 20 06:53:59 PM PDT 24
Finished Jul 20 06:54:01 PM PDT 24
Peak memory 206380 kb
Host smart-6f8928ee-2f37-44f4-bd5c-7e25b9ed906d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350389490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1350389490
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.518822860
Short name T690
Test name
Test status
Simulation time 25243251 ps
CPU time 0.77 seconds
Started Jul 20 06:54:00 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 206436 kb
Host smart-27b1cf2e-02c3-49c4-90f5-b85831ae3277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518822860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.518822860
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1921980333
Short name T189
Test name
Test status
Simulation time 804113637 ps
CPU time 3.74 seconds
Started Jul 20 06:54:01 PM PDT 24
Finished Jul 20 06:54:08 PM PDT 24
Peak memory 233160 kb
Host smart-00dd50dc-38a0-43af-bfa4-0e3139e7bd4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921980333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1921980333
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2161026160
Short name T759
Test name
Test status
Simulation time 39615533 ps
CPU time 0.74 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:17 PM PDT 24
Peak memory 205980 kb
Host smart-4ee4da75-65a7-4db9-b3b3-9be47645ca11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161026160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2161026160
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.2037669932
Short name T970
Test name
Test status
Simulation time 420852709 ps
CPU time 3.36 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 224888 kb
Host smart-f06caf72-f58b-4550-8bbd-5abb3a0afcf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037669932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.2037669932
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.894431068
Short name T718
Test name
Test status
Simulation time 66487437 ps
CPU time 0.79 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:54:11 PM PDT 24
Peak memory 207096 kb
Host smart-ca00e515-f313-4ca1-99be-1ffdf121e4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894431068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.894431068
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.1207021323
Short name T27
Test name
Test status
Simulation time 95243736098 ps
CPU time 142.23 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:56:33 PM PDT 24
Peak memory 249560 kb
Host smart-7b370830-60f2-4036-8933-b5057b30cbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207021323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.1207021323
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3721228098
Short name T158
Test name
Test status
Simulation time 9075298366 ps
CPU time 97.73 seconds
Started Jul 20 06:54:13 PM PDT 24
Finished Jul 20 06:55:52 PM PDT 24
Peak memory 240888 kb
Host smart-2e72d44c-8bd6-4e3b-b2b0-34a678f48114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721228098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3721228098
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2139686452
Short name T946
Test name
Test status
Simulation time 21956871583 ps
CPU time 77.32 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:55:31 PM PDT 24
Peak memory 241436 kb
Host smart-7390c000-1482-4c6e-bb8c-f6c921c538ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139686452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2139686452
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2187300735
Short name T930
Test name
Test status
Simulation time 121798163 ps
CPU time 4.28 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:18 PM PDT 24
Peak memory 234340 kb
Host smart-3346e50e-1843-42fb-9e33-3ceb2830faf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187300735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2187300735
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.2423787319
Short name T598
Test name
Test status
Simulation time 31226420289 ps
CPU time 38.35 seconds
Started Jul 20 06:54:12 PM PDT 24
Finished Jul 20 06:54:52 PM PDT 24
Peak memory 241400 kb
Host smart-f675c199-3826-4e47-b971-6c3a84d89d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423787319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.2423787319
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.4024453183
Short name T841
Test name
Test status
Simulation time 119933925 ps
CPU time 3.02 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 224832 kb
Host smart-aa66f4bc-4fe0-41ee-92fd-0e015333edec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024453183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.4024453183
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.444042622
Short name T488
Test name
Test status
Simulation time 39809282343 ps
CPU time 73.89 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:55:25 PM PDT 24
Peak memory 241020 kb
Host smart-6f270201-f1d3-49c8-8ca2-d4e93ad9ea0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444042622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.444042622
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2941487194
Short name T736
Test name
Test status
Simulation time 3773575962 ps
CPU time 13.97 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:54:25 PM PDT 24
Peak memory 233132 kb
Host smart-aa24a788-945c-42ce-886d-a44bf1f738c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941487194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2941487194
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3275507141
Short name T429
Test name
Test status
Simulation time 1349730483 ps
CPU time 8.85 seconds
Started Jul 20 06:54:12 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 224912 kb
Host smart-dbfa63dc-6cba-4b26-9c66-164c0832800c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275507141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3275507141
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4009816494
Short name T606
Test name
Test status
Simulation time 235092139 ps
CPU time 4.06 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:54:15 PM PDT 24
Peak memory 220956 kb
Host smart-33bcf834-2bdf-410e-a88d-f9626316483b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4009816494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4009816494
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2148196209
Short name T683
Test name
Test status
Simulation time 16801043266 ps
CPU time 43.82 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:55:00 PM PDT 24
Peak memory 216776 kb
Host smart-b78ba178-c536-4ce7-a87a-b70c7666568d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148196209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2148196209
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2755220030
Short name T1009
Test name
Test status
Simulation time 377288248 ps
CPU time 3.43 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:14 PM PDT 24
Peak memory 216620 kb
Host smart-a07e22e5-6cd4-427c-af13-05141ff14996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755220030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2755220030
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3841127996
Short name T947
Test name
Test status
Simulation time 64897584 ps
CPU time 1.06 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:13 PM PDT 24
Peak memory 207732 kb
Host smart-83b01fd6-a1de-415e-a440-95abb7ec2119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841127996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3841127996
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1039212972
Short name T31
Test name
Test status
Simulation time 102588144 ps
CPU time 0.99 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:17 PM PDT 24
Peak memory 206680 kb
Host smart-5ddc33b6-19ec-4212-8648-23a883269dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039212972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1039212972
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1483346403
Short name T626
Test name
Test status
Simulation time 5173192470 ps
CPU time 5.2 seconds
Started Jul 20 06:54:12 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 224956 kb
Host smart-0cfe8bd9-2adf-40e2-9525-b11ea0c9379f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483346403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1483346403
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2261464837
Short name T752
Test name
Test status
Simulation time 14336985 ps
CPU time 0.71 seconds
Started Jul 20 06:54:16 PM PDT 24
Finished Jul 20 06:54:18 PM PDT 24
Peak memory 205320 kb
Host smart-f0650245-9816-44b9-bc06-b0df2b38424c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261464837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2261464837
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3220730477
Short name T84
Test name
Test status
Simulation time 135492525 ps
CPU time 2.9 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:16 PM PDT 24
Peak memory 233080 kb
Host smart-674dfea6-4776-478f-bda8-d2f120df98bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220730477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3220730477
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3865180121
Short name T625
Test name
Test status
Simulation time 71911577 ps
CPU time 0.82 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:13 PM PDT 24
Peak memory 207056 kb
Host smart-47d164bf-9865-4b81-b990-539670638393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865180121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3865180121
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.1298602794
Short name T186
Test name
Test status
Simulation time 84185029591 ps
CPU time 169.98 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:57:00 PM PDT 24
Peak memory 255560 kb
Host smart-ed0def2f-4f0f-4567-83a0-d722a248628d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298602794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.1298602794
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2111110915
Short name T952
Test name
Test status
Simulation time 61257945957 ps
CPU time 465.79 seconds
Started Jul 20 06:54:12 PM PDT 24
Finished Jul 20 07:02:00 PM PDT 24
Peak memory 263852 kb
Host smart-b35d6a78-d243-46dd-b597-1bd9b3af1798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111110915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2111110915
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3575857533
Short name T52
Test name
Test status
Simulation time 1053942272693 ps
CPU time 616.09 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 07:04:32 PM PDT 24
Peak memory 265632 kb
Host smart-5f2458e2-36a5-4600-9c7b-5768b7d9b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575857533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3575857533
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3255768054
Short name T452
Test name
Test status
Simulation time 9019288916 ps
CPU time 17.88 seconds
Started Jul 20 06:54:15 PM PDT 24
Finished Jul 20 06:54:35 PM PDT 24
Peak memory 235340 kb
Host smart-6d882cf6-0245-4aa3-8e85-72791169cf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255768054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3255768054
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2081209557
Short name T303
Test name
Test status
Simulation time 328322491957 ps
CPU time 277.7 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:58:49 PM PDT 24
Peak memory 250636 kb
Host smart-fc77fcdc-b7f0-4cb5-9b82-c5e5c15c2078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081209557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2081209557
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3322878385
Short name T934
Test name
Test status
Simulation time 1260821884 ps
CPU time 11.37 seconds
Started Jul 20 06:54:16 PM PDT 24
Finished Jul 20 06:54:29 PM PDT 24
Peak memory 233092 kb
Host smart-c45ee426-8531-4a71-84f8-3a826f8c0cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322878385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3322878385
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4263559835
Short name T802
Test name
Test status
Simulation time 3643999174 ps
CPU time 19.81 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:36 PM PDT 24
Peak memory 233236 kb
Host smart-480494bc-eacf-4130-b48a-57322db5bf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263559835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4263559835
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3538104166
Short name T645
Test name
Test status
Simulation time 65100973 ps
CPU time 2.29 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:14 PM PDT 24
Peak memory 232772 kb
Host smart-52cb81bd-8c85-4450-b01e-ef776333677c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538104166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3538104166
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3041437601
Short name T376
Test name
Test status
Simulation time 11599223469 ps
CPU time 5.59 seconds
Started Jul 20 06:54:12 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 233164 kb
Host smart-25c5330e-e3a6-4c78-8a1c-6a0410bdeb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041437601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3041437601
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.592038602
Short name T360
Test name
Test status
Simulation time 105819939 ps
CPU time 4.53 seconds
Started Jul 20 06:54:13 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 223004 kb
Host smart-baf89a90-558f-42bb-83cb-10948fcc3eee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=592038602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.592038602
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.341269837
Short name T944
Test name
Test status
Simulation time 147012898 ps
CPU time 0.99 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:13 PM PDT 24
Peak memory 207428 kb
Host smart-130feaa7-f565-4ea1-8bdd-84f58aad3ab0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341269837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.341269837
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1524859584
Short name T327
Test name
Test status
Simulation time 21068301102 ps
CPU time 28.44 seconds
Started Jul 20 06:54:13 PM PDT 24
Finished Jul 20 06:54:43 PM PDT 24
Peak memory 216692 kb
Host smart-58d0e930-b8cd-4a0a-908f-f0ac3005fb40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524859584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1524859584
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4110047283
Short name T857
Test name
Test status
Simulation time 2743104869 ps
CPU time 8.17 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 216760 kb
Host smart-090fcfef-9b07-4eca-8571-3605099ed890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110047283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4110047283
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4030566873
Short name T60
Test name
Test status
Simulation time 267442111 ps
CPU time 2.36 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 216656 kb
Host smart-9c7d00bb-b695-4203-8aac-8b50826058d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030566873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4030566873
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2780198308
Short name T154
Test name
Test status
Simulation time 63008553 ps
CPU time 0.91 seconds
Started Jul 20 06:54:13 PM PDT 24
Finished Jul 20 06:54:16 PM PDT 24
Peak memory 206440 kb
Host smart-7097d41e-881d-4e2f-94a2-1ce5f4d9e1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780198308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2780198308
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.195065647
Short name T419
Test name
Test status
Simulation time 1389870945 ps
CPU time 6.36 seconds
Started Jul 20 06:54:13 PM PDT 24
Finished Jul 20 06:54:21 PM PDT 24
Peak memory 233100 kb
Host smart-d5376cc1-46c4-4485-bcb4-a7f1f2249f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195065647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.195065647
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4096500484
Short name T803
Test name
Test status
Simulation time 12869245 ps
CPU time 0.72 seconds
Started Jul 20 06:54:22 PM PDT 24
Finished Jul 20 06:54:24 PM PDT 24
Peak memory 205016 kb
Host smart-e0bf4d86-8ef0-4844-abcb-7ebab74a90ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096500484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4096500484
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1118510878
Short name T957
Test name
Test status
Simulation time 296905837 ps
CPU time 5.38 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 233124 kb
Host smart-88e6a34b-38b6-4c0d-bee7-a174a11e5faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118510878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1118510878
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.177077168
Short name T593
Test name
Test status
Simulation time 21815370 ps
CPU time 0.83 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:14 PM PDT 24
Peak memory 207072 kb
Host smart-6cac2aff-ed1b-464c-9baf-fa3a13c22a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177077168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.177077168
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.272099418
Short name T584
Test name
Test status
Simulation time 11296380 ps
CPU time 0.76 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:17 PM PDT 24
Peak memory 216252 kb
Host smart-5c99fcaf-9b23-4a6e-b33c-34399b85c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272099418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.272099418
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1398095505
Short name T46
Test name
Test status
Simulation time 6686635268 ps
CPU time 23.49 seconds
Started Jul 20 06:54:17 PM PDT 24
Finished Jul 20 06:54:42 PM PDT 24
Peak memory 233212 kb
Host smart-be14fd5a-befb-41ba-ac5f-7df72a1555fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398095505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1398095505
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2240177817
Short name T309
Test name
Test status
Simulation time 32996817072 ps
CPU time 219.18 seconds
Started Jul 20 06:54:19 PM PDT 24
Finished Jul 20 06:57:59 PM PDT 24
Peak memory 240852 kb
Host smart-43c719f5-f4cc-482f-b9b8-987ed7f93c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240177817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2240177817
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2597307048
Short name T705
Test name
Test status
Simulation time 1890972227 ps
CPU time 21.07 seconds
Started Jul 20 06:54:12 PM PDT 24
Finished Jul 20 06:54:35 PM PDT 24
Peak memory 237628 kb
Host smart-21f9e95f-b8b8-4d77-8e01-dc5e16edfb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597307048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2597307048
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.927761814
Short name T895
Test name
Test status
Simulation time 700399509 ps
CPU time 15.56 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:27 PM PDT 24
Peak memory 224952 kb
Host smart-802de38d-bb23-4960-958a-a2d328d93395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927761814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.927761814
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2848207580
Short name T607
Test name
Test status
Simulation time 308314628 ps
CPU time 5.71 seconds
Started Jul 20 06:54:16 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 227984 kb
Host smart-68fa238f-211c-404d-9ab2-06bd556bca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848207580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2848207580
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.2260388296
Short name T742
Test name
Test status
Simulation time 1788309503 ps
CPU time 27.71 seconds
Started Jul 20 06:54:13 PM PDT 24
Finished Jul 20 06:54:42 PM PDT 24
Peak memory 236512 kb
Host smart-e7140a4a-38a7-4483-a12f-7dd68a17a58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260388296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2260388296
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3611071160
Short name T796
Test name
Test status
Simulation time 5969803786 ps
CPU time 7.01 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 225032 kb
Host smart-01342e08-fb8d-445d-890d-ae04a3d6bded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611071160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3611071160
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3970672896
Short name T562
Test name
Test status
Simulation time 1058275330 ps
CPU time 6.6 seconds
Started Jul 20 06:54:16 PM PDT 24
Finished Jul 20 06:54:24 PM PDT 24
Peak memory 233100 kb
Host smart-4677ebe8-cced-4c81-a244-96a05d081fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970672896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3970672896
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.709150588
Short name T388
Test name
Test status
Simulation time 647263695 ps
CPU time 8.85 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:21 PM PDT 24
Peak memory 222884 kb
Host smart-73095b63-7b0b-4917-8c87-1579c5f7a406
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=709150588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.709150588
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.649744007
Short name T665
Test name
Test status
Simulation time 527163490227 ps
CPU time 542.73 seconds
Started Jul 20 06:54:20 PM PDT 24
Finished Jul 20 07:03:24 PM PDT 24
Peak memory 266088 kb
Host smart-601c8efa-cfe1-402a-bd6d-25bc464acf57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649744007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.649744007
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1397480184
Short name T914
Test name
Test status
Simulation time 9346320212 ps
CPU time 13.91 seconds
Started Jul 20 06:54:11 PM PDT 24
Finished Jul 20 06:54:27 PM PDT 24
Peak memory 216692 kb
Host smart-c9b6e8cc-d248-42f8-8abc-c27a835a124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397480184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1397480184
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1636506271
Short name T358
Test name
Test status
Simulation time 1375659554 ps
CPU time 4.38 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:54:14 PM PDT 24
Peak memory 216552 kb
Host smart-31ed1ded-07b7-4194-88fb-916d53f5dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636506271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1636506271
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.4046475458
Short name T344
Test name
Test status
Simulation time 585012745 ps
CPU time 1.87 seconds
Started Jul 20 06:54:10 PM PDT 24
Finished Jul 20 06:54:14 PM PDT 24
Peak memory 216656 kb
Host smart-666e59c6-f6bb-4caf-95d5-d9c5eb540d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046475458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4046475458
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2657744248
Short name T385
Test name
Test status
Simulation time 116597014 ps
CPU time 1.01 seconds
Started Jul 20 06:54:14 PM PDT 24
Finished Jul 20 06:54:18 PM PDT 24
Peak memory 207420 kb
Host smart-54792012-3e95-4673-9b48-90cac3533b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657744248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2657744248
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3254910363
Short name T624
Test name
Test status
Simulation time 26453746444 ps
CPU time 23.07 seconds
Started Jul 20 06:54:09 PM PDT 24
Finished Jul 20 06:54:33 PM PDT 24
Peak memory 224980 kb
Host smart-a8b68deb-6a4e-4520-9c41-0d2969a8a02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254910363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3254910363
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2922134761
Short name T681
Test name
Test status
Simulation time 20241708 ps
CPU time 0.74 seconds
Started Jul 20 06:54:19 PM PDT 24
Finished Jul 20 06:54:21 PM PDT 24
Peak memory 205904 kb
Host smart-7235b74f-16d8-48cf-ad98-87815e94b232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922134761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2922134761
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1118554258
Short name T241
Test name
Test status
Simulation time 1198211581 ps
CPU time 3.39 seconds
Started Jul 20 06:54:19 PM PDT 24
Finished Jul 20 06:54:24 PM PDT 24
Peak memory 233152 kb
Host smart-45ee3490-f7d4-43ab-989a-fb898aaf51b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118554258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1118554258
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3970656709
Short name T965
Test name
Test status
Simulation time 26128343 ps
CPU time 0.81 seconds
Started Jul 20 06:54:18 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 207072 kb
Host smart-c3d55a8f-cc92-480d-a7f2-c9629b36e419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970656709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3970656709
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3314965544
Short name T177
Test name
Test status
Simulation time 1962591099 ps
CPU time 26.93 seconds
Started Jul 20 06:54:20 PM PDT 24
Finished Jul 20 06:54:48 PM PDT 24
Peak memory 239624 kb
Host smart-226d10eb-1aba-41fb-a142-e69f4ec6d7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314965544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3314965544
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3515653713
Short name T713
Test name
Test status
Simulation time 14715075235 ps
CPU time 148.63 seconds
Started Jul 20 06:54:20 PM PDT 24
Finished Jul 20 06:56:50 PM PDT 24
Peak memory 248988 kb
Host smart-e9786675-acb5-4da6-902b-758c34a217a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515653713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3515653713
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2338275827
Short name T650
Test name
Test status
Simulation time 498227746 ps
CPU time 3.39 seconds
Started Jul 20 06:54:20 PM PDT 24
Finished Jul 20 06:54:24 PM PDT 24
Peak memory 224976 kb
Host smart-e95a979b-4604-4ab4-be8e-d5e3369610c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338275827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2338275827
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2940825062
Short name T310
Test name
Test status
Simulation time 2894561685 ps
CPU time 21.16 seconds
Started Jul 20 06:54:19 PM PDT 24
Finished Jul 20 06:54:41 PM PDT 24
Peak memory 241036 kb
Host smart-bb1c4514-d2d2-4d27-8658-5ea6008baba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940825062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2940825062
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3753420191
Short name T498
Test name
Test status
Simulation time 53067740 ps
CPU time 2.93 seconds
Started Jul 20 06:54:19 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 228404 kb
Host smart-a358a037-5ce1-4a64-9a1f-0a2fd91baba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753420191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3753420191
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1902457615
Short name T569
Test name
Test status
Simulation time 3480430983 ps
CPU time 16.54 seconds
Started Jul 20 06:54:17 PM PDT 24
Finished Jul 20 06:54:35 PM PDT 24
Peak memory 250960 kb
Host smart-71ae52e6-db42-47ef-8555-1d6da4b8e4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902457615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1902457615
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2007813567
Short name T414
Test name
Test status
Simulation time 5050141711 ps
CPU time 8.97 seconds
Started Jul 20 06:54:22 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 241192 kb
Host smart-75cff112-1bf5-4f35-bb5c-27deb8a22d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007813567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2007813567
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3488198451
Short name T853
Test name
Test status
Simulation time 6529681330 ps
CPU time 18.95 seconds
Started Jul 20 06:54:19 PM PDT 24
Finished Jul 20 06:54:39 PM PDT 24
Peak memory 233304 kb
Host smart-5e19a423-3c77-46b5-a39f-8ef2e13c3c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488198451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3488198451
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.961718231
Short name T754
Test name
Test status
Simulation time 774416990 ps
CPU time 9.47 seconds
Started Jul 20 06:54:22 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 220524 kb
Host smart-3d26d98a-5a58-40b9-b630-3472b57f5615
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=961718231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.961718231
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.780619564
Short name T191
Test name
Test status
Simulation time 4647133217 ps
CPU time 26.99 seconds
Started Jul 20 06:54:22 PM PDT 24
Finished Jul 20 06:54:50 PM PDT 24
Peak memory 249544 kb
Host smart-3ec90297-d598-4287-a08a-2ef231d6daf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780619564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.780619564
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.1552942065
Short name T338
Test name
Test status
Simulation time 2197078629 ps
CPU time 21.94 seconds
Started Jul 20 06:54:22 PM PDT 24
Finished Jul 20 06:54:45 PM PDT 24
Peak memory 216464 kb
Host smart-8b535906-d41f-49b5-ba51-baa2b38357e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552942065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1552942065
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3007320791
Short name T935
Test name
Test status
Simulation time 639769126 ps
CPU time 3.21 seconds
Started Jul 20 06:54:17 PM PDT 24
Finished Jul 20 06:54:22 PM PDT 24
Peak memory 216612 kb
Host smart-0b8bb27f-64ce-4fda-8d32-716b7f4b367c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007320791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3007320791
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.3380717535
Short name T686
Test name
Test status
Simulation time 79033624 ps
CPU time 1.35 seconds
Started Jul 20 06:54:18 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 216724 kb
Host smart-5dc3a941-9de7-48bd-8e21-3d813d8dc120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380717535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.3380717535
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1189915456
Short name T564
Test name
Test status
Simulation time 146247530 ps
CPU time 0.92 seconds
Started Jul 20 06:54:18 PM PDT 24
Finished Jul 20 06:54:20 PM PDT 24
Peak memory 207468 kb
Host smart-f7854269-7a6b-400d-9e39-00405ef853ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189915456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1189915456
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1527659261
Short name T948
Test name
Test status
Simulation time 277690050 ps
CPU time 2.75 seconds
Started Jul 20 06:54:24 PM PDT 24
Finished Jul 20 06:54:27 PM PDT 24
Peak memory 233248 kb
Host smart-44ad78da-8317-4305-aa15-3a8770dda8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527659261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1527659261
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1221221329
Short name T975
Test name
Test status
Simulation time 37651794 ps
CPU time 0.73 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:29 PM PDT 24
Peak memory 205496 kb
Host smart-bd56eec3-3f0b-43b4-9149-3f704b1a8f93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221221329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1221221329
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2087197800
Short name T693
Test name
Test status
Simulation time 745397891 ps
CPU time 6.66 seconds
Started Jul 20 06:54:23 PM PDT 24
Finished Jul 20 06:54:31 PM PDT 24
Peak memory 225064 kb
Host smart-4ec7166d-a0f4-4efd-8ef4-255f9a439535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087197800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2087197800
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3029236598
Short name T621
Test name
Test status
Simulation time 18702613 ps
CPU time 0.79 seconds
Started Jul 20 06:54:20 PM PDT 24
Finished Jul 20 06:54:21 PM PDT 24
Peak memory 207084 kb
Host smart-aa7d6122-6847-49f2-91f6-0d981832e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029236598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3029236598
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2296406828
Short name T9
Test name
Test status
Simulation time 4276097971 ps
CPU time 40.47 seconds
Started Jul 20 06:54:26 PM PDT 24
Finished Jul 20 06:55:07 PM PDT 24
Peak memory 249596 kb
Host smart-19f9e612-7a1d-4186-8594-abac646a3b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296406828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2296406828
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3065632291
Short name T788
Test name
Test status
Simulation time 3176382148 ps
CPU time 71.8 seconds
Started Jul 20 06:54:30 PM PDT 24
Finished Jul 20 06:55:42 PM PDT 24
Peak memory 264196 kb
Host smart-af8f2006-c3a3-40ec-a1f8-6e1b4d2c9db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065632291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3065632291
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.940377009
Short name T996
Test name
Test status
Simulation time 5563105597 ps
CPU time 38.99 seconds
Started Jul 20 06:54:23 PM PDT 24
Finished Jul 20 06:55:03 PM PDT 24
Peak memory 249412 kb
Host smart-fca4f2df-d7a3-4733-a939-988db6c8c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940377009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.940377009
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.1862702250
Short name T171
Test name
Test status
Simulation time 2588620736 ps
CPU time 32.36 seconds
Started Jul 20 06:54:23 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 240764 kb
Host smart-eb2f964b-6bcc-4aad-bd34-2b92f69f12f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862702250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.1862702250
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.312794641
Short name T644
Test name
Test status
Simulation time 207226629 ps
CPU time 2.16 seconds
Started Jul 20 06:54:23 PM PDT 24
Finished Jul 20 06:54:26 PM PDT 24
Peak memory 232928 kb
Host smart-2e45e65b-b5be-42f3-89c6-f885df2a08a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312794641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.312794641
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3785750166
Short name T821
Test name
Test status
Simulation time 5038369982 ps
CPU time 16.78 seconds
Started Jul 20 06:54:21 PM PDT 24
Finished Jul 20 06:54:39 PM PDT 24
Peak memory 233168 kb
Host smart-f6fe7a14-4cae-4935-822b-1d93c9f0b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785750166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3785750166
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1883679949
Short name T29
Test name
Test status
Simulation time 414385600 ps
CPU time 2.36 seconds
Started Jul 20 06:54:23 PM PDT 24
Finished Jul 20 06:54:27 PM PDT 24
Peak memory 224352 kb
Host smart-af6587de-4152-444d-939d-add2a4620603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883679949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1883679949
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3286841767
Short name T938
Test name
Test status
Simulation time 410112970 ps
CPU time 4.57 seconds
Started Jul 20 06:54:21 PM PDT 24
Finished Jul 20 06:54:26 PM PDT 24
Peak memory 233080 kb
Host smart-2748d47f-c34b-4c13-8bbf-00457b35af60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286841767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3286841767
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2742980814
Short name T622
Test name
Test status
Simulation time 5892121590 ps
CPU time 19.57 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:48 PM PDT 24
Peak memory 222028 kb
Host smart-2948383e-b0f7-4b47-9b38-fe8f9f6ea324
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2742980814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2742980814
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.2200199703
Short name T51
Test name
Test status
Simulation time 51342645210 ps
CPU time 472.78 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 07:02:21 PM PDT 24
Peak memory 285968 kb
Host smart-e6a80867-f48f-4a0a-95a3-89fa4d44f0a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200199703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.2200199703
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2517488956
Short name T618
Test name
Test status
Simulation time 5929080594 ps
CPU time 28.27 seconds
Started Jul 20 06:54:20 PM PDT 24
Finished Jul 20 06:54:49 PM PDT 24
Peak memory 220184 kb
Host smart-c5069438-c6f2-4f37-b956-d9bdc2e4f73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517488956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2517488956
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.325253459
Short name T155
Test name
Test status
Simulation time 556563936 ps
CPU time 2.94 seconds
Started Jul 20 06:54:24 PM PDT 24
Finished Jul 20 06:54:27 PM PDT 24
Peak memory 216796 kb
Host smart-62904d02-2ba6-4dc4-bb88-5a519df5b83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325253459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.325253459
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.4065577543
Short name T787
Test name
Test status
Simulation time 13069702 ps
CPU time 0.71 seconds
Started Jul 20 06:54:18 PM PDT 24
Finished Jul 20 06:54:19 PM PDT 24
Peak memory 206056 kb
Host smart-f92796e6-4a5d-4632-850d-a087c3ecdadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065577543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.4065577543
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1761881594
Short name T543
Test name
Test status
Simulation time 400029910 ps
CPU time 0.91 seconds
Started Jul 20 06:54:22 PM PDT 24
Finished Jul 20 06:54:23 PM PDT 24
Peak memory 206404 kb
Host smart-5175ebcc-f5ac-4c51-b695-9b3b61e478ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761881594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1761881594
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1008786061
Short name T801
Test name
Test status
Simulation time 1029495157 ps
CPU time 5.1 seconds
Started Jul 20 06:54:23 PM PDT 24
Finished Jul 20 06:54:29 PM PDT 24
Peak memory 232868 kb
Host smart-9fed1ff2-5fdc-4309-a99c-f83098fae43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008786061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1008786061
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1516678395
Short name T507
Test name
Test status
Simulation time 14591021 ps
CPU time 0.73 seconds
Started Jul 20 06:52:07 PM PDT 24
Finished Jul 20 06:52:09 PM PDT 24
Peak memory 206292 kb
Host smart-53991820-82b6-4257-b6df-a46fc7e52310
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516678395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
516678395
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.3224111120
Short name T282
Test name
Test status
Simulation time 2399620149 ps
CPU time 12.01 seconds
Started Jul 20 06:52:02 PM PDT 24
Finished Jul 20 06:52:14 PM PDT 24
Peak memory 233136 kb
Host smart-fe065136-1c8c-4828-8ab4-59a5f61fcbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224111120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.3224111120
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.730344874
Short name T820
Test name
Test status
Simulation time 26296039 ps
CPU time 0.8 seconds
Started Jul 20 06:52:03 PM PDT 24
Finished Jul 20 06:52:05 PM PDT 24
Peak memory 206312 kb
Host smart-555c4052-cba1-46a2-ad5e-273b93b91335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730344874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.730344874
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2678308505
Short name T874
Test name
Test status
Simulation time 34097345405 ps
CPU time 116.76 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:54:03 PM PDT 24
Peak memory 249660 kb
Host smart-5e866480-bf14-4f21-96ba-be7f5f3265bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678308505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2678308505
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3732886537
Short name T195
Test name
Test status
Simulation time 16684265889 ps
CPU time 62.35 seconds
Started Jul 20 06:52:03 PM PDT 24
Finished Jul 20 06:53:06 PM PDT 24
Peak memory 249688 kb
Host smart-8584c55f-34b8-44c2-9129-e2822a121bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732886537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3732886537
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_intercept.685049577
Short name T732
Test name
Test status
Simulation time 5641808924 ps
CPU time 6.22 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:19 PM PDT 24
Peak memory 224968 kb
Host smart-b263dc26-52da-40b5-9412-20bcde6cd381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685049577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.685049577
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3147449577
Short name T980
Test name
Test status
Simulation time 733688391 ps
CPU time 8.4 seconds
Started Jul 20 06:52:04 PM PDT 24
Finished Jul 20 06:52:13 PM PDT 24
Peak memory 237076 kb
Host smart-d1e5ae79-ce6d-4837-b66b-c0bb5e181f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147449577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3147449577
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3447672949
Short name T875
Test name
Test status
Simulation time 4285374457 ps
CPU time 11.43 seconds
Started Jul 20 06:52:08 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 224972 kb
Host smart-0e06b21c-32fb-4d42-a453-85e22bb2ca42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447672949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3447672949
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.817373021
Short name T226
Test name
Test status
Simulation time 1732750340 ps
CPU time 4.89 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:15 PM PDT 24
Peak memory 224992 kb
Host smart-ece11ece-bcbe-4ddd-b1b6-9f2e49eae95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817373021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.817373021
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.48986887
Short name T745
Test name
Test status
Simulation time 383761112 ps
CPU time 4.32 seconds
Started Jul 20 06:52:03 PM PDT 24
Finished Jul 20 06:52:08 PM PDT 24
Peak memory 223504 kb
Host smart-c3a099e1-efb2-40e1-a528-a19fcb007eea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=48986887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct
.48986887
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.820109560
Short name T148
Test name
Test status
Simulation time 11848518520 ps
CPU time 75.79 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:53:22 PM PDT 24
Peak memory 241560 kb
Host smart-eca19c36-dcfe-4425-aa8c-1ffe3120c12e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820109560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.820109560
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2292823106
Short name T953
Test name
Test status
Simulation time 5247421689 ps
CPU time 26.7 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:40 PM PDT 24
Peak memory 216772 kb
Host smart-180cf67f-c642-42c6-be91-8befd591b3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292823106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2292823106
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2914578475
Short name T522
Test name
Test status
Simulation time 364445126 ps
CPU time 3.13 seconds
Started Jul 20 06:52:08 PM PDT 24
Finished Jul 20 06:52:12 PM PDT 24
Peak memory 216696 kb
Host smart-f3ed7d02-a1f9-49f4-acb2-5a8d5a6cee69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914578475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2914578475
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2809717500
Short name T1005
Test name
Test status
Simulation time 119859024 ps
CPU time 1.4 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:52:08 PM PDT 24
Peak memory 216700 kb
Host smart-905d6edc-759e-43a0-89ea-92d89d67077b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809717500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2809717500
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1643674339
Short name T491
Test name
Test status
Simulation time 118864079 ps
CPU time 0.83 seconds
Started Jul 20 06:52:02 PM PDT 24
Finished Jul 20 06:52:04 PM PDT 24
Peak memory 206440 kb
Host smart-0e7844d0-6bfc-4a37-ac18-49cd4cb068de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643674339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1643674339
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2468883108
Short name T287
Test name
Test status
Simulation time 3139694682 ps
CPU time 12.64 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 232632 kb
Host smart-77c9e846-850d-420f-9a41-7cee5816c081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468883108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2468883108
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.403936982
Short name T453
Test name
Test status
Simulation time 67009919 ps
CPU time 0.77 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:29 PM PDT 24
Peak memory 205900 kb
Host smart-9cd5b3ee-ef8c-4122-90f3-faab3b2e42f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403936982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.403936982
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1830624600
Short name T482
Test name
Test status
Simulation time 564508471 ps
CPU time 8.08 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:37 PM PDT 24
Peak memory 224820 kb
Host smart-95eb28b9-7cbd-49d3-98ed-a0851647486d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830624600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1830624600
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2875226435
Short name T817
Test name
Test status
Simulation time 36010988 ps
CPU time 0.78 seconds
Started Jul 20 06:54:29 PM PDT 24
Finished Jul 20 06:54:31 PM PDT 24
Peak memory 206024 kb
Host smart-9037a9e4-e56a-432d-8466-eeb2c0355298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875226435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2875226435
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.4254859076
Short name T184
Test name
Test status
Simulation time 49983750385 ps
CPU time 98.31 seconds
Started Jul 20 06:54:30 PM PDT 24
Finished Jul 20 06:56:09 PM PDT 24
Peak memory 241376 kb
Host smart-f8d62644-ee63-4f77-adba-be878ac215c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254859076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4254859076
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3094729809
Short name T782
Test name
Test status
Simulation time 13907439580 ps
CPU time 127.46 seconds
Started Jul 20 06:54:29 PM PDT 24
Finished Jul 20 06:56:37 PM PDT 24
Peak memory 255632 kb
Host smart-6eb31c9d-b799-4957-91b5-670ccee6ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094729809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3094729809
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.89422166
Short name T227
Test name
Test status
Simulation time 2285877936 ps
CPU time 50.71 seconds
Started Jul 20 06:54:28 PM PDT 24
Finished Jul 20 06:55:20 PM PDT 24
Peak memory 249832 kb
Host smart-afbe5740-e906-4f71-8835-68b6510dccca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89422166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.89422166
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2177478129
Short name T370
Test name
Test status
Simulation time 228882196 ps
CPU time 4.44 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:33 PM PDT 24
Peak memory 233172 kb
Host smart-68ae41f7-156f-4ec9-b006-6f58a42b86f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177478129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2177478129
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.3181648142
Short name T905
Test name
Test status
Simulation time 38104738190 ps
CPU time 270.73 seconds
Started Jul 20 06:54:30 PM PDT 24
Finished Jul 20 06:59:02 PM PDT 24
Peak memory 255532 kb
Host smart-131dc024-9f94-4c19-bd76-7379ec9c730b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181648142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.3181648142
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.422498575
Short name T255
Test name
Test status
Simulation time 3656615185 ps
CPU time 22.76 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:52 PM PDT 24
Peak memory 233168 kb
Host smart-94eae7ca-2556-46de-b15a-63ec840507c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422498575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.422498575
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2364371606
Short name T467
Test name
Test status
Simulation time 346070969 ps
CPU time 9.07 seconds
Started Jul 20 06:54:28 PM PDT 24
Finished Jul 20 06:54:38 PM PDT 24
Peak memory 241288 kb
Host smart-7ae7707e-ff2f-4a27-b7a6-8a5963b44726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364371606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2364371606
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2857575688
Short name T706
Test name
Test status
Simulation time 34389873014 ps
CPU time 13.7 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:42 PM PDT 24
Peak memory 224984 kb
Host smart-e3585212-914e-4c26-81dd-8253dc640882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857575688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2857575688
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2101708295
Short name T199
Test name
Test status
Simulation time 9384474053 ps
CPU time 15.35 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:44 PM PDT 24
Peak memory 233132 kb
Host smart-10b96de1-7995-48d8-b121-67f5460acb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101708295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2101708295
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4286263840
Short name T863
Test name
Test status
Simulation time 191830319 ps
CPU time 4.89 seconds
Started Jul 20 06:55:05 PM PDT 24
Finished Jul 20 06:55:12 PM PDT 24
Peak memory 223468 kb
Host smart-da08872c-6d1d-4301-8977-ed8190a13487
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4286263840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4286263840
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.1628941985
Short name T772
Test name
Test status
Simulation time 6294680288 ps
CPU time 17.2 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:46 PM PDT 24
Peak memory 216780 kb
Host smart-f61facee-ab3d-4b7f-ba29-1d574d37ba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628941985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.1628941985
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2844652723
Short name T479
Test name
Test status
Simulation time 3135864772 ps
CPU time 4.56 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:33 PM PDT 24
Peak memory 216776 kb
Host smart-e69d1be2-958c-4013-b762-e486b85d53ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844652723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2844652723
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.4166426645
Short name T724
Test name
Test status
Simulation time 363106875 ps
CPU time 1.46 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:30 PM PDT 24
Peak memory 216704 kb
Host smart-78e8cf63-2b15-4d04-88fa-94b492999a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166426645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.4166426645
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1448750106
Short name T536
Test name
Test status
Simulation time 40295280 ps
CPU time 0.8 seconds
Started Jul 20 06:54:29 PM PDT 24
Finished Jul 20 06:54:31 PM PDT 24
Peak memory 206436 kb
Host smart-b6821577-b1e4-4725-85c8-1c441268aa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448750106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1448750106
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.664482257
Short name T386
Test name
Test status
Simulation time 199361681 ps
CPU time 3.13 seconds
Started Jul 20 06:54:26 PM PDT 24
Finished Jul 20 06:54:30 PM PDT 24
Peak memory 233156 kb
Host smart-0c7360b0-5de0-4064-9479-82f560531eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664482257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.664482257
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2718856769
Short name T373
Test name
Test status
Simulation time 15085471 ps
CPU time 0.76 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:54:37 PM PDT 24
Peak memory 205940 kb
Host smart-16934357-ebb5-4f47-bb23-8b8f7499899b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718856769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2718856769
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1142714933
Short name T175
Test name
Test status
Simulation time 1018093040 ps
CPU time 2.35 seconds
Started Jul 20 06:54:33 PM PDT 24
Finished Jul 20 06:54:36 PM PDT 24
Peak memory 224888 kb
Host smart-61292f5f-35b0-4dab-a080-a4e912cad2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142714933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1142714933
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2215486476
Short name T668
Test name
Test status
Simulation time 56899659 ps
CPU time 0.83 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:30 PM PDT 24
Peak memory 207188 kb
Host smart-4ec88d2d-ad72-4e4d-9b9f-0919af435f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215486476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2215486476
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3731711073
Short name T193
Test name
Test status
Simulation time 211112554328 ps
CPU time 250.46 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:58:47 PM PDT 24
Peak memory 250832 kb
Host smart-13b0da74-9365-4b8b-8862-bf676a2bf195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731711073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3731711073
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2914143268
Short name T899
Test name
Test status
Simulation time 17850919084 ps
CPU time 151.18 seconds
Started Jul 20 06:54:40 PM PDT 24
Finished Jul 20 06:57:12 PM PDT 24
Peak memory 249688 kb
Host smart-a05ea1d0-fb31-4cd4-8340-c02cc45a3add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914143268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2914143268
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1570400516
Short name T893
Test name
Test status
Simulation time 28292776814 ps
CPU time 271.54 seconds
Started Jul 20 06:54:37 PM PDT 24
Finished Jul 20 06:59:09 PM PDT 24
Peak memory 254936 kb
Host smart-ec18002d-4fd3-431e-8481-c3aa884d3515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570400516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1570400516
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3559444482
Short name T325
Test name
Test status
Simulation time 15251422214 ps
CPU time 55.67 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:55:30 PM PDT 24
Peak memory 249604 kb
Host smart-96fe74bd-3bba-4cde-a5c3-32d1490fd119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559444482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3559444482
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2882774671
Short name T239
Test name
Test status
Simulation time 15339739035 ps
CPU time 85.94 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:56:02 PM PDT 24
Peak memory 257716 kb
Host smart-5e9cd8b9-4104-4566-9458-bd97d5f8e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882774671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2882774671
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3794179877
Short name T219
Test name
Test status
Simulation time 1189972369 ps
CPU time 4.02 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:40 PM PDT 24
Peak memory 224908 kb
Host smart-6e05d1a7-ecce-471f-bbc2-4af01793a84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794179877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3794179877
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.752940990
Short name T909
Test name
Test status
Simulation time 3701887711 ps
CPU time 16.84 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:51 PM PDT 24
Peak memory 233124 kb
Host smart-45e3e69c-bf32-49d8-aac4-cb5d570fa58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752940990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.752940990
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2538463727
Short name T888
Test name
Test status
Simulation time 1162823532 ps
CPU time 5.94 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:54:42 PM PDT 24
Peak memory 224932 kb
Host smart-54dd1ff3-634d-44a3-bcfb-0dc19f2d017d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538463727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2538463727
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.186543842
Short name T395
Test name
Test status
Simulation time 1388009451 ps
CPU time 7.14 seconds
Started Jul 20 06:54:40 PM PDT 24
Finished Jul 20 06:54:47 PM PDT 24
Peak memory 241188 kb
Host smart-fe1c3117-b03d-4a20-943d-f1f6e98035f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186543842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.186543842
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3384926521
Short name T36
Test name
Test status
Simulation time 342499672 ps
CPU time 3.69 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:39 PM PDT 24
Peak memory 220852 kb
Host smart-1d7a5659-70b8-4e38-bb3d-e0a1e18dcae7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3384926521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3384926521
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.2179748901
Short name T335
Test name
Test status
Simulation time 86957522697 ps
CPU time 230.85 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:58:25 PM PDT 24
Peak memory 254904 kb
Host smart-32705447-a5ec-4d8d-a401-be340cf63aec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179748901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.2179748901
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3349389148
Short name T331
Test name
Test status
Simulation time 975056044 ps
CPU time 7.64 seconds
Started Jul 20 06:54:27 PM PDT 24
Finished Jul 20 06:54:37 PM PDT 24
Peak memory 216632 kb
Host smart-3ce99297-0012-4cf0-b480-0d80e4dc8c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349389148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3349389148
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1955568719
Short name T832
Test name
Test status
Simulation time 1747241340 ps
CPU time 6.97 seconds
Started Jul 20 06:54:30 PM PDT 24
Finished Jul 20 06:54:37 PM PDT 24
Peak memory 216696 kb
Host smart-45e63515-f5b1-4ee7-8fea-666df55a225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955568719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1955568719
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.454402604
Short name T731
Test name
Test status
Simulation time 40951237 ps
CPU time 1.17 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:54:38 PM PDT 24
Peak memory 207712 kb
Host smart-52ca4c23-a9e2-4984-af4b-3eb92ee500e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454402604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.454402604
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4206386181
Short name T128
Test name
Test status
Simulation time 232801874 ps
CPU time 0.9 seconds
Started Jul 20 06:54:30 PM PDT 24
Finished Jul 20 06:54:32 PM PDT 24
Peak memory 206440 kb
Host smart-6c7ff6a5-339f-485b-bf37-67caad183092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206386181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4206386181
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.602952137
Short name T589
Test name
Test status
Simulation time 4495756562 ps
CPU time 9.58 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:45 PM PDT 24
Peak memory 233156 kb
Host smart-fc6e077f-18bd-4586-969d-09897a4e9681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602952137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.602952137
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.4021958901
Short name T920
Test name
Test status
Simulation time 12851711 ps
CPU time 0.72 seconds
Started Jul 20 06:54:33 PM PDT 24
Finished Jul 20 06:54:35 PM PDT 24
Peak memory 206264 kb
Host smart-3555dfc0-70ae-42f3-844a-50c486dbc0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021958901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
4021958901
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3938266176
Short name T516
Test name
Test status
Simulation time 285850931 ps
CPU time 5.51 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:54:42 PM PDT 24
Peak memory 224892 kb
Host smart-af170df4-1e82-4a6e-8e72-56feea7ac57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938266176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3938266176
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2395669962
Short name T503
Test name
Test status
Simulation time 16522491 ps
CPU time 0.78 seconds
Started Jul 20 06:54:38 PM PDT 24
Finished Jul 20 06:54:39 PM PDT 24
Peak memory 206056 kb
Host smart-b021bf43-1add-496f-8c92-6701eea21b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395669962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2395669962
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2199174987
Short name T298
Test name
Test status
Simulation time 3974789635 ps
CPU time 85.82 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:56:03 PM PDT 24
Peak memory 264792 kb
Host smart-127987a3-5bf0-4a42-9ac0-3ebeeb04fb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199174987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2199174987
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1062525620
Short name T590
Test name
Test status
Simulation time 89261785023 ps
CPU time 108.27 seconds
Started Jul 20 06:54:37 PM PDT 24
Finished Jul 20 06:56:26 PM PDT 24
Peak memory 239496 kb
Host smart-dcc66ee8-90f1-445a-b267-8e7f3acd4c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062525620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1062525620
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3421056361
Short name T653
Test name
Test status
Simulation time 5527205396 ps
CPU time 62.35 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:55:38 PM PDT 24
Peak memory 248828 kb
Host smart-719299f7-67e4-4764-8ae4-e32370a387d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421056361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3421056361
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3733957089
Short name T508
Test name
Test status
Simulation time 2829705976 ps
CPU time 7.18 seconds
Started Jul 20 06:54:38 PM PDT 24
Finished Jul 20 06:54:46 PM PDT 24
Peak memory 225012 kb
Host smart-6d2a487e-08e7-4c78-85f4-65623bfb79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733957089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3733957089
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3442389344
Short name T312
Test name
Test status
Simulation time 3229076645 ps
CPU time 78.01 seconds
Started Jul 20 06:54:36 PM PDT 24
Finished Jul 20 06:55:55 PM PDT 24
Peak memory 255036 kb
Host smart-3df4d6b6-8b1c-4fe0-b3a2-625ff33eb715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442389344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3442389344
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.604607096
Short name T89
Test name
Test status
Simulation time 2084705629 ps
CPU time 10.21 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:46 PM PDT 24
Peak memory 233160 kb
Host smart-51292fa4-87c4-4608-82f6-8ecb2bd41df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604607096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.604607096
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3304870701
Short name T252
Test name
Test status
Simulation time 6617356231 ps
CPU time 57.05 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:55:33 PM PDT 24
Peak memory 240580 kb
Host smart-94f7a56a-c26d-4a99-80a1-486d8dafcece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304870701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3304870701
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.264737417
Short name T230
Test name
Test status
Simulation time 51304008330 ps
CPU time 23.47 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:59 PM PDT 24
Peak memory 241032 kb
Host smart-04123e3a-f134-4fbf-9b82-4df28de07c5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264737417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.264737417
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1528769179
Short name T229
Test name
Test status
Simulation time 6707074117 ps
CPU time 6.97 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:54:43 PM PDT 24
Peak memory 233148 kb
Host smart-6a4b7008-d61f-4e06-ae12-b5da8fc67378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528769179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1528769179
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3873970074
Short name T936
Test name
Test status
Simulation time 3106912800 ps
CPU time 13.89 seconds
Started Jul 20 06:54:40 PM PDT 24
Finished Jul 20 06:54:54 PM PDT 24
Peak memory 220784 kb
Host smart-bbe25f96-3be4-4acc-b4b1-166f58366864
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3873970074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3873970074
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2977157618
Short name T133
Test name
Test status
Simulation time 89809628515 ps
CPU time 793.68 seconds
Started Jul 20 06:54:39 PM PDT 24
Finished Jul 20 07:07:53 PM PDT 24
Peak memory 265264 kb
Host smart-d6427bfa-777f-403d-b640-1e52346770bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977157618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2977157618
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2319269198
Short name T779
Test name
Test status
Simulation time 63739172708 ps
CPU time 26.52 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:55:01 PM PDT 24
Peak memory 216900 kb
Host smart-3cd70c1d-fa8e-40b2-91cc-70af671d2492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319269198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2319269198
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3118452072
Short name T382
Test name
Test status
Simulation time 574756062 ps
CPU time 5.07 seconds
Started Jul 20 06:54:36 PM PDT 24
Finished Jul 20 06:54:42 PM PDT 24
Peak memory 216664 kb
Host smart-7eaa64ce-5172-4beb-8f40-6a14a2d28cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118452072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3118452072
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4028745992
Short name T652
Test name
Test status
Simulation time 14211311 ps
CPU time 0.77 seconds
Started Jul 20 06:54:34 PM PDT 24
Finished Jul 20 06:54:37 PM PDT 24
Peak memory 206448 kb
Host smart-e4a749c8-6003-49c1-8863-7a7c7a71962c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028745992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4028745992
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2266812672
Short name T631
Test name
Test status
Simulation time 483544608 ps
CPU time 1.08 seconds
Started Jul 20 06:54:35 PM PDT 24
Finished Jul 20 06:54:38 PM PDT 24
Peak memory 206684 kb
Host smart-55a0887a-1f3d-41e7-b40f-6eef0858ffa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266812672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2266812672
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2259600237
Short name T766
Test name
Test status
Simulation time 912219162 ps
CPU time 8.19 seconds
Started Jul 20 06:54:36 PM PDT 24
Finished Jul 20 06:54:46 PM PDT 24
Peak memory 224852 kb
Host smart-72adf447-d8e8-41ec-905b-4ee20d7bc259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259600237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2259600237
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.548073472
Short name T501
Test name
Test status
Simulation time 14974695 ps
CPU time 0.76 seconds
Started Jul 20 06:54:46 PM PDT 24
Finished Jul 20 06:54:48 PM PDT 24
Peak memory 205284 kb
Host smart-f4404ab3-51ee-4c66-b62e-23fbe08cb2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548073472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.548073472
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.517752175
Short name T403
Test name
Test status
Simulation time 476213364 ps
CPU time 2.85 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:48 PM PDT 24
Peak memory 224940 kb
Host smart-bcf6dc49-0ee4-45e7-88e7-95afd21020d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517752175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.517752175
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.505038145
Short name T517
Test name
Test status
Simulation time 90770909 ps
CPU time 0.8 seconds
Started Jul 20 06:54:45 PM PDT 24
Finished Jul 20 06:54:47 PM PDT 24
Peak memory 206064 kb
Host smart-e909286d-ebdc-4d20-98fe-8914e27de66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505038145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.505038145
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1472402310
Short name T823
Test name
Test status
Simulation time 43568409567 ps
CPU time 21.86 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:55:15 PM PDT 24
Peak memory 238000 kb
Host smart-3edc1e07-fe85-45e8-986e-bb02e6e8b118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472402310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1472402310
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.504542609
Short name T962
Test name
Test status
Simulation time 615364395 ps
CPU time 7.96 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:53 PM PDT 24
Peak memory 219960 kb
Host smart-60f9ac56-9e2a-4846-94ee-2af922f9b515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504542609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.504542609
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2823090918
Short name T737
Test name
Test status
Simulation time 1183963896 ps
CPU time 31.56 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:55:16 PM PDT 24
Peak memory 249748 kb
Host smart-5b6e7c45-29a4-4698-b253-0722428fe6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823090918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2823090918
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1293920693
Short name T494
Test name
Test status
Simulation time 159823849 ps
CPU time 4.98 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:50 PM PDT 24
Peak memory 225092 kb
Host smart-af7e4eca-bce5-4f4c-b9d4-09616f13b307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293920693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1293920693
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4015745773
Short name T425
Test name
Test status
Simulation time 2775676419 ps
CPU time 11.02 seconds
Started Jul 20 06:54:48 PM PDT 24
Finished Jul 20 06:55:00 PM PDT 24
Peak memory 224956 kb
Host smart-8ec909a2-78ae-48c5-aef4-8ff256229961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015745773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4015745773
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1774173658
Short name T677
Test name
Test status
Simulation time 2567290371 ps
CPU time 7.91 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:54 PM PDT 24
Peak memory 224960 kb
Host smart-69be1379-21e4-4daa-b0df-892cd4def387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774173658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1774173658
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1301094848
Short name T209
Test name
Test status
Simulation time 111198819790 ps
CPU time 37.17 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:55:23 PM PDT 24
Peak memory 240952 kb
Host smart-7675d09b-fe5b-4fc1-a0a2-1db2433799d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301094848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1301094848
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2379865577
Short name T280
Test name
Test status
Simulation time 101030370 ps
CPU time 2.2 seconds
Started Jul 20 06:54:50 PM PDT 24
Finished Jul 20 06:54:53 PM PDT 24
Peak memory 224924 kb
Host smart-4083a8f2-8a79-4e3e-9cb9-ce611d476c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379865577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2379865577
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1353942555
Short name T950
Test name
Test status
Simulation time 85983756 ps
CPU time 4.14 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:54:58 PM PDT 24
Peak memory 223220 kb
Host smart-ca2b3d74-172f-4aa6-834c-bb981d90107c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1353942555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1353942555
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.2586890751
Short name T520
Test name
Test status
Simulation time 25060155439 ps
CPU time 272.59 seconds
Started Jul 20 06:54:43 PM PDT 24
Finished Jul 20 06:59:16 PM PDT 24
Peak memory 266052 kb
Host smart-d1f4ca11-52b7-4f4b-b845-3a245be82536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586890751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.2586890751
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3519014702
Short name T672
Test name
Test status
Simulation time 2710025411 ps
CPU time 25.89 seconds
Started Jul 20 06:54:48 PM PDT 24
Finished Jul 20 06:55:15 PM PDT 24
Peak memory 216764 kb
Host smart-960855b5-8bd3-40ef-a757-c8b024cc5e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519014702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3519014702
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2736283582
Short name T651
Test name
Test status
Simulation time 4666156542 ps
CPU time 16.84 seconds
Started Jul 20 06:54:46 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 216792 kb
Host smart-a11bac7f-71fb-4d06-ac6a-81d8b2413292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736283582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2736283582
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1584645061
Short name T527
Test name
Test status
Simulation time 118776471 ps
CPU time 3.2 seconds
Started Jul 20 06:54:43 PM PDT 24
Finished Jul 20 06:54:47 PM PDT 24
Peak memory 216732 kb
Host smart-8c46c645-2785-42b4-bab6-29cc9a7d8e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584645061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1584645061
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3471860200
Short name T639
Test name
Test status
Simulation time 116617876 ps
CPU time 0.89 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:54:54 PM PDT 24
Peak memory 206440 kb
Host smart-55dbec16-7b55-429a-899e-533c0c7cefc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471860200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3471860200
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3641732757
Short name T466
Test name
Test status
Simulation time 188538148 ps
CPU time 3.39 seconds
Started Jul 20 06:54:46 PM PDT 24
Finished Jul 20 06:54:51 PM PDT 24
Peak memory 233164 kb
Host smart-a8aac62c-9bc7-450b-b8bb-5442c85853c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641732757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3641732757
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.250901818
Short name T454
Test name
Test status
Simulation time 31655877 ps
CPU time 0.68 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:05 PM PDT 24
Peak memory 205932 kb
Host smart-6a03b6e1-a7eb-413b-9658-cafd41711b13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250901818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.250901818
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1096596454
Short name T417
Test name
Test status
Simulation time 492776497 ps
CPU time 3.67 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:49 PM PDT 24
Peak memory 233164 kb
Host smart-0f991fb8-8e5c-4a79-8003-5908e513c98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096596454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1096596454
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3161078258
Short name T883
Test name
Test status
Simulation time 22782666 ps
CPU time 0.77 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:46 PM PDT 24
Peak memory 206036 kb
Host smart-748f5423-adf0-48b5-bca7-b14b424ea4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161078258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3161078258
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.328682425
Short name T848
Test name
Test status
Simulation time 4222768794 ps
CPU time 22.79 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:16 PM PDT 24
Peak memory 249616 kb
Host smart-9aad824e-fad6-40f5-93ea-5044a17f79d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328682425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.328682425
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2722560412
Short name T702
Test name
Test status
Simulation time 4409789023 ps
CPU time 10.2 seconds
Started Jul 20 06:54:53 PM PDT 24
Finished Jul 20 06:55:05 PM PDT 24
Peak memory 224988 kb
Host smart-c0630a18-0d0c-4d9d-b96d-13792dc371d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722560412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2722560412
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2009454814
Short name T326
Test name
Test status
Simulation time 573410894 ps
CPU time 8.13 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:03 PM PDT 24
Peak memory 233032 kb
Host smart-6ea8d343-e1be-4fa9-a6d7-6cf6af244827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009454814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2009454814
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1956045243
Short name T588
Test name
Test status
Simulation time 306171097 ps
CPU time 6.82 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:01 PM PDT 24
Peak memory 224944 kb
Host smart-e876744d-b39a-40aa-ac5d-52a44fdb313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956045243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1956045243
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1063197468
Short name T489
Test name
Test status
Simulation time 3796067528 ps
CPU time 32.36 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:55:17 PM PDT 24
Peak memory 233240 kb
Host smart-377d462c-4b03-42c7-9553-87f2a2d99922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063197468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1063197468
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2924045176
Short name T440
Test name
Test status
Simulation time 3315376996 ps
CPU time 16.82 seconds
Started Jul 20 06:54:46 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 241000 kb
Host smart-778c42e8-c287-4240-8481-c7fe61fb026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924045176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2924045176
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2503380710
Short name T277
Test name
Test status
Simulation time 718704457 ps
CPU time 9.62 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:55:02 PM PDT 24
Peak memory 235612 kb
Host smart-f4451981-e394-4c2c-84ce-a73a8ca3e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503380710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2503380710
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2441542580
Short name T735
Test name
Test status
Simulation time 13519445914 ps
CPU time 18.48 seconds
Started Jul 20 06:54:46 PM PDT 24
Finished Jul 20 06:55:06 PM PDT 24
Peak memory 241332 kb
Host smart-690df508-f798-4be3-9b3e-c59ea9290555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441542580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2441542580
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2765841109
Short name T979
Test name
Test status
Simulation time 279426758 ps
CPU time 4.69 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 220868 kb
Host smart-9f5f0e03-227f-4630-8303-bea7e24ad9b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2765841109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2765841109
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2990729812
Short name T332
Test name
Test status
Simulation time 3200861276 ps
CPU time 19.22 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:13 PM PDT 24
Peak memory 216940 kb
Host smart-77374ec7-9a61-4d2b-b0a1-32aa74bbbc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990729812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2990729812
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.3436885109
Short name T813
Test name
Test status
Simulation time 5453540477 ps
CPU time 13.36 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:07 PM PDT 24
Peak memory 216780 kb
Host smart-a4991ae9-1d37-498c-917b-9e96b47ababf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436885109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3436885109
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.518695311
Short name T729
Test name
Test status
Simulation time 11896294 ps
CPU time 0.71 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:46 PM PDT 24
Peak memory 206072 kb
Host smart-cba6e296-8f97-458f-b9f2-4cdc23abceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518695311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.518695311
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1077335105
Short name T592
Test name
Test status
Simulation time 53337097 ps
CPU time 0.74 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:45 PM PDT 24
Peak memory 206444 kb
Host smart-e15eabcb-5b74-4a5e-a70c-f53992c96a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077335105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1077335105
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.946629567
Short name T915
Test name
Test status
Simulation time 9149487468 ps
CPU time 8.48 seconds
Started Jul 20 06:54:44 PM PDT 24
Finished Jul 20 06:54:53 PM PDT 24
Peak memory 225012 kb
Host smart-14ec0ea7-7023-4a55-94ce-e52f41b180a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946629567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.946629567
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3652180179
Short name T627
Test name
Test status
Simulation time 12461080 ps
CPU time 0.71 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:06 PM PDT 24
Peak memory 205960 kb
Host smart-4285ee80-218f-48ae-8b72-6e1fe9aa47ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652180179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3652180179
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.4140567520
Short name T727
Test name
Test status
Simulation time 167217263 ps
CPU time 4.34 seconds
Started Jul 20 06:54:53 PM PDT 24
Finished Jul 20 06:54:59 PM PDT 24
Peak memory 224900 kb
Host smart-34ebbe46-91ec-48df-8ddd-75fd4f47eefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140567520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.4140567520
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.329761141
Short name T867
Test name
Test status
Simulation time 29966227 ps
CPU time 0.8 seconds
Started Jul 20 06:54:53 PM PDT 24
Finished Jul 20 06:54:56 PM PDT 24
Peak memory 207384 kb
Host smart-f8eb4e95-c921-4cd6-93e6-4c05cc4ccf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329761141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.329761141
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2803161619
Short name T399
Test name
Test status
Simulation time 4487451501 ps
CPU time 25.71 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:55:17 PM PDT 24
Peak memory 250216 kb
Host smart-c6bc319b-72a9-470c-b4bb-b89eacfeda45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803161619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2803161619
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1444777052
Short name T416
Test name
Test status
Simulation time 5271449581 ps
CPU time 27.94 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:21 PM PDT 24
Peak memory 218200 kb
Host smart-1233e57b-249d-457d-b653-62e4ec96cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444777052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1444777052
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.329924205
Short name T210
Test name
Test status
Simulation time 23136878003 ps
CPU time 148.19 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:57:33 PM PDT 24
Peak memory 252716 kb
Host smart-df6d69a8-80cb-42f1-b2c1-d724e0b5965e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329924205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.329924205
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3351323398
Short name T528
Test name
Test status
Simulation time 2334983239 ps
CPU time 3.45 seconds
Started Jul 20 06:54:54 PM PDT 24
Finished Jul 20 06:54:58 PM PDT 24
Peak memory 225004 kb
Host smart-997a6d4a-e276-48e4-87f3-901fd2b0375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351323398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3351323398
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3891393602
Short name T196
Test name
Test status
Simulation time 2745673575 ps
CPU time 6.22 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:54:59 PM PDT 24
Peak memory 233156 kb
Host smart-10e3387e-7467-4cc8-b3c8-96f93ee53f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891393602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3891393602
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.115347919
Short name T250
Test name
Test status
Simulation time 3291676215 ps
CPU time 19.39 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:25 PM PDT 24
Peak memory 224976 kb
Host smart-9c428bf7-cafe-46e5-a7e8-7208778a807e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115347919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.115347919
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3423202626
Short name T305
Test name
Test status
Simulation time 351828402 ps
CPU time 4.89 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 224916 kb
Host smart-99a653ad-deda-4573-b103-c31b9dbb657e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423202626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3423202626
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1336637707
Short name T798
Test name
Test status
Simulation time 144297411 ps
CPU time 3.54 seconds
Started Jul 20 06:54:54 PM PDT 24
Finished Jul 20 06:54:59 PM PDT 24
Peak memory 233064 kb
Host smart-8d853152-c9b3-41f4-bd6b-3b30f83049eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336637707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1336637707
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2781268611
Short name T574
Test name
Test status
Simulation time 1780104126 ps
CPU time 8.61 seconds
Started Jul 20 06:54:54 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 223480 kb
Host smart-dcf00bbd-ef42-4636-8cc9-cd1ded592b62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2781268611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2781268611
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3263164264
Short name T187
Test name
Test status
Simulation time 2715528011 ps
CPU time 66 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:56:11 PM PDT 24
Peak memory 249688 kb
Host smart-3afaf760-52c7-4360-80b9-c580bce6d53d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263164264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3263164264
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.778968915
Short name T608
Test name
Test status
Simulation time 1168071935 ps
CPU time 9.96 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 216648 kb
Host smart-b7b0456f-ca3f-474b-8205-bfe6dc103dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778968915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.778968915
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2295928930
Short name T347
Test name
Test status
Simulation time 1998876023 ps
CPU time 5.74 seconds
Started Jul 20 06:54:51 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 216708 kb
Host smart-00f9232d-ac4b-4a13-a48e-8985d17da4d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295928930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2295928930
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3300349721
Short name T680
Test name
Test status
Simulation time 65675118 ps
CPU time 1.86 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:54:55 PM PDT 24
Peak memory 216700 kb
Host smart-3fedf794-9d6f-4c02-995e-e783f69c9ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300349721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3300349721
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.95891975
Short name T884
Test name
Test status
Simulation time 44192684 ps
CPU time 0.73 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:54:54 PM PDT 24
Peak memory 206412 kb
Host smart-62da7865-84c9-48f9-833f-0320cfd031ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95891975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.95891975
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1398162882
Short name T860
Test name
Test status
Simulation time 171566733 ps
CPU time 2.25 seconds
Started Jul 20 06:54:55 PM PDT 24
Finished Jul 20 06:54:58 PM PDT 24
Peak memory 224896 kb
Host smart-bf420640-827f-4f7a-b607-4b728e7e4237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398162882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1398162882
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2615805119
Short name T444
Test name
Test status
Simulation time 25161771 ps
CPU time 0.74 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:03 PM PDT 24
Peak memory 205924 kb
Host smart-3ec3972e-9829-427c-9342-1023b81b7d04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615805119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2615805119
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.506691248
Short name T176
Test name
Test status
Simulation time 1122314349 ps
CPU time 3.43 seconds
Started Jul 20 06:54:53 PM PDT 24
Finished Jul 20 06:54:58 PM PDT 24
Peak memory 224936 kb
Host smart-1c92bdbc-fa19-4473-9c5a-6c0fc444c1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506691248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.506691248
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1831206778
Short name T666
Test name
Test status
Simulation time 37080975 ps
CPU time 0.78 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:54:55 PM PDT 24
Peak memory 206316 kb
Host smart-e7fc46c1-d21e-4d74-acc0-673641dfce9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831206778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1831206778
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1233151914
Short name T224
Test name
Test status
Simulation time 197085453083 ps
CPU time 332.4 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 07:00:35 PM PDT 24
Peak memory 256216 kb
Host smart-cd2b195b-d1fb-4650-874d-2c572ebf570e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233151914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1233151914
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2569748933
Short name T262
Test name
Test status
Simulation time 3137989185 ps
CPU time 32.99 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:35 PM PDT 24
Peak memory 257280 kb
Host smart-ea17734f-d445-49f8-9037-7665732124ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569748933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2569748933
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2466288364
Short name T33
Test name
Test status
Simulation time 8072085085 ps
CPU time 57.91 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:56:04 PM PDT 24
Peak memory 249664 kb
Host smart-1b47d84c-a8b6-42a1-a99e-272d2d919aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466288364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2466288364
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3203106919
Short name T926
Test name
Test status
Simulation time 3412949784 ps
CPU time 16.71 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:11 PM PDT 24
Peak memory 225012 kb
Host smart-c28e8d50-a53b-4a83-b410-94a0e504a6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203106919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3203106919
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1495101995
Short name T741
Test name
Test status
Simulation time 19533116146 ps
CPU time 139.83 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:57:22 PM PDT 24
Peak memory 249596 kb
Host smart-93f95b41-8764-453e-94c6-d6449c78cf16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495101995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1495101995
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.565199175
Short name T85
Test name
Test status
Simulation time 2281320211 ps
CPU time 4.65 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:54:58 PM PDT 24
Peak memory 233152 kb
Host smart-d567d19e-3936-4865-92df-41350ac41fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565199175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.565199175
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.394574439
Short name T976
Test name
Test status
Simulation time 23343069365 ps
CPU time 81.48 seconds
Started Jul 20 06:54:55 PM PDT 24
Finished Jul 20 06:56:17 PM PDT 24
Peak memory 240020 kb
Host smart-6b046d50-9db1-468c-9226-6f25569b0926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394574439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.394574439
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3312982262
Short name T7
Test name
Test status
Simulation time 18064103919 ps
CPU time 10.83 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:15 PM PDT 24
Peak memory 240420 kb
Host smart-37f635a6-7b4d-4065-8e2c-b3971b36ecc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312982262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3312982262
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4188690442
Short name T1006
Test name
Test status
Simulation time 1320769880 ps
CPU time 6.67 seconds
Started Jul 20 06:54:54 PM PDT 24
Finished Jul 20 06:55:02 PM PDT 24
Peak memory 233152 kb
Host smart-fece2fde-87ee-4608-8a1b-0b5625a48813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188690442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4188690442
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2879741410
Short name T474
Test name
Test status
Simulation time 110462118 ps
CPU time 4.45 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:06 PM PDT 24
Peak memory 223076 kb
Host smart-5acc837c-fcd4-40a3-a52f-9c29ed47d309
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2879741410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2879741410
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2446329431
Short name T59
Test name
Test status
Simulation time 43376596991 ps
CPU time 71.83 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:56:15 PM PDT 24
Peak memory 257864 kb
Host smart-6055e382-e63f-4855-b21e-ef7228904c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446329431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2446329431
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.730958752
Short name T964
Test name
Test status
Simulation time 18204637469 ps
CPU time 28.6 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:55:23 PM PDT 24
Peak memory 216744 kb
Host smart-1a000b33-0833-4e15-813f-eaa1ee6bf6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730958752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.730958752
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1626214232
Short name T375
Test name
Test status
Simulation time 464704120 ps
CPU time 2.47 seconds
Started Jul 20 06:54:52 PM PDT 24
Finished Jul 20 06:54:57 PM PDT 24
Peak memory 216524 kb
Host smart-1317de07-2d17-424e-be2e-8fae79614312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626214232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1626214232
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3942979503
Short name T928
Test name
Test status
Simulation time 11185771 ps
CPU time 0.7 seconds
Started Jul 20 06:54:53 PM PDT 24
Finished Jul 20 06:54:55 PM PDT 24
Peak memory 206120 kb
Host smart-a1014a22-936d-474c-9bd9-937f871f0d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942979503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3942979503
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3241760650
Short name T730
Test name
Test status
Simulation time 227245890 ps
CPU time 0.94 seconds
Started Jul 20 06:54:53 PM PDT 24
Finished Jul 20 06:54:56 PM PDT 24
Peak memory 206584 kb
Host smart-3d2ff92d-16a4-49aa-b9c7-273c7b8edb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241760650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3241760650
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.388891341
Short name T849
Test name
Test status
Simulation time 530294552 ps
CPU time 2.8 seconds
Started Jul 20 06:54:54 PM PDT 24
Finished Jul 20 06:54:58 PM PDT 24
Peak memory 233084 kb
Host smart-080cb2a2-ffd6-48d3-8f85-01ad98667d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388891341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.388891341
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3641059267
Short name T405
Test name
Test status
Simulation time 81566955 ps
CPU time 0.74 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:05 PM PDT 24
Peak memory 205344 kb
Host smart-94455a33-9fb8-4b7f-8746-7939c0cb15d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641059267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3641059267
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3433817463
Short name T242
Test name
Test status
Simulation time 79609225 ps
CPU time 2.8 seconds
Started Jul 20 06:55:06 PM PDT 24
Finished Jul 20 06:55:10 PM PDT 24
Peak memory 233136 kb
Host smart-a88d4e88-a69e-4d30-ad4b-902770c1e5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433817463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3433817463
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1302532348
Short name T703
Test name
Test status
Simulation time 45267145 ps
CPU time 0.82 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 207060 kb
Host smart-54023d0d-611c-4d35-9070-53633cecf72d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302532348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1302532348
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1760487235
Short name T306
Test name
Test status
Simulation time 3770190020 ps
CPU time 47.26 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:53 PM PDT 24
Peak memory 257776 kb
Host smart-ae8c65f9-5a6d-4994-a022-7839dfb0a792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760487235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1760487235
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3118332849
Short name T134
Test name
Test status
Simulation time 465100931463 ps
CPU time 636.68 seconds
Started Jul 20 06:55:06 PM PDT 24
Finished Jul 20 07:05:44 PM PDT 24
Peak memory 262884 kb
Host smart-3b92327e-ae66-4890-8acd-3fb1957f4610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118332849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3118332849
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3400641088
Short name T894
Test name
Test status
Simulation time 1039649032 ps
CPU time 11.77 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:17 PM PDT 24
Peak memory 224988 kb
Host smart-91c13d1c-2774-40d4-acc7-2d04153ed210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400641088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3400641088
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3484113678
Short name T178
Test name
Test status
Simulation time 143957154 ps
CPU time 3.74 seconds
Started Jul 20 06:55:07 PM PDT 24
Finished Jul 20 06:55:12 PM PDT 24
Peak memory 224944 kb
Host smart-3f3c154a-fff2-4a31-9188-c300307ee3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484113678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3484113678
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.1255184688
Short name T695
Test name
Test status
Simulation time 7263169136 ps
CPU time 32.19 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:34 PM PDT 24
Peak memory 239144 kb
Host smart-fcdb98b5-b92b-48ab-ba3f-cf48f29a9758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255184688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.1255184688
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1569103945
Short name T714
Test name
Test status
Simulation time 120699037 ps
CPU time 3.44 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:08 PM PDT 24
Peak memory 233096 kb
Host smart-de3ef960-4e6b-4e91-a918-dcccb8c92f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569103945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1569103945
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2210265757
Short name T502
Test name
Test status
Simulation time 161843181327 ps
CPU time 83.7 seconds
Started Jul 20 06:54:59 PM PDT 24
Finished Jul 20 06:56:23 PM PDT 24
Peak memory 233144 kb
Host smart-53335dcb-0023-4ca8-9611-1275d1791f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210265757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2210265757
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2124567778
Short name T307
Test name
Test status
Simulation time 9135312081 ps
CPU time 12.58 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:17 PM PDT 24
Peak memory 224928 kb
Host smart-598a6131-07a9-4759-b6d9-20a76ac11d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124567778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2124567778
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2145581471
Short name T587
Test name
Test status
Simulation time 19843518563 ps
CPU time 16.47 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:22 PM PDT 24
Peak memory 233136 kb
Host smart-3545fc74-1bff-4698-8054-5495326768be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145581471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2145581471
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1309607730
Short name T939
Test name
Test status
Simulation time 858978437 ps
CPU time 7.42 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:13 PM PDT 24
Peak memory 222000 kb
Host smart-988ba24c-d48c-45a7-9b51-65f8d8b47ecf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1309607730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1309607730
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2922644490
Short name T908
Test name
Test status
Simulation time 18639503447 ps
CPU time 188.62 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:58:12 PM PDT 24
Peak memory 255884 kb
Host smart-c5742bfd-04ff-4682-9325-f5cc26ba1217
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922644490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2922644490
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1400954011
Short name T716
Test name
Test status
Simulation time 1738172818 ps
CPU time 3.59 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:09 PM PDT 24
Peak memory 216648 kb
Host smart-9adfad9c-1faf-47e2-a242-fb19d58846e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400954011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1400954011
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3880574393
Short name T445
Test name
Test status
Simulation time 1830905594 ps
CPU time 1.71 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:07 PM PDT 24
Peak memory 207516 kb
Host smart-2ca3b7da-0746-4bcc-965c-7afef62f4d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880574393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3880574393
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3201823921
Short name T662
Test name
Test status
Simulation time 93710507 ps
CPU time 1.93 seconds
Started Jul 20 06:55:06 PM PDT 24
Finished Jul 20 06:55:09 PM PDT 24
Peak memory 216696 kb
Host smart-ad7a5d9f-83b3-4fad-b6e9-a2641e5f8ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201823921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3201823921
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2361751200
Short name T469
Test name
Test status
Simulation time 56753786 ps
CPU time 0.75 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:03 PM PDT 24
Peak memory 206432 kb
Host smart-9f5f4390-3f1a-4a61-89c3-e74b01e4bdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361751200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2361751200
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.853033087
Short name T217
Test name
Test status
Simulation time 11858282264 ps
CPU time 17.07 seconds
Started Jul 20 06:55:04 PM PDT 24
Finished Jul 20 06:55:23 PM PDT 24
Peak memory 241008 kb
Host smart-397e1730-4302-4412-8f8a-11514ed1fc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853033087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.853033087
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2390600662
Short name T640
Test name
Test status
Simulation time 27872529 ps
CPU time 0.75 seconds
Started Jul 20 06:55:05 PM PDT 24
Finished Jul 20 06:55:08 PM PDT 24
Peak memory 206248 kb
Host smart-5bbf3941-e349-443a-b76d-1c7f45bc70fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390600662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2390600662
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3795051226
Short name T845
Test name
Test status
Simulation time 38612242 ps
CPU time 2.26 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:08 PM PDT 24
Peak memory 224920 kb
Host smart-a9c4151e-e0cd-49ca-bbce-2f3d3d40cd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795051226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3795051226
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3207851040
Short name T129
Test name
Test status
Simulation time 72338660 ps
CPU time 0.81 seconds
Started Jul 20 06:55:05 PM PDT 24
Finished Jul 20 06:55:08 PM PDT 24
Peak memory 207032 kb
Host smart-97e89877-bfd3-4aa8-a2f8-6a3fedb1b1b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207851040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3207851040
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2217535373
Short name T1000
Test name
Test status
Simulation time 1147778045 ps
CPU time 17.58 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:20 PM PDT 24
Peak memory 252540 kb
Host smart-d13872f0-abb4-4f56-8155-fe80d37aca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217535373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2217535373
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.921435360
Short name T987
Test name
Test status
Simulation time 2266012909 ps
CPU time 21.69 seconds
Started Jul 20 06:55:04 PM PDT 24
Finished Jul 20 06:55:28 PM PDT 24
Peak memory 217920 kb
Host smart-ed302ea0-b2ed-435f-bde4-3ff1f8362b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921435360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.921435360
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3393231748
Short name T773
Test name
Test status
Simulation time 13510245721 ps
CPU time 84.38 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:56:30 PM PDT 24
Peak memory 249640 kb
Host smart-c19b7c8c-537a-43bf-89c8-8319d1f284a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393231748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3393231748
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3965719573
Short name T322
Test name
Test status
Simulation time 479221017 ps
CPU time 13.62 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:14 PM PDT 24
Peak memory 249508 kb
Host smart-f453dac1-40e9-41e0-9cc6-9ab83eac7597
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965719573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3965719573
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.676373463
Short name T281
Test name
Test status
Simulation time 290455217 ps
CPU time 4.07 seconds
Started Jul 20 06:55:02 PM PDT 24
Finished Jul 20 06:55:09 PM PDT 24
Peak memory 233072 kb
Host smart-13caab80-dd89-4982-8254-7c3d7894a63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676373463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.676373463
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3255697216
Short name T761
Test name
Test status
Simulation time 376389394 ps
CPU time 3.13 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 224940 kb
Host smart-e7c8633e-946e-4d4a-a436-a0393064f6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255697216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3255697216
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.422140443
Short name T903
Test name
Test status
Simulation time 403132316 ps
CPU time 3.97 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:09 PM PDT 24
Peak memory 224948 kb
Host smart-dcff65f9-78dd-4e38-9015-033f85306371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422140443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.422140443
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1682891613
Short name T246
Test name
Test status
Simulation time 1378277227 ps
CPU time 7.68 seconds
Started Jul 20 06:55:05 PM PDT 24
Finished Jul 20 06:55:14 PM PDT 24
Peak memory 233084 kb
Host smart-b4856e90-55c2-4346-b3a6-7ffca176c2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682891613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1682891613
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1203016671
Short name T13
Test name
Test status
Simulation time 401098730 ps
CPU time 4.91 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:07 PM PDT 24
Peak memory 219332 kb
Host smart-6b13bb29-e1b1-48fa-8e0f-d29b0f41c1e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1203016671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1203016671
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3810384928
Short name T19
Test name
Test status
Simulation time 65949571 ps
CPU time 1.25 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:03 PM PDT 24
Peak memory 207644 kb
Host smart-aa39bc0c-054c-4949-ad6c-790ac0a86ce7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810384928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3810384928
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.402428998
Short name T534
Test name
Test status
Simulation time 14948493762 ps
CPU time 32.74 seconds
Started Jul 20 06:55:01 PM PDT 24
Finished Jul 20 06:55:35 PM PDT 24
Peak memory 216776 kb
Host smart-f4587b37-4436-40b6-bfcb-6a00a540abf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402428998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.402428998
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1459216930
Short name T423
Test name
Test status
Simulation time 727487605 ps
CPU time 2.81 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:09 PM PDT 24
Peak memory 216644 kb
Host smart-b0c6a80d-dd41-4ece-9116-9ece867d0705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459216930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1459216930
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2716616243
Short name T634
Test name
Test status
Simulation time 168322593 ps
CPU time 1.45 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:02 PM PDT 24
Peak memory 208448 kb
Host smart-d5e93585-e9a1-4504-a7ff-bae24d4e5ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716616243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2716616243
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3185069937
Short name T350
Test name
Test status
Simulation time 51328247 ps
CPU time 0.76 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:02 PM PDT 24
Peak memory 206268 kb
Host smart-a947e513-e38b-41fa-8bb6-76fb476de766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185069937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3185069937
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.3739957627
Short name T570
Test name
Test status
Simulation time 109928667 ps
CPU time 2.53 seconds
Started Jul 20 06:55:00 PM PDT 24
Finished Jul 20 06:55:04 PM PDT 24
Peak memory 224600 kb
Host smart-ba82243f-6aca-48ac-a86e-dbb585333821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739957627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3739957627
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2880297907
Short name T565
Test name
Test status
Simulation time 47497784 ps
CPU time 0.73 seconds
Started Jul 20 06:55:10 PM PDT 24
Finished Jul 20 06:55:12 PM PDT 24
Peak memory 205920 kb
Host smart-745dca34-8bae-4991-ba42-a207486db683
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880297907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2880297907
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.2822738073
Short name T1010
Test name
Test status
Simulation time 216466161 ps
CPU time 3.69 seconds
Started Jul 20 06:55:08 PM PDT 24
Finished Jul 20 06:55:12 PM PDT 24
Peak memory 224948 kb
Host smart-8abe1450-1c17-41fc-809e-d75c8ac86343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822738073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2822738073
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1807483901
Short name T694
Test name
Test status
Simulation time 158841189 ps
CPU time 0.76 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:06 PM PDT 24
Peak memory 207080 kb
Host smart-7c1cdc20-30e2-4182-97b0-844fceaa3271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807483901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1807483901
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2969343963
Short name T265
Test name
Test status
Simulation time 8540817913 ps
CPU time 28.78 seconds
Started Jul 20 06:55:09 PM PDT 24
Finished Jul 20 06:55:39 PM PDT 24
Peak memory 235864 kb
Host smart-4dabf415-d40b-4d66-bd12-c8eb63b59af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969343963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2969343963
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2749340963
Short name T637
Test name
Test status
Simulation time 1608849120 ps
CPU time 32.61 seconds
Started Jul 20 06:55:08 PM PDT 24
Finished Jul 20 06:55:42 PM PDT 24
Peak memory 225000 kb
Host smart-7da11cfa-cc81-4519-90ab-50ad62ef21ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749340963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2749340963
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3355619855
Short name T42
Test name
Test status
Simulation time 11473670361 ps
CPU time 59.25 seconds
Started Jul 20 06:55:09 PM PDT 24
Finished Jul 20 06:56:10 PM PDT 24
Peak memory 254552 kb
Host smart-8412300d-e8b7-4bc4-9c72-ad487774fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355619855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3355619855
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2851482750
Short name T320
Test name
Test status
Simulation time 1120088063 ps
CPU time 28.15 seconds
Started Jul 20 06:55:12 PM PDT 24
Finished Jul 20 06:55:41 PM PDT 24
Peak memory 234408 kb
Host smart-ce7db3ae-c5ea-4fb3-b18d-8a5b69f082be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851482750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2851482750
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1669203466
Short name T87
Test name
Test status
Simulation time 1911351929 ps
CPU time 41.12 seconds
Started Jul 20 06:55:12 PM PDT 24
Finished Jul 20 06:55:54 PM PDT 24
Peak memory 241484 kb
Host smart-a0b0e5d0-85ff-45e8-bad3-23a07449d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669203466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1669203466
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3436448724
Short name T124
Test name
Test status
Simulation time 163522188 ps
CPU time 3.7 seconds
Started Jul 20 06:55:08 PM PDT 24
Finished Jul 20 06:55:13 PM PDT 24
Peak memory 233140 kb
Host smart-4e373e40-8889-42b8-bf0f-cd1876dd589d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436448724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3436448724
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2603053956
Short name T251
Test name
Test status
Simulation time 1718117513 ps
CPU time 10.48 seconds
Started Jul 20 06:55:09 PM PDT 24
Finished Jul 20 06:55:21 PM PDT 24
Peak memory 224868 kb
Host smart-a82886e8-e8cb-45ab-9ea7-88a1a3ecadf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603053956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2603053956
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3852004764
Short name T649
Test name
Test status
Simulation time 1111716278 ps
CPU time 4.05 seconds
Started Jul 20 06:55:07 PM PDT 24
Finished Jul 20 06:55:12 PM PDT 24
Peak memory 232996 kb
Host smart-288d0c3d-0f71-4a32-b9f0-a0fa91fad8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852004764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3852004764
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2277761734
Short name T810
Test name
Test status
Simulation time 713598449 ps
CPU time 6.44 seconds
Started Jul 20 06:55:07 PM PDT 24
Finished Jul 20 06:55:15 PM PDT 24
Peak memory 233088 kb
Host smart-fcddc142-832c-4b9d-9ede-261bab2170ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277761734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2277761734
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1956683094
Short name T635
Test name
Test status
Simulation time 15917268696 ps
CPU time 6.6 seconds
Started Jul 20 06:55:07 PM PDT 24
Finished Jul 20 06:55:15 PM PDT 24
Peak memory 219624 kb
Host smart-b06ccfaa-fb6f-4510-bf00-04f4e4ae16d1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1956683094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1956683094
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.3587875793
Short name T984
Test name
Test status
Simulation time 44114989250 ps
CPU time 419.98 seconds
Started Jul 20 06:55:09 PM PDT 24
Finished Jul 20 07:02:10 PM PDT 24
Peak memory 282396 kb
Host smart-a28b39fe-bf76-4804-8654-ac2a9eb0fa2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587875793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.3587875793
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3874760869
Short name T797
Test name
Test status
Simulation time 4750121458 ps
CPU time 14.4 seconds
Started Jul 20 06:55:06 PM PDT 24
Finished Jul 20 06:55:21 PM PDT 24
Peak memory 216708 kb
Host smart-ed067bac-1012-422f-92cf-1bee5be30772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874760869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3874760869
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1338499164
Short name T30
Test name
Test status
Simulation time 15592207877 ps
CPU time 20.69 seconds
Started Jul 20 06:55:03 PM PDT 24
Finished Jul 20 06:55:26 PM PDT 24
Peak memory 216764 kb
Host smart-bc91f8de-b6de-4520-8819-6f3e7bd63f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338499164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1338499164
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2786695956
Short name T468
Test name
Test status
Simulation time 53569021 ps
CPU time 1.42 seconds
Started Jul 20 06:55:08 PM PDT 24
Finished Jul 20 06:55:10 PM PDT 24
Peak memory 216764 kb
Host smart-6730b8e7-2792-4bc4-91d0-6ed3e7f3d002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786695956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2786695956
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1106259967
Short name T698
Test name
Test status
Simulation time 49402258 ps
CPU time 0.87 seconds
Started Jul 20 06:55:08 PM PDT 24
Finished Jul 20 06:55:10 PM PDT 24
Peak memory 206444 kb
Host smart-2e260234-4940-4125-bb4a-e1b74dfbc277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106259967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1106259967
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2907399506
Short name T812
Test name
Test status
Simulation time 49484167439 ps
CPU time 17.08 seconds
Started Jul 20 06:55:07 PM PDT 24
Finished Jul 20 06:55:25 PM PDT 24
Peak memory 240796 kb
Host smart-f0520e8c-88ca-4602-8918-5d720a01cc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907399506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2907399506
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.348976900
Short name T933
Test name
Test status
Simulation time 12591808 ps
CPU time 0.73 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:52:13 PM PDT 24
Peak memory 205916 kb
Host smart-03d3ea6d-86c9-456d-8fdb-749e5e90cc86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348976900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.348976900
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.121416677
Short name T443
Test name
Test status
Simulation time 245050224 ps
CPU time 3.44 seconds
Started Jul 20 06:52:14 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 224944 kb
Host smart-f6b66cf8-438d-43b7-aec5-1d27fcbfe147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121416677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.121416677
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3646449843
Short name T591
Test name
Test status
Simulation time 21606300 ps
CPU time 0.86 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:11 PM PDT 24
Peak memory 207420 kb
Host smart-b61c45a1-24a0-4eb4-92c0-a25c99ed57d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646449843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3646449843
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.114000991
Short name T55
Test name
Test status
Simulation time 3207374844 ps
CPU time 76.22 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:53:32 PM PDT 24
Peak memory 257020 kb
Host smart-ad689861-fec6-4a31-a4aa-8d0251df2655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114000991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.114000991
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4242904822
Short name T174
Test name
Test status
Simulation time 6898273028 ps
CPU time 43.73 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:57 PM PDT 24
Peak memory 236848 kb
Host smart-44e60d89-4163-4564-a511-e888711514ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242904822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4242904822
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1547388724
Short name T26
Test name
Test status
Simulation time 7672517887 ps
CPU time 28.18 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:38 PM PDT 24
Peak memory 239424 kb
Host smart-137867c8-7efe-482b-a222-2b7239e90875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547388724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1547388724
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.1907325708
Short name T922
Test name
Test status
Simulation time 1902861648 ps
CPU time 11.71 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:52:18 PM PDT 24
Peak memory 224948 kb
Host smart-72e8648d-3e73-40a1-b1c4-4e9e2b60f93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907325708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.1907325708
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.804236702
Short name T776
Test name
Test status
Simulation time 12613003215 ps
CPU time 34.27 seconds
Started Jul 20 06:52:04 PM PDT 24
Finished Jul 20 06:52:40 PM PDT 24
Peak memory 238972 kb
Host smart-2ba3b116-4143-46d6-988d-6ad3afa2cdf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804236702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.804236702
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1167990575
Short name T993
Test name
Test status
Simulation time 553070471 ps
CPU time 3.45 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:52:10 PM PDT 24
Peak memory 224856 kb
Host smart-0c683311-a593-4dab-bde3-e86ac89e1c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167990575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1167990575
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3179974155
Short name T793
Test name
Test status
Simulation time 1487560342 ps
CPU time 4.1 seconds
Started Jul 20 06:52:02 PM PDT 24
Finished Jul 20 06:52:07 PM PDT 24
Peak memory 234100 kb
Host smart-ad19fd26-dab1-4bdc-9fd4-ff98d992437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179974155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3179974155
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.579427438
Short name T357
Test name
Test status
Simulation time 6481431824 ps
CPU time 11.98 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 219932 kb
Host smart-1f289747-3ba8-47ca-9771-f67809468d2f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=579427438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.579427438
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.164078733
Short name T581
Test name
Test status
Simulation time 154066757 ps
CPU time 0.93 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:52:13 PM PDT 24
Peak memory 206168 kb
Host smart-9ff34e1e-98d5-44ff-9bc9-bed344218c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164078733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.164078733
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.734159571
Short name T329
Test name
Test status
Simulation time 3511146377 ps
CPU time 6.57 seconds
Started Jul 20 06:52:02 PM PDT 24
Finished Jul 20 06:52:09 PM PDT 24
Peak memory 216756 kb
Host smart-337812a4-871c-4b48-aa76-693e9031dea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734159571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.734159571
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2940366857
Short name T152
Test name
Test status
Simulation time 9199620027 ps
CPU time 10.38 seconds
Started Jul 20 06:52:04 PM PDT 24
Finished Jul 20 06:52:15 PM PDT 24
Peak memory 216544 kb
Host smart-6fba34fa-fedf-4f8d-80ad-f45b196d941f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940366857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2940366857
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2861746006
Short name T578
Test name
Test status
Simulation time 298149675 ps
CPU time 2.17 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:15 PM PDT 24
Peak memory 216304 kb
Host smart-040bd596-d4d8-4c5b-981d-fbe3a45c6f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861746006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2861746006
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3268942583
Short name T519
Test name
Test status
Simulation time 245520418 ps
CPU time 0.88 seconds
Started Jul 20 06:52:05 PM PDT 24
Finished Jul 20 06:52:07 PM PDT 24
Peak memory 206416 kb
Host smart-27340e36-f7b0-440b-a6ec-071b81ad46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268942583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3268942583
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2322018337
Short name T958
Test name
Test status
Simulation time 1963181273 ps
CPU time 10.31 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:26 PM PDT 24
Peak memory 224848 kb
Host smart-0a899709-32d0-428d-91b8-d0ad2596bf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322018337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2322018337
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3770014572
Short name T778
Test name
Test status
Simulation time 40732507 ps
CPU time 0.71 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 205936 kb
Host smart-216eb7f3-1f4f-4140-860a-79de9c325462
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770014572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
770014572
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4267222220
Short name T986
Test name
Test status
Simulation time 2385069113 ps
CPU time 14.75 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 224948 kb
Host smart-793fe19e-267c-4324-9eb1-176e9246faa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267222220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4267222220
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3207854630
Short name T378
Test name
Test status
Simulation time 25703116 ps
CPU time 0.75 seconds
Started Jul 20 06:52:14 PM PDT 24
Finished Jul 20 06:52:17 PM PDT 24
Peak memory 205980 kb
Host smart-98335baa-7f83-4325-b7e6-4075b238a1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207854630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3207854630
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3206613184
Short name T462
Test name
Test status
Simulation time 16129131698 ps
CPU time 60.49 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:53:12 PM PDT 24
Peak memory 249612 kb
Host smart-ea270025-2899-443a-b5fb-dad5477e2e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206613184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3206613184
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3620498434
Short name T532
Test name
Test status
Simulation time 3000067197 ps
CPU time 62.57 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:53:18 PM PDT 24
Peak memory 250920 kb
Host smart-680c6c35-9ac4-4c93-ae03-2b66a3d5424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620498434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3620498434
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.42151661
Short name T318
Test name
Test status
Simulation time 348381371 ps
CPU time 5.99 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:16 PM PDT 24
Peak memory 224968 kb
Host smart-2604368d-e67a-434a-a97e-13ca428f5395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42151661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.42151661
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1847863801
Short name T550
Test name
Test status
Simulation time 1582076461 ps
CPU time 6.69 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:21 PM PDT 24
Peak memory 224876 kb
Host smart-e00eb536-e1a2-406a-ad78-b763b7bffb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847863801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1847863801
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2138256967
Short name T464
Test name
Test status
Simulation time 391520912 ps
CPU time 3.16 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:22 PM PDT 24
Peak memory 224908 kb
Host smart-47b49e65-3f0b-42ea-89f2-ef1ca0f3032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138256967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2138256967
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.31147118
Short name T583
Test name
Test status
Simulation time 26800388626 ps
CPU time 74.67 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:53:31 PM PDT 24
Peak memory 224864 kb
Host smart-1a3b7a4c-9389-4a60-ab02-43f2bf83d049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31147118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.31147118
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2801936544
Short name T876
Test name
Test status
Simulation time 834121102 ps
CPU time 5.14 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:19 PM PDT 24
Peak memory 233096 kb
Host smart-06d7cf62-4aa9-478b-b41f-8f3331de37d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801936544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2801936544
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2889220325
Short name T513
Test name
Test status
Simulation time 1391968846 ps
CPU time 5.81 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 233096 kb
Host smart-d85a9df0-60cf-4692-9f10-8796fb06de0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889220325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2889220325
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2838439386
Short name T138
Test name
Test status
Simulation time 3148761861 ps
CPU time 10.78 seconds
Started Jul 20 06:52:14 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 223648 kb
Host smart-49ad6c34-b4fa-40f9-8ba5-f87afe6e7bcb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2838439386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2838439386
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.716891773
Short name T814
Test name
Test status
Simulation time 52875859210 ps
CPU time 238.39 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:56:12 PM PDT 24
Peak memory 256680 kb
Host smart-98f5ac5e-fe71-439e-8be2-d9f1b4b6a6c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716891773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.716891773
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1865453479
Short name T475
Test name
Test status
Simulation time 3053639442 ps
CPU time 5.15 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 216708 kb
Host smart-9978118b-3a55-4372-a28b-5e1c11e77135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865453479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1865453479
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2610642560
Short name T551
Test name
Test status
Simulation time 16694268316 ps
CPU time 13.25 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:29 PM PDT 24
Peak memory 216752 kb
Host smart-44266f19-f753-40d9-8258-7502de290be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610642560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2610642560
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1293312624
Short name T719
Test name
Test status
Simulation time 106197544 ps
CPU time 1.06 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:16 PM PDT 24
Peak memory 207832 kb
Host smart-164457ec-0d04-4284-915f-cf17f5391655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293312624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1293312624
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3852108898
Short name T994
Test name
Test status
Simulation time 384249813 ps
CPU time 1.06 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:16 PM PDT 24
Peak memory 207464 kb
Host smart-fd9f6fb5-5aa4-4a02-af01-f78c9e365b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852108898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3852108898
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.4273399585
Short name T633
Test name
Test status
Simulation time 665758850 ps
CPU time 8.28 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 249084 kb
Host smart-65017e09-ac52-47bd-871c-6006395b2b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273399585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4273399585
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2293241814
Short name T367
Test name
Test status
Simulation time 24945834 ps
CPU time 0.76 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:16 PM PDT 24
Peak memory 205916 kb
Host smart-2125e410-927a-4131-9a52-a74ccd913de6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293241814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
293241814
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1249609605
Short name T978
Test name
Test status
Simulation time 414858711 ps
CPU time 8.35 seconds
Started Jul 20 06:52:14 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 224896 kb
Host smart-e47ed101-a52b-40d0-9abb-ab1406c43171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249609605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1249609605
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1959415500
Short name T862
Test name
Test status
Simulation time 44820846 ps
CPU time 0.78 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:52:11 PM PDT 24
Peak memory 206048 kb
Host smart-ce7c2b47-9a48-4b45-ab31-d837e85a77aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959415500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1959415500
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1257344257
Short name T998
Test name
Test status
Simulation time 14245464419 ps
CPU time 59.43 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:53:14 PM PDT 24
Peak memory 252908 kb
Host smart-abf85f8a-576b-4d5c-ae3c-a04e45b72627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257344257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1257344257
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1561763324
Short name T49
Test name
Test status
Simulation time 41691669163 ps
CPU time 296.44 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:57:15 PM PDT 24
Peak memory 257840 kb
Host smart-8551f98e-0acb-4db6-9000-b099fb05236d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561763324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1561763324
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3260314792
Short name T990
Test name
Test status
Simulation time 5412320472 ps
CPU time 57.76 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:53:11 PM PDT 24
Peak memory 249660 kb
Host smart-f66f9361-1b74-4e61-bbb0-dd58d267e463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260314792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3260314792
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.2516240555
Short name T463
Test name
Test status
Simulation time 2066798736 ps
CPU time 8.08 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:24 PM PDT 24
Peak memory 234424 kb
Host smart-4e33328d-b474-4ba3-be53-8add4707cd9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516240555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.2516240555
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3730725881
Short name T966
Test name
Test status
Simulation time 190685975 ps
CPU time 3.49 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:19 PM PDT 24
Peak memory 224884 kb
Host smart-0cb29110-4fb0-4491-a365-3b0f725f3ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730725881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3730725881
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3848895195
Short name T261
Test name
Test status
Simulation time 72286723355 ps
CPU time 91.01 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:53:43 PM PDT 24
Peak memory 224940 kb
Host smart-ca1419c0-8f49-4783-a1d1-d40613cb5669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848895195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3848895195
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2615973708
Short name T890
Test name
Test status
Simulation time 4815451886 ps
CPU time 16.38 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 233156 kb
Host smart-a3758aa9-e7ea-4df8-b974-02605a801157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615973708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2615973708
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1200132743
Short name T805
Test name
Test status
Simulation time 6917423410 ps
CPU time 6.57 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:22 PM PDT 24
Peak memory 233156 kb
Host smart-490715e5-d35d-47fc-a5fa-d1d881065a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200132743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1200132743
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.3663221538
Short name T744
Test name
Test status
Simulation time 2463290957 ps
CPU time 14.32 seconds
Started Jul 20 06:52:15 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 222572 kb
Host smart-1595d67e-336b-44b3-abcd-7e27aaf4360f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3663221538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.3663221538
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.2606820442
Short name T397
Test name
Test status
Simulation time 35441290 ps
CPU time 0.94 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 207072 kb
Host smart-6f1b3e06-5dde-4b20-a579-1c6e568e5385
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606820442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.2606820442
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1385947600
Short name T526
Test name
Test status
Simulation time 4124412746 ps
CPU time 26.39 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:41 PM PDT 24
Peak memory 216708 kb
Host smart-e0b192fc-c546-4b47-8c23-cdee8be68a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385947600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1385947600
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.636253127
Short name T601
Test name
Test status
Simulation time 11958990 ps
CPU time 0.72 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:15 PM PDT 24
Peak memory 206160 kb
Host smart-1965da8e-e056-4ee9-af21-2b791f3dbb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636253127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.636253127
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3265195171
Short name T11
Test name
Test status
Simulation time 1471261639 ps
CPU time 1.96 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:18 PM PDT 24
Peak memory 216632 kb
Host smart-21d117c8-1ebe-4e44-bee7-64cb5af520ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265195171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3265195171
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.321675816
Short name T348
Test name
Test status
Simulation time 159253288 ps
CPU time 0.96 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:16 PM PDT 24
Peak memory 206432 kb
Host smart-e47d7c05-b315-490d-9f1a-23421d4acdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321675816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.321675816
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3324348346
Short name T836
Test name
Test status
Simulation time 38404564181 ps
CPU time 13.05 seconds
Started Jul 20 06:52:12 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 233196 kb
Host smart-2c7484b3-63c6-4075-9a16-47988ec6f004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324348346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3324348346
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1305664153
Short name T992
Test name
Test status
Simulation time 52731891 ps
CPU time 0.74 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 205356 kb
Host smart-e79dad2e-3779-4d32-b777-988d21022c84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305664153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
305664153
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2506228329
Short name T530
Test name
Test status
Simulation time 2066295688 ps
CPU time 6.05 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 224828 kb
Host smart-36d3fcd1-27f0-4f2e-8fe8-873bd9812eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506228329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2506228329
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.2952908624
Short name T648
Test name
Test status
Simulation time 38829668 ps
CPU time 0.78 seconds
Started Jul 20 06:52:11 PM PDT 24
Finished Jul 20 06:52:15 PM PDT 24
Peak memory 207048 kb
Host smart-43157b70-30d8-47b5-b132-24310fe5ef09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952908624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.2952908624
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2430284587
Short name T240
Test name
Test status
Simulation time 13280751477 ps
CPU time 93.76 seconds
Started Jul 20 06:52:17 PM PDT 24
Finished Jul 20 06:53:52 PM PDT 24
Peak memory 257264 kb
Host smart-0d3bde9b-34be-42ab-825f-b387471f6b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430284587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2430284587
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.152509219
Short name T404
Test name
Test status
Simulation time 41193447723 ps
CPU time 107.2 seconds
Started Jul 20 06:52:20 PM PDT 24
Finished Jul 20 06:54:08 PM PDT 24
Peak memory 236120 kb
Host smart-e48e004d-eccf-4cce-8336-e56849f7694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152509219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.152509219
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1147300224
Short name T222
Test name
Test status
Simulation time 52127264518 ps
CPU time 256.2 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:56:41 PM PDT 24
Peak memory 252132 kb
Host smart-4ad4229a-1b94-4955-b0f8-4af9174aa0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147300224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1147300224
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3629021066
Short name T669
Test name
Test status
Simulation time 2242963892 ps
CPU time 7.57 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 241344 kb
Host smart-5df77b4d-d7ed-4505-86f7-f05827754946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629021066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3629021066
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1934037054
Short name T1004
Test name
Test status
Simulation time 98597401427 ps
CPU time 153.35 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:54:53 PM PDT 24
Peak memory 249588 kb
Host smart-e21bce42-6fae-4700-b838-d76e8824f246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934037054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1934037054
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.368105855
Short name T667
Test name
Test status
Simulation time 1408910886 ps
CPU time 4.02 seconds
Started Jul 20 06:52:10 PM PDT 24
Finished Jul 20 06:52:15 PM PDT 24
Peak memory 224892 kb
Host smart-4b0edc77-a97e-4bec-9b4a-5454736f0cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368105855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.368105855
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.464242525
Short name T263
Test name
Test status
Simulation time 16954394751 ps
CPU time 51.68 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:53:16 PM PDT 24
Peak memory 233188 kb
Host smart-3b94ceff-8499-43ca-a139-ec339d1f0c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464242525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.464242525
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.144543525
Short name T739
Test name
Test status
Simulation time 277372611 ps
CPU time 3.32 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:19 PM PDT 24
Peak memory 233108 kb
Host smart-3e047f7a-3ffb-4844-a5d5-cc12eea1adff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144543525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
144543525
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2775289569
Short name T406
Test name
Test status
Simulation time 6515530590 ps
CPU time 12.54 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 233236 kb
Host smart-02941a36-2b21-4908-af55-a908e798f7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775289569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2775289569
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.202316723
Short name T711
Test name
Test status
Simulation time 304242551 ps
CPU time 4.26 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:31 PM PDT 24
Peak memory 219788 kb
Host smart-d39aa98b-2c8b-45d2-8351-1df8cb7c0a8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202316723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.202316723
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2701594996
Short name T632
Test name
Test status
Simulation time 544795802 ps
CPU time 1.05 seconds
Started Jul 20 06:52:24 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 207516 kb
Host smart-4f760734-a67e-4a97-a741-056c1996748e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701594996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2701594996
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.24794720
Short name T330
Test name
Test status
Simulation time 6277805481 ps
CPU time 17.17 seconds
Started Jul 20 06:52:09 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 216692 kb
Host smart-f9814ead-f350-4e92-978f-2e94073e2fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24794720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.24794720
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1659547942
Short name T800
Test name
Test status
Simulation time 2554256737 ps
CPU time 4.17 seconds
Started Jul 20 06:52:14 PM PDT 24
Finished Jul 20 06:52:21 PM PDT 24
Peak memory 216768 kb
Host smart-38bc6b80-76db-4af2-95b1-8eac2aa1e998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659547942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1659547942
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1242812364
Short name T811
Test name
Test status
Simulation time 65078484 ps
CPU time 1.22 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:17 PM PDT 24
Peak memory 208496 kb
Host smart-a7e7a9d7-28ae-4537-9065-c62cfcbae792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242812364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1242812364
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3810252356
Short name T402
Test name
Test status
Simulation time 70510210 ps
CPU time 0.87 seconds
Started Jul 20 06:52:13 PM PDT 24
Finished Jul 20 06:52:17 PM PDT 24
Peak memory 206428 kb
Host smart-4a4dfc7f-b3f9-4da3-84d0-7c010bd2517d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810252356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3810252356
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2977134765
Short name T784
Test name
Test status
Simulation time 220925855 ps
CPU time 3.61 seconds
Started Jul 20 06:52:17 PM PDT 24
Finished Jul 20 06:52:21 PM PDT 24
Peak memory 233116 kb
Host smart-fe295a2b-1536-4192-bdbc-2bfb0e7eca00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977134765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2977134765
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3684219883
Short name T641
Test name
Test status
Simulation time 16194409 ps
CPU time 0.72 seconds
Started Jul 20 06:52:19 PM PDT 24
Finished Jul 20 06:52:21 PM PDT 24
Peak memory 205936 kb
Host smart-a5a88eeb-7928-4057-b888-58f9871ea510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684219883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
684219883
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3036541031
Short name T941
Test name
Test status
Simulation time 695488665 ps
CPU time 6.06 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:33 PM PDT 24
Peak memory 233080 kb
Host smart-4e9bfb77-a78d-4386-8145-848ebefea776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036541031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3036541031
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2989160704
Short name T437
Test name
Test status
Simulation time 25908198 ps
CPU time 0.83 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:24 PM PDT 24
Peak memory 207072 kb
Host smart-89dd33cb-66ed-4301-b171-4737ab2fc05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989160704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2989160704
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.831798532
Short name T493
Test name
Test status
Simulation time 2740458504 ps
CPU time 55.54 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:53:20 PM PDT 24
Peak memory 252832 kb
Host smart-07054307-50c5-47ab-a710-0b610745546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831798532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.831798532
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4190653594
Short name T302
Test name
Test status
Simulation time 23249820138 ps
CPU time 159.49 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:54:59 PM PDT 24
Peak memory 273316 kb
Host smart-1d0e4a50-9f7e-4270-971d-d532d1881eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190653594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4190653594
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3271418380
Short name T792
Test name
Test status
Simulation time 8138813146 ps
CPU time 85.16 seconds
Started Jul 20 06:52:17 PM PDT 24
Finished Jul 20 06:53:43 PM PDT 24
Peak memory 240576 kb
Host smart-7d074e08-7cff-4906-9b0b-5d80066a0a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271418380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3271418380
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.4062942724
Short name T359
Test name
Test status
Simulation time 584436491 ps
CPU time 5.05 seconds
Started Jul 20 06:52:17 PM PDT 24
Finished Jul 20 06:52:23 PM PDT 24
Peak memory 224956 kb
Host smart-38797bf8-14e4-4720-9fc3-085494a3f353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062942724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.4062942724
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.157078581
Short name T173
Test name
Test status
Simulation time 12405285935 ps
CPU time 34.72 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:59 PM PDT 24
Peak memory 224996 kb
Host smart-f6eb3ed9-51d7-40f0-adb9-945e62e979b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157078581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.
157078581
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2927549714
Short name T179
Test name
Test status
Simulation time 610690999 ps
CPU time 8.3 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:32 PM PDT 24
Peak memory 233128 kb
Host smart-f25ff837-5034-4564-b8bb-6157e4d52e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927549714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2927549714
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.790877912
Short name T5
Test name
Test status
Simulation time 7782821553 ps
CPU time 25.46 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:45 PM PDT 24
Peak memory 234616 kb
Host smart-68a20c3c-33e4-46cf-a007-ed1831e65fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790877912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.790877912
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2418314765
Short name T512
Test name
Test status
Simulation time 4373658823 ps
CPU time 16.02 seconds
Started Jul 20 06:52:25 PM PDT 24
Finished Jul 20 06:52:42 PM PDT 24
Peak memory 233164 kb
Host smart-e3fa93d0-3eff-487d-9feb-5bdd90eeff1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418314765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2418314765
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1031525895
Short name T764
Test name
Test status
Simulation time 4662420763 ps
CPU time 5.16 seconds
Started Jul 20 06:52:19 PM PDT 24
Finished Jul 20 06:52:25 PM PDT 24
Peak memory 233188 kb
Host smart-75f32e91-a278-4bad-aec3-1d0b86b67ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031525895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1031525895
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.300606141
Short name T780
Test name
Test status
Simulation time 14370958606 ps
CPU time 19.47 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:38 PM PDT 24
Peak memory 222600 kb
Host smart-44d281d3-66ff-4303-9e42-87e016d96f97
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=300606141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.300606141
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.3180132698
Short name T200
Test name
Test status
Simulation time 8363174329 ps
CPU time 53.31 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:53:17 PM PDT 24
Peak memory 266028 kb
Host smart-ae8a4ff0-d6e8-433d-8e7c-342f00244943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180132698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.3180132698
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3795453054
Short name T749
Test name
Test status
Simulation time 5562412845 ps
CPU time 32.29 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:55 PM PDT 24
Peak memory 216896 kb
Host smart-e86638fa-ae79-43a2-9ae1-f7467505c686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795453054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3795453054
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2434470
Short name T636
Test name
Test status
Simulation time 25356560260 ps
CPU time 8.07 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:27 PM PDT 24
Peak memory 216696 kb
Host smart-9540d73a-a501-40cc-b00a-ee9ad76711b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2434470
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1347017420
Short name T339
Test name
Test status
Simulation time 455429752 ps
CPU time 4.22 seconds
Started Jul 20 06:52:22 PM PDT 24
Finished Jul 20 06:52:28 PM PDT 24
Peak memory 216628 kb
Host smart-476a1c75-4a5f-4d37-89a4-b312bfc0adf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347017420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1347017420
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1915899869
Short name T126
Test name
Test status
Simulation time 96153642 ps
CPU time 0.84 seconds
Started Jul 20 06:52:18 PM PDT 24
Finished Jul 20 06:52:20 PM PDT 24
Peak memory 206416 kb
Host smart-486a2f56-6b51-4cb4-8043-f8a0d454f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915899869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1915899869
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4121495746
Short name T568
Test name
Test status
Simulation time 40636427200 ps
CPU time 24.99 seconds
Started Jul 20 06:52:21 PM PDT 24
Finished Jul 20 06:52:46 PM PDT 24
Peak memory 233300 kb
Host smart-1782f218-a01a-4ce2-a842-843948dd259a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121495746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4121495746
Directory /workspace/9.spi_device_upload/latest
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