Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2444373	1			T1	1		T2	2605		T3	28
all_values[1]	2444373	1			T1	1		T2	2605		T3	28
all_values[2]	2444373	1			T1	1		T2	2605		T3	28
all_values[3]	2444373	1			T1	1		T2	2605		T3	28
all_values[4]	2444373	1			T1	1		T2	2605		T3	28
all_values[5]	2444373	1			T1	1		T2	2605		T3	28
all_values[6]	2444373	1			T1	1		T2	2605		T3	28
all_values[7]	2444373	1			T1	1		T2	2605		T3	28

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19065917

1

T1

8

T2

20840

T3

224

auto[1]

489067

1

T12

81

T13

102

T14

35

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19528648

1

T1

8

T2

20840

T3

224

auto[1]

26336

1

T12

416

T22

246

T13

384

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2369855	1			T1	1		T2	2605		T3	28
all_values[0]	auto[0]	auto[1]	12037	1			T12	190		T22	109		T13	172
all_values[0]	auto[1]	auto[0]	61715	1			T12	8		T13	6		T14	2
all_values[0]	auto[1]	auto[1]	766	1			T13	9		T14	5		T15	2
all_values[1]	auto[0]	auto[0]	2368069	1			T1	1		T2	2605		T3	28
all_values[1]	auto[0]	auto[1]	7807	1			T12	108		T22	109		T13	123
all_values[1]	auto[1]	auto[0]	67858	1			T12	10		T13	12		T14	3
all_values[1]	auto[1]	auto[1]	639	1			T12	4		T13	3		T14	2
all_values[2]	auto[0]	auto[0]	2386662	1			T1	1		T2	2605		T3	28
all_values[2]	auto[0]	auto[1]	2729	1			T12	72		T22	28		T13	31
all_values[2]	auto[1]	auto[0]	54621	1			T12	2		T13	12		T14	2
all_values[2]	auto[1]	auto[1]	361	1			T12	8		T14	2		T15	2
all_values[3]	auto[0]	auto[0]	2343369	1			T1	1		T2	2605		T3	28
all_values[3]	auto[0]	auto[1]	199	1			T12	6		T13	3		T15	4
all_values[3]	auto[1]	auto[0]	100610	1			T12	2		T13	9		T14	5
all_values[3]	auto[1]	auto[1]	195	1			T12	1		T13	4		T14	1
all_values[4]	auto[0]	auto[0]	2430379	1			T1	1		T2	2605		T3	28
all_values[4]	auto[0]	auto[1]	185	1			T12	1		T13	6		T14	4
all_values[4]	auto[1]	auto[0]	13586	1			T12	8		T13	7		T14	2
all_values[4]	auto[1]	auto[1]	223	1			T12	5		T13	6		T14	1
all_values[5]	auto[0]	auto[0]	2353205	1			T1	1		T2	2605		T3	28
all_values[5]	auto[0]	auto[1]	184	1			T12	4		T13	7		T14	3
all_values[5]	auto[1]	auto[0]	90791	1			T12	8		T13	8		T15	1884
all_values[5]	auto[1]	auto[1]	193	1			T12	2		T13	3		T14	1
all_values[6]	auto[0]	auto[0]	2376465	1			T1	1		T2	2605		T3	28
all_values[6]	auto[0]	auto[1]	186	1			T12	4		T13	6		T15	1
all_values[6]	auto[1]	auto[0]	67496	1			T12	7		T13	10		T14	5
all_values[6]	auto[1]	auto[1]	226	1			T12	4		T13	3		T14	1
all_values[7]	auto[0]	auto[0]	2414372	1			T1	1		T2	2605		T3	28
all_values[7]	auto[0]	auto[1]	214	1			T12	3		T13	5		T14	2
all_values[7]	auto[1]	auto[0]	29595	1			T12	8		T13	7		T14	2
all_values[7]	auto[1]	auto[1]	192	1			T12	4		T13	3		T14	1