Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	33285	1			T2	154		T6	91		T7	166
auto[SpiFlashAddrCfg]	7488	1			T1	1		T2	27		T6	63
auto[SpiFlashAddr3b]	9015	1			T2	41		T3	2		T5	8
auto[SpiFlashAddr4b]	7505	1			T2	33		T5	4		T6	46

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32930

1

T1

1

T2

134

T3

2

auto[1]

24363

1

T2

121

T6

105

T7

119

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30412

1

T2

167

T6

140

T7

128

auto[1]

26881

1

T1

1

T2

88

T3

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	37921	1			T2	173		T3	2		T6	117
values[1]	1085	1			T2	3		T6	10		T7	5
values[2]	1465	1			T2	8		T6	13		T7	15
values[3]	1527	1			T2	11		T6	6		T7	6
values[4]	1362	1			T2	3		T6	11		T7	6
values[5]	1425	1			T1	1		T2	6		T6	13
values[6]	1425	1			T2	3		T6	7		T7	9
values[7]	1401	1			T2	8		T6	14		T7	7
values[8]	9682	1			T2	40		T5	12		T6	69

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31646

1

T3

2

T5

12

T6

260

auto[1]

25647

1

T1

1

T2

255

T7

302

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

54095

1

T1

1

T2

248

T5

12

write

3198

1

T2

7

T3

2

T6

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18916

1

T2

95

T6

135

T7

98

valids[0x1]

38377

1

T1

1

T2

160

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1592	1			T2	6		T6	9		T7	12
internal_process_ops[0x5a]	1491	1			T2	8		T6	8		T7	11
internal_process_ops[0x05]	19581	1			T2	91		T6	6		T7	89
internal_process_ops[0x35]	1560	1			T2	6		T6	16		T7	6
internal_process_ops[0x15]	1597	1			T2	6		T6	8		T7	7
internal_process_ops[0x03]	1058	1			T1	1		T2	2		T5	8
internal_process_ops[0x0b]	1119	1			T5	4		T6	7		T7	2
internal_process_ops[0x3b]	1064	1			T2	4		T6	7		T7	1
internal_process_ops[0x6b]	1106	1			T2	2		T6	10		T7	4
internal_process_ops[0xbb]	1084	1			T2	2		T6	8		T7	1
internal_process_ops[0xeb]	1071	1			T2	2		T6	12		T7	5

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55663

1

T1

1

T2

252

T3

2

auto[1]

1630

1

T2

3

T6

11

T7

9

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55010

1

T1

1

T2

246

T3

2

auto[1]

2283

1

T2

9

T6

21

T7

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10640

1

T6

69

T9

6

T10

53

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6289

1

T6

20

T47

2

T12

95

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2133

1

T6

31

T8

4

T9

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1979

1

T6

26

T47

4

T12

27

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2632

1

T5

8

T6

34

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2262

1

T6

24

T12

27

T22

7

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2064

1

T5

4

T6

16

T9

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1953

1

T6

23

T47

4

T12

21

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

147

1

T10

4

T13

2

T184

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

85

1

T22

1

T13

4

T49

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

92

1

T6

1

T12

3

T22

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

122

1

T6

1

T47

2

T101

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

89

1

T6

1

T12

1

T13

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T6

2

T22

1

T13

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

108

1

T12

2

T22

1

T36

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

110

1

T6

3

T25

4

T13

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

95

1

T3

2

T12

3

T40

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

106

1

T22

1

T50

3

T185

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

83

1

T12

1

T13

4

T101

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

106

1

T6

2

T12

1

T22

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

130

1

T6

2

T8

4

T22

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T12

2

T14

4

T49

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

98

1

T6

2

T12

3

T13

7

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

108

1

T6

3

T47

4

T50

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9519

1

T2

84

T7

115

T52

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6056

1

T2

68

T7

49

T46

35

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1320

1

T1

1

T2

9

T7

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1246

1

T2

16

T7

14

T46

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1692

1

T2

21

T7

25

T44

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1670

1

T2

20

T7

29

T46

14

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1333

1

T2

15

T7

12

T43

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1307

1

T2

15

T7

23

T46

12

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

74

1

T2

2

T186

1

T187

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

110

1

T7

1

T46

2

T70

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

61

1

T7

1

T46

3

T187

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

90

1

T46

2

T70

3

T188

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

103

1

T46

2

T37

1

T189

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

92

1

T7

1

T46

1

T70

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

106

1

T2

2

T46

1

T186

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

98

1

T7

2

T46

1

T70

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

75

1

T46

1

T186

1

T189

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

98

1

T7

1

T37

1

T187

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

112

1

T187

2

T190

1

T191

10

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T70

1

T187

2

T91

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

88

1

T7

4

T37

1

T189

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

90

1

T2

3

T7

3

T70

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

107

1

T37

3

T189

1

T191

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T7

1

T46

1

T188

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4124	1			T6	51		T11	18		T47	2
auto[0]	values[0]	valids[0x1]	15871	1			T3	2		T6	66		T8	4
auto[0]	values[1]	valids[0x1]	614	1			T6	10		T12	14		T22	2
auto[0]	values[2]	valids[0x0]	547	1			T6	5		T12	5		T22	5
auto[0]	values[2]	valids[0x1]	319	1			T6	8		T192	2		T13	5
auto[0]	values[3]	valids[0x0]	615	1			T6	4		T12	5		T36	1
auto[0]	values[3]	valids[0x1]	304	1			T6	2		T12	1		T36	2
auto[0]	values[4]	valids[0x0]	520	1			T6	7		T12	4		T22	3
auto[0]	values[4]	valids[0x1]	306	1			T6	4		T12	4		T13	1
auto[0]	values[5]	valids[0x0]	601	1			T6	9		T8	2		T47	2
auto[0]	values[5]	valids[0x1]	318	1			T6	4		T8	2		T12	5
auto[0]	values[6]	valids[0x0]	571	1			T6	5		T12	13		T22	2
auto[0]	values[6]	valids[0x1]	305	1			T6	2		T12	1		T13	1
auto[0]	values[7]	valids[0x0]	540	1			T6	14		T12	5		T22	3
auto[0]	values[7]	valids[0x1]	301	1			T12	1		T22	3		T13	8
auto[0]	values[8]	valids[0x0]	3668	1			T6	40		T8	2		T48	2
auto[0]	values[8]	valids[0x1]	2122	1			T5	12		T6	29		T8	2
auto[1]	values[0]	valids[0x0]	3466	1			T2	43		T7	45		T52	1
auto[1]	values[0]	valids[0x1]	14460	1			T2	130		T7	142		T45	2
auto[1]	values[1]	valids[0x1]	471	1			T2	3		T7	5		T46	8
auto[1]	values[2]	valids[0x0]	341	1			T2	3		T7	8		T44	2
auto[1]	values[2]	valids[0x1]	258	1			T2	5		T7	7		T46	1
auto[1]	values[3]	valids[0x0]	353	1			T2	9		T7	3		T46	3
auto[1]	values[3]	valids[0x1]	255	1			T2	2		T7	3		T70	1
auto[1]	values[4]	valids[0x0]	303	1			T2	3		T7	2		T46	7
auto[1]	values[4]	valids[0x1]	233	1			T7	4		T46	2		T70	7
auto[1]	values[5]	valids[0x0]	302	1			T2	4		T46	2		T70	2
auto[1]	values[5]	valids[0x1]	204	1			T1	1		T2	2		T7	7
auto[1]	values[6]	valids[0x0]	307	1			T2	3		T7	8		T45	2
auto[1]	values[6]	valids[0x1]	242	1			T7	1		T46	3		T70	7
auto[1]	values[7]	valids[0x0]	327	1			T2	5		T7	1		T70	2
auto[1]	values[7]	valids[0x1]	233	1			T2	3		T7	6		T46	2
auto[1]	values[8]	valids[0x0]	2331	1			T2	25		T7	31		T43	3
auto[1]	values[8]	valids[0x1]	1561	1			T2	15		T7	29		T46	21