Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3507787

1

T1

4070

T2

7919

T3

1

auto[1]

30782

1

T2

75

T6

456

T7

82

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1073319

1

T1

4070

T2

61

T3

1

auto[1]

2465250

1

T2

7933

T6

27987

T7

6057

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	638007	1			T1	3934		T2	3506		T3	1
auto[524288:1048575]	415529	1			T1	132		T2	439		T5	34
auto[1048576:1572863]	356702	1			T2	279		T5	1		T6	4402
auto[1572864:2097151]	431229	1			T1	3		T2	1369		T6	3666
auto[2097152:2621439]	422531	1			T1	1		T2	17		T5	29
auto[2621440:3145727]	438737	1			T2	136		T5	12800		T6	27
auto[3145728:3670015]	430878	1			T2	708		T5	4071		T6	1035
auto[3670016:4194303]	404956	1			T2	1540		T5	1576		T6	11175

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2500401

1

T1

5

T2

7987

T3

1

auto[1]

1038168

1

T1

4065

T2

7

T5

19559

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3060274

1

T1

4070

T2

4605

T3

1

auto[1]

478295

1

T2

3389

T6

6852

T7

1723

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	227054	1			T1	3934		T2	12		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	361505	1			T2	2959		T6	2883		T7	1538
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	122902	1			T1	132		T2	7		T5	34
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	225105	1			T2	426		T6	2307		T7	260
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	109584	1			T2	5		T5	1		T6	32
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	190040	1			T2	259		T6	328		T12	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	144979	1			T1	3		T2	2		T6	37
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	234461	1			T2	3		T6	3619		T7	17
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	78962	1			T1	1		T2	4		T5	29
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	283150	1			T2	1		T6	2399		T7	1
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	131866	1			T2	5		T5	12800		T6	8
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	219806	1			T2	122		T7	132		T12	3351
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	130646	1			T2	6		T5	4071		T6	81
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	241268	1			T2	484		T6	768		T7	1589
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105484	1			T5	1576		T6	69		T7	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	227689	1			T2	256		T6	8692		T7	768
auto[0]	auto[1]	auto[0:524287]	auto[0]	2919	1			T2	3		T6	23		T7	6
auto[0]	auto[1]	auto[0:524287]	auto[1]	42205	1			T2	519		T7	2		T12	791
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	777	1			T2	1		T6	12		T7	9
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	63870	1			T7	513		T50	1		T37	98
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	7739	1			T6	36		T12	2		T14	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	45610	1			T6	3720		T7	256		T46	407
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1226	1			T2	4		T7	4		T12	5
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	45007	1			T2	1339		T12	2		T22	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1916	1			T6	21		T7	1		T22	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	54131	1			T6	521		T7	396		T13	256
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1643	1			T6	13		T7	1		T12	6
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	81699	1			T12	514		T22	128		T13	5335
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	965	1			T6	44		T22	1		T170	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	54300	1			T2	218		T6	133		T22	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	742	1			T2	3		T6	45		T11	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	68537	1			T2	1281		T6	2250		T7	512
auto[1]	auto[0]	auto[0:524287]	auto[0]	517	1			T2	2		T6	10		T7	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3513	1			T2	11		T7	33		T10	49
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	368	1			T2	1		T6	7		T12	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2074	1			T2	4		T14	1		T70	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	382	1			T2	1		T6	7		T12	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2957	1			T2	14		T6	276		T12	7
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	394	1			T6	10		T7	2		T13	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3962	1			T7	20		T13	3		T46	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	334	1			T2	1		T6	6		T7	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3217	1			T2	11		T7	1		T12	5
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	363	1			T2	2		T6	6		T22	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2559	1			T2	7		T22	3		T13	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	392	1			T6	3		T22	2		T46	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2741	1			T22	5		T46	2		T186	21
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	416	1			T6	6		T12	5		T13	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1584	1			T6	91		T12	20		T13	23
auto[1]	auto[1]	auto[0:524287]	auto[0]	65	1			T7	2		T188	1		T195	4
auto[1]	auto[1]	auto[0:524287]	auto[1]	229	1			T7	14		T188	1		T207	9
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	67	1			T6	3		T7	1		T50	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	366	1			T7	5		T39	62		T206	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	56	1			T6	3		T46	2		T191	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	334	1			T46	2		T208	1		T236	9
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	129	1			T2	2		T12	2		T46	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1071	1			T2	19		T12	18		T101	128
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	123	1			T7	1		T46	1		T101	11
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	698	1			T101	256		T39	13		T225	10
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	113	1			T12	2		T46	1		T49	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	688	1			T12	2		T46	1		T188	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	90	1			T6	6		T22	1		T46	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	476	1			T187	5		T222	26		T225	25
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	106	1			T6	22		T12	2		T13	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	398	1			T12	8		T13	1		T38	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2009988	1			T1	5		T2	4549		T3	1
auto[0]	auto[0]	auto[1]	1024513	1			T1	4065		T2	2		T5	19559
auto[0]	auto[1]	auto[0]	460291	1			T2	3367		T6	6818		T7	1700
auto[0]	auto[1]	auto[1]	12995	1			T2	1		T11	5		T51	33
auto[1]	auto[0]	auto[0]	25241	1			T2	51		T6	410		T7	55
auto[1]	auto[0]	auto[1]	532	1			T2	3		T6	12		T7	4
auto[1]	auto[1]	auto[0]	4881	1			T2	20		T6	27		T7	22
auto[1]	auto[1]	auto[1]	128	1			T2	1		T6	7		T7	1