Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2444373	1			T1	1		T2	2605		T3	28
all_pins[1]	2444373	1			T1	1		T2	2605		T3	28
all_pins[2]	2444373	1			T1	1		T2	2605		T3	28
all_pins[3]	2444373	1			T1	1		T2	2605		T3	28
all_pins[4]	2444373	1			T1	1		T2	2605		T3	28
all_pins[5]	2444373	1			T1	1		T2	2605		T3	28
all_pins[6]	2444373	1			T1	1		T2	2605		T3	28
all_pins[7]	2444373	1			T1	1		T2	2605		T3	28

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19482771	1			T1	8		T2	20840		T3	224
values[0x1]	72213	1			T12	28		T13	31		T14	14
transitions[0x0=>0x1]	70152	1			T12	24		T13	24		T14	12
transitions[0x1=>0x0]	70167	1			T12	24		T13	25		T14	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2443545	1			T1	1		T2	2605		T3	28
all_pins[0]	values[0x1]	828	1			T13	9		T14	5		T15	2
all_pins[0]	transitions[0x0=>0x1]	481	1			T13	6		T14	4		T15	2
all_pins[0]	transitions[0x1=>0x0]	341	1			T12	4		T14	1		T15	1
all_pins[1]	values[0x0]	2443685	1			T1	1		T2	2605		T3	28
all_pins[1]	values[0x1]	688	1			T12	4		T13	3		T14	2
all_pins[1]	transitions[0x0=>0x1]	525	1			T12	2		T13	3		T14	2
all_pins[1]	transitions[0x1=>0x0]	210	1			T12	6		T14	2		T15	2
all_pins[2]	values[0x0]	2444000	1			T1	1		T2	2605		T3	28
all_pins[2]	values[0x1]	373	1			T12	8		T14	2		T15	2
all_pins[2]	transitions[0x0=>0x1]	322	1			T12	8		T14	2		T15	1
all_pins[2]	transitions[0x1=>0x0]	144	1			T12	1		T13	4		T14	1
all_pins[3]	values[0x0]	2444178	1			T1	1		T2	2605		T3	28
all_pins[3]	values[0x1]	195	1			T12	1		T13	4		T14	1
all_pins[3]	transitions[0x0=>0x1]	127	1			T13	2		T14	1		T15	1
all_pins[3]	transitions[0x1=>0x0]	155	1			T12	4		T13	4		T14	1
all_pins[4]	values[0x0]	2444150	1			T1	1		T2	2605		T3	28
all_pins[4]	values[0x1]	223	1			T12	5		T13	6		T14	1
all_pins[4]	transitions[0x0=>0x1]	178	1			T12	5		T13	6		T14	1
all_pins[4]	transitions[0x1=>0x0]	2342	1			T12	2		T13	3		T14	1
all_pins[5]	values[0x0]	2441986	1			T1	1		T2	2605		T3	28
all_pins[5]	values[0x1]	2387	1			T12	2		T13	3		T14	1
all_pins[5]	transitions[0x0=>0x1]	1100	1			T12	1		T13	3		T14	1
all_pins[5]	transitions[0x1=>0x0]	66040	1			T12	3		T13	3		T14	1
all_pins[6]	values[0x0]	2377046	1			T1	1		T2	2605		T3	28
all_pins[6]	values[0x1]	67327	1			T12	4		T13	3		T14	1
all_pins[6]	transitions[0x0=>0x1]	67275	1			T12	4		T13	3		T14	1
all_pins[6]	transitions[0x1=>0x0]	140	1			T12	4		T13	3		T14	1
all_pins[7]	values[0x0]	2444181	1			T1	1		T2	2605		T3	28
all_pins[7]	values[0x1]	192	1			T12	4		T13	3		T14	1
all_pins[7]	transitions[0x0=>0x1]	144	1			T12	4		T13	1		T15	5
all_pins[7]	transitions[0x1=>0x0]	795	1			T13	8		T14	4		T15	1