Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18336

1

T3

2

T5

12

T6

155

auto[1]

13310

1

T6

105

T47

16

T12

180

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4350	1			T5	12		T6	60		T12	97
values[1]	3337	1			T9	12		T12	42		T13	79
values[2]	4196	1			T3	2		T6	20		T8	12
values[3]	4098	1			T6	40		T47	16		T12	49
values[4]	3431	1			T6	20		T48	2		T12	40
values[5]	4530	1			T6	40		T25	18		T36	20
values[6]	3783	1			T6	60		T10	57		T12	20
values[7]	3921	1			T6	20		T11	18		T12	26

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3592	1			T12	48		T22	27		T170	8
values[1]	4327	1			T6	40		T12	46		T22	25
values[2]	4400	1			T5	12		T6	20		T9	12
values[3]	4125	1			T6	40		T8	12		T12	70
values[4]	3291	1			T3	2		T6	20		T10	57
values[5]	3699	1			T6	40		T13	68		T50	43
values[6]	4278	1			T6	60		T47	16		T12	89
values[7]	3934	1			T6	40		T12	22		T13	93

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	316	1			T99	20		T101	13		T263	12
auto[0]	values[0]	values[1]	409	1			T210	10		T101	9		T197	12
auto[0]	values[0]	values[2]	295	1			T5	12		T12	11		T38	19
auto[0]	values[0]	values[3]	347	1			T12	9		T243	11		T207	12
auto[0]	values[0]	values[4]	205	1			T6	15		T14	7		T207	9
auto[0]	values[0]	values[5]	261	1			T13	15		T236	14		T264	13
auto[0]	values[0]	values[6]	293	1			T6	7		T12	17		T23	18
auto[0]	values[0]	values[7]	342	1			T6	10		T13	12		T265	6
auto[0]	values[1]	values[0]	188	1			T266	2		T196	15		T197	10
auto[0]	values[1]	values[1]	176	1			T14	16		T239	8		T267	12
auto[0]	values[1]	values[2]	297	1			T9	12		T207	15		T20	17
auto[0]	values[1]	values[3]	320	1			T12	13		T198	11		T263	8
auto[0]	values[1]	values[4]	170	1			T222	7		T268	2		T269	10
auto[0]	values[1]	values[5]	275	1			T13	20		T185	13		T270	14
auto[0]	values[1]	values[6]	187	1			T185	11		T101	13		T211	11
auto[0]	values[1]	values[7]	212	1			T12	17		T13	11		T198	13
auto[0]	values[2]	values[0]	218	1			T170	8		T14	12		T205	16
auto[0]	values[2]	values[1]	267	1			T6	13		T192	2		T101	13
auto[0]	values[2]	values[2]	345	1			T50	19		T207	12		T222	38
auto[0]	values[2]	values[3]	342	1			T8	12		T22	21		T40	71
auto[0]	values[2]	values[4]	266	1			T3	2		T51	2		T12	11
auto[0]	values[2]	values[5]	243	1			T96	11		T196	14		T253	8
auto[0]	values[2]	values[6]	385	1			T12	7		T22	10		T24	4
auto[0]	values[2]	values[7]	271	1			T49	10		T101	16		T196	20
auto[0]	values[3]	values[0]	299	1			T12	12		T50	11		T185	8
auto[0]	values[3]	values[1]	327	1			T207	22		T211	10		T206	8
auto[0]	values[3]	values[2]	360	1			T271	14		T38	14		T222	21
auto[0]	values[3]	values[3]	233	1			T185	11		T101	13		T272	14
auto[0]	values[3]	values[4]	249	1			T14	12		T42	12		T243	13
auto[0]	values[3]	values[5]	234	1			T50	17		T198	14		T38	10
auto[0]	values[3]	values[6]	464	1			T6	12		T12	8		T13	13
auto[0]	values[3]	values[7]	205	1			T6	16		T102	4		T101	6
auto[0]	values[4]	values[0]	234	1			T12	9		T219	4		T13	10
auto[0]	values[4]	values[1]	302	1			T184	72		T49	12		T243	9
auto[0]	values[4]	values[2]	194	1			T48	2		T12	13		T211	13
auto[0]	values[4]	values[3]	224	1			T6	15		T273	18		T198	16
auto[0]	values[4]	values[4]	248	1			T208	33		T274	4		T275	2
auto[0]	values[4]	values[5]	217	1			T205	9		T276	6		T263	10
auto[0]	values[4]	values[6]	233	1			T49	17		T96	11		T206	7
auto[0]	values[4]	values[7]	348	1			T277	6		T38	13		T242	11
auto[0]	values[5]	values[0]	373	1			T42	10		T195	8		T278	10
auto[0]	values[5]	values[1]	478	1			T6	8		T104	6		T49	12
auto[0]	values[5]	values[2]	440	1			T13	11		T49	10		T96	13
auto[0]	values[5]	values[3]	423	1			T6	12		T36	9		T253	147
auto[0]	values[5]	values[4]	243	1			T196	15		T198	8		T38	9
auto[0]	values[5]	values[5]	396	1			T49	9		T279	12		T280	2
auto[0]	values[5]	values[6]	297	1			T198	13		T206	16		T281	12
auto[0]	values[5]	values[7]	226	1			T49	14		T198	10		T243	12
auto[0]	values[6]	values[0]	343	1			T22	20		T38	20		T197	11
auto[0]	values[6]	values[1]	285	1			T12	10		T42	12		T96	16
auto[0]	values[6]	values[2]	297	1			T6	15		T242	12		T282	16
auto[0]	values[6]	values[3]	201	1			T69	29		T38	14		T205	13
auto[0]	values[6]	values[4]	221	1			T10	57		T13	15		T198	9
auto[0]	values[6]	values[5]	345	1			T6	23		T50	9		T196	8
auto[0]	values[6]	values[6]	426	1			T207	12		T236	150		T281	9
auto[0]	values[6]	values[7]	191	1			T283	12		T174	22		T229	18
auto[0]	values[7]	values[0]	136	1			T207	9		T208	12		T229	11
auto[0]	values[7]	values[1]	356	1			T12	19		T22	3		T246	2
auto[0]	values[7]	values[2]	369	1			T195	7		T38	8		T201	14
auto[0]	values[7]	values[3]	249	1			T42	12		T198	16		T284	52
auto[0]	values[7]	values[4]	283	1			T11	18		T101	7		T207	9
auto[0]	values[7]	values[5]	207	1			T42	11		T285	16		T286	14
auto[0]	values[7]	values[6]	201	1			T6	9		T49	9		T283	10
auto[0]	values[7]	values[7]	349	1			T13	10		T101	11		T287	2
auto[1]	values[0]	values[0]	153	1			T101	7		T288	2		T263	8
auto[1]	values[0]	values[1]	306	1			T101	11		T197	8		T289	10
auto[1]	values[0]	values[2]	127	1			T12	9		T38	5		T206	8
auto[1]	values[0]	values[3]	197	1			T12	41		T243	14		T207	8
auto[1]	values[0]	values[4]	136	1			T6	5		T14	13		T41	2
auto[1]	values[0]	values[5]	263	1			T13	7		T236	6		T264	7
auto[1]	values[0]	values[6]	355	1			T6	13		T12	10		T38	11
auto[1]	values[0]	values[7]	345	1			T6	10		T13	20		T49	6
auto[1]	values[1]	values[0]	138	1			T196	5		T197	10		T290	10
auto[1]	values[1]	values[1]	158	1			T14	6		T267	8		T20	14
auto[1]	values[1]	values[2]	271	1			T207	5		T20	9		T281	11
auto[1]	values[1]	values[3]	187	1			T12	7		T198	9		T263	12
auto[1]	values[1]	values[4]	168	1			T222	62		T283	5		T251	14
auto[1]	values[1]	values[5]	232	1			T13	26		T185	7		T270	6
auto[1]	values[1]	values[6]	141	1			T185	9		T101	7		T211	32
auto[1]	values[1]	values[7]	217	1			T12	5		T13	22		T198	7
auto[1]	values[2]	values[0]	197	1			T14	11		T244	6		T205	6
auto[1]	values[2]	values[1]	211	1			T6	7		T291	8		T101	7
auto[1]	values[2]	values[2]	206	1			T50	8		T207	17		T222	5
auto[1]	values[2]	values[3]	327	1			T22	2		T185	68		T101	9
auto[1]	values[2]	values[4]	165	1			T12	10		T197	11		T236	8
auto[1]	values[2]	values[5]	153	1			T96	11		T196	6		T253	12
auto[1]	values[2]	values[6]	299	1			T12	34		T22	10		T13	28
auto[1]	values[2]	values[7]	301	1			T49	10		T101	4		T196	20
auto[1]	values[3]	values[0]	277	1			T12	16		T50	9		T185	57
auto[1]	values[3]	values[1]	239	1			T207	9		T211	10		T206	12
auto[1]	values[3]	values[2]	246	1			T38	8		T222	4		T292	9
auto[1]	values[3]	values[3]	204	1			T185	9		T101	7		T293	6
auto[1]	values[3]	values[4]	164	1			T14	8		T261	8		T42	8
auto[1]	values[3]	values[5]	193	1			T50	6		T198	6		T38	12
auto[1]	values[3]	values[6]	169	1			T6	8		T47	16		T12	13
auto[1]	values[3]	values[7]	235	1			T6	4		T101	14		T236	10
auto[1]	values[4]	values[0]	147	1			T12	11		T13	10		T101	5
auto[1]	values[4]	values[1]	252	1			T49	8		T243	11		T236	8
auto[1]	values[4]	values[2]	160	1			T12	7		T211	8		T230	11
auto[1]	values[4]	values[3]	225	1			T6	5		T198	4		T174	8
auto[1]	values[4]	values[4]	179	1			T208	11		T214	7		T174	6
auto[1]	values[4]	values[5]	93	1			T205	11		T263	10		T249	5
auto[1]	values[4]	values[6]	148	1			T49	3		T96	10		T206	13
auto[1]	values[4]	values[7]	227	1			T38	8		T242	124		T205	13
auto[1]	values[5]	values[0]	154	1			T42	10		T195	12		T211	4
auto[1]	values[5]	values[1]	164	1			T6	12		T49	8		T229	17
auto[1]	values[5]	values[2]	269	1			T25	18		T13	9		T49	10
auto[1]	values[5]	values[3]	258	1			T6	8		T36	11		T253	4
auto[1]	values[5]	values[4]	140	1			T196	5		T198	12		T38	11
auto[1]	values[5]	values[5]	276	1			T49	11		T294	14		T295	14
auto[1]	values[5]	values[6]	211	1			T198	7		T296	20		T206	4
auto[1]	values[5]	values[7]	182	1			T49	6		T198	10		T243	8
auto[1]	values[6]	values[0]	183	1			T22	7		T38	7		T197	9
auto[1]	values[6]	values[1]	228	1			T12	10		T42	8		T96	8
auto[1]	values[6]	values[2]	195	1			T6	5		T242	45		T20	8
auto[1]	values[6]	values[3]	175	1			T38	10		T205	7		T211	5
auto[1]	values[6]	values[4]	252	1			T13	7		T198	11		T230	12
auto[1]	values[6]	values[5]	169	1			T6	17		T50	11		T196	12
auto[1]	values[6]	values[6]	173	1			T207	8		T236	30		T281	19
auto[1]	values[6]	values[7]	99	1			T297	14		T298	6		T283	8
auto[1]	values[7]	values[0]	236	1			T207	57		T208	8		T229	10
auto[1]	values[7]	values[1]	169	1			T12	7		T22	22		T256	10
auto[1]	values[7]	values[2]	329	1			T195	13		T38	38		T253	8
auto[1]	values[7]	values[3]	213	1			T42	8		T198	4		T234	20
auto[1]	values[7]	values[4]	202	1			T101	13		T207	11		T208	9
auto[1]	values[7]	values[5]	142	1			T42	9		T149	5		T251	9
auto[1]	values[7]	values[6]	296	1			T6	11		T49	11		T252	10
auto[1]	values[7]	values[7]	184	1			T13	18		T103	18		T101	9