Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	431	1			T6	5		T48	2		T12	1
auto[ReadAddrCrossIntoMailbox]	307	1			T5	4		T6	1		T12	3
auto[ReadAddrCrossOutOfMailbox]	325	1			T6	3		T12	2		T22	2
auto[ReadAddrCrossAllMailbox]	244	1			T6	2		T12	2		T22	1
auto[ReadAddrOutsideMailbox]	3789	1			T5	8		T6	45		T8	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2477

1

T5

6

T6

15

T8

3

auto[1]

2619

1

T5

6

T6

41

T8

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	838	1			T5	8		T6	12		T9	4
read_ops[0x0b]	873	1			T5	4		T6	7		T8	2
read_ops[0x3b]	834	1			T6	7		T12	4		T22	1
read_ops[0x6b]	835	1			T6	10		T8	2		T12	5
read_ops[0xbb]	877	1			T6	8		T12	8		T22	3
read_ops[0xeb]	839	1			T6	12		T8	2		T47	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T13	2		T198	1		T38	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T6	2		T50	2		T96	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T185	1		T101	1		T236	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T6	1		T236	2		T20	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T13	1		T185	1		T242	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	34	1			T36	1		T49	1		T101	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	26	1			T6	1		T101	1		T38	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T270	1		T208	1		T211	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T5	4		T6	3		T9	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	329	1			T5	4		T6	5		T9	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T96	1		T38	1		T222	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T197	1		T264	1		T299	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T5	2		T13	1		T50	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T5	2		T13	1		T207	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T12	1		T196	1		T198	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T22	1		T14	1		T185	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T12	1		T196	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T13	1		T38	1		T207	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	324	1			T6	4		T8	1		T12	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	334	1			T6	3		T8	1		T12	7
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T13	1		T14	1		T49	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	48	1			T6	1		T185	1		T198	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T36	1		T13	1		T50	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T42	1		T282	2		T207	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T38	1		T222	2		T281	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T22	1		T101	1		T96	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T36	1		T13	1		T269	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T222	1		T269	1		T206	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T6	3		T12	2		T13	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	330	1			T6	3		T12	2		T13	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T42	1		T38	1		T282	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T12	1		T13	1		T101	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	35	1			T12	1		T270	1		T211	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T14	1		T101	1		T242	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T38	2		T242	1		T282	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T12	1		T282	1		T257	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	23	1			T13	2		T50	1		T42	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T197	1		T236	2		T283	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T6	1		T8	1		T22	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	323	1			T6	9		T8	1		T12	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T49	1		T243	1		T209	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T14	1		T50	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T12	1		T22	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T13	1		T185	1		T42	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T197	2		T207	2		T257	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T6	2		T185	1		T257	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T198	1		T243	1		T207	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T14	1		T185	1		T101	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	296	1			T6	1		T12	4		T22	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	345	1			T6	5		T12	3		T13	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T48	1		T49	1		T282	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T6	2		T48	1		T13	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T12	1		T270	1		T243	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T185	1		T101	1		T196	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T198	1		T197	1		T282	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T6	1		T282	1		T283	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T6	1		T12	1		T22	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T50	1		T101	2		T207	3
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	316	1			T6	1		T8	1		T47	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	322	1			T6	7		T8	1		T47	1