Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4052	1			T6	60		T9	12		T12	114
values[1]	3696	1			T6	80		T11	18		T47	16
values[2]	4367	1			T10	57		T48	2		T12	28
values[3]	4525	1			T6	20		T12	112		T22	23
values[4]	2979	1			T3	2		T13	32		T41	2
values[5]	4117	1			T8	12		T12	41		T22	45
values[6]	3689	1			T5	12		T6	40		T51	2
values[7]	4221	1			T6	60		T12	21		T22	27

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4635	1			T12	26		T22	47		T36	20
values[1]	3785	1			T3	2		T6	20		T12	62
values[2]	4636	1			T6	60		T48	2		T219	4
values[3]	4008	1			T6	40		T12	61		T40	71
values[4]	3101	1			T9	12		T11	18		T12	90
values[5]	3698	1			T6	100		T8	12		T51	2
values[6]	3791	1			T5	12		T6	40		T47	16
values[7]	3992	1			T10	57		T12	47		T22	25

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30794

1

T3

2

T5

12

T6

249

auto[1]

852

1

T6

11

T47

6

T12

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	486	1			T12	26		T50	27		T42	17
auto[0]	values[0]	values[1]	294	1			T6	20		T12	18		T50	21
auto[0]	values[0]	values[2]	701	1			T6	39		T49	18		T205	21
auto[0]	values[0]	values[3]	787	1			T12	20		T102	4		T285	16
auto[0]	values[0]	values[4]	567	1			T9	12		T12	21		T184	72
auto[0]	values[0]	values[5]	191	1			T195	19		T296	20		T300	27
auto[0]	values[0]	values[6]	515	1			T49	18		T96	20		T38	23
auto[0]	values[0]	values[7]	402	1			T12	27		T49	19		T205	23
auto[0]	values[1]	values[0]	456	1			T99	20		T198	19		T294	12
auto[0]	values[1]	values[1]	343	1			T23	18		T49	19		T270	20
auto[0]	values[1]	values[2]	629	1			T50	20		T101	57		T197	19
auto[0]	values[1]	values[3]	354	1			T6	17		T12	20		T13	20
auto[0]	values[1]	values[4]	297	1			T11	18		T104	6		T20	20
auto[0]	values[1]	values[5]	525	1			T6	37		T50	25		T196	20
auto[0]	values[1]	values[6]	517	1			T6	20		T47	10		T185	20
auto[0]	values[1]	values[7]	462	1			T196	38		T207	66		T211	21
auto[0]	values[2]	values[0]	472	1			T13	20		T278	10		T283	18
auto[0]	values[2]	values[1]	544	1			T14	22		T255	12		T42	19
auto[0]	values[2]	values[2]	707	1			T48	2		T219	4		T103	18
auto[0]	values[2]	values[3]	365	1			T14	42		T207	38		T301	10
auto[0]	values[2]	values[4]	353	1			T12	27		T198	19		T38	24
auto[0]	values[2]	values[5]	463	1			T101	40		T38	22		T302	18
auto[0]	values[2]	values[6]	591	1			T96	21		T206	20		T17	58
auto[0]	values[2]	values[7]	763	1			T10	57		T49	20		T243	20
auto[0]	values[3]	values[0]	367	1			T196	18		T290	20		T281	28
auto[0]	values[3]	values[1]	778	1			T12	42		T42	19		T303	8
auto[0]	values[3]	values[2]	489	1			T185	20		T38	43		T17	49
auto[0]	values[3]	values[3]	604	1			T13	22		T261	8		T244	6
auto[0]	values[3]	values[4]	301	1			T24	4		T243	19		T197	20
auto[0]	values[3]	values[5]	602	1			T6	20		T22	21		T13	32
auto[0]	values[3]	values[6]	507	1			T12	50		T69	29		T101	19
auto[0]	values[3]	values[7]	759	1			T12	20		T263	20		T206	61
auto[0]	values[4]	values[0]	876	1			T13	28		T297	12		T222	45
auto[0]	values[4]	values[1]	294	1			T3	2		T196	19		T304	2
auto[0]	values[4]	values[2]	373	1			T196	20		T252	10		T206	48
auto[0]	values[4]	values[3]	256	1			T196	20		T243	32		T21	19
auto[0]	values[4]	values[4]	189	1			T305	14		T306	6		T269	10
auto[0]	values[4]	values[5]	372	1			T243	20		T276	6		T267	20
auto[0]	values[4]	values[6]	245	1			T307	2		T266	2		T239	8
auto[0]	values[4]	values[7]	284	1			T41	2		T198	20		T197	19
auto[0]	values[5]	values[0]	847	1			T22	18		T308	271		T253	151
auto[0]	values[5]	values[1]	424	1			T197	20		T309	2		T310	2
auto[0]	values[5]	values[2]	503	1			T13	28		T195	20		T207	19
auto[0]	values[5]	values[3]	496	1			T198	40		T311	4		T206	24
auto[0]	values[5]	values[4]	477	1			T12	41		T312	16		T313	21
auto[0]	values[5]	values[5]	420	1			T8	12		T246	2		T49	19
auto[0]	values[5]	values[6]	366	1			T256	10		T49	20		T314	45
auto[0]	values[5]	values[7]	498	1			T22	25		T185	80		T208	27
auto[0]	values[6]	values[0]	419	1			T14	17		T101	19		T211	62
auto[0]	values[6]	values[1]	487	1			T315	4		T242	30		T316	4
auto[0]	values[6]	values[2]	445	1			T13	72		T198	20		T230	18
auto[0]	values[6]	values[3]	525	1			T6	20		T185	64		T96	20
auto[0]	values[6]	values[4]	540	1			T210	10		T317	6		T242	57
auto[0]	values[6]	values[5]	405	1			T51	2		T208	41		T235	16
auto[0]	values[6]	values[6]	373	1			T5	12		T6	20		T50	20
auto[0]	values[6]	values[7]	382	1			T25	14		T42	20		T198	19
auto[0]	values[7]	values[0]	591	1			T22	26		T36	20		T192	2
auto[0]	values[7]	values[1]	528	1			T13	19		T271	14		T49	20
auto[0]	values[7]	values[2]	672	1			T6	20		T13	44		T101	20
auto[0]	values[7]	values[3]	518	1			T12	21		T40	71		T42	20
auto[0]	values[7]	values[4]	295	1			T291	8		T101	17		T253	19
auto[0]	values[7]	values[5]	608	1			T6	36		T243	20		T38	44
auto[0]	values[7]	values[6]	557	1			T170	8		T42	17		T205	21
auto[0]	values[7]	values[7]	338	1			T211	20		T318	12		T264	19
auto[1]	values[0]	values[0]	13	1			T50	3		T42	3		T198	1
auto[1]	values[0]	values[1]	8	1			T12	2		T50	2		T38	3
auto[1]	values[0]	values[2]	13	1			T6	1		T49	2		T205	2
auto[1]	values[0]	values[3]	20	1			T38	3		T283	1		T149	1
auto[1]	values[0]	values[4]	16	1			T206	1		T251	2		T319	3
auto[1]	values[0]	values[5]	11	1			T195	1		T300	1		T177	1
auto[1]	values[0]	values[6]	17	1			T49	2		T38	1		T205	2
auto[1]	values[0]	values[7]	11	1			T49	1		T320	2		T293	1
auto[1]	values[1]	values[0]	25	1			T198	1		T294	2		T150	4
auto[1]	values[1]	values[1]	5	1			T49	1		T231	2		T321	1
auto[1]	values[1]	values[2]	13	1			T101	3		T197	1		T207	1
auto[1]	values[1]	values[3]	15	1			T6	3		T243	1		T322	1
auto[1]	values[1]	values[4]	7	1			T323	1		T324	2		T216	1
auto[1]	values[1]	values[5]	17	1			T6	3		T50	2		T320	4
auto[1]	values[1]	values[6]	20	1			T47	6		T300	4		T325	1
auto[1]	values[1]	values[7]	11	1			T196	2		T149	1		T326	4
auto[1]	values[2]	values[0]	13	1			T283	2		T174	1		T176	2
auto[1]	values[2]	values[1]	9	1			T42	1		T197	3		T208	1
auto[1]	values[2]	values[2]	16	1			T49	2		T198	1		T242	1
auto[1]	values[2]	values[3]	10	1			T14	1		T207	1		T211	1
auto[1]	values[2]	values[4]	14	1			T12	1		T198	1		T38	3
auto[1]	values[2]	values[5]	14	1			T38	2		T222	2		T326	2
auto[1]	values[2]	values[6]	20	1			T281	2		T327	7		T328	1
auto[1]	values[2]	values[7]	13	1			T206	3		T236	3		T213	2
auto[1]	values[3]	values[0]	8	1			T196	2		T149	1		T329	1
auto[1]	values[3]	values[1]	14	1			T42	1		T222	1		T229	1
auto[1]	values[3]	values[2]	14	1			T38	3		T17	2		T149	2
auto[1]	values[3]	values[3]	19	1			T101	3		T243	2		T249	1
auto[1]	values[3]	values[4]	9	1			T243	1		T250	3		T61	2
auto[1]	values[3]	values[5]	13	1			T22	2		T13	1		T17	1
auto[1]	values[3]	values[6]	14	1			T101	1		T222	1		T330	1
auto[1]	values[3]	values[7]	27	1			T206	2		T236	2		T199	2
auto[1]	values[4]	values[0]	28	1			T13	4		T297	2		T17	2
auto[1]	values[4]	values[1]	10	1			T196	1		T231	1		T331	2
auto[1]	values[4]	values[2]	18	1			T206	1		T17	1		T283	1
auto[1]	values[4]	values[3]	6	1			T21	1		T227	3		T332	2
auto[1]	values[4]	values[4]	4	1			T283	1		T149	1		T250	1
auto[1]	values[4]	values[5]	4	1			T237	3		T333	1		-	-
auto[1]	values[4]	values[6]	6	1			T334	1		T335	3		T258	2
auto[1]	values[4]	values[7]	14	1			T197	1		T234	6		T320	1
auto[1]	values[5]	values[0]	10	1			T22	2		T334	2		T313	3
auto[1]	values[5]	values[1]	18	1			T20	1		T293	1		T199	2
auto[1]	values[5]	values[2]	11	1			T207	1		T199	1		T333	2
auto[1]	values[5]	values[3]	10	1			T206	1		T199	1		T238	3
auto[1]	values[5]	values[4]	6	1			T313	1		T57	3		T336	1
auto[1]	values[5]	values[5]	12	1			T49	1		T197	1		T205	1
auto[1]	values[5]	values[6]	10	1			T206	1		T264	2		T337	4
auto[1]	values[5]	values[7]	9	1			T185	2		T206	1		T236	1
auto[1]	values[6]	values[0]	10	1			T14	3		T101	1		T211	1
auto[1]	values[6]	values[1]	8	1			T242	1		T338	2		T217	3
auto[1]	values[6]	values[2]	15	1			T13	2		T230	2		T249	1
auto[1]	values[6]	values[3]	18	1			T185	1		T96	2		T20	2
auto[1]	values[6]	values[4]	16	1			T293	1		T178	2		T179	3
auto[1]	values[6]	values[5]	17	1			T208	3		T235	4		T229	2
auto[1]	values[6]	values[6]	17	1			T250	2		T330	5		T238	1
auto[1]	values[6]	values[7]	12	1			T25	4		T198	1		T230	1
auto[1]	values[7]	values[0]	14	1			T22	1		T298	2		T230	1
auto[1]	values[7]	values[1]	21	1			T13	1		T221	3		T149	2
auto[1]	values[7]	values[2]	17	1			T13	3		T198	1		T20	1
auto[1]	values[7]	values[3]	5	1			T230	2		T333	1		T339	2
auto[1]	values[7]	values[4]	10	1			T101	3		T253	1		T229	1
auto[1]	values[7]	values[5]	24	1			T6	4		T38	2		T222	3
auto[1]	values[7]	values[6]	16	1			T42	3		T205	1		T208	2
auto[1]	values[7]	values[7]	7	1			T264	1		T340	1		T57	2