SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_flip_position | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_opcode | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 113 | 1 | T44 | 3 | T45 | 8 | T165 | 2 | ||||
auto[1] | 34 | 1 | T44 | 1 | T45 | 2 | T166 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 6 | 0 | 6 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
read_ops[0x03] | 18 | 1 | T45 | 4 | T341 | 4 | T342 | 2 | ||||
read_ops[0x0b] | 39 | 1 | T45 | 2 | T165 | 2 | T168 | 4 | ||||
read_ops[0x3b] | 10 | 1 | T168 | 2 | T343 | 2 | T344 | 4 | ||||
read_ops[0x6b] | 28 | 1 | T44 | 4 | T166 | 8 | T345 | 2 | ||||
read_ops[0xbb] | 23 | 1 | T346 | 1 | T347 | 4 | T348 | 4 | ||||
read_ops[0xeb] | 29 | 1 | T45 | 4 | T341 | 1 | T349 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |