Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	854	1			T12	18		T13	20		T14	7
all_values[1]	854	1			T12	18		T13	20		T14	7
all_values[2]	854	1			T12	18		T13	20		T14	7
all_values[3]	854	1			T12	18		T13	20		T14	7
all_values[4]	854	1			T12	18		T13	20		T14	7
all_values[5]	854	1			T12	18		T13	20		T14	7
all_values[6]	854	1			T12	18		T13	20		T14	7
all_values[7]	854	1			T12	18		T13	20		T14	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3545

1

T12

84

T13

72

T14

26

auto[1]

3287

1

T12

60

T13

88

T14

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2726

1

T12

59

T13

68

T14

27

auto[1]

4106

1

T12

85

T13

92

T14

29

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3906

1

T12

85

T13

88

T14

32

auto[1]

2926

1

T12

59

T13

72

T14

24

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	185	1			T12	3		T13	3		T15	4
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T12	3		T13	2		T16	5
all_values[0]	auto[0]	auto[1]	auto[0]	145	1			T12	5		T13	2		T14	1
all_values[0]	auto[0]	auto[1]	auto[1]	74	1			T13	3		T14	1		T15	1
all_values[0]	auto[1]	auto[0]	auto[1]	205	1			T12	5		T13	3		T15	3
all_values[0]	auto[1]	auto[1]	auto[1]	170	1			T12	2		T13	7		T14	5
all_values[1]	auto[0]	auto[0]	auto[0]	155	1			T12	4		T14	1		T15	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T15	2		T39	1		T16	3
all_values[1]	auto[0]	auto[1]	auto[0]	157	1			T12	5		T13	10		T14	2
all_values[1]	auto[0]	auto[1]	auto[1]	96	1			T12	4		T13	1		T14	1
all_values[1]	auto[1]	auto[0]	auto[1]	195	1			T12	2		T13	5		T14	2
all_values[1]	auto[1]	auto[1]	auto[1]	174	1			T12	3		T13	4		T14	1
all_values[2]	auto[0]	auto[0]	auto[0]	176	1			T12	3		T13	7		T14	3
all_values[2]	auto[0]	auto[0]	auto[1]	69	1			T12	3		T15	1		T39	1
all_values[2]	auto[0]	auto[1]	auto[0]	148	1			T13	7		T14	1		T15	5
all_values[2]	auto[0]	auto[1]	auto[1]	99	1			T12	4		T14	1		T39	2
all_values[2]	auto[1]	auto[0]	auto[1]	184	1			T12	6		T13	2		T14	1
all_values[2]	auto[1]	auto[1]	auto[1]	178	1			T12	2		T13	4		T14	1
all_values[3]	auto[0]	auto[0]	auto[0]	184	1			T12	4		T13	3		T14	3
all_values[3]	auto[0]	auto[0]	auto[1]	80	1			T12	1		T13	1		T15	1
all_values[3]	auto[0]	auto[1]	auto[0]	148	1			T12	2		T13	7		T14	3
all_values[3]	auto[0]	auto[1]	auto[1]	90	1			T15	2		T16	7		T17	3
all_values[3]	auto[1]	auto[0]	auto[1]	199	1			T12	11		T13	3		T15	3
all_values[3]	auto[1]	auto[1]	auto[1]	153	1			T13	6		T14	1		T15	4
all_values[4]	auto[0]	auto[0]	auto[0]	177	1			T12	4		T13	2		T15	4
all_values[4]	auto[0]	auto[0]	auto[1]	76	1			T12	1		T13	3		T14	1
all_values[4]	auto[0]	auto[1]	auto[0]	144	1			T12	4		T13	2		T14	1
all_values[4]	auto[0]	auto[1]	auto[1]	100	1			T12	1		T13	3		T15	2
all_values[4]	auto[1]	auto[0]	auto[1]	164	1			T12	4		T13	5		T14	3
all_values[4]	auto[1]	auto[1]	auto[1]	193	1			T12	4		T13	5		T14	2
all_values[5]	auto[0]	auto[0]	auto[0]	250	1			T12	8		T13	4		T14	3
all_values[5]	auto[0]	auto[1]	auto[0]	227	1			T12	4		T13	6		T15	2
all_values[5]	auto[1]	auto[0]	auto[1]	196	1			T12	3		T13	6		T14	3
all_values[5]	auto[1]	auto[1]	auto[1]	181	1			T12	3		T13	4		T14	1
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T12	2		T13	3		T14	1
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T12	2		T13	1		T16	3
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T12	5		T13	5		T14	5
all_values[6]	auto[0]	auto[1]	auto[1]	94	1			T12	3		T13	1		T15	2
all_values[6]	auto[1]	auto[0]	auto[1]	173	1			T12	3		T13	5		T15	1
all_values[6]	auto[1]	auto[1]	auto[1]	187	1			T12	3		T13	5		T14	1
all_values[7]	auto[0]	auto[0]	auto[0]	178	1			T12	4		T13	4		T14	2
all_values[7]	auto[0]	auto[0]	auto[1]	95	1			T12	2		T13	4		T14	1
all_values[7]	auto[0]	auto[1]	auto[0]	128	1			T12	2		T13	3		T14	1
all_values[7]	auto[0]	auto[1]	auto[1]	79	1			T12	2		T13	1		T15	2
all_values[7]	auto[1]	auto[0]	auto[1]	206	1			T12	6		T13	6		T14	2
all_values[7]	auto[1]	auto[1]	auto[1]	168	1			T12	2		T13	2		T14	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal