Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1778

1

T4

1

T31

1

T32

2

auto[1]

1886

1

T4

10

T32

2

T12

17

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2016

1

T31

1

T12

28

T22

5

auto[1]

1648

1

T4

11

T32

4

T27

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2908

1

T4

11

T32

4

T12

21

auto[1]

756

1

T31

1

T12

7

T22

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	769	1			T4	2		T31	1		T12	12
valid[1]	745	1			T4	1		T12	4		T22	1
valid[2]	710	1			T4	1		T12	5		T22	1
valid[3]	690	1			T4	5		T32	3		T12	4
valid[4]	750	1			T4	2		T32	1		T12	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	120	1			T12	4		T36	1		T46	1
auto[0]	auto[0]	valid[0]	auto[1]	167	1			T35	3		T13	2		T98	1
auto[0]	auto[0]	valid[1]	auto[0]	139	1			T12	1		T14	1		T46	1
auto[0]	auto[0]	valid[1]	auto[1]	175	1			T34	2		T35	2		T13	2
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T12	2		T22	1		T36	1
auto[0]	auto[0]	valid[2]	auto[1]	165	1			T4	1		T34	1		T98	4
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T12	1		T13	2		T50	1
auto[0]	auto[0]	valid[3]	auto[1]	135	1			T32	2		T35	1		T13	2
auto[0]	auto[0]	valid[4]	auto[0]	113	1			T12	1		T22	1		T36	1
auto[0]	auto[0]	valid[4]	auto[1]	159	1			T35	1		T13	2		T97	1
auto[0]	auto[1]	valid[0]	auto[0]	137	1			T12	5		T13	2		T50	3
auto[0]	auto[1]	valid[0]	auto[1]	181	1			T4	2		T34	4		T35	6
auto[0]	auto[1]	valid[1]	auto[0]	134	1			T12	1		T22	1		T36	3
auto[0]	auto[1]	valid[1]	auto[1]	164	1			T4	1		T35	2		T13	1
auto[0]	auto[1]	valid[2]	auto[0]	114	1			T12	3		T36	1		T14	1
auto[0]	auto[1]	valid[2]	auto[1]	162	1			T27	1		T34	1		T35	1
auto[0]	auto[1]	valid[3]	auto[0]	132	1			T12	2		T22	1		T36	2
auto[0]	auto[1]	valid[3]	auto[1]	164	1			T4	5		T32	1		T27	1
auto[0]	auto[1]	valid[4]	auto[0]	127	1			T12	1		T36	1		T46	2
auto[0]	auto[1]	valid[4]	auto[1]	176	1			T4	2		T32	1		T34	2
auto[1]	auto[0]	valid[0]	auto[0]	74	1			T31	1		T12	2		T22	1
auto[1]	auto[0]	valid[1]	auto[0]	68	1			T36	1		T46	1		T50	1
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T15	1		T188	1		T96	1
auto[1]	auto[0]	valid[3]	auto[0]	66	1			T36	1		T14	1		T96	1
auto[1]	auto[0]	valid[4]	auto[0]	82	1			T33	1		T37	1		T188	1
auto[1]	auto[1]	valid[0]	auto[0]	90	1			T12	1		T46	1		T96	1
auto[1]	auto[1]	valid[1]	auto[0]	65	1			T12	2		T36	1		T13	2
auto[1]	auto[1]	valid[2]	auto[0]	71	1			T46	1		T188	2		T187	2
auto[1]	auto[1]	valid[3]	auto[0]	76	1			T12	1		T15	1		T38	2
auto[1]	auto[1]	valid[4]	auto[0]	93	1			T12	1		T14	1		T50	3

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal