Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50011

1

T31

8

T12

484

T22

270

auto[1]

16989

1

T4

172

T32

4

T27

2

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48792

1

T4

172

T31

2

T32

4

auto[1]

18208

1

T31

6

T12

176

T22

96

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34610	1			T4	77		T31	6		T32	4
others[1]	5609	1			T4	15		T12	39		T22	17
others[2]	5614	1			T4	14		T12	43		T22	19
others[3]	6449	1			T4	25		T12	51		T22	38
interest[1]	3654	1			T4	13		T31	2		T12	29
interest[4]	22584	1			T4	45		T31	3		T32	4
interest[64]	11064	1			T4	28		T12	86		T22	40

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16374	1			T31	1		T12	155		T22	88
auto[0]	auto[0]	others[1]	2716	1			T12	24		T22	13		T36	11
auto[0]	auto[0]	others[2]	2661	1			T12	28		T22	12		T36	13
auto[0]	auto[0]	others[3]	3025	1			T12	34		T22	22		T36	16
auto[0]	auto[0]	interest[1]	1695	1			T31	1		T12	19		T22	12
auto[0]	auto[0]	interest[4]	10660	1			T31	1		T12	112		T22	64
auto[0]	auto[0]	interest[64]	5332	1			T12	48		T22	27		T33	1
auto[0]	auto[1]	others[0]	8903	1			T4	77		T32	4		T27	2
auto[0]	auto[1]	others[1]	1415	1			T4	15		T35	16		T13	15
auto[0]	auto[1]	others[2]	1438	1			T4	14		T35	19		T13	15
auto[0]	auto[1]	others[3]	1590	1			T4	25		T35	23		T13	10
auto[0]	auto[1]	interest[1]	944	1			T4	13		T35	16		T13	6
auto[0]	auto[1]	interest[4]	5848	1			T4	45		T32	4		T27	2
auto[0]	auto[1]	interest[64]	2699	1			T4	28		T35	38		T13	8
auto[1]	auto[0]	others[0]	9333	1			T31	5		T12	81		T22	54
auto[1]	auto[0]	others[1]	1478	1			T12	15		T22	4		T33	1
auto[1]	auto[0]	others[2]	1515	1			T12	15		T22	7		T33	1
auto[1]	auto[0]	others[3]	1834	1			T12	17		T22	16		T33	1
auto[1]	auto[0]	interest[1]	1015	1			T31	1		T12	10		T22	2
auto[1]	auto[0]	interest[4]	6076	1			T31	2		T12	56		T22	42
auto[1]	auto[0]	interest[64]	3033	1			T12	38		T22	13		T36	14

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal