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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1033 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1363377630 Jul 21 06:24:24 PM PDT 24 Jul 21 06:24:26 PM PDT 24 13658760 ps
T182 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.133919976 Jul 21 06:24:26 PM PDT 24 Jul 21 06:24:35 PM PDT 24 3756253076 ps
T118 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2239579978 Jul 21 06:24:26 PM PDT 24 Jul 21 06:24:32 PM PDT 24 466802197 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.298143851 Jul 21 06:24:18 PM PDT 24 Jul 21 06:24:20 PM PDT 24 25690161 ps
T92 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3635134748 Jul 21 06:24:13 PM PDT 24 Jul 21 06:24:16 PM PDT 24 21438865 ps
T1035 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.66809011 Jul 21 06:24:05 PM PDT 24 Jul 21 06:24:09 PM PDT 24 144887528 ps
T110 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1667823551 Jul 21 06:24:16 PM PDT 24 Jul 21 06:24:21 PM PDT 24 160003278 ps
T1036 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3380259761 Jul 21 06:24:05 PM PDT 24 Jul 21 06:24:10 PM PDT 24 31625408 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2355066150 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:27 PM PDT 24 2419776862 ps
T115 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.491678432 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:11 PM PDT 24 646261606 ps
T136 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1665959023 Jul 21 06:24:14 PM PDT 24 Jul 21 06:24:23 PM PDT 24 142340117 ps
T1037 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3877902418 Jul 21 06:24:31 PM PDT 24 Jul 21 06:24:33 PM PDT 24 33952499 ps
T1038 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.733427508 Jul 21 06:24:09 PM PDT 24 Jul 21 06:24:13 PM PDT 24 87296183 ps
T111 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1298116636 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:28 PM PDT 24 212913643 ps
T1039 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2149464334 Jul 21 06:24:09 PM PDT 24 Jul 21 06:24:11 PM PDT 24 38180209 ps
T1040 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4281730288 Jul 21 06:24:32 PM PDT 24 Jul 21 06:24:34 PM PDT 24 83926613 ps
T194 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1019509795 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:25 PM PDT 24 817983619 ps
T138 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2136441871 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:08 PM PDT 24 34103152 ps
T180 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1128922150 Jul 21 06:24:19 PM PDT 24 Jul 21 06:24:39 PM PDT 24 3988968674 ps
T1041 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2035034038 Jul 21 06:24:05 PM PDT 24 Jul 21 06:24:09 PM PDT 24 34113678 ps
T114 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.637366629 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:14 PM PDT 24 236614599 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3336530323 Jul 21 06:24:13 PM PDT 24 Jul 21 06:24:18 PM PDT 24 409124764 ps
T1043 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3910868564 Jul 21 06:24:23 PM PDT 24 Jul 21 06:24:27 PM PDT 24 45676045 ps
T112 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4078993366 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:17 PM PDT 24 98834474 ps
T1044 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2202168795 Jul 21 06:24:22 PM PDT 24 Jul 21 06:24:23 PM PDT 24 14146948 ps
T1045 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1107431850 Jul 21 06:24:32 PM PDT 24 Jul 21 06:24:34 PM PDT 24 11531720 ps
T1046 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2647944488 Jul 21 06:24:23 PM PDT 24 Jul 21 06:24:24 PM PDT 24 123387792 ps
T1047 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1929677622 Jul 21 06:24:16 PM PDT 24 Jul 21 06:24:20 PM PDT 24 108648802 ps
T1048 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3310144977 Jul 21 06:24:36 PM PDT 24 Jul 21 06:24:37 PM PDT 24 13986215 ps
T171 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1719133791 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:34 PM PDT 24 1455507269 ps
T137 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2143242764 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:47 PM PDT 24 2368544343 ps
T1049 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2154773984 Jul 21 06:24:18 PM PDT 24 Jul 21 06:24:21 PM PDT 24 83506471 ps
T113 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2451039511 Jul 21 06:24:15 PM PDT 24 Jul 21 06:24:19 PM PDT 24 148933490 ps
T172 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1620782524 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:18 PM PDT 24 1107561119 ps
T173 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.826554884 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:28 PM PDT 24 3163473489 ps
T181 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1704501608 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:41 PM PDT 24 975370127 ps
T119 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3277456286 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:14 PM PDT 24 55633591 ps
T1050 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3606620562 Jul 21 06:24:26 PM PDT 24 Jul 21 06:24:28 PM PDT 24 18788693 ps
T183 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3322015358 Jul 21 06:24:09 PM PDT 24 Jul 21 06:24:24 PM PDT 24 2315057059 ps
T93 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1567241552 Jul 21 06:24:03 PM PDT 24 Jul 21 06:24:07 PM PDT 24 171628795 ps
T116 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1218799319 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:30 PM PDT 24 171208859 ps
T1051 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2826969463 Jul 21 06:24:33 PM PDT 24 Jul 21 06:24:34 PM PDT 24 34783898 ps
T1052 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.414180457 Jul 21 06:24:24 PM PDT 24 Jul 21 06:24:28 PM PDT 24 65159522 ps
T1053 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3331726439 Jul 21 06:24:18 PM PDT 24 Jul 21 06:24:20 PM PDT 24 16999237 ps
T1054 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.474919075 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:14 PM PDT 24 58819177 ps
T120 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3522958931 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:11 PM PDT 24 134797477 ps
T121 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2607070909 Jul 21 06:24:24 PM PDT 24 Jul 21 06:24:27 PM PDT 24 432494383 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2022928388 Jul 21 06:24:03 PM PDT 24 Jul 21 06:24:07 PM PDT 24 14320362 ps
T1056 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1158675147 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:19 PM PDT 24 35779664 ps
T139 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4041087906 Jul 21 06:24:13 PM PDT 24 Jul 21 06:24:18 PM PDT 24 108850363 ps
T1057 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3902447689 Jul 21 06:24:09 PM PDT 24 Jul 21 06:24:13 PM PDT 24 118293792 ps
T1058 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1096526247 Jul 21 06:24:18 PM PDT 24 Jul 21 06:24:23 PM PDT 24 104035620 ps
T1059 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3052025407 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:24 PM PDT 24 752166297 ps
T1060 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1442787949 Jul 21 06:24:33 PM PDT 24 Jul 21 06:24:35 PM PDT 24 14342255 ps
T1061 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3741024825 Jul 21 06:24:06 PM PDT 24 Jul 21 06:24:22 PM PDT 24 417165754 ps
T1062 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.738539601 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:29 PM PDT 24 85840672 ps
T1063 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.624913911 Jul 21 06:24:33 PM PDT 24 Jul 21 06:24:35 PM PDT 24 16174376 ps
T1064 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4234616006 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:27 PM PDT 24 19190759 ps
T1065 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2595628679 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:21 PM PDT 24 249679642 ps
T1066 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1811000448 Jul 21 06:24:27 PM PDT 24 Jul 21 06:24:29 PM PDT 24 24574353 ps
T1067 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.855553091 Jul 21 06:24:31 PM PDT 24 Jul 21 06:24:33 PM PDT 24 63792989 ps
T94 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3794873077 Jul 21 06:24:06 PM PDT 24 Jul 21 06:24:10 PM PDT 24 173369424 ps
T1068 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.750800928 Jul 21 06:24:31 PM PDT 24 Jul 21 06:24:33 PM PDT 24 21350485 ps
T1069 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.193995969 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:19 PM PDT 24 156900226 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2666131433 Jul 21 06:24:24 PM PDT 24 Jul 21 06:24:32 PM PDT 24 443304937 ps
T140 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2163898908 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:16 PM PDT 24 70936236 ps
T141 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4083641320 Jul 21 06:24:09 PM PDT 24 Jul 21 06:24:12 PM PDT 24 421696205 ps
T1071 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3985134092 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:27 PM PDT 24 113269226 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2429563000 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:11 PM PDT 24 138847998 ps
T193 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3605976208 Jul 21 06:24:18 PM PDT 24 Jul 21 06:24:23 PM PDT 24 118751742 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2519594237 Jul 21 06:23:56 PM PDT 24 Jul 21 06:24:15 PM PDT 24 622020332 ps
T1074 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3544805847 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:15 PM PDT 24 25957211 ps
T1075 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.460862010 Jul 21 06:24:40 PM PDT 24 Jul 21 06:24:41 PM PDT 24 16163551 ps
T1076 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3660709979 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:20 PM PDT 24 52322661 ps
T1077 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2264966256 Jul 21 06:24:16 PM PDT 24 Jul 21 06:24:20 PM PDT 24 478553435 ps
T1078 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.482249477 Jul 21 06:24:21 PM PDT 24 Jul 21 06:24:26 PM PDT 24 727600012 ps
T1079 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1448192254 Jul 21 06:24:22 PM PDT 24 Jul 21 06:24:23 PM PDT 24 12472887 ps
T142 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.267956977 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:13 PM PDT 24 74220529 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.166298062 Jul 21 06:23:58 PM PDT 24 Jul 21 06:24:04 PM PDT 24 26440897 ps
T1081 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3828537269 Jul 21 06:24:23 PM PDT 24 Jul 21 06:24:24 PM PDT 24 34981178 ps
T1082 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3682184980 Jul 21 06:24:15 PM PDT 24 Jul 21 06:24:19 PM PDT 24 45915442 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2183897337 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:36 PM PDT 24 4984242168 ps
T1084 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2891698148 Jul 21 06:24:06 PM PDT 24 Jul 21 06:24:44 PM PDT 24 3671675725 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3210450108 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:14 PM PDT 24 94206627 ps
T1086 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1834507082 Jul 21 06:24:27 PM PDT 24 Jul 21 06:24:29 PM PDT 24 11520643 ps
T95 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3620699304 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:08 PM PDT 24 34440734 ps
T1087 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2366311286 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:15 PM PDT 24 11481161 ps
T1088 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4265814999 Jul 21 06:24:06 PM PDT 24 Jul 21 06:24:12 PM PDT 24 113147337 ps
T1089 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3938992004 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:27 PM PDT 24 100896372 ps
T1090 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3563337124 Jul 21 06:24:24 PM PDT 24 Jul 21 06:24:25 PM PDT 24 41303902 ps
T1091 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2305043906 Jul 21 06:24:23 PM PDT 24 Jul 21 06:24:25 PM PDT 24 159767004 ps
T1092 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3214321560 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:21 PM PDT 24 31169965 ps
T1093 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1240891040 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:16 PM PDT 24 15599776 ps
T1094 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3270778287 Jul 21 06:24:31 PM PDT 24 Jul 21 06:24:33 PM PDT 24 44806765 ps
T1095 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2931047490 Jul 21 06:24:26 PM PDT 24 Jul 21 06:24:34 PM PDT 24 142258250 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3636152626 Jul 21 06:24:00 PM PDT 24 Jul 21 06:24:05 PM PDT 24 75824802 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3220316986 Jul 21 06:24:13 PM PDT 24 Jul 21 06:24:17 PM PDT 24 27241567 ps
T1098 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1556521060 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:15 PM PDT 24 27115467 ps
T1099 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.464980259 Jul 21 06:24:10 PM PDT 24 Jul 21 06:24:12 PM PDT 24 12639665 ps
T1100 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.390788117 Jul 21 06:24:39 PM PDT 24 Jul 21 06:24:41 PM PDT 24 27403425 ps
T1101 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3174659721 Jul 21 06:24:03 PM PDT 24 Jul 21 06:24:07 PM PDT 24 14877209 ps
T1102 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4150591844 Jul 21 06:24:37 PM PDT 24 Jul 21 06:24:39 PM PDT 24 13303693 ps
T1103 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2721491562 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:08 PM PDT 24 61085388 ps
T1104 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.682618848 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:16 PM PDT 24 106192903 ps
T1105 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.945070233 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:18 PM PDT 24 301276209 ps
T1106 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3557928100 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:16 PM PDT 24 30249705 ps
T1107 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2423820836 Jul 21 06:24:15 PM PDT 24 Jul 21 06:24:31 PM PDT 24 2513850269 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.958493958 Jul 21 06:24:13 PM PDT 24 Jul 21 06:24:17 PM PDT 24 39066683 ps
T1109 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1637968446 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:14 PM PDT 24 55451969 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1639849609 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:15 PM PDT 24 42391631 ps
T1111 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3906955786 Jul 21 06:24:11 PM PDT 24 Jul 21 06:24:18 PM PDT 24 52246939 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.965008888 Jul 21 06:24:16 PM PDT 24 Jul 21 06:24:20 PM PDT 24 215518172 ps
T1113 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3680544762 Jul 21 06:24:12 PM PDT 24 Jul 21 06:24:19 PM PDT 24 257205014 ps
T1114 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1858306792 Jul 21 06:24:02 PM PDT 24 Jul 21 06:24:06 PM PDT 24 19523942 ps
T1115 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.998778395 Jul 21 06:24:06 PM PDT 24 Jul 21 06:24:12 PM PDT 24 232376499 ps
T1116 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3215445955 Jul 21 06:24:09 PM PDT 24 Jul 21 06:24:12 PM PDT 24 57179937 ps
T1117 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1750452670 Jul 21 06:24:21 PM PDT 24 Jul 21 06:24:23 PM PDT 24 286701878 ps
T1118 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3364682714 Jul 21 06:24:02 PM PDT 24 Jul 21 06:24:14 PM PDT 24 608220704 ps
T1119 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.662876919 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:27 PM PDT 24 12460702 ps
T1120 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1403337333 Jul 21 06:24:24 PM PDT 24 Jul 21 06:24:29 PM PDT 24 147380521 ps
T1121 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1573099231 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:28 PM PDT 24 290481963 ps
T1122 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.963920695 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:28 PM PDT 24 48334245 ps
T1123 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3828604584 Jul 21 06:24:17 PM PDT 24 Jul 21 06:24:20 PM PDT 24 136210069 ps
T1124 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2130923361 Jul 21 06:24:15 PM PDT 24 Jul 21 06:24:21 PM PDT 24 145071309 ps
T1125 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2659542322 Jul 21 06:24:04 PM PDT 24 Jul 21 06:24:09 PM PDT 24 33241396 ps
T1126 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4112476445 Jul 21 06:24:05 PM PDT 24 Jul 21 06:24:29 PM PDT 24 944131964 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2398983694 Jul 21 06:24:03 PM PDT 24 Jul 21 06:24:06 PM PDT 24 120869142 ps
T1128 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2560417451 Jul 21 06:24:25 PM PDT 24 Jul 21 06:24:29 PM PDT 24 95015258 ps
T1129 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2821254443 Jul 21 06:24:16 PM PDT 24 Jul 21 06:24:20 PM PDT 24 216455251 ps

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.4122404322
Short name T7
Test name
Test status
Simulation time 74564987766 ps
CPU time 245.03 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 249624 kb
Host smart-3d22d6ee-1234-45e4-864c-afb722d2dc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122404322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.4122404322
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1248343686
Short name T12
Test name
Test status
Simulation time 8201880649 ps
CPU time 175.18 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:35:07 PM PDT 24
Peak memory 265464 kb
Host smart-4377fc76-5669-413c-9067-ff713cb63aad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248343686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1248343686
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2480457409
Short name T13
Test name
Test status
Simulation time 7586667104 ps
CPU time 160.81 seconds
Started Jul 21 06:32:01 PM PDT 24
Finished Jul 21 06:34:43 PM PDT 24
Peak memory 269772 kb
Host smart-c531f1a0-af60-40f2-a93d-611cf08f02b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480457409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2480457409
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.205818821
Short name T106
Test name
Test status
Simulation time 4081361608 ps
CPU time 23.03 seconds
Started Jul 21 06:24:05 PM PDT 24
Finished Jul 21 06:24:31 PM PDT 24
Peak memory 223560 kb
Host smart-9e6f1757-d977-408f-87c6-68504fb4b278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205818821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.205818821
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.1957793227
Short name T6
Test name
Test status
Simulation time 22325262085 ps
CPU time 231.16 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 267432 kb
Host smart-5f18c5a1-b07b-4686-8b98-e351e5952042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957793227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.1957793227
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1327424329
Short name T17
Test name
Test status
Simulation time 19602196578 ps
CPU time 110.49 seconds
Started Jul 21 06:30:47 PM PDT 24
Finished Jul 21 06:32:38 PM PDT 24
Peak memory 251920 kb
Host smart-f5ff73bf-68ec-4bfe-8a10-d38e7c052843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327424329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1327424329
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1766234532
Short name T76
Test name
Test status
Simulation time 43405939 ps
CPU time 0.74 seconds
Started Jul 21 06:29:11 PM PDT 24
Finished Jul 21 06:29:12 PM PDT 24
Peak memory 216532 kb
Host smart-2ca9add1-23ae-4844-8ad8-042d57746766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766234532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1766234532
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3524247410
Short name T236
Test name
Test status
Simulation time 20061554594 ps
CPU time 133.67 seconds
Started Jul 21 06:30:54 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 274260 kb
Host smart-7e7bddde-0c7f-4ce0-8e95-44b585e706d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524247410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3524247410
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2408253454
Short name T46
Test name
Test status
Simulation time 23559217762 ps
CPU time 238.92 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:36:15 PM PDT 24
Peak memory 257080 kb
Host smart-e2ed349b-db83-4557-9717-29db6bbd28d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408253454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2408253454
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.599247315
Short name T206
Test name
Test status
Simulation time 42472414988 ps
CPU time 176.39 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:33:20 PM PDT 24
Peak memory 262184 kb
Host smart-8ba559af-fd5b-4dfd-996a-149a3fcad138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599247315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.599247315
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1877296392
Short name T108
Test name
Test status
Simulation time 69092405 ps
CPU time 4.65 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:22 PM PDT 24
Peak memory 216448 kb
Host smart-b1f10d18-4c71-4ebf-9dda-7fbf5233ebae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877296392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1877296392
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.650874030
Short name T38
Test name
Test status
Simulation time 155935210285 ps
CPU time 772.88 seconds
Started Jul 21 06:31:23 PM PDT 24
Finished Jul 21 06:44:16 PM PDT 24
Peak memory 270228 kb
Host smart-89debaa2-9212-4c79-a6cb-bea59b1f7eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650874030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.650874030
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.183586625
Short name T153
Test name
Test status
Simulation time 351915059489 ps
CPU time 935.32 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:46:34 PM PDT 24
Peak memory 282464 kb
Host smart-53548120-8ff0-44a5-aef2-2e1e2716fa00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183586625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.183586625
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.1919325227
Short name T44
Test name
Test status
Simulation time 1946800261 ps
CPU time 10.94 seconds
Started Jul 21 06:31:17 PM PDT 24
Finished Jul 21 06:31:29 PM PDT 24
Peak memory 234152 kb
Host smart-b3120bb8-1aba-4c22-951a-b0ac6ae83197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919325227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.1919325227
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1223211844
Short name T71
Test name
Test status
Simulation time 29366909 ps
CPU time 0.73 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:30:12 PM PDT 24
Peak memory 205936 kb
Host smart-b7a5eabf-1a2a-4e22-bd12-25a208e40c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223211844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1223211844
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2121902729
Short name T101
Test name
Test status
Simulation time 31463159067 ps
CPU time 86.74 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 256448 kb
Host smart-cbecdb87-0f79-4208-ab5d-4e1fa72b395c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121902729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2121902729
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2979324966
Short name T250
Test name
Test status
Simulation time 42242037380 ps
CPU time 399.44 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:37:29 PM PDT 24
Peak memory 250780 kb
Host smart-63e2a3c6-0b72-43ca-9c0b-4f1e22b0d7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979324966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2979324966
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2372377191
Short name T20
Test name
Test status
Simulation time 3908766468 ps
CPU time 106.87 seconds
Started Jul 21 06:29:29 PM PDT 24
Finished Jul 21 06:31:17 PM PDT 24
Peak memory 262944 kb
Host smart-2c03acf5-45da-41ea-b09c-49b8d5fe8ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372377191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2372377191
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2914775247
Short name T127
Test name
Test status
Simulation time 7205011048 ps
CPU time 38.46 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:45 PM PDT 24
Peak memory 207212 kb
Host smart-224ef3e1-a4b9-4f7a-87c6-d002a57b13b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914775247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2914775247
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.520192323
Short name T229
Test name
Test status
Simulation time 24758045269 ps
CPU time 262.08 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 254408 kb
Host smart-a9f5c2c4-65c3-4637-824c-bf41b3ac8f0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520192323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.520192323
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.2621293948
Short name T205
Test name
Test status
Simulation time 38906144365 ps
CPU time 381.01 seconds
Started Jul 21 06:30:46 PM PDT 24
Finished Jul 21 06:37:08 PM PDT 24
Peak memory 251876 kb
Host smart-4f2ea5f8-2ac0-4b29-bdb1-6f427792d0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621293948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.2621293948
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.134446860
Short name T187
Test name
Test status
Simulation time 28691375519 ps
CPU time 86.7 seconds
Started Jul 21 06:31:39 PM PDT 24
Finished Jul 21 06:33:07 PM PDT 24
Peak memory 251412 kb
Host smart-15ecd3b2-6af6-496b-b77a-024b03afddae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134446860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.134446860
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.278223111
Short name T57
Test name
Test status
Simulation time 199790785298 ps
CPU time 504.47 seconds
Started Jul 21 06:31:04 PM PDT 24
Finished Jul 21 06:39:29 PM PDT 24
Peak memory 273232 kb
Host smart-6ff1b05b-e46b-4a39-9131-bb0e4b07eb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278223111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.278223111
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1954955908
Short name T78
Test name
Test status
Simulation time 93977615 ps
CPU time 1.1 seconds
Started Jul 21 06:29:15 PM PDT 24
Finished Jul 21 06:29:17 PM PDT 24
Peak memory 235904 kb
Host smart-dab38731-554a-4540-8dab-6e5bb0e47fcc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954955908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1954955908
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2686845809
Short name T333
Test name
Test status
Simulation time 5667363532 ps
CPU time 97.86 seconds
Started Jul 21 06:29:56 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 252312 kb
Host smart-eedf9b9a-91c1-4d3c-bc2c-15c7d36bbdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686845809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2686845809
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.333228339
Short name T4
Test name
Test status
Simulation time 3466539935 ps
CPU time 10.63 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 216728 kb
Host smart-44094663-7bdb-4d46-acc7-d0b217c124ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333228339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.333228339
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.668562529
Short name T177
Test name
Test status
Simulation time 43896733715 ps
CPU time 309.01 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:35:01 PM PDT 24
Peak memory 262712 kb
Host smart-de0cd668-0576-4de6-82d2-d2c181621b9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668562529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress
_all.668562529
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.843511799
Short name T196
Test name
Test status
Simulation time 182594187880 ps
CPU time 277.48 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 252596 kb
Host smart-c0672be9-9555-4927-8e13-16b870862d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843511799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.843511799
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1926295490
Short name T188
Test name
Test status
Simulation time 68586325017 ps
CPU time 189.56 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:34:01 PM PDT 24
Peak memory 250588 kb
Host smart-4f869f6e-047b-4138-ba78-03ec5cf6cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926295490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1926295490
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2524358567
Short name T21
Test name
Test status
Simulation time 197450852551 ps
CPU time 352.74 seconds
Started Jul 21 06:31:46 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 255068 kb
Host smart-01914a7c-b512-4eab-ac08-0c46161ba4ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524358567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2524358567
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1218799319
Short name T116
Test name
Test status
Simulation time 171208859 ps
CPU time 4.34 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:30 PM PDT 24
Peak memory 216424 kb
Host smart-2fa99fbd-92a1-4c0c-be13-3ff8ab11815d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218799319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1218799319
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1981157592
Short name T320
Test name
Test status
Simulation time 36846322231 ps
CPU time 134.89 seconds
Started Jul 21 06:30:46 PM PDT 24
Finished Jul 21 06:33:02 PM PDT 24
Peak memory 253328 kb
Host smart-27f997e3-f0ee-409b-8e48-16b5a3e62a51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981157592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1981157592
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3225176878
Short name T217
Test name
Test status
Simulation time 112806030054 ps
CPU time 452.14 seconds
Started Jul 21 06:31:22 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 257712 kb
Host smart-290918e1-10a9-451d-aabf-4674caee2a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225176878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3225176878
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1782255916
Short name T45
Test name
Test status
Simulation time 7523766697 ps
CPU time 45.08 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:32:06 PM PDT 24
Peak memory 235572 kb
Host smart-372fd744-a46c-4668-9fae-68647aab7b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782255916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1782255916
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2800695818
Short name T334
Test name
Test status
Simulation time 43495293828 ps
CPU time 473.08 seconds
Started Jul 21 06:32:00 PM PDT 24
Finished Jul 21 06:39:53 PM PDT 24
Peak memory 264544 kb
Host smart-19a19458-b624-420d-88a2-fa987d904ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800695818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2800695818
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1704501608
Short name T181
Test name
Test status
Simulation time 975370127 ps
CPU time 22.36 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:41 PM PDT 24
Peak memory 215352 kb
Host smart-b1aac19b-3f39-41f6-9aae-1c52420a583c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704501608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1704501608
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.133919976
Short name T182
Test name
Test status
Simulation time 3756253076 ps
CPU time 8.21 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:35 PM PDT 24
Peak memory 215356 kb
Host smart-0250e534-8399-4692-ae95-8e897f674d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133919976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.133919976
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1064196529
Short name T993
Test name
Test status
Simulation time 173575427027 ps
CPU time 267.9 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:33:52 PM PDT 24
Peak memory 255628 kb
Host smart-8f389872-2753-4df4-b5ff-af3c54e88f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064196529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1064196529
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.407281857
Short name T91
Test name
Test status
Simulation time 8004711140 ps
CPU time 93.31 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:31:45 PM PDT 24
Peak memory 269360 kb
Host smart-dbb1674e-c9be-4143-b6ec-3b493fc3c9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407281857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.407281857
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.3442831337
Short name T42
Test name
Test status
Simulation time 6426678207 ps
CPU time 32.81 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:30:45 PM PDT 24
Peak memory 250216 kb
Host smart-8a965b52-0b11-41d2-ae9d-88e8951d11c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442831337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.3442831337
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.307048068
Short name T344
Test name
Test status
Simulation time 190426904 ps
CPU time 9.24 seconds
Started Jul 21 06:30:54 PM PDT 24
Finished Jul 21 06:31:04 PM PDT 24
Peak memory 224916 kb
Host smart-849f804b-d0b6-4d07-802f-50c4ee56190e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307048068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.307048068
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3473581098
Short name T216
Test name
Test status
Simulation time 216388036818 ps
CPU time 408.76 seconds
Started Jul 21 06:31:25 PM PDT 24
Finished Jul 21 06:38:15 PM PDT 24
Peak memory 265992 kb
Host smart-484d36c8-e009-4b9f-ad30-881efe4f5b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473581098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3473581098
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3605976208
Short name T193
Test name
Test status
Simulation time 118751742 ps
CPU time 3.43 seconds
Started Jul 21 06:24:18 PM PDT 24
Finished Jul 21 06:24:23 PM PDT 24
Peak memory 215480 kb
Host smart-226366c6-5750-4d87-b264-aafdd4f6767d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605976208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3605976208
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.697901681
Short name T226
Test name
Test status
Simulation time 42332842661 ps
CPU time 143.86 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:31:59 PM PDT 24
Peak memory 253008 kb
Host smart-9d6d2eea-1d0c-43bd-b584-6c1c2077741a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697901681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.697901681
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3378355983
Short name T1001
Test name
Test status
Simulation time 61169598592 ps
CPU time 360.93 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 268960 kb
Host smart-df85a998-52d2-4742-b447-94ecfdf22084
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378355983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3378355983
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2198061509
Short name T35
Test name
Test status
Simulation time 1287446231 ps
CPU time 5.38 seconds
Started Jul 21 06:29:15 PM PDT 24
Finished Jul 21 06:29:21 PM PDT 24
Peak memory 216648 kb
Host smart-6c846045-ae47-4f99-a191-4acf6bee44bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198061509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2198061509
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2827127631
Short name T2
Test name
Test status
Simulation time 73877527228 ps
CPU time 136.88 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 253780 kb
Host smart-bddd3685-b216-4af0-a51f-37179323bcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827127631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2827127631
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4034821677
Short name T302
Test name
Test status
Simulation time 11625098171 ps
CPU time 10.97 seconds
Started Jul 21 06:30:27 PM PDT 24
Finished Jul 21 06:30:39 PM PDT 24
Peak memory 233232 kb
Host smart-c37315c5-9a9a-4d8d-bda3-b3b6a0c8bf83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034821677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4034821677
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3620699304
Short name T95
Test name
Test status
Simulation time 34440734 ps
CPU time 1.19 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:08 PM PDT 24
Peak memory 207056 kb
Host smart-438e3aff-2b3d-4816-834c-bbe688747bc7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620699304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3620699304
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3364682714
Short name T1118
Test name
Test status
Simulation time 608220704 ps
CPU time 8.36 seconds
Started Jul 21 06:24:02 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 207052 kb
Host smart-fdc569b8-b98d-469b-9739-66b7277d2dc3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364682714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3364682714
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.998778395
Short name T1115
Test name
Test status
Simulation time 232376499 ps
CPU time 3.04 seconds
Started Jul 21 06:24:06 PM PDT 24
Finished Jul 21 06:24:12 PM PDT 24
Peak memory 217152 kb
Host smart-2bd86399-0449-4ff9-8f2a-f96ed151efbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998778395 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.998778395
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3847799239
Short name T131
Test name
Test status
Simulation time 158355799 ps
CPU time 1.2 seconds
Started Jul 21 06:24:07 PM PDT 24
Finished Jul 21 06:24:10 PM PDT 24
Peak memory 207076 kb
Host smart-1094cf50-e202-4d65-ab87-f5daefc921f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847799239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
847799239
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.3636152626
Short name T1096
Test name
Test status
Simulation time 75824802 ps
CPU time 0.8 seconds
Started Jul 21 06:24:00 PM PDT 24
Finished Jul 21 06:24:05 PM PDT 24
Peak memory 203812 kb
Host smart-e5058085-ce33-4c8f-8fc3-04152f7fd0bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636152626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.3
636152626
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2136441871
Short name T138
Test name
Test status
Simulation time 34103152 ps
CPU time 1.29 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:08 PM PDT 24
Peak memory 215272 kb
Host smart-e7dcb7e6-05a7-4887-99ec-a2a8d99cc1cb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136441871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2136441871
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2035034038
Short name T1041
Test name
Test status
Simulation time 34113678 ps
CPU time 0.65 seconds
Started Jul 21 06:24:05 PM PDT 24
Finished Jul 21 06:24:09 PM PDT 24
Peak memory 204040 kb
Host smart-7eaaa523-ed10-4473-8117-cd894500d858
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035034038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2035034038
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2678367220
Short name T161
Test name
Test status
Simulation time 531059978 ps
CPU time 3.25 seconds
Started Jul 21 06:24:06 PM PDT 24
Finished Jul 21 06:24:12 PM PDT 24
Peak memory 215300 kb
Host smart-fe35dc07-a57d-44ed-9ddb-c369937bb909
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678367220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2678367220
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.166298062
Short name T1080
Test name
Test status
Simulation time 26440897 ps
CPU time 1.65 seconds
Started Jul 21 06:23:58 PM PDT 24
Finished Jul 21 06:24:04 PM PDT 24
Peak memory 216436 kb
Host smart-3b01a57a-12e6-46f3-8173-867fa8ef3ac3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166298062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.166298062
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2519594237
Short name T1073
Test name
Test status
Simulation time 622020332 ps
CPU time 14.59 seconds
Started Jul 21 06:23:56 PM PDT 24
Finished Jul 21 06:24:15 PM PDT 24
Peak memory 215172 kb
Host smart-cef7e349-c977-46cb-9da3-6c343b3aab54
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519594237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2519594237
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.858441610
Short name T130
Test name
Test status
Simulation time 540663664 ps
CPU time 7.68 seconds
Started Jul 21 06:24:08 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 207080 kb
Host smart-08471d44-a7a3-44f9-8f55-63bb6c4ea987
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858441610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.858441610
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4182076550
Short name T1021
Test name
Test status
Simulation time 1289665612 ps
CPU time 25.17 seconds
Started Jul 21 06:24:05 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 215220 kb
Host smart-7812a30d-e302-4c57-aa2c-cc8d1b18e8ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182076550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.4182076550
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3794873077
Short name T94
Test name
Test status
Simulation time 173369424 ps
CPU time 1.6 seconds
Started Jul 21 06:24:06 PM PDT 24
Finished Jul 21 06:24:10 PM PDT 24
Peak memory 215324 kb
Host smart-bee00432-8c11-4a49-8f15-9fdddc80e7bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794873077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.3794873077
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3380259761
Short name T1036
Test name
Test status
Simulation time 31625408 ps
CPU time 1.6 seconds
Started Jul 21 06:24:05 PM PDT 24
Finished Jul 21 06:24:10 PM PDT 24
Peak memory 215452 kb
Host smart-38c42602-453c-4790-a677-ababd1a3e5c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380259761 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3380259761
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.2721491562
Short name T1103
Test name
Test status
Simulation time 61085388 ps
CPU time 1.19 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:08 PM PDT 24
Peak memory 207120 kb
Host smart-9e3a2029-abd1-4083-851a-0e5d8ee3c271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721491562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2
721491562
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3174659721
Short name T1101
Test name
Test status
Simulation time 14877209 ps
CPU time 0.81 seconds
Started Jul 21 06:24:03 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 203832 kb
Host smart-873c6e4b-6215-4703-b4b7-0f3dede24cdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174659721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
174659721
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.683645270
Short name T1011
Test name
Test status
Simulation time 271871603 ps
CPU time 2.3 seconds
Started Jul 21 06:24:07 PM PDT 24
Finished Jul 21 06:24:11 PM PDT 24
Peak memory 215416 kb
Host smart-3ae27cfc-1534-4c77-b39f-375cd4003f6a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683645270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.683645270
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3399706344
Short name T1014
Test name
Test status
Simulation time 13773536 ps
CPU time 0.7 seconds
Started Jul 21 06:24:03 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 203724 kb
Host smart-84778e87-71ea-4dda-9c6a-c23cdd9fdf32
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399706344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3399706344
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4265814999
Short name T1088
Test name
Test status
Simulation time 113147337 ps
CPU time 2.94 seconds
Started Jul 21 06:24:06 PM PDT 24
Finished Jul 21 06:24:12 PM PDT 24
Peak memory 215172 kb
Host smart-dfb1aa24-3c05-4aa7-954b-74a790888828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265814999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.4265814999
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2659542322
Short name T1125
Test name
Test status
Simulation time 33241396 ps
CPU time 2.23 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:09 PM PDT 24
Peak memory 215388 kb
Host smart-e574a825-7183-4e6d-8129-63fe5ba561e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659542322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
659542322
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.806666996
Short name T107
Test name
Test status
Simulation time 808224672 ps
CPU time 12.81 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 215240 kb
Host smart-42b074d5-199e-4705-809e-a0e8c4e36e73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806666996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.806666996
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1821779769
Short name T75
Test name
Test status
Simulation time 43787937 ps
CPU time 3.07 seconds
Started Jul 21 06:24:15 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 217596 kb
Host smart-e5118961-6c5d-4214-8232-d7338bcff3a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821779769 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1821779769
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3215729888
Short name T128
Test name
Test status
Simulation time 215893893 ps
CPU time 1.93 seconds
Started Jul 21 06:24:19 PM PDT 24
Finished Jul 21 06:24:22 PM PDT 24
Peak memory 215312 kb
Host smart-780de96c-27cb-4daf-a03c-b3ac25ac1d71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215729888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3215729888
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.193995969
Short name T1069
Test name
Test status
Simulation time 156900226 ps
CPU time 0.72 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 203844 kb
Host smart-a899ed63-8454-41c6-8d09-b6df5207604a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193995969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.193995969
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2582918580
Short name T1025
Test name
Test status
Simulation time 155284111 ps
CPU time 2.73 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 215176 kb
Host smart-48e44a02-a062-4b07-b0ac-8212708de0a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582918580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2582918580
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1667823551
Short name T110
Test name
Test status
Simulation time 160003278 ps
CPU time 3.6 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:21 PM PDT 24
Peak memory 215420 kb
Host smart-93aa8782-ed8a-439c-b0b8-6f4c19b5bb87
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667823551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1667823551
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3214321560
Short name T1092
Test name
Test status
Simulation time 31169965 ps
CPU time 1.94 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:21 PM PDT 24
Peak memory 216468 kb
Host smart-a1068892-55b3-4a68-a513-6169f214b4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214321560 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3214321560
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2154773984
Short name T1049
Test name
Test status
Simulation time 83506471 ps
CPU time 1.76 seconds
Started Jul 21 06:24:18 PM PDT 24
Finished Jul 21 06:24:21 PM PDT 24
Peak memory 215232 kb
Host smart-d263b8d2-ab4c-4171-94d5-1b457be30617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154773984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2154773984
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3331726439
Short name T1053
Test name
Test status
Simulation time 16999237 ps
CPU time 0.72 seconds
Started Jul 21 06:24:18 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 203816 kb
Host smart-03145678-e7cb-4179-bd71-fb05933a3c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331726439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3331726439
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.482249477
Short name T1078
Test name
Test status
Simulation time 727600012 ps
CPU time 4.17 seconds
Started Jul 21 06:24:21 PM PDT 24
Finished Jul 21 06:24:26 PM PDT 24
Peak memory 214520 kb
Host smart-9cf811b0-2e11-4212-bfb9-cc2324ab17cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482249477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.482249477
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1719133791
Short name T171
Test name
Test status
Simulation time 1455507269 ps
CPU time 15.78 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 215324 kb
Host smart-edfec9a7-0942-4b1e-8bf3-07fc119b3ead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719133791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1719133791
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3305368516
Short name T74
Test name
Test status
Simulation time 101427788 ps
CPU time 3.41 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:21 PM PDT 24
Peak memory 217444 kb
Host smart-1a914a0e-01c8-48d5-b767-273996a45d94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305368516 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3305368516
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3828604584
Short name T1123
Test name
Test status
Simulation time 136210069 ps
CPU time 1.26 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 207068 kb
Host smart-3377d791-2e10-4109-8fa7-88e06a541754
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828604584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3828604584
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3802156197
Short name T1017
Test name
Test status
Simulation time 13961556 ps
CPU time 0.78 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:18 PM PDT 24
Peak memory 203816 kb
Host smart-1f63ebf5-ad93-45b0-8cf8-4361bddf4c59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802156197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3802156197
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1929677622
Short name T1047
Test name
Test status
Simulation time 108648802 ps
CPU time 3.01 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 215300 kb
Host smart-115cfb24-bbc6-4cc7-bd63-941a2f957f7b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929677622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1929677622
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2130923361
Short name T1124
Test name
Test status
Simulation time 145071309 ps
CPU time 4.53 seconds
Started Jul 21 06:24:15 PM PDT 24
Finished Jul 21 06:24:21 PM PDT 24
Peak memory 215440 kb
Host smart-cd586780-5f1d-4789-badb-bfd119394004
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130923361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2130923361
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3467589698
Short name T73
Test name
Test status
Simulation time 702433625 ps
CPU time 14.34 seconds
Started Jul 21 06:24:22 PM PDT 24
Finished Jul 21 06:24:37 PM PDT 24
Peak memory 215244 kb
Host smart-115be558-66ad-4152-b5ae-e190e4eb8bbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467589698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3467589698
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2595628679
Short name T1065
Test name
Test status
Simulation time 249679642 ps
CPU time 3.28 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:21 PM PDT 24
Peak memory 216468 kb
Host smart-397c2e03-285d-400b-84c5-98843bbde1d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595628679 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2595628679
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.1750452670
Short name T1117
Test name
Test status
Simulation time 286701878 ps
CPU time 1.3 seconds
Started Jul 21 06:24:21 PM PDT 24
Finished Jul 21 06:24:23 PM PDT 24
Peak memory 214616 kb
Host smart-da3b2bb9-3317-4f2d-923a-0491d702507c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750452670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
1750452670
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1158675147
Short name T1056
Test name
Test status
Simulation time 35779664 ps
CPU time 0.71 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 203824 kb
Host smart-5348d4bb-e80b-4df3-bda2-63dcb4716028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158675147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1158675147
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.3682184980
Short name T1082
Test name
Test status
Simulation time 45915442 ps
CPU time 2.86 seconds
Started Jul 21 06:24:15 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 215268 kb
Host smart-0361f81f-1a94-4320-8eb4-6b7ab0f28619
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682184980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.3682184980
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1128922150
Short name T180
Test name
Test status
Simulation time 3988968674 ps
CPU time 18.47 seconds
Started Jul 21 06:24:19 PM PDT 24
Finished Jul 21 06:24:39 PM PDT 24
Peak memory 215296 kb
Host smart-7310947c-f87a-4816-b779-92f5d49ec71f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128922150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1128922150
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3660709979
Short name T1076
Test name
Test status
Simulation time 52322661 ps
CPU time 1.74 seconds
Started Jul 21 06:24:17 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 216484 kb
Host smart-177ac7b0-8a28-49ad-bdad-4087e945d034
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660709979 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3660709979
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3968856858
Short name T129
Test name
Test status
Simulation time 172495057 ps
CPU time 1.39 seconds
Started Jul 21 06:24:14 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 215260 kb
Host smart-843031c3-635e-4aa3-92b3-b206286c3d6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968856858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3968856858
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.298143851
Short name T1034
Test name
Test status
Simulation time 25690161 ps
CPU time 0.73 seconds
Started Jul 21 06:24:18 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 203884 kb
Host smart-a8b656ff-4a14-4145-8e74-863fda298654
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298143851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.298143851
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2264966256
Short name T1077
Test name
Test status
Simulation time 478553435 ps
CPU time 2.95 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 215244 kb
Host smart-3271d93b-1d73-4e0f-89b9-dcf804b5e8aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264966256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2264966256
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2821254443
Short name T1129
Test name
Test status
Simulation time 216455251 ps
CPU time 2.79 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 216440 kb
Host smart-7c4cd0a9-07bf-4539-a6ff-aa897b23cbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821254443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2821254443
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.995834743
Short name T124
Test name
Test status
Simulation time 114375713 ps
CPU time 6.61 seconds
Started Jul 21 06:24:19 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 215572 kb
Host smart-6184d86f-b4a9-4f2f-aa59-f2b0ecbc862b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995834743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.995834743
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2560417451
Short name T1128
Test name
Test status
Simulation time 95015258 ps
CPU time 2.89 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 217656 kb
Host smart-4e25995c-8174-4f60-bd9d-139c682d6efb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560417451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.2560417451
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.561523937
Short name T126
Test name
Test status
Simulation time 276762627 ps
CPU time 2.07 seconds
Started Jul 21 06:24:19 PM PDT 24
Finished Jul 21 06:24:22 PM PDT 24
Peak memory 215292 kb
Host smart-26e59511-e222-43e3-9d67-75c78f9b67d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561523937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.561523937
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2202168795
Short name T1044
Test name
Test status
Simulation time 14146948 ps
CPU time 0.78 seconds
Started Jul 21 06:24:22 PM PDT 24
Finished Jul 21 06:24:23 PM PDT 24
Peak memory 204124 kb
Host smart-7c66a23d-b080-4ced-97b6-f3fb4b4ec066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202168795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2202168795
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1403337333
Short name T1120
Test name
Test status
Simulation time 147380521 ps
CPU time 4.04 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 215284 kb
Host smart-0d7b93cd-a0e8-4833-a5ac-afc8215cd69f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403337333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.1403337333
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2451039511
Short name T113
Test name
Test status
Simulation time 148933490 ps
CPU time 1.96 seconds
Started Jul 21 06:24:15 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 215392 kb
Host smart-3e6c2e48-5f83-409c-8bf2-ae69b369f33b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451039511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2451039511
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2423820836
Short name T1107
Test name
Test status
Simulation time 2513850269 ps
CPU time 14.33 seconds
Started Jul 21 06:24:15 PM PDT 24
Finished Jul 21 06:24:31 PM PDT 24
Peak memory 215384 kb
Host smart-f3d9cafe-8ec4-4310-8e34-95cf74f5f7f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423820836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2423820836
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.963920695
Short name T1122
Test name
Test status
Simulation time 48334245 ps
CPU time 1.73 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 215436 kb
Host smart-7f89de9b-224c-4327-b540-737a599b0b92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963920695 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.963920695
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.738539601
Short name T1062
Test name
Test status
Simulation time 85840672 ps
CPU time 2.31 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 215284 kb
Host smart-2160d302-2f57-46f3-af88-a3647f9b42e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738539601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.738539601
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.1363377630
Short name T1033
Test name
Test status
Simulation time 13658760 ps
CPU time 0.71 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:26 PM PDT 24
Peak memory 203852 kb
Host smart-e49c63d5-cb65-436b-bd3e-f8e4f139d63d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363377630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
1363377630
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1689630441
Short name T1016
Test name
Test status
Simulation time 130750780 ps
CPU time 3.76 seconds
Started Jul 21 06:24:29 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 215320 kb
Host smart-59e8ebde-8247-49b6-84e3-66edd2a5b527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689630441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1689630441
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1298116636
Short name T111
Test name
Test status
Simulation time 212913643 ps
CPU time 1.85 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 215376 kb
Host smart-0f4fde37-4215-45e5-8999-247523412c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298116636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1298116636
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2931047490
Short name T1095
Test name
Test status
Simulation time 142258250 ps
CPU time 6.92 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 215544 kb
Host smart-91d5dec3-ef30-4d0c-bd36-ba535ac6ffdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931047490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2931047490
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.60362216
Short name T109
Test name
Test status
Simulation time 132134140 ps
CPU time 2.99 seconds
Started Jul 21 06:24:29 PM PDT 24
Finished Jul 21 06:24:32 PM PDT 24
Peak memory 216376 kb
Host smart-50a53af3-daec-4ff3-8f45-e8e0656c91ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60362216 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.60362216
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2647944488
Short name T1046
Test name
Test status
Simulation time 123387792 ps
CPU time 1.33 seconds
Started Jul 21 06:24:23 PM PDT 24
Finished Jul 21 06:24:24 PM PDT 24
Peak memory 215216 kb
Host smart-b8b9990e-2699-4bdc-ab92-bdb17bc6cafa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647944488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2647944488
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3606620562
Short name T1050
Test name
Test status
Simulation time 18788693 ps
CPU time 0.75 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 203828 kb
Host smart-550d246b-dbc5-46c6-997d-0ff2f5bc84bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606620562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3606620562
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3322838883
Short name T1026
Test name
Test status
Simulation time 28195470 ps
CPU time 1.71 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 215268 kb
Host smart-738828ac-4f7f-4392-a172-fc6a9a24470d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322838883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3322838883
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2607070909
Short name T121
Test name
Test status
Simulation time 432494383 ps
CPU time 2.48 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 216428 kb
Host smart-542010d1-4f6c-48b9-b0a9-c5424c9b96e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607070909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2607070909
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2666131433
Short name T1070
Test name
Test status
Simulation time 443304937 ps
CPU time 6.95 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:32 PM PDT 24
Peak memory 215244 kb
Host smart-8cc710aa-ad21-4082-b6f8-eb033266494a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666131433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2666131433
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.3938992004
Short name T1089
Test name
Test status
Simulation time 100896372 ps
CPU time 1.76 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 216396 kb
Host smart-81778c38-ce0f-4765-9f3a-b6cb5a0831ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938992004 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.3938992004
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3985134092
Short name T1071
Test name
Test status
Simulation time 113269226 ps
CPU time 1.42 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 215248 kb
Host smart-96eae921-77b2-4a15-9dee-386ccce98bb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985134092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3985134092
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.1834507082
Short name T1086
Test name
Test status
Simulation time 11520643 ps
CPU time 0.75 seconds
Started Jul 21 06:24:27 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 203756 kb
Host smart-7604e234-5e8c-439f-a1b7-04a2885dbdfe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834507082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
1834507082
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3910868564
Short name T1043
Test name
Test status
Simulation time 45676045 ps
CPU time 3.05 seconds
Started Jul 21 06:24:23 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 215324 kb
Host smart-4ad49b7d-ee4a-4977-a5db-a896f14c02ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910868564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3910868564
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1573099231
Short name T1121
Test name
Test status
Simulation time 290481963 ps
CPU time 2.2 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 215452 kb
Host smart-261bec51-e127-486f-bcd6-d24d0955bfd7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573099231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1573099231
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2239579978
Short name T118
Test name
Test status
Simulation time 466802197 ps
CPU time 3.88 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:32 PM PDT 24
Peak memory 217464 kb
Host smart-0367f5cf-2018-4ac0-b0f1-915d927bed5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239579978 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2239579978
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.2305043906
Short name T1091
Test name
Test status
Simulation time 159767004 ps
CPU time 1.93 seconds
Started Jul 21 06:24:23 PM PDT 24
Finished Jul 21 06:24:25 PM PDT 24
Peak memory 215352 kb
Host smart-849f9578-2809-44e9-ad4c-3e67a799841d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305043906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
2305043906
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.662876919
Short name T1119
Test name
Test status
Simulation time 12460702 ps
CPU time 0.69 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 203860 kb
Host smart-7b085bad-c136-4a29-9989-e034861e480d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662876919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.662876919
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.414180457
Short name T1052
Test name
Test status
Simulation time 65159522 ps
CPU time 3.66 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 215236 kb
Host smart-0a5aea52-c082-4b25-8c8f-a687825317e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414180457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.414180457
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.676876588
Short name T123
Test name
Test status
Simulation time 778708116 ps
CPU time 13.75 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:41 PM PDT 24
Peak memory 216020 kb
Host smart-d432bbff-dd35-48b1-811b-dd43cef87b0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676876588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device
_tl_intg_err.676876588
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3741024825
Short name T1061
Test name
Test status
Simulation time 417165754 ps
CPU time 13.09 seconds
Started Jul 21 06:24:06 PM PDT 24
Finished Jul 21 06:24:22 PM PDT 24
Peak memory 206900 kb
Host smart-ffe84b0c-2bc1-4773-a85d-47222fd16c8e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741024825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3741024825
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2891698148
Short name T1084
Test name
Test status
Simulation time 3671675725 ps
CPU time 35.55 seconds
Started Jul 21 06:24:06 PM PDT 24
Finished Jul 21 06:24:44 PM PDT 24
Peak memory 207040 kb
Host smart-aa6db2b8-87af-49b4-9ba7-6b9a07c4fc70
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891698148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2891698148
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1567241552
Short name T93
Test name
Test status
Simulation time 171628795 ps
CPU time 1.45 seconds
Started Jul 21 06:24:03 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 207120 kb
Host smart-a09f45d9-535c-4a88-b636-ab4397d39bbf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567241552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1567241552
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.491678432
Short name T115
Test name
Test status
Simulation time 646261606 ps
CPU time 3.93 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:11 PM PDT 24
Peak memory 217228 kb
Host smart-1079e067-f605-4da7-89b5-ce5d24a4e04b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491678432 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.491678432
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.66809011
Short name T1035
Test name
Test status
Simulation time 144887528 ps
CPU time 1.2 seconds
Started Jul 21 06:24:05 PM PDT 24
Finished Jul 21 06:24:09 PM PDT 24
Peak memory 215364 kb
Host smart-3658bf8b-dbe7-45d2-b135-61a8bee04061
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66809011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.66809011
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1858306792
Short name T1114
Test name
Test status
Simulation time 19523942 ps
CPU time 0.72 seconds
Started Jul 21 06:24:02 PM PDT 24
Finished Jul 21 06:24:06 PM PDT 24
Peak memory 203836 kb
Host smart-6f39fb9e-1303-4fdb-9450-4d0f27b1d859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858306792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
858306792
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2525093253
Short name T132
Test name
Test status
Simulation time 20521304 ps
CPU time 1.35 seconds
Started Jul 21 06:24:03 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 215412 kb
Host smart-8d6477ff-c008-4ce3-8a98-aba07a999176
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525093253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2525093253
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.4237779510
Short name T1028
Test name
Test status
Simulation time 39560113 ps
CPU time 0.67 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 203708 kb
Host smart-2386e528-8076-4427-be34-aa5c97fa5f66
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237779510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.4237779510
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1674391465
Short name T1031
Test name
Test status
Simulation time 45724460 ps
CPU time 2.78 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:09 PM PDT 24
Peak memory 215232 kb
Host smart-6c4a0bb3-c356-4f60-89f0-61929ba42241
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674391465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1674391465
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.3522958931
Short name T120
Test name
Test status
Simulation time 134797477 ps
CPU time 3.62 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:11 PM PDT 24
Peak memory 215464 kb
Host smart-3ce8aee3-b678-4821-bd54-535663b55f34
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522958931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3
522958931
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3563337124
Short name T1090
Test name
Test status
Simulation time 41303902 ps
CPU time 0.76 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:25 PM PDT 24
Peak memory 203840 kb
Host smart-9fe2e4a6-6952-4351-9b7d-47db003aae30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563337124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3563337124
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2357278575
Short name T1013
Test name
Test status
Simulation time 13543073 ps
CPU time 0.74 seconds
Started Jul 21 06:24:24 PM PDT 24
Finished Jul 21 06:24:26 PM PDT 24
Peak memory 203852 kb
Host smart-fb6d438d-5f11-4ef9-9448-bc22520120c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357278575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2357278575
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.1229433340
Short name T1023
Test name
Test status
Simulation time 24082222 ps
CPU time 0.75 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 204128 kb
Host smart-52a2d0d4-70f2-42fc-9d1c-6480367ab100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229433340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
1229433340
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1811000448
Short name T1066
Test name
Test status
Simulation time 24574353 ps
CPU time 0.74 seconds
Started Jul 21 06:24:27 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 204156 kb
Host smart-b45bfaa7-0d57-44d4-956e-b3e6f9e95146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811000448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1811000448
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4234616006
Short name T1064
Test name
Test status
Simulation time 19190759 ps
CPU time 0.72 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 204296 kb
Host smart-1416c647-b05d-407c-b7bd-d382ef6d8f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234616006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4234616006
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3828537269
Short name T1081
Test name
Test status
Simulation time 34981178 ps
CPU time 0.72 seconds
Started Jul 21 06:24:23 PM PDT 24
Finished Jul 21 06:24:24 PM PDT 24
Peak memory 203852 kb
Host smart-61f83784-c4c6-407a-92a3-65a34ba341fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828537269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3828537269
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1637833168
Short name T1027
Test name
Test status
Simulation time 40574595 ps
CPU time 0.77 seconds
Started Jul 21 06:24:27 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 204132 kb
Host smart-3653f6ad-ff43-4ea6-b1fe-c375ff544a46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637833168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1637833168
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1322826322
Short name T1010
Test name
Test status
Simulation time 49289603 ps
CPU time 0.78 seconds
Started Jul 21 06:24:25 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 203668 kb
Host smart-e8da65cc-f6e5-4b80-b459-2cc00d5106ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322826322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1322826322
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3104608853
Short name T1022
Test name
Test status
Simulation time 22042738 ps
CPU time 0.72 seconds
Started Jul 21 06:24:26 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 203816 kb
Host smart-35961838-a4ff-42f2-943c-00143083db4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104608853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3104608853
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1448192254
Short name T1079
Test name
Test status
Simulation time 12472887 ps
CPU time 0.76 seconds
Started Jul 21 06:24:22 PM PDT 24
Finished Jul 21 06:24:23 PM PDT 24
Peak memory 203800 kb
Host smart-bad3f99e-5a65-4a38-a486-aac39107a191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448192254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1448192254
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2355066150
Short name T135
Test name
Test status
Simulation time 2419776862 ps
CPU time 15.87 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 215320 kb
Host smart-cfd12a84-fcba-434a-be1e-5c01db8655ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355066150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2355066150
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2143242764
Short name T137
Test name
Test status
Simulation time 2368544343 ps
CPU time 36 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:47 PM PDT 24
Peak memory 207208 kb
Host smart-a049d3bf-ebb4-43fc-b555-251134e916d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143242764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2143242764
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3635134748
Short name T92
Test name
Test status
Simulation time 21438865 ps
CPU time 0.99 seconds
Started Jul 21 06:24:13 PM PDT 24
Finished Jul 21 06:24:16 PM PDT 24
Peak memory 206848 kb
Host smart-7fd5c759-d09b-4eb1-b10a-4e2794ebb79f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635134748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3635134748
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.474919075
Short name T1054
Test name
Test status
Simulation time 58819177 ps
CPU time 1.77 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 215476 kb
Host smart-d9d11536-fc97-4208-ae80-f2594e5897a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474919075 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.474919075
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.4083641320
Short name T141
Test name
Test status
Simulation time 421696205 ps
CPU time 2.09 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:12 PM PDT 24
Peak memory 215220 kb
Host smart-517d9a80-f2df-41d3-aba2-50ac2d1b70cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083641320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.4
083641320
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2022928388
Short name T1055
Test name
Test status
Simulation time 14320362 ps
CPU time 0.79 seconds
Started Jul 21 06:24:03 PM PDT 24
Finished Jul 21 06:24:07 PM PDT 24
Peak memory 203804 kb
Host smart-4d400674-61b3-45e9-af84-4c88ae4e2b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022928388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
022928388
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.958493958
Short name T1108
Test name
Test status
Simulation time 39066683 ps
CPU time 1.34 seconds
Started Jul 21 06:24:13 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 215392 kb
Host smart-386f4068-7c94-4b90-aa6f-94e98560408c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958493958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.958493958
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.2398983694
Short name T1127
Test name
Test status
Simulation time 120869142 ps
CPU time 0.67 seconds
Started Jul 21 06:24:03 PM PDT 24
Finished Jul 21 06:24:06 PM PDT 24
Peak memory 203656 kb
Host smart-1018899b-bba5-4285-9d6c-5e0e2edddaea
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398983694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.2398983694
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3220316986
Short name T1097
Test name
Test status
Simulation time 27241567 ps
CPU time 1.81 seconds
Started Jul 21 06:24:13 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 215272 kb
Host smart-6694139e-00b3-4015-bd1b-988cf8d705c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220316986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3220316986
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2429563000
Short name T1072
Test name
Test status
Simulation time 138847998 ps
CPU time 4.2 seconds
Started Jul 21 06:24:04 PM PDT 24
Finished Jul 21 06:24:11 PM PDT 24
Peak memory 215480 kb
Host smart-ba343e3a-2c87-4382-931a-a2780c7f4a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429563000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
429563000
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4112476445
Short name T1126
Test name
Test status
Simulation time 944131964 ps
CPU time 20.72 seconds
Started Jul 21 06:24:05 PM PDT 24
Finished Jul 21 06:24:29 PM PDT 24
Peak memory 215392 kb
Host smart-806173bd-3925-4b6b-a3f2-3ae8498c384b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112476445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4112476445
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.477352095
Short name T1032
Test name
Test status
Simulation time 16679620 ps
CPU time 0.69 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 203848 kb
Host smart-6aa80d6e-354f-4051-b6a5-9ccc50096e61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477352095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.477352095
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3270778287
Short name T1094
Test name
Test status
Simulation time 44806765 ps
CPU time 0.7 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 203832 kb
Host smart-5ae3cd79-1f8a-4f13-a965-41ddd38c8445
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270778287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3270778287
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3310144977
Short name T1048
Test name
Test status
Simulation time 13986215 ps
CPU time 0.76 seconds
Started Jul 21 06:24:36 PM PDT 24
Finished Jul 21 06:24:37 PM PDT 24
Peak memory 203812 kb
Host smart-802ba292-2662-435e-9048-22517ea5aded
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310144977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3310144977
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3877902418
Short name T1037
Test name
Test status
Simulation time 33952499 ps
CPU time 0.7 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 204136 kb
Host smart-d0cd8805-f3a7-42b5-80f7-b040d6a3da52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877902418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3877902418
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1107431850
Short name T1045
Test name
Test status
Simulation time 11531720 ps
CPU time 0.71 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 204136 kb
Host smart-547046e1-dcd1-4437-b51f-b5daff235271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107431850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1107431850
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.390788117
Short name T1100
Test name
Test status
Simulation time 27403425 ps
CPU time 0.71 seconds
Started Jul 21 06:24:39 PM PDT 24
Finished Jul 21 06:24:41 PM PDT 24
Peak memory 203816 kb
Host smart-bb36187c-d52c-4218-9f5f-2cc06cc9014e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390788117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.390788117
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.4281730288
Short name T1040
Test name
Test status
Simulation time 83926613 ps
CPU time 0.79 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 203848 kb
Host smart-6961e160-d3e0-4ba6-bfd7-9129d6f9b5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281730288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
4281730288
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2826969463
Short name T1051
Test name
Test status
Simulation time 34783898 ps
CPU time 0.73 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 203856 kb
Host smart-118fdc2e-21f2-4593-a698-adc3634601f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826969463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2826969463
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.750800928
Short name T1068
Test name
Test status
Simulation time 21350485 ps
CPU time 0.73 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 204144 kb
Host smart-8b2b0ad3-ccfd-43c4-812b-d17ba5fe3426
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750800928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.750800928
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.573255148
Short name T1018
Test name
Test status
Simulation time 14398826 ps
CPU time 0.74 seconds
Started Jul 21 06:24:32 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 203868 kb
Host smart-acf3648d-e649-477a-8862-fd2e4edba4f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573255148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.573255148
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1665959023
Short name T136
Test name
Test status
Simulation time 142340117 ps
CPU time 7.69 seconds
Started Jul 21 06:24:14 PM PDT 24
Finished Jul 21 06:24:23 PM PDT 24
Peak memory 215248 kb
Host smart-37895724-d9ee-4228-84ad-2dc9122698f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665959023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1665959023
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2183897337
Short name T1083
Test name
Test status
Simulation time 4984242168 ps
CPU time 23.6 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:36 PM PDT 24
Peak memory 215308 kb
Host smart-8ee2d8ad-375b-4407-9528-2623a7a63f05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183897337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2183897337
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1639849609
Short name T1110
Test name
Test status
Simulation time 42391631 ps
CPU time 0.99 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:15 PM PDT 24
Peak memory 206836 kb
Host smart-1624c784-60d0-4655-9f44-adba51733528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639849609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1639849609
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3336530323
Short name T1042
Test name
Test status
Simulation time 409124764 ps
CPU time 2.78 seconds
Started Jul 21 06:24:13 PM PDT 24
Finished Jul 21 06:24:18 PM PDT 24
Peak memory 217140 kb
Host smart-b6f7a8a0-e351-4339-b4c7-bdede0a22259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336530323 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3336530323
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.3182447464
Short name T133
Test name
Test status
Simulation time 38356242 ps
CPU time 1.32 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 215152 kb
Host smart-cae47244-9406-46f0-a56f-26bc37c66be5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182447464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.3
182447464
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3557928100
Short name T1106
Test name
Test status
Simulation time 30249705 ps
CPU time 0.76 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:16 PM PDT 24
Peak memory 203844 kb
Host smart-3f11a24b-99ff-4464-82cb-2c6268c75b87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557928100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
557928100
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1953384767
Short name T134
Test name
Test status
Simulation time 25031943 ps
CPU time 1.7 seconds
Started Jul 21 06:24:14 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 215412 kb
Host smart-63586ee1-3a3b-4474-bd97-6424045ee73b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953384767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1953384767
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1556521060
Short name T1098
Test name
Test status
Simulation time 27115467 ps
CPU time 0.65 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:15 PM PDT 24
Peak memory 203740 kb
Host smart-5ea0fc35-97eb-4879-ba28-2a98cba7f0eb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556521060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1556521060
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1620782524
Short name T172
Test name
Test status
Simulation time 1107561119 ps
CPU time 2.99 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:18 PM PDT 24
Peak memory 215240 kb
Host smart-1e6c4357-175c-40e4-9a57-b29b24bc347a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620782524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.1620782524
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.18782806
Short name T105
Test name
Test status
Simulation time 60316539 ps
CPU time 3.85 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 216512 kb
Host smart-9902913a-8185-4050-aed6-44da0325ad26
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18782806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.18782806
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.732595887
Short name T122
Test name
Test status
Simulation time 1771920766 ps
CPU time 8.35 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 216000 kb
Host smart-bdae6061-6a5c-4728-be93-7000e86e1ece
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732595887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.732595887
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2798787863
Short name T1012
Test name
Test status
Simulation time 18833253 ps
CPU time 0.73 seconds
Started Jul 21 06:24:35 PM PDT 24
Finished Jul 21 06:24:37 PM PDT 24
Peak memory 203856 kb
Host smart-beb417db-54d5-483a-9b44-26037d53fda1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798787863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2798787863
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.855553091
Short name T1067
Test name
Test status
Simulation time 63792989 ps
CPU time 0.79 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:33 PM PDT 24
Peak memory 203864 kb
Host smart-6c715d88-b2a6-4a1a-aba4-25b1aab5695b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855553091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.855553091
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1603917876
Short name T1015
Test name
Test status
Simulation time 79780575 ps
CPU time 0.69 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:34 PM PDT 24
Peak memory 203844 kb
Host smart-02d6d607-d061-4f46-ba6c-5734a290174c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603917876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1603917876
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1835204837
Short name T1019
Test name
Test status
Simulation time 41266212 ps
CPU time 0.72 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:32 PM PDT 24
Peak memory 203816 kb
Host smart-8bd0617b-3840-4b2d-a759-cf54057b7bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835204837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1835204837
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1595379953
Short name T1024
Test name
Test status
Simulation time 57879206 ps
CPU time 0.72 seconds
Started Jul 21 06:24:31 PM PDT 24
Finished Jul 21 06:24:32 PM PDT 24
Peak memory 203812 kb
Host smart-261f5715-77e6-4bda-8b9c-730ee2af3b3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595379953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1595379953
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.624913911
Short name T1063
Test name
Test status
Simulation time 16174376 ps
CPU time 0.75 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:35 PM PDT 24
Peak memory 204072 kb
Host smart-ee3c1350-e11e-4687-8e16-965e5bd11e9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624913911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.624913911
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.4150591844
Short name T1102
Test name
Test status
Simulation time 13303693 ps
CPU time 0.77 seconds
Started Jul 21 06:24:37 PM PDT 24
Finished Jul 21 06:24:39 PM PDT 24
Peak memory 203832 kb
Host smart-de63adfc-4a4b-4b40-8e16-7138cd2b076e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150591844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
4150591844
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1442787949
Short name T1060
Test name
Test status
Simulation time 14342255 ps
CPU time 0.82 seconds
Started Jul 21 06:24:33 PM PDT 24
Finished Jul 21 06:24:35 PM PDT 24
Peak memory 204300 kb
Host smart-edfb2b32-b061-42ff-bb40-92485dd86d50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442787949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1442787949
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.523051455
Short name T1020
Test name
Test status
Simulation time 14577956 ps
CPU time 0.73 seconds
Started Jul 21 06:24:35 PM PDT 24
Finished Jul 21 06:24:36 PM PDT 24
Peak memory 203844 kb
Host smart-69928f2c-d080-40fb-a6df-54d5b5980030
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523051455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.523051455
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.460862010
Short name T1075
Test name
Test status
Simulation time 16163551 ps
CPU time 0.77 seconds
Started Jul 21 06:24:40 PM PDT 24
Finished Jul 21 06:24:41 PM PDT 24
Peak memory 203820 kb
Host smart-327cb909-f993-4a55-aa57-36a7be795bab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460862010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.460862010
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.682618848
Short name T1104
Test name
Test status
Simulation time 106192903 ps
CPU time 1.73 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:16 PM PDT 24
Peak memory 215440 kb
Host smart-1039f659-fd06-4b5e-929d-8360608e50ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682618848 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.682618848
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.733427508
Short name T1038
Test name
Test status
Simulation time 87296183 ps
CPU time 2.81 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:13 PM PDT 24
Peak memory 215260 kb
Host smart-44306fcc-7ea5-4f40-b489-75d4987f6a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733427508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.733427508
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.1637968446
Short name T1109
Test name
Test status
Simulation time 55451969 ps
CPU time 0.76 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 203808 kb
Host smart-b56678c9-b1b3-4ed7-8006-f3df43642e87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637968446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.1
637968446
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2350491965
Short name T1030
Test name
Test status
Simulation time 468282633 ps
CPU time 1.72 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:16 PM PDT 24
Peak memory 207304 kb
Host smart-14ebc825-44dc-46ff-b84d-cbd69ba5e949
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350491965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2350491965
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3277456286
Short name T119
Test name
Test status
Simulation time 55633591 ps
CPU time 3.44 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 215360 kb
Host smart-1b383f33-8095-49b1-bdaf-366452297169
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277456286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
277456286
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1729160147
Short name T125
Test name
Test status
Simulation time 364758280 ps
CPU time 8.89 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 215440 kb
Host smart-d9ae1280-3a8b-4611-bcea-c4785d7cf1c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729160147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1729160147
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3215445955
Short name T1116
Test name
Test status
Simulation time 57179937 ps
CPU time 1.59 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:12 PM PDT 24
Peak memory 215452 kb
Host smart-79be58cc-eeaf-444d-ba76-319d2cf387ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215445955 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3215445955
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.298605917
Short name T1029
Test name
Test status
Simulation time 122495960 ps
CPU time 1.89 seconds
Started Jul 21 06:24:08 PM PDT 24
Finished Jul 21 06:24:11 PM PDT 24
Peak memory 215208 kb
Host smart-3f2f21ad-a2af-4482-af2b-f647ab9df6e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298605917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.298605917
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2149464334
Short name T1039
Test name
Test status
Simulation time 38180209 ps
CPU time 0.79 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:11 PM PDT 24
Peak memory 203864 kb
Host smart-e2984ead-3537-4db2-9f3f-a19c706d97f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149464334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
149464334
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.3902447689
Short name T1057
Test name
Test status
Simulation time 118293792 ps
CPU time 2.95 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:13 PM PDT 24
Peak memory 215216 kb
Host smart-1f11ad2f-7baf-4352-a9d9-5e0d54e02e88
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902447689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.3902447689
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3906955786
Short name T1111
Test name
Test status
Simulation time 52246939 ps
CPU time 3.52 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:18 PM PDT 24
Peak memory 215412 kb
Host smart-2f611e20-15ee-4067-8708-6ee969614568
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906955786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
906955786
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.3322015358
Short name T183
Test name
Test status
Simulation time 2315057059 ps
CPU time 14.43 seconds
Started Jul 21 06:24:09 PM PDT 24
Finished Jul 21 06:24:24 PM PDT 24
Peak memory 216024 kb
Host smart-5cfe58a5-20d1-4320-93bd-49be336a2ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322015358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.3322015358
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2878159908
Short name T117
Test name
Test status
Simulation time 920225101 ps
CPU time 4.24 seconds
Started Jul 21 06:24:13 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 217632 kb
Host smart-82d66aa2-ff08-4012-846f-0543eef351b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878159908 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2878159908
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.267956977
Short name T142
Test name
Test status
Simulation time 74220529 ps
CPU time 2.03 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:13 PM PDT 24
Peak memory 215248 kb
Host smart-8a390d50-b37b-4301-9bed-618aca20f2ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267956977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.267956977
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.464980259
Short name T1099
Test name
Test status
Simulation time 12639665 ps
CPU time 0.71 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:12 PM PDT 24
Peak memory 203772 kb
Host smart-eb80312c-3b95-4c8e-882c-67ac532ca93a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464980259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.464980259
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3210450108
Short name T1085
Test name
Test status
Simulation time 94206627 ps
CPU time 1.83 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 215796 kb
Host smart-fbe213e2-fc50-4315-8259-ee67558a29cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210450108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3210450108
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.637366629
Short name T114
Test name
Test status
Simulation time 236614599 ps
CPU time 2.59 seconds
Started Jul 21 06:24:10 PM PDT 24
Finished Jul 21 06:24:14 PM PDT 24
Peak memory 215516 kb
Host smart-2263f8b9-b5f7-4f2d-b6c3-5e17d0aa58b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637366629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.637366629
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3052025407
Short name T1059
Test name
Test status
Simulation time 752166297 ps
CPU time 8.58 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:24 PM PDT 24
Peak memory 215484 kb
Host smart-e9879e0d-4c57-4d49-85fd-0c825487077a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052025407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3052025407
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.945070233
Short name T1105
Test name
Test status
Simulation time 301276209 ps
CPU time 3.77 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:18 PM PDT 24
Peak memory 217296 kb
Host smart-8c351cf3-da3a-4109-9ade-5974f45ad1d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945070233 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.945070233
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2163898908
Short name T140
Test name
Test status
Simulation time 70936236 ps
CPU time 1.34 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:16 PM PDT 24
Peak memory 207136 kb
Host smart-766bee86-d401-41b4-b409-d7d72566f684
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163898908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
163898908
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1240891040
Short name T1093
Test name
Test status
Simulation time 15599776 ps
CPU time 0.8 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:16 PM PDT 24
Peak memory 203824 kb
Host smart-88d72193-e5c5-4809-8100-d2494bbf672b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240891040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
240891040
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3544805847
Short name T1074
Test name
Test status
Simulation time 25957211 ps
CPU time 1.56 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:15 PM PDT 24
Peak memory 206980 kb
Host smart-0bc00ee4-6a72-41aa-b177-2e04658886b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544805847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3544805847
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3680544762
Short name T1113
Test name
Test status
Simulation time 257205014 ps
CPU time 3.81 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:19 PM PDT 24
Peak memory 216420 kb
Host smart-595906d1-d5a5-42cc-a37a-a1d63f6b4ddb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680544762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
680544762
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.826554884
Short name T173
Test name
Test status
Simulation time 3163473489 ps
CPU time 14.59 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:28 PM PDT 24
Peak memory 215448 kb
Host smart-13b48784-1294-42b7-83b3-4a5fa3ea3b79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826554884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.826554884
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1096526247
Short name T1058
Test name
Test status
Simulation time 104035620 ps
CPU time 4.08 seconds
Started Jul 21 06:24:18 PM PDT 24
Finished Jul 21 06:24:23 PM PDT 24
Peak memory 218012 kb
Host smart-c913e817-95de-492b-aba0-c673d8735eb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096526247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1096526247
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4041087906
Short name T139
Test name
Test status
Simulation time 108850363 ps
CPU time 2.68 seconds
Started Jul 21 06:24:13 PM PDT 24
Finished Jul 21 06:24:18 PM PDT 24
Peak memory 215352 kb
Host smart-aa0d6c7d-99be-4baf-a00e-3d08d6f36ed4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041087906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
041087906
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2366311286
Short name T1087
Test name
Test status
Simulation time 11481161 ps
CPU time 0.67 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:15 PM PDT 24
Peak memory 203696 kb
Host smart-8198b37c-e334-43c5-b6fd-e151033d8911
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366311286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
366311286
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.965008888
Short name T1112
Test name
Test status
Simulation time 215518172 ps
CPU time 2.85 seconds
Started Jul 21 06:24:16 PM PDT 24
Finished Jul 21 06:24:20 PM PDT 24
Peak memory 215232 kb
Host smart-21d50a72-6e65-4798-9e8c-0b6e6c34f684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965008888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.965008888
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4078993366
Short name T112
Test name
Test status
Simulation time 98834474 ps
CPU time 1.82 seconds
Started Jul 21 06:24:12 PM PDT 24
Finished Jul 21 06:24:17 PM PDT 24
Peak memory 215452 kb
Host smart-9638e350-438f-4986-a389-b2000115a0a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078993366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
078993366
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1019509795
Short name T194
Test name
Test status
Simulation time 817983619 ps
CPU time 11.69 seconds
Started Jul 21 06:24:11 PM PDT 24
Finished Jul 21 06:24:25 PM PDT 24
Peak memory 215164 kb
Host smart-451ce9b9-b127-4165-bea9-ccdad3e8f91a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019509795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1019509795
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.40555542
Short name T379
Test name
Test status
Simulation time 44255588 ps
CPU time 0.69 seconds
Started Jul 21 06:29:15 PM PDT 24
Finished Jul 21 06:29:17 PM PDT 24
Peak memory 205372 kb
Host smart-21044d40-2993-43f6-b1d7-7d9b78373f58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40555542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.40555542
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.3610500841
Short name T937
Test name
Test status
Simulation time 206476102 ps
CPU time 3.74 seconds
Started Jul 21 06:29:15 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 224864 kb
Host smart-0d5b5ea7-597f-42c8-ab77-f3d19d892a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610500841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.3610500841
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1357216353
Short name T645
Test name
Test status
Simulation time 136462638 ps
CPU time 0.74 seconds
Started Jul 21 06:29:09 PM PDT 24
Finished Jul 21 06:29:10 PM PDT 24
Peak memory 206008 kb
Host smart-c6a155b0-984d-4fba-897e-5c5dbcb63d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357216353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1357216353
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.748740904
Short name T807
Test name
Test status
Simulation time 39668341705 ps
CPU time 263.71 seconds
Started Jul 21 06:29:16 PM PDT 24
Finished Jul 21 06:33:40 PM PDT 24
Peak memory 256612 kb
Host smart-c28be016-19b9-4cb2-8892-b2355ddc372d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748740904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.748740904
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.2241314937
Short name T889
Test name
Test status
Simulation time 122608443959 ps
CPU time 140.73 seconds
Started Jul 21 06:29:15 PM PDT 24
Finished Jul 21 06:31:37 PM PDT 24
Peak memory 249548 kb
Host smart-3c112410-6fd8-4a9f-97eb-dce258231dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241314937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.2241314937
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2264322444
Short name T632
Test name
Test status
Simulation time 10065023042 ps
CPU time 61.69 seconds
Started Jul 21 06:29:17 PM PDT 24
Finished Jul 21 06:30:19 PM PDT 24
Peak memory 256212 kb
Host smart-cb40a147-1071-426d-9f67-cb9a6d2e928e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264322444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2264322444
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2437431980
Short name T43
Test name
Test status
Simulation time 445590383 ps
CPU time 6.14 seconds
Started Jul 21 06:29:16 PM PDT 24
Finished Jul 21 06:29:22 PM PDT 24
Peak memory 224868 kb
Host smart-4dc78b9d-9ff4-494c-84ce-20b2c888afcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437431980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2437431980
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1633410367
Short name T561
Test name
Test status
Simulation time 36535062469 ps
CPU time 253.45 seconds
Started Jul 21 06:29:16 PM PDT 24
Finished Jul 21 06:33:30 PM PDT 24
Peak memory 257868 kb
Host smart-9bbc872a-85ff-4e94-b20d-d6bf00cb3b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633410367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1633410367
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3799640126
Short name T316
Test name
Test status
Simulation time 996193507 ps
CPU time 12.64 seconds
Started Jul 21 06:29:16 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 224936 kb
Host smart-90416b68-fae2-4605-9c76-fff0ad37c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799640126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3799640126
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2357704014
Short name T960
Test name
Test status
Simulation time 1525394566 ps
CPU time 4.61 seconds
Started Jul 21 06:29:15 PM PDT 24
Finished Jul 21 06:29:21 PM PDT 24
Peak memory 233092 kb
Host smart-0812f624-bff7-4824-8dbe-3dcc28d9e2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357704014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2357704014
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.445107012
Short name T702
Test name
Test status
Simulation time 3676805934 ps
CPU time 6.37 seconds
Started Jul 21 06:29:06 PM PDT 24
Finished Jul 21 06:29:13 PM PDT 24
Peak memory 233244 kb
Host smart-86d44146-d816-4eba-8609-44d8258fb9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445107012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
445107012
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1365425159
Short name T721
Test name
Test status
Simulation time 3596628606 ps
CPU time 10.96 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:19 PM PDT 24
Peak memory 233096 kb
Host smart-f8c8cf4d-5c79-4d95-b32d-6cc2df0bfe6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365425159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1365425159
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3996301177
Short name T503
Test name
Test status
Simulation time 3960441685 ps
CPU time 6 seconds
Started Jul 21 06:29:17 PM PDT 24
Finished Jul 21 06:29:24 PM PDT 24
Peak memory 220664 kb
Host smart-91de22a2-b022-4fe9-98b6-3426f87304ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996301177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3996301177
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3621870954
Short name T61
Test name
Test status
Simulation time 225602051390 ps
CPU time 483.79 seconds
Started Jul 21 06:29:14 PM PDT 24
Finished Jul 21 06:37:19 PM PDT 24
Peak memory 282456 kb
Host smart-ea93815e-0e2b-40db-9cb3-814ffc087840
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621870954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3621870954
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2091404845
Short name T942
Test name
Test status
Simulation time 4012348978 ps
CPU time 11.42 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 216692 kb
Host smart-dd00bab3-5a83-48de-aeeb-44b2bc902f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091404845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2091404845
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.821069638
Short name T914
Test name
Test status
Simulation time 38323161386 ps
CPU time 25.43 seconds
Started Jul 21 06:29:07 PM PDT 24
Finished Jul 21 06:29:33 PM PDT 24
Peak memory 216820 kb
Host smart-80e7a2c6-a9da-4af9-a859-900c567e23e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821069638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.821069638
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2228800274
Short name T443
Test name
Test status
Simulation time 29703720 ps
CPU time 0.93 seconds
Started Jul 21 06:29:08 PM PDT 24
Finished Jul 21 06:29:10 PM PDT 24
Peak memory 208332 kb
Host smart-567b71d5-c183-4d28-a3d1-08c0758d274b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228800274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2228800274
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.530857342
Short name T440
Test name
Test status
Simulation time 154194654 ps
CPU time 0.78 seconds
Started Jul 21 06:29:10 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 206428 kb
Host smart-d10f73cd-c50c-4c6a-8fff-85c393ac9d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530857342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.530857342
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.109473330
Short name T498
Test name
Test status
Simulation time 2086138152 ps
CPU time 3.79 seconds
Started Jul 21 06:29:16 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 233084 kb
Host smart-507b9752-73c0-4d8e-9f7e-8e96ffc83ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109473330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.109473330
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.4260666855
Short name T499
Test name
Test status
Simulation time 11271569 ps
CPU time 0.73 seconds
Started Jul 21 06:29:20 PM PDT 24
Finished Jul 21 06:29:22 PM PDT 24
Peak memory 206276 kb
Host smart-6a220ab5-b0f2-422a-bb6f-0c349605bd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260666855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.4
260666855
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1234504908
Short name T643
Test name
Test status
Simulation time 152869482 ps
CPU time 2.15 seconds
Started Jul 21 06:29:21 PM PDT 24
Finished Jul 21 06:29:23 PM PDT 24
Peak memory 224900 kb
Host smart-12556cfa-5341-40af-8894-1eef7a6937d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234504908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1234504908
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4211940452
Short name T509
Test name
Test status
Simulation time 18770481 ps
CPU time 0.78 seconds
Started Jul 21 06:29:14 PM PDT 24
Finished Jul 21 06:29:15 PM PDT 24
Peak memory 207084 kb
Host smart-8a2c7d61-4017-4bb3-bfa1-ce1fbfbc7bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211940452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4211940452
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2285769264
Short name T361
Test name
Test status
Simulation time 23358273565 ps
CPU time 106.24 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:31:10 PM PDT 24
Peak memory 241440 kb
Host smart-62b65c33-edbe-4e3b-a591-f93f7fbbfd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285769264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2285769264
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2380546007
Short name T452
Test name
Test status
Simulation time 446365000 ps
CPU time 3.48 seconds
Started Jul 21 06:29:21 PM PDT 24
Finished Jul 21 06:29:25 PM PDT 24
Peak memory 224916 kb
Host smart-ca36752d-66dd-4126-bba2-296568a0bcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380546007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2380546007
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.311355091
Short name T198
Test name
Test status
Simulation time 3542393523 ps
CPU time 91.5 seconds
Started Jul 21 06:29:20 PM PDT 24
Finished Jul 21 06:30:52 PM PDT 24
Peak memory 255312 kb
Host smart-f820093b-4395-42c5-8721-6ad3c14fbe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311355091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
311355091
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2979229060
Short name T428
Test name
Test status
Simulation time 726350455 ps
CPU time 5.75 seconds
Started Jul 21 06:29:20 PM PDT 24
Finished Jul 21 06:29:26 PM PDT 24
Peak memory 224948 kb
Host smart-44b0e91e-bfec-48fb-9581-8bf05d0075d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979229060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2979229060
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.636239955
Short name T550
Test name
Test status
Simulation time 660427368 ps
CPU time 10.69 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:29:35 PM PDT 24
Peak memory 241352 kb
Host smart-7f976cb4-0871-4679-ace1-116569b56b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636239955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.636239955
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3688233023
Short name T234
Test name
Test status
Simulation time 471494481 ps
CPU time 7.09 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:29:42 PM PDT 24
Peak memory 233096 kb
Host smart-900b89eb-e1e5-449f-bc0e-65c5a51fc96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688233023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3688233023
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.76253612
Short name T819
Test name
Test status
Simulation time 13938864807 ps
CPU time 14.2 seconds
Started Jul 21 06:29:21 PM PDT 24
Finished Jul 21 06:29:36 PM PDT 24
Peak memory 241448 kb
Host smart-4b20de49-8fc1-4e2d-8814-fa9018de91c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76253612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.76253612
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3526502615
Short name T902
Test name
Test status
Simulation time 611655007 ps
CPU time 3.61 seconds
Started Jul 21 06:29:22 PM PDT 24
Finished Jul 21 06:29:26 PM PDT 24
Peak memory 219700 kb
Host smart-85ee3245-5de2-458d-b912-ef584ba19152
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3526502615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3526502615
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3054519532
Short name T81
Test name
Test status
Simulation time 242473495 ps
CPU time 1.09 seconds
Started Jul 21 06:29:19 PM PDT 24
Finished Jul 21 06:29:20 PM PDT 24
Peak memory 235468 kb
Host smart-97a4c17e-478a-45d2-a878-5032c727f18e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054519532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3054519532
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3721017721
Short name T1008
Test name
Test status
Simulation time 1104406435 ps
CPU time 18.14 seconds
Started Jul 21 06:29:14 PM PDT 24
Finished Jul 21 06:29:32 PM PDT 24
Peak memory 220440 kb
Host smart-4587c5fd-f35c-43ae-87e1-98219bca5a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721017721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3721017721
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2663116914
Short name T616
Test name
Test status
Simulation time 108482237 ps
CPU time 1.49 seconds
Started Jul 21 06:29:20 PM PDT 24
Finished Jul 21 06:29:22 PM PDT 24
Peak memory 216712 kb
Host smart-c3612e77-e9f6-4598-bfa6-21f2ff4a5cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663116914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2663116914
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2836968324
Short name T34
Test name
Test status
Simulation time 141917630 ps
CPU time 0.87 seconds
Started Jul 21 06:29:16 PM PDT 24
Finished Jul 21 06:29:17 PM PDT 24
Peak memory 206380 kb
Host smart-1838a749-2c3b-4463-b329-d131b8084e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836968324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2836968324
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.967879253
Short name T841
Test name
Test status
Simulation time 8374389322 ps
CPU time 5.43 seconds
Started Jul 21 06:29:33 PM PDT 24
Finished Jul 21 06:29:39 PM PDT 24
Peak memory 233124 kb
Host smart-66c4ab61-75fc-48b7-bab5-224170f173f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967879253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.967879253
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1281392859
Short name T89
Test name
Test status
Simulation time 14060277 ps
CPU time 0.74 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 206276 kb
Host smart-a2f46eb3-3b5d-409d-b8f7-73115b963b86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281392859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1281392859
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.489376892
Short name T834
Test name
Test status
Simulation time 399199095 ps
CPU time 3.52 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:30:10 PM PDT 24
Peak memory 224848 kb
Host smart-2b7f54a4-866a-4dc4-822d-399b4bade6be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489376892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.489376892
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.674164288
Short name T370
Test name
Test status
Simulation time 16155183 ps
CPU time 0.76 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 206012 kb
Host smart-d4157933-d7f8-4e2f-a1e7-cc56ce9aa3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674164288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.674164288
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1973484505
Short name T186
Test name
Test status
Simulation time 42681892358 ps
CPU time 42.33 seconds
Started Jul 21 06:30:04 PM PDT 24
Finished Jul 21 06:30:46 PM PDT 24
Peak memory 233224 kb
Host smart-f9c74bbb-f974-4d06-8c98-610cdb72fd67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973484505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1973484505
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.925956550
Short name T190
Test name
Test status
Simulation time 74534483067 ps
CPU time 108.43 seconds
Started Jul 21 06:30:03 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 251712 kb
Host smart-5c7fb522-65dc-4a45-bdaa-cce506cb3842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925956550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.925956550
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3795994732
Short name T615
Test name
Test status
Simulation time 1573095567 ps
CPU time 10.16 seconds
Started Jul 21 06:30:03 PM PDT 24
Finished Jul 21 06:30:14 PM PDT 24
Peak memory 221932 kb
Host smart-b136ed5f-59b8-4280-ba2e-fe432e6c35a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795994732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3795994732
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.500851370
Short name T165
Test name
Test status
Simulation time 4824468174 ps
CPU time 20.66 seconds
Started Jul 21 06:30:07 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 233200 kb
Host smart-24e80ff5-b3a2-4f16-8a33-adc5040dc267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500851370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.500851370
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3292313893
Short name T740
Test name
Test status
Simulation time 243306438 ps
CPU time 6.54 seconds
Started Jul 21 06:30:04 PM PDT 24
Finished Jul 21 06:30:11 PM PDT 24
Peak memory 224912 kb
Host smart-591bebf9-2570-431c-8172-cee1c9a58fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292313893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3292313893
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3183783275
Short name T762
Test name
Test status
Simulation time 983055115 ps
CPU time 11.47 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:30:10 PM PDT 24
Peak memory 233240 kb
Host smart-9ccd0654-0080-44a5-9f10-df7304ae152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183783275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3183783275
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.601688094
Short name T997
Test name
Test status
Simulation time 29457874714 ps
CPU time 61.62 seconds
Started Jul 21 06:30:04 PM PDT 24
Finished Jul 21 06:31:06 PM PDT 24
Peak memory 233188 kb
Host smart-c7f3c3bc-2abc-44f4-90d5-84bac5d575c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601688094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.601688094
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.15371144
Short name T485
Test name
Test status
Simulation time 1563798955 ps
CPU time 8.13 seconds
Started Jul 21 06:30:00 PM PDT 24
Finished Jul 21 06:30:08 PM PDT 24
Peak memory 224812 kb
Host smart-cc6d8a39-030f-4f31-982d-167159689cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15371144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.15371144
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1502115653
Short name T23
Test name
Test status
Simulation time 4043834001 ps
CPU time 8.05 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 225032 kb
Host smart-db3014ad-2579-457d-a34e-a8047983ca1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502115653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1502115653
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3678952123
Short name T865
Test name
Test status
Simulation time 331499901 ps
CPU time 3.46 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:30:11 PM PDT 24
Peak memory 220044 kb
Host smart-16b3e1b4-60c7-4f67-bb71-745e70e41909
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3678952123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3678952123
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2833723105
Short name T839
Test name
Test status
Simulation time 21113772078 ps
CPU time 153.52 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:32:40 PM PDT 24
Peak memory 250656 kb
Host smart-159e1324-7118-419e-abb1-809c7057849f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833723105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2833723105
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.632824875
Short name T1002
Test name
Test status
Simulation time 15438143470 ps
CPU time 29.63 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 216700 kb
Host smart-e372c3ad-3fc8-475d-a70a-a619bd969273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632824875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.632824875
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2069936182
Short name T948
Test name
Test status
Simulation time 11251333861 ps
CPU time 9 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:30:06 PM PDT 24
Peak memory 216716 kb
Host smart-f2fc65e8-4ebb-486b-bc77-56b08d558bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069936182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2069936182
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1869003681
Short name T524
Test name
Test status
Simulation time 138907964 ps
CPU time 1.19 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:30:00 PM PDT 24
Peak memory 208344 kb
Host smart-18d121d9-8d24-48e2-b869-b6efac3e30b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869003681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1869003681
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4242013932
Short name T459
Test name
Test status
Simulation time 50406585 ps
CPU time 0.91 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 206448 kb
Host smart-3fa1081f-a158-475e-84ba-3e5f1cd1a60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242013932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4242013932
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3170274047
Short name T966
Test name
Test status
Simulation time 5237055807 ps
CPU time 15.25 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:21 PM PDT 24
Peak memory 224952 kb
Host smart-407a0e86-a0b3-41a2-a9e0-54af664963ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170274047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3170274047
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3356151597
Short name T68
Test name
Test status
Simulation time 73448319 ps
CPU time 0.7 seconds
Started Jul 21 06:30:03 PM PDT 24
Finished Jul 21 06:30:04 PM PDT 24
Peak memory 205432 kb
Host smart-3f63d4f4-3203-4c0e-8b21-ed469dd73c1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356151597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3356151597
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3471989503
Short name T277
Test name
Test status
Simulation time 15473851406 ps
CPU time 21.4 seconds
Started Jul 21 06:30:07 PM PDT 24
Finished Jul 21 06:30:29 PM PDT 24
Peak memory 224932 kb
Host smart-00bc85e8-d2bc-44fa-9be0-884327ab0b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471989503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3471989503
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.4087040611
Short name T826
Test name
Test status
Simulation time 22666884 ps
CPU time 0.88 seconds
Started Jul 21 06:30:07 PM PDT 24
Finished Jul 21 06:30:08 PM PDT 24
Peak memory 207388 kb
Host smart-d0266693-1e41-49eb-a481-b07f627a2f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087040611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.4087040611
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3693127943
Short name T888
Test name
Test status
Simulation time 40997405604 ps
CPU time 80 seconds
Started Jul 21 06:30:07 PM PDT 24
Finished Jul 21 06:31:28 PM PDT 24
Peak memory 224980 kb
Host smart-1f5a6347-5bda-4142-9434-62e0f4dc4645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693127943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3693127943
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1070900987
Short name T353
Test name
Test status
Simulation time 6897742179 ps
CPU time 49.81 seconds
Started Jul 21 06:30:04 PM PDT 24
Finished Jul 21 06:30:54 PM PDT 24
Peak memory 249660 kb
Host smart-3bf4e130-8559-4d15-9aed-5f91d4d76228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070900987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1070900987
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1353629956
Short name T156
Test name
Test status
Simulation time 1913516321 ps
CPU time 40.14 seconds
Started Jul 21 06:30:04 PM PDT 24
Finished Jul 21 06:30:45 PM PDT 24
Peak memory 241364 kb
Host smart-1b312f52-776c-4049-b678-771e2d4d27f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353629956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1353629956
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1317548112
Short name T868
Test name
Test status
Simulation time 1774244879 ps
CPU time 8.78 seconds
Started Jul 21 06:30:04 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 234096 kb
Host smart-e2c04f80-126d-42c6-aaba-bca3606b3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317548112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1317548112
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.4291885748
Short name T325
Test name
Test status
Simulation time 28412182099 ps
CPU time 71.02 seconds
Started Jul 21 06:30:07 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 256868 kb
Host smart-b3ad7810-6691-431d-9761-ef2d180e7e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291885748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.4291885748
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3164147724
Short name T209
Test name
Test status
Simulation time 272758864 ps
CPU time 5.18 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:30:11 PM PDT 24
Peak memory 224888 kb
Host smart-6731a0a7-3ae7-4343-8358-2ceb55be7377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164147724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3164147724
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2580188535
Short name T257
Test name
Test status
Simulation time 3780173657 ps
CPU time 44.23 seconds
Started Jul 21 06:30:03 PM PDT 24
Finished Jul 21 06:30:48 PM PDT 24
Peak memory 234332 kb
Host smart-c2ca03e8-29f6-41ca-8b89-7bf05b175289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580188535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2580188535
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2400826519
Short name T252
Test name
Test status
Simulation time 960749350 ps
CPU time 8.65 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:30:16 PM PDT 24
Peak memory 239488 kb
Host smart-6cef4355-b26d-4a07-9607-5f73d34da294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400826519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2400826519
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2667409062
Short name T212
Test name
Test status
Simulation time 3374775016 ps
CPU time 7.66 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 241096 kb
Host smart-49f7aea8-8d14-43d0-a6cf-d66ea0f30001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667409062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2667409062
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1706481099
Short name T163
Test name
Test status
Simulation time 564144217 ps
CPU time 4.06 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:10 PM PDT 24
Peak memory 223560 kb
Host smart-06c0b70a-f3b9-4bd2-95ed-ad253a1684c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1706481099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1706481099
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2355864636
Short name T179
Test name
Test status
Simulation time 14092818592 ps
CPU time 107.63 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:31:55 PM PDT 24
Peak memory 253944 kb
Host smart-5d696046-d626-4b78-9be4-b702d51f3d32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355864636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2355864636
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.3017725598
Short name T837
Test name
Test status
Simulation time 12094052205 ps
CPU time 19.73 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:25 PM PDT 24
Peak memory 216956 kb
Host smart-147b49e2-683d-4e42-be4e-46aa2cddb6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017725598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3017725598
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2121950398
Short name T411
Test name
Test status
Simulation time 1153747329 ps
CPU time 4.92 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:10 PM PDT 24
Peak memory 216836 kb
Host smart-2844683e-8963-4a53-935b-dfa147b9dc96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121950398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2121950398
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1654192682
Short name T619
Test name
Test status
Simulation time 174496576 ps
CPU time 1.16 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 207828 kb
Host smart-e385eef7-d3c8-4a45-8df7-8ac8fdcaa765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654192682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1654192682
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.623446564
Short name T855
Test name
Test status
Simulation time 78016348 ps
CPU time 0.88 seconds
Started Jul 21 06:30:06 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 206436 kb
Host smart-af490df8-e503-44ee-9ab3-f6891ca0a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623446564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.623446564
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2780598540
Short name T184
Test name
Test status
Simulation time 13463741122 ps
CPU time 19.85 seconds
Started Jul 21 06:30:05 PM PDT 24
Finished Jul 21 06:30:25 PM PDT 24
Peak memory 235172 kb
Host smart-b5c6d589-378d-4caa-afb4-adba3c9cf03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780598540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2780598540
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1926347821
Short name T791
Test name
Test status
Simulation time 378995134 ps
CPU time 3.59 seconds
Started Jul 21 06:30:09 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 224928 kb
Host smart-72ba52cd-3bc8-48fd-a5d7-e5a6bea39d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926347821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1926347821
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.334173460
Short name T984
Test name
Test status
Simulation time 38450392 ps
CPU time 0.77 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:30:11 PM PDT 24
Peak memory 207112 kb
Host smart-d525f6be-4b30-495f-9685-9e5ea0df92d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334173460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.334173460
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1216273995
Short name T814
Test name
Test status
Simulation time 13207967879 ps
CPU time 111.45 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 249900 kb
Host smart-5a8f5e68-2c7f-4adc-a00d-c16807c909d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216273995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1216273995
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.402323045
Short name T214
Test name
Test status
Simulation time 21208359127 ps
CPU time 192.44 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:33:23 PM PDT 24
Peak memory 249624 kb
Host smart-c6caae0f-52bb-4b30-a72e-8635d8deafb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402323045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.402323045
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2895667647
Short name T87
Test name
Test status
Simulation time 2011063173 ps
CPU time 12.08 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:30:24 PM PDT 24
Peak memory 235388 kb
Host smart-339ebbd8-2b12-434f-8cd8-07c47487a1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895667647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2895667647
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.124116891
Short name T310
Test name
Test status
Simulation time 132824417 ps
CPU time 2.47 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:30:14 PM PDT 24
Peak memory 233128 kb
Host smart-98f54581-5fbd-4832-8c65-68fb8f200763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124116891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.124116891
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.2911415907
Short name T851
Test name
Test status
Simulation time 757198723 ps
CPU time 12.66 seconds
Started Jul 21 06:30:09 PM PDT 24
Finished Jul 21 06:30:22 PM PDT 24
Peak memory 224852 kb
Host smart-fd3bf233-ba70-47a1-b162-d3b3cc59cc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911415907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2911415907
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1028267899
Short name T255
Test name
Test status
Simulation time 1965900777 ps
CPU time 3.93 seconds
Started Jul 21 06:30:09 PM PDT 24
Finished Jul 21 06:30:14 PM PDT 24
Peak memory 227628 kb
Host smart-b4acab95-0f5b-409c-86ed-01c42e43dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028267899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1028267899
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2709408868
Short name T864
Test name
Test status
Simulation time 1837972217 ps
CPU time 8.76 seconds
Started Jul 21 06:30:09 PM PDT 24
Finished Jul 21 06:30:18 PM PDT 24
Peak memory 233064 kb
Host smart-87892800-f5f2-4563-b587-5c9bbdfea65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709408868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2709408868
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1617031961
Short name T801
Test name
Test status
Simulation time 904167759 ps
CPU time 7.99 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:30:20 PM PDT 24
Peak memory 220304 kb
Host smart-90e7be05-d000-468e-94e1-ac55e6f62b47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1617031961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1617031961
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2853164435
Short name T174
Test name
Test status
Simulation time 51791800990 ps
CPU time 356.32 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:36:08 PM PDT 24
Peak memory 266340 kb
Host smart-98c41065-9a56-4b40-8ccd-453d3a47cd1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853164435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2853164435
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3992529303
Short name T574
Test name
Test status
Simulation time 3015164043 ps
CPU time 27.57 seconds
Started Jul 21 06:30:12 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 216840 kb
Host smart-38c5e01d-ba03-4463-9acc-28a99c6b0590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992529303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3992529303
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.503788811
Short name T796
Test name
Test status
Simulation time 1074284813 ps
CPU time 5.08 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:30:17 PM PDT 24
Peak memory 216664 kb
Host smart-93e75367-ce1f-447a-a52c-924da98e0bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503788811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.503788811
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1716829248
Short name T646
Test name
Test status
Simulation time 854889773 ps
CPU time 3.27 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 216668 kb
Host smart-3a3ebd56-2436-4cf4-9921-6dbab89cb00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716829248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1716829248
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1648638473
Short name T653
Test name
Test status
Simulation time 222251993 ps
CPU time 0.8 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 206452 kb
Host smart-21e06260-7518-40b5-a2c7-85b7b03763d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648638473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1648638473
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.417203342
Short name T838
Test name
Test status
Simulation time 123705350 ps
CPU time 2.47 seconds
Started Jul 21 06:30:13 PM PDT 24
Finished Jul 21 06:30:16 PM PDT 24
Peak memory 224552 kb
Host smart-1738eb4a-2f20-4d47-aff4-d2ff14d6fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417203342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.417203342
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3786241782
Short name T874
Test name
Test status
Simulation time 28676628 ps
CPU time 0.68 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:18 PM PDT 24
Peak memory 206268 kb
Host smart-4223ac50-7be0-4a7d-8695-ed07407a3aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786241782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3786241782
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.3402762754
Short name T201
Test name
Test status
Simulation time 391695396 ps
CPU time 3.48 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:20 PM PDT 24
Peak memory 233096 kb
Host smart-c9cf97f7-5ebd-4594-9089-617b0ae1af35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402762754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.3402762754
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2005000483
Short name T890
Test name
Test status
Simulation time 24044723 ps
CPU time 0.79 seconds
Started Jul 21 06:30:09 PM PDT 24
Finished Jul 21 06:30:10 PM PDT 24
Peak memory 206044 kb
Host smart-9d3283f5-8f5d-4c84-bac2-3c5fec52209d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005000483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2005000483
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.852491518
Short name T848
Test name
Test status
Simulation time 30638081 ps
CPU time 0.77 seconds
Started Jul 21 06:30:18 PM PDT 24
Finished Jul 21 06:30:19 PM PDT 24
Peak memory 216232 kb
Host smart-9e2b85e0-c5b2-4cc4-a219-73d0ddc94a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852491518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.852491518
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2482901085
Short name T328
Test name
Test status
Simulation time 16073974174 ps
CPU time 79.17 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:31:36 PM PDT 24
Peak memory 252744 kb
Host smart-6990762e-873e-419d-90f4-cfee89677ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482901085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2482901085
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4679822
Short name T758
Test name
Test status
Simulation time 29774819193 ps
CPU time 311.08 seconds
Started Jul 21 06:30:15 PM PDT 24
Finished Jul 21 06:35:27 PM PDT 24
Peak memory 257788 kb
Host smart-8a58e71b-c04d-470d-9efb-74fb1b69376f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4679822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.4679822
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.899664387
Short name T883
Test name
Test status
Simulation time 323312222 ps
CPU time 4.7 seconds
Started Jul 21 06:30:17 PM PDT 24
Finished Jul 21 06:30:22 PM PDT 24
Peak memory 235956 kb
Host smart-855f2fce-4744-431e-a078-8b8d71370246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899664387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.899664387
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.4031557639
Short name T224
Test name
Test status
Simulation time 19631001534 ps
CPU time 182.07 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 267552 kb
Host smart-91e36412-1e4b-42cf-aaae-c8323f0eb218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031557639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.4031557639
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2261854812
Short name T86
Test name
Test status
Simulation time 897440013 ps
CPU time 11.19 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 233124 kb
Host smart-f02a5b2e-1df9-4357-8f46-2ba5e8534388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261854812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2261854812
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.977499837
Short name T192
Test name
Test status
Simulation time 2085825993 ps
CPU time 22.6 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 233112 kb
Host smart-325d8f0b-fb47-437d-8d76-93235a1059ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977499837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.977499837
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.700844903
Short name T297
Test name
Test status
Simulation time 672805014 ps
CPU time 3.45 seconds
Started Jul 21 06:30:20 PM PDT 24
Finished Jul 21 06:30:24 PM PDT 24
Peak memory 224968 kb
Host smart-8b111e10-0f2d-46cf-95a3-e0c3a59173f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700844903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.700844903
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1603860318
Short name T726
Test name
Test status
Simulation time 4869548885 ps
CPU time 5.55 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:22 PM PDT 24
Peak memory 225024 kb
Host smart-c2269154-9e7e-45eb-900d-4ad327602ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603860318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1603860318
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.838277808
Short name T719
Test name
Test status
Simulation time 340005191 ps
CPU time 3.66 seconds
Started Jul 21 06:30:21 PM PDT 24
Finished Jul 21 06:30:26 PM PDT 24
Peak memory 223656 kb
Host smart-ae2fba3e-62d0-478d-94a8-ff8bedaa4958
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=838277808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.838277808
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1050138924
Short name T338
Test name
Test status
Simulation time 35747288328 ps
CPU time 101.23 seconds
Started Jul 21 06:30:17 PM PDT 24
Finished Jul 21 06:31:59 PM PDT 24
Peak memory 255068 kb
Host smart-7b621e01-0441-4018-8f5f-c44927f5ff98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050138924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1050138924
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2877522612
Short name T497
Test name
Test status
Simulation time 66284697 ps
CPU time 0.72 seconds
Started Jul 21 06:30:10 PM PDT 24
Finished Jul 21 06:30:12 PM PDT 24
Peak memory 206212 kb
Host smart-7dd3adb5-30bc-4454-8956-9539f8182273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877522612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2877522612
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.665935607
Short name T755
Test name
Test status
Simulation time 3716975478 ps
CPU time 4.33 seconds
Started Jul 21 06:30:11 PM PDT 24
Finished Jul 21 06:30:16 PM PDT 24
Peak memory 216764 kb
Host smart-e8b3c8f2-c393-4781-9f00-ff9ec4dfcffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665935607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.665935607
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2667973445
Short name T617
Test name
Test status
Simulation time 756517198 ps
CPU time 1.65 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:18 PM PDT 24
Peak memory 216688 kb
Host smart-b31700ee-2b95-4d72-95d6-39c092d54cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667973445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2667973445
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2235797083
Short name T892
Test name
Test status
Simulation time 14004277 ps
CPU time 0.72 seconds
Started Jul 21 06:30:21 PM PDT 24
Finished Jul 21 06:30:22 PM PDT 24
Peak memory 206104 kb
Host smart-9c3e32f3-6acb-40c0-af08-0a7d08885afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235797083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2235797083
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3951451795
Short name T259
Test name
Test status
Simulation time 1071958088 ps
CPU time 7.71 seconds
Started Jul 21 06:30:21 PM PDT 24
Finished Jul 21 06:30:30 PM PDT 24
Peak memory 224896 kb
Host smart-680e42db-0c3a-430a-a944-af9ffd81825d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951451795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3951451795
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3817763311
Short name T708
Test name
Test status
Simulation time 11432843 ps
CPU time 0.73 seconds
Started Jul 21 06:30:24 PM PDT 24
Finished Jul 21 06:30:25 PM PDT 24
Peak memory 206304 kb
Host smart-d464f2e8-bf73-4d35-a251-fdba06b79d57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817763311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3817763311
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1444680509
Short name T487
Test name
Test status
Simulation time 213721304 ps
CPU time 3.76 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:27 PM PDT 24
Peak memory 233092 kb
Host smart-34ccaf2f-38af-4d7b-955f-893914623768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444680509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1444680509
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3588048008
Short name T454
Test name
Test status
Simulation time 33894943 ps
CPU time 0.8 seconds
Started Jul 21 06:30:17 PM PDT 24
Finished Jul 21 06:30:18 PM PDT 24
Peak memory 207100 kb
Host smart-acabc636-a835-4aa6-a906-a4921c6feac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588048008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3588048008
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4119420142
Short name T952
Test name
Test status
Simulation time 2029061807 ps
CPU time 35.48 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 236816 kb
Host smart-6523461b-5e54-4ec8-beff-deba132a458c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119420142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4119420142
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.308008828
Short name T366
Test name
Test status
Simulation time 903900435 ps
CPU time 4.94 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 218068 kb
Host smart-95ee414c-b213-4002-aa2e-801910c7ce98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308008828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.308008828
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1539882057
Short name T730
Test name
Test status
Simulation time 8325176255 ps
CPU time 13.51 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:37 PM PDT 24
Peak memory 234212 kb
Host smart-a77c74f4-874c-4914-9405-bfb7a2377e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539882057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1539882057
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.154348908
Short name T228
Test name
Test status
Simulation time 9586848362 ps
CPU time 77.15 seconds
Started Jul 21 06:30:23 PM PDT 24
Finished Jul 21 06:31:41 PM PDT 24
Peak memory 239376 kb
Host smart-bec62682-32e3-4f7c-a349-5e7c3039ef99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154348908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.154348908
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4040999514
Short name T579
Test name
Test status
Simulation time 1307973130 ps
CPU time 4.93 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 224936 kb
Host smart-17b8cb75-49e8-43d8-b40a-60bda68f3957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040999514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4040999514
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.1053486610
Short name T951
Test name
Test status
Simulation time 1552272042 ps
CPU time 13.07 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 224796 kb
Host smart-42bf0a38-6915-4b2b-87e8-aa450fc00c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053486610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.1053486610
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.803469929
Short name T936
Test name
Test status
Simulation time 1408211641 ps
CPU time 3.69 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:27 PM PDT 24
Peak memory 224916 kb
Host smart-504d0027-145f-4490-8b23-e1fd5fcac2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803469929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.803469929
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3291490763
Short name T825
Test name
Test status
Simulation time 2380190191 ps
CPU time 12.94 seconds
Started Jul 21 06:30:27 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 233196 kb
Host smart-7f6164b4-f3b0-4bf4-8bb7-3cf07f64de13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291490763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3291490763
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2622414307
Short name T444
Test name
Test status
Simulation time 693168735 ps
CPU time 5.26 seconds
Started Jul 21 06:30:21 PM PDT 24
Finished Jul 21 06:30:27 PM PDT 24
Peak memory 222664 kb
Host smart-409a3f38-b985-4063-aa43-392146c651fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2622414307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2622414307
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1404384237
Short name T981
Test name
Test status
Simulation time 60437073896 ps
CPU time 451.14 seconds
Started Jul 21 06:30:21 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 267016 kb
Host smart-5c21d7da-4c91-487d-943c-5557dfe7a7dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404384237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1404384237
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.515965295
Short name T600
Test name
Test status
Simulation time 16458013521 ps
CPU time 18.27 seconds
Started Jul 21 06:30:21 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 216660 kb
Host smart-c02b3fdf-3e00-4c2e-989e-f557618ef587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515965295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.515965295
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.643738471
Short name T358
Test name
Test status
Simulation time 71325320985 ps
CPU time 19.24 seconds
Started Jul 21 06:30:16 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 216692 kb
Host smart-6caa47f0-fa52-4ad6-a96c-49ff4a1a0de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643738471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.643738471
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3331952438
Short name T53
Test name
Test status
Simulation time 29376640 ps
CPU time 0.97 seconds
Started Jul 21 06:30:27 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 208320 kb
Host smart-461129c0-55b8-432c-8785-1e9b6301d9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331952438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3331952438
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3373704853
Short name T152
Test name
Test status
Simulation time 52766320 ps
CPU time 0.72 seconds
Started Jul 21 06:30:23 PM PDT 24
Finished Jul 21 06:30:25 PM PDT 24
Peak memory 206608 kb
Host smart-4f08acde-6873-45ac-abb3-262b6f0b67ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373704853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3373704853
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1162681017
Short name T869
Test name
Test status
Simulation time 276159072 ps
CPU time 5.11 seconds
Started Jul 21 06:30:23 PM PDT 24
Finished Jul 21 06:30:29 PM PDT 24
Peak memory 224888 kb
Host smart-25a39f51-f5f5-48f6-beae-80363812ca5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162681017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1162681017
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1257659585
Short name T456
Test name
Test status
Simulation time 13618446 ps
CPU time 0.74 seconds
Started Jul 21 06:30:28 PM PDT 24
Finished Jul 21 06:30:29 PM PDT 24
Peak memory 205908 kb
Host smart-d39a943f-cf0f-432b-b723-05031c50f66a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257659585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1257659585
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.847376728
Short name T893
Test name
Test status
Simulation time 69798667 ps
CPU time 2.96 seconds
Started Jul 21 06:30:28 PM PDT 24
Finished Jul 21 06:30:31 PM PDT 24
Peak memory 233072 kb
Host smart-838788de-f837-479a-a86a-5f10e16cc9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847376728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.847376728
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.155599462
Short name T412
Test name
Test status
Simulation time 34317404 ps
CPU time 0.79 seconds
Started Jul 21 06:30:23 PM PDT 24
Finished Jul 21 06:30:24 PM PDT 24
Peak memory 207124 kb
Host smart-721f7b48-9b9b-4a83-a70b-8d1dbb68c39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155599462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.155599462
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3125769003
Short name T251
Test name
Test status
Simulation time 152387645028 ps
CPU time 169.17 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 233400 kb
Host smart-6c68fc59-f889-4422-a408-720477386159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125769003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3125769003
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3648221164
Short name T362
Test name
Test status
Simulation time 25406554472 ps
CPU time 89.93 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:32:01 PM PDT 24
Peak memory 252624 kb
Host smart-36c16c8a-246f-473a-8447-02c2cb467c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648221164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3648221164
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.278289243
Short name T154
Test name
Test status
Simulation time 23776623149 ps
CPU time 227.24 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 250640 kb
Host smart-efbe648d-dc1f-4636-8ad2-5f7b03ec00e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278289243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.278289243
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.763842516
Short name T168
Test name
Test status
Simulation time 297109000 ps
CPU time 8.63 seconds
Started Jul 21 06:30:31 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 225008 kb
Host smart-33ea1cd9-c842-44c7-914a-445e624d7747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763842516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.763842516
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.64022629
Short name T551
Test name
Test status
Simulation time 5637122025 ps
CPU time 52.7 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:31:22 PM PDT 24
Peak memory 239032 kb
Host smart-73b9ecc3-002b-4196-bab7-71d2a0a6ac29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64022629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.64022629
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1025352593
Short name T468
Test name
Test status
Simulation time 2680338411 ps
CPU time 14.29 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:37 PM PDT 24
Peak memory 233236 kb
Host smart-2dc8d461-bb55-4853-99f6-aa86c544f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025352593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1025352593
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2754590405
Short name T299
Test name
Test status
Simulation time 1832322883 ps
CPU time 26.74 seconds
Started Jul 21 06:30:31 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 234820 kb
Host smart-02f04caf-d6d4-4ffa-83a3-3c3b83145e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754590405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2754590405
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2676624513
Short name T244
Test name
Test status
Simulation time 6716227232 ps
CPU time 4.75 seconds
Started Jul 21 06:30:23 PM PDT 24
Finished Jul 21 06:30:29 PM PDT 24
Peak memory 224884 kb
Host smart-62053ce1-f644-4c95-ac67-b1641773fe86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676624513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2676624513
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2920473379
Short name T788
Test name
Test status
Simulation time 2221717812 ps
CPU time 10.45 seconds
Started Jul 21 06:30:23 PM PDT 24
Finished Jul 21 06:30:34 PM PDT 24
Peak memory 233164 kb
Host smart-aa5f52f5-2cb0-4eef-8081-90e6541d29b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920473379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2920473379
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.430335951
Short name T904
Test name
Test status
Simulation time 163230897 ps
CPU time 4.39 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:39 PM PDT 24
Peak memory 223512 kb
Host smart-89284d49-4d18-48ec-bcc8-9e21d74173bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=430335951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dire
ct.430335951
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3031285895
Short name T157
Test name
Test status
Simulation time 42183516756 ps
CPU time 170.07 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:33:20 PM PDT 24
Peak memory 249684 kb
Host smart-54c68671-8d44-4f14-addd-683bf1809cde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031285895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3031285895
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.320852402
Short name T629
Test name
Test status
Simulation time 1557195605 ps
CPU time 25.06 seconds
Started Jul 21 06:30:24 PM PDT 24
Finished Jul 21 06:30:49 PM PDT 24
Peak memory 216884 kb
Host smart-15e167ad-8eba-46d9-8dab-fb21c1eeac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320852402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.320852402
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.2161041121
Short name T381
Test name
Test status
Simulation time 21495274683 ps
CPU time 18.41 seconds
Started Jul 21 06:30:27 PM PDT 24
Finished Jul 21 06:30:46 PM PDT 24
Peak memory 216740 kb
Host smart-cfc44e47-edb6-4e99-80a4-c1e82cbdcb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161041121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.2161041121
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.632425333
Short name T778
Test name
Test status
Simulation time 109716179 ps
CPU time 1.45 seconds
Started Jul 21 06:30:22 PM PDT 24
Finished Jul 21 06:30:25 PM PDT 24
Peak memory 216660 kb
Host smart-f3d0f3d3-8b1f-40e4-b4e5-a5f33899c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632425333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.632425333
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2281077336
Short name T923
Test name
Test status
Simulation time 201089697 ps
CPU time 0.88 seconds
Started Jul 21 06:30:27 PM PDT 24
Finished Jul 21 06:30:28 PM PDT 24
Peak memory 206420 kb
Host smart-6da9c00b-338e-4aa4-b828-0ac1a8d79987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281077336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2281077336
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.879435754
Short name T246
Test name
Test status
Simulation time 83899685 ps
CPU time 2.62 seconds
Started Jul 21 06:30:31 PM PDT 24
Finished Jul 21 06:30:34 PM PDT 24
Peak memory 224860 kb
Host smart-00ac14bf-e6fa-49b2-a411-3f57efa3293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879435754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.879435754
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2504600245
Short name T637
Test name
Test status
Simulation time 59632776 ps
CPU time 0.78 seconds
Started Jul 21 06:30:32 PM PDT 24
Finished Jul 21 06:30:33 PM PDT 24
Peak memory 205408 kb
Host smart-6ce1cf09-709d-4550-931a-ba842df18bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504600245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2504600245
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1601407806
Short name T772
Test name
Test status
Simulation time 1104699329 ps
CPU time 3.83 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:38 PM PDT 24
Peak memory 224896 kb
Host smart-ffe0834e-0ac9-4fcd-9ab9-c5b98c8a3168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601407806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1601407806
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3536116647
Short name T420
Test name
Test status
Simulation time 62370595 ps
CPU time 0.83 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:30:31 PM PDT 24
Peak memory 207064 kb
Host smart-7812c984-046d-406e-8bf0-8a14d912d946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536116647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3536116647
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.463987800
Short name T779
Test name
Test status
Simulation time 3886005560 ps
CPU time 68.82 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:31:40 PM PDT 24
Peak memory 263012 kb
Host smart-34a438f1-85a7-4908-9b73-777a458751e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463987800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.463987800
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2703530462
Short name T771
Test name
Test status
Simulation time 8012260575 ps
CPU time 85.29 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 256740 kb
Host smart-4a361fc9-b169-441c-85ed-942a346914c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703530462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2703530462
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1363548362
Short name T677
Test name
Test status
Simulation time 2667248923 ps
CPU time 8.99 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:30:46 PM PDT 24
Peak memory 223468 kb
Host smart-b719cb4f-76bd-4940-bb13-6f79c3dae629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363548362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1363548362
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.802584732
Short name T368
Test name
Test status
Simulation time 91948152 ps
CPU time 2.68 seconds
Started Jul 21 06:30:31 PM PDT 24
Finished Jul 21 06:30:34 PM PDT 24
Peak memory 224936 kb
Host smart-8d2cb830-ce91-4688-9389-79d0a119982f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802584732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.802584732
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2356556397
Short name T258
Test name
Test status
Simulation time 94666047923 ps
CPU time 318.21 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:35:47 PM PDT 24
Peak memory 266048 kb
Host smart-d9768188-2b22-45dd-ae5c-88182f1809bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356556397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2356556397
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1284578419
Short name T656
Test name
Test status
Simulation time 55821920 ps
CPU time 2.51 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:30:32 PM PDT 24
Peak memory 232780 kb
Host smart-5f15644c-8445-4c06-912e-eea9e6a2c04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284578419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1284578419
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3331946237
Short name T513
Test name
Test status
Simulation time 2377922855 ps
CPU time 8.84 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 224976 kb
Host smart-8f843236-58ce-479a-95e5-db15a0f28b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331946237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3331946237
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1016670255
Short name T703
Test name
Test status
Simulation time 9216265588 ps
CPU time 9.34 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 233072 kb
Host smart-1f0da1aa-0255-4b20-b308-84895d0e66ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016670255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1016670255
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.233537779
Short name T515
Test name
Test status
Simulation time 225371210 ps
CPU time 4.48 seconds
Started Jul 21 06:30:40 PM PDT 24
Finished Jul 21 06:30:45 PM PDT 24
Peak memory 223572 kb
Host smart-3b56e6cc-3ae3-4133-a10c-d233ddf93192
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=233537779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dire
ct.233537779
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.541072517
Short name T143
Test name
Test status
Simulation time 54339722349 ps
CPU time 508.66 seconds
Started Jul 21 06:30:27 PM PDT 24
Finished Jul 21 06:38:57 PM PDT 24
Peak memory 265992 kb
Host smart-95c9fb1a-ff13-458c-9321-da3e43327ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541072517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.541072517
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.669971136
Short name T609
Test name
Test status
Simulation time 2310452591 ps
CPU time 19.02 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:54 PM PDT 24
Peak memory 216776 kb
Host smart-0275b559-d150-481d-b6e7-a84e48e00334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669971136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.669971136
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.791820504
Short name T404
Test name
Test status
Simulation time 9396318130 ps
CPU time 24.81 seconds
Started Jul 21 06:30:41 PM PDT 24
Finished Jul 21 06:31:07 PM PDT 24
Peak memory 216672 kb
Host smart-a40341bc-08b8-4f1f-b8ca-467ea4cba268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791820504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.791820504
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1194966372
Short name T792
Test name
Test status
Simulation time 420028748 ps
CPU time 4.29 seconds
Started Jul 21 06:30:31 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 216644 kb
Host smart-86c8874b-9f60-43f7-a9bc-4a598a3c0390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194966372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1194966372
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.2287814893
Short name T413
Test name
Test status
Simulation time 19594317 ps
CPU time 0.72 seconds
Started Jul 21 06:30:31 PM PDT 24
Finished Jul 21 06:30:32 PM PDT 24
Peak memory 206456 kb
Host smart-cc395628-4f55-4e95-b5ac-c1ef46dbcf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287814893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.2287814893
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2035347182
Short name T962
Test name
Test status
Simulation time 24392248819 ps
CPU time 10.43 seconds
Started Jul 21 06:30:29 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 224944 kb
Host smart-0782039a-7a5f-44cc-96c6-a11282baafed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035347182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2035347182
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2238208769
Short name T695
Test name
Test status
Simulation time 62780455 ps
CPU time 0.72 seconds
Started Jul 21 06:30:46 PM PDT 24
Finished Jul 21 06:30:48 PM PDT 24
Peak memory 205376 kb
Host smart-0ff22e96-c8d8-4714-8491-1cf7d65755a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238208769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2238208769
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3397941971
Short name T781
Test name
Test status
Simulation time 1648800988 ps
CPU time 17.79 seconds
Started Jul 21 06:30:46 PM PDT 24
Finished Jul 21 06:31:04 PM PDT 24
Peak memory 224948 kb
Host smart-a315a3c9-2dc8-48d5-bd33-f96d6649da0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397941971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3397941971
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2838782515
Short name T606
Test name
Test status
Simulation time 25626476 ps
CPU time 0.87 seconds
Started Jul 21 06:30:30 PM PDT 24
Finished Jul 21 06:30:32 PM PDT 24
Peak memory 207372 kb
Host smart-91a8673e-cf16-49d0-b74a-2e18d596aea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838782515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2838782515
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.375812708
Short name T696
Test name
Test status
Simulation time 4658872389 ps
CPU time 49.69 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:31:24 PM PDT 24
Peak memory 249700 kb
Host smart-505fd461-13f3-48bb-a1e4-0ec58271820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375812708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.375812708
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3640639
Short name T663
Test name
Test status
Simulation time 34689424395 ps
CPU time 133.17 seconds
Started Jul 21 06:30:35 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 257552 kb
Host smart-813ec03f-d2ad-472c-b554-58b3e36bc9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3640639
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.842475630
Short name T281
Test name
Test status
Simulation time 23337478509 ps
CPU time 230.68 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:34:28 PM PDT 24
Peak memory 251584 kb
Host smart-d929effb-31cb-4e3d-9cd3-82678f3fcd98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842475630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.842475630
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1972049690
Short name T833
Test name
Test status
Simulation time 240643524 ps
CPU time 6.98 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:30:44 PM PDT 24
Peak memory 241304 kb
Host smart-d7d6cbc6-88de-4d9d-89d8-483f28b6dbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972049690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1972049690
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.220845301
Short name T330
Test name
Test status
Simulation time 4284985870 ps
CPU time 70.14 seconds
Started Jul 21 06:30:47 PM PDT 24
Finished Jul 21 06:31:57 PM PDT 24
Peak memory 250048 kb
Host smart-927f8eda-70fa-408d-9dcb-5d32c0206655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220845301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.220845301
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3777865344
Short name T786
Test name
Test status
Simulation time 6719031780 ps
CPU time 26.03 seconds
Started Jul 21 06:30:44 PM PDT 24
Finished Jul 21 06:31:11 PM PDT 24
Peak memory 233224 kb
Host smart-47b1f48f-dc70-417f-b6b5-c0cd5f075bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777865344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3777865344
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3597242154
Short name T5
Test name
Test status
Simulation time 12651097538 ps
CPU time 53.95 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:31:31 PM PDT 24
Peak memory 233156 kb
Host smart-e1bb5774-550a-4024-845e-e4068298b7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597242154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3597242154
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3461902703
Short name T150
Test name
Test status
Simulation time 6140884981 ps
CPU time 8.17 seconds
Started Jul 21 06:30:40 PM PDT 24
Finished Jul 21 06:30:48 PM PDT 24
Peak memory 233220 kb
Host smart-9e56caa7-7e69-418c-8a63-05d5e9d0d9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461902703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3461902703
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2536773586
Short name T540
Test name
Test status
Simulation time 5695830813 ps
CPU time 17.63 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 224968 kb
Host smart-001a005b-627e-422b-8255-44fb83fd9c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536773586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2536773586
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2994701641
Short name T162
Test name
Test status
Simulation time 962158426 ps
CPU time 7.65 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:30:45 PM PDT 24
Peak memory 222608 kb
Host smart-decffe56-3005-4da1-87d5-3016780f84ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2994701641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2994701641
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3965027357
Short name T356
Test name
Test status
Simulation time 2865942748 ps
CPU time 27.02 seconds
Started Jul 21 06:30:44 PM PDT 24
Finished Jul 21 06:31:12 PM PDT 24
Peak memory 216776 kb
Host smart-a3e39da4-89a0-4f46-8f77-9ad302ce5840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965027357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3965027357
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2615586434
Short name T519
Test name
Test status
Simulation time 1333325163 ps
CPU time 2.29 seconds
Started Jul 21 06:30:33 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 208364 kb
Host smart-097cfad3-5a37-430d-be85-1bfe8634478a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615586434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2615586434
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.540183223
Short name T806
Test name
Test status
Simulation time 46917694 ps
CPU time 1.03 seconds
Started Jul 21 06:30:35 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 207540 kb
Host smart-5d79d752-af40-4f54-9c3d-3d765e798974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540183223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.540183223
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2515774880
Short name T514
Test name
Test status
Simulation time 21878748 ps
CPU time 0.78 seconds
Started Jul 21 06:30:35 PM PDT 24
Finished Jul 21 06:30:37 PM PDT 24
Peak memory 206388 kb
Host smart-009a9c50-2b75-471b-85a9-bd88a1e42935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515774880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2515774880
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3809090654
Short name T584
Test name
Test status
Simulation time 5283760928 ps
CPU time 5.41 seconds
Started Jul 21 06:30:39 PM PDT 24
Finished Jul 21 06:30:45 PM PDT 24
Peak memory 233168 kb
Host smart-b2bca98a-ce30-4e59-b3e8-f97f7b729830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809090654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3809090654
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2164514300
Short name T885
Test name
Test status
Simulation time 11114850 ps
CPU time 0.71 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:50 PM PDT 24
Peak memory 205984 kb
Host smart-cc237c0e-1d33-4317-9759-657903524819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164514300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2164514300
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2050374567
Short name T614
Test name
Test status
Simulation time 230963890 ps
CPU time 2.41 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:37 PM PDT 24
Peak memory 225064 kb
Host smart-3159b552-ce5a-4af9-b4ea-d902c0162b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050374567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2050374567
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.806479975
Short name T961
Test name
Test status
Simulation time 13305088 ps
CPU time 0.79 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:35 PM PDT 24
Peak memory 207084 kb
Host smart-bba1b558-a23b-4b54-ad83-31e138a66028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806479975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.806479975
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1061661526
Short name T249
Test name
Test status
Simulation time 17580538290 ps
CPU time 140.55 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 261956 kb
Host smart-04765918-1e6d-44e9-866a-2ca84150536e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061661526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1061661526
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2878575242
Short name T729
Test name
Test status
Simulation time 60972884655 ps
CPU time 82.62 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:32:14 PM PDT 24
Peak memory 253064 kb
Host smart-16b5299e-866d-4901-af4c-a512e6a65280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878575242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2878575242
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4248632479
Short name T633
Test name
Test status
Simulation time 56674947249 ps
CPU time 38.25 seconds
Started Jul 21 06:30:47 PM PDT 24
Finished Jul 21 06:31:25 PM PDT 24
Peak memory 232528 kb
Host smart-53f1da6a-9a28-4586-a80d-52008565d8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248632479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4248632479
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1307853007
Short name T49
Test name
Test status
Simulation time 34721540179 ps
CPU time 178.32 seconds
Started Jul 21 06:30:47 PM PDT 24
Finished Jul 21 06:33:46 PM PDT 24
Peak memory 267172 kb
Host smart-8de9f5ba-36af-43c9-a4d6-d98720aadedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307853007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1307853007
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3994380779
Short name T693
Test name
Test status
Simulation time 3691478490 ps
CPU time 11.36 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:30:46 PM PDT 24
Peak memory 224932 kb
Host smart-012eea6d-721b-4fc6-a2af-8914b9b5297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994380779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3994380779
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3525884989
Short name T304
Test name
Test status
Simulation time 15341263898 ps
CPU time 37.46 seconds
Started Jul 21 06:30:34 PM PDT 24
Finished Jul 21 06:31:13 PM PDT 24
Peak memory 241356 kb
Host smart-2ae5c46f-22fe-4a44-b0e2-672a2716af28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525884989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3525884989
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.198801418
Short name T669
Test name
Test status
Simulation time 40442624585 ps
CPU time 27.94 seconds
Started Jul 21 06:30:35 PM PDT 24
Finished Jul 21 06:31:03 PM PDT 24
Peak memory 224984 kb
Host smart-a94007e2-3647-4ffb-9b2c-5142a815ac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198801418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.198801418
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.833341442
Short name T655
Test name
Test status
Simulation time 212020622 ps
CPU time 2.64 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:30:39 PM PDT 24
Peak memory 233216 kb
Host smart-80aaef11-9cd2-44a7-8d3b-5b969191fe66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833341442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.833341442
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1543305514
Short name T523
Test name
Test status
Simulation time 1045070249 ps
CPU time 7.67 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 223528 kb
Host smart-77821da5-a9ae-4684-a100-16abc9d2e6a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1543305514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1543305514
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.272662948
Short name T861
Test name
Test status
Simulation time 2086796485 ps
CPU time 13.78 seconds
Started Jul 21 06:30:37 PM PDT 24
Finished Jul 21 06:30:52 PM PDT 24
Peak memory 216832 kb
Host smart-f437baf6-73b5-4b13-be18-2ffc61eaa98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272662948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.272662948
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1925015638
Short name T926
Test name
Test status
Simulation time 22030654722 ps
CPU time 17.02 seconds
Started Jul 21 06:30:36 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 216656 kb
Host smart-a062e462-88b6-42d3-b0cd-32373498839a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925015638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1925015638
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2616620267
Short name T569
Test name
Test status
Simulation time 128176600 ps
CPU time 0.77 seconds
Started Jul 21 06:30:35 PM PDT 24
Finished Jul 21 06:30:37 PM PDT 24
Peak memory 206440 kb
Host smart-3a56ddd7-323f-4704-86c6-46e116898711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616620267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2616620267
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2751869678
Short name T27
Test name
Test status
Simulation time 26895768 ps
CPU time 0.73 seconds
Started Jul 21 06:30:37 PM PDT 24
Finished Jul 21 06:30:39 PM PDT 24
Peak memory 206436 kb
Host smart-7f15b1e1-ee06-4785-8a9d-f5db9fe68d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751869678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2751869678
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3154785954
Short name T549
Test name
Test status
Simulation time 1259694318 ps
CPU time 6.35 seconds
Started Jul 21 06:30:37 PM PDT 24
Finished Jul 21 06:30:44 PM PDT 24
Peak memory 233072 kb
Host smart-9d727a54-36c1-48c6-86a6-a3a11eeee5a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154785954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3154785954
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2857590327
Short name T822
Test name
Test status
Simulation time 43375044 ps
CPU time 0.73 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:52 PM PDT 24
Peak memory 206252 kb
Host smart-ab669e1f-65cd-48b7-9d3d-937796f5d909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857590327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2857590327
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2887555509
Short name T701
Test name
Test status
Simulation time 2667189016 ps
CPU time 6.52 seconds
Started Jul 21 06:30:47 PM PDT 24
Finished Jul 21 06:30:54 PM PDT 24
Peak memory 233176 kb
Host smart-c5e0775b-a9e8-4829-92c3-62b9d2d4189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887555509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2887555509
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3104812037
Short name T507
Test name
Test status
Simulation time 17498385 ps
CPU time 0.82 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:30:49 PM PDT 24
Peak memory 207236 kb
Host smart-775accfb-5a5c-47f4-b491-868705c8f175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104812037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3104812037
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.4272410627
Short name T931
Test name
Test status
Simulation time 114128272 ps
CPU time 4.14 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:54 PM PDT 24
Peak memory 241348 kb
Host smart-1c261aaa-ba9b-4c40-85b1-6045fa29969d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272410627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.4272410627
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.136521879
Short name T511
Test name
Test status
Simulation time 870081806 ps
CPU time 3.48 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 224892 kb
Host smart-82d3d253-c05d-4931-8c63-735a7663ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136521879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.136521879
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3733896017
Short name T598
Test name
Test status
Simulation time 10713713195 ps
CPU time 20.72 seconds
Started Jul 21 06:30:58 PM PDT 24
Finished Jul 21 06:31:20 PM PDT 24
Peak memory 233188 kb
Host smart-afa45bb1-d324-41cb-bdf3-dcb1ae2785b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733896017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3733896017
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3020502228
Short name T453
Test name
Test status
Simulation time 8240103498 ps
CPU time 15.81 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:31:05 PM PDT 24
Peak memory 233264 kb
Host smart-7025a5cb-d1f0-43f8-b938-c58da7778903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020502228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3020502228
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3466522882
Short name T256
Test name
Test status
Simulation time 452505014 ps
CPU time 3.76 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:55 PM PDT 24
Peak memory 233172 kb
Host smart-7eb0ee7d-e2c7-4d9d-9461-a87498dc0a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466522882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3466522882
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2957721443
Short name T830
Test name
Test status
Simulation time 16968456571 ps
CPU time 14.3 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:31:03 PM PDT 24
Peak memory 233180 kb
Host smart-f1c062ff-c984-43c6-a7e2-0f871aa57b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957721443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2957721443
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1733883212
Short name T782
Test name
Test status
Simulation time 131326710 ps
CPU time 3.96 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:56 PM PDT 24
Peak memory 219440 kb
Host smart-affc88be-2d78-4906-b8f4-41938b4216de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1733883212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1733883212
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1990385668
Short name T178
Test name
Test status
Simulation time 30274041126 ps
CPU time 165.04 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 255784 kb
Host smart-89302496-7510-4420-a051-9dd057acc582
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990385668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1990385668
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.3266726212
Short name T544
Test name
Test status
Simulation time 37151165825 ps
CPU time 47.21 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:31:35 PM PDT 24
Peak memory 216860 kb
Host smart-cc2c4ed9-11f5-4674-a1c0-9825e1972eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266726212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3266726212
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3710493781
Short name T857
Test name
Test status
Simulation time 17728772359 ps
CPU time 21.66 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:31:11 PM PDT 24
Peak memory 216780 kb
Host smart-91f4f0bc-eb20-4b62-8d9b-0d584eb84326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710493781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3710493781
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2562660381
Short name T430
Test name
Test status
Simulation time 897600145 ps
CPU time 2.03 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:30:51 PM PDT 24
Peak memory 216624 kb
Host smart-9ef360ff-6609-4a40-8062-0cbb97e5077a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562660381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2562660381
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.4191207071
Short name T576
Test name
Test status
Simulation time 27923690 ps
CPU time 0.78 seconds
Started Jul 21 06:30:47 PM PDT 24
Finished Jul 21 06:30:48 PM PDT 24
Peak memory 206448 kb
Host smart-84c541e5-1022-4b40-923d-d5ef07eee4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191207071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.4191207071
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2040312965
Short name T684
Test name
Test status
Simulation time 1577876666 ps
CPU time 7.96 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:31:03 PM PDT 24
Peak memory 233076 kb
Host smart-7c9d581f-b63f-4ff0-b87d-c3b9ab6213b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040312965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2040312965
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1090930140
Short name T939
Test name
Test status
Simulation time 39317636 ps
CPU time 0.81 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 206196 kb
Host smart-21f7d3a7-b7ff-4318-a8ea-a174a5668f0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090930140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
090930140
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.878036993
Short name T650
Test name
Test status
Simulation time 1799061695 ps
CPU time 20.6 seconds
Started Jul 21 06:29:35 PM PDT 24
Finished Jul 21 06:29:56 PM PDT 24
Peak memory 233084 kb
Host smart-5a362a29-2d6c-4657-8923-d75f865f1ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878036993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.878036993
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2313639670
Short name T470
Test name
Test status
Simulation time 41848857 ps
CPU time 0.79 seconds
Started Jul 21 06:29:22 PM PDT 24
Finished Jul 21 06:29:23 PM PDT 24
Peak memory 207112 kb
Host smart-c3ef84b6-aa7b-470a-b7bb-6c91fab7d09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313639670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2313639670
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.959011826
Short name T928
Test name
Test status
Simulation time 75928228937 ps
CPU time 191.08 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:32:34 PM PDT 24
Peak memory 261584 kb
Host smart-37947735-1dfe-4de7-8364-ec4033192d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959011826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.959011826
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1534681517
Short name T563
Test name
Test status
Simulation time 2881145119 ps
CPU time 30.18 seconds
Started Jul 21 06:29:29 PM PDT 24
Finished Jul 21 06:30:00 PM PDT 24
Peak memory 225068 kb
Host smart-722ad787-62f8-43cb-aa99-b5cbacdb5a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534681517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1534681517
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.2963833612
Short name T681
Test name
Test status
Simulation time 566011854 ps
CPU time 3.01 seconds
Started Jul 21 06:29:21 PM PDT 24
Finished Jul 21 06:29:25 PM PDT 24
Peak memory 233288 kb
Host smart-e71472f0-8b9d-4fc3-9866-8b07237d36db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963833612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.2963833612
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4077636761
Short name T191
Test name
Test status
Simulation time 13539013610 ps
CPU time 93.84 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:31:08 PM PDT 24
Peak memory 257796 kb
Host smart-3693af01-975a-47a8-a1cc-be00ca716248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077636761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4077636761
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.4290150802
Short name T816
Test name
Test status
Simulation time 1714277759 ps
CPU time 12.49 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:29:36 PM PDT 24
Peak memory 228936 kb
Host smart-6b7c76c0-e250-4bf3-9438-694967a49f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290150802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.4290150802
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3744247515
Short name T676
Test name
Test status
Simulation time 20483118873 ps
CPU time 117.93 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:31:21 PM PDT 24
Peak memory 224012 kb
Host smart-83ec6886-ed5d-4005-ad1c-1457ae4d70c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744247515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3744247515
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3525560159
Short name T949
Test name
Test status
Simulation time 448469273 ps
CPU time 3.27 seconds
Started Jul 21 06:29:24 PM PDT 24
Finished Jul 21 06:29:27 PM PDT 24
Peak memory 233140 kb
Host smart-5639cd79-f11d-412c-855c-fd314f430663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525560159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3525560159
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.430585602
Short name T587
Test name
Test status
Simulation time 31684662 ps
CPU time 2.55 seconds
Started Jul 21 06:29:21 PM PDT 24
Finished Jul 21 06:29:24 PM PDT 24
Peak memory 233180 kb
Host smart-5ee4a5e4-7ced-4509-8dc8-3f39ca9da26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430585602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.430585602
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3345012759
Short name T416
Test name
Test status
Simulation time 323817543 ps
CPU time 4.84 seconds
Started Jul 21 06:29:21 PM PDT 24
Finished Jul 21 06:29:27 PM PDT 24
Peak memory 219888 kb
Host smart-75c1c4c0-a90f-412a-9d1c-0100ec242c09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3345012759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3345012759
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2550523002
Short name T79
Test name
Test status
Simulation time 326894921 ps
CPU time 1.26 seconds
Started Jul 21 06:29:26 PM PDT 24
Finished Jul 21 06:29:28 PM PDT 24
Peak memory 236116 kb
Host smart-ddef2043-b9b5-4877-8f57-b819944243c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550523002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2550523002
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2059376039
Short name T717
Test name
Test status
Simulation time 19323104903 ps
CPU time 23.15 seconds
Started Jul 21 06:29:22 PM PDT 24
Finished Jul 21 06:29:46 PM PDT 24
Peak memory 216708 kb
Host smart-f4d84f28-13b7-44a6-b613-e3837e685724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059376039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2059376039
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4110114076
Short name T562
Test name
Test status
Simulation time 1556184717 ps
CPU time 6.26 seconds
Started Jul 21 06:29:22 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 216648 kb
Host smart-ab26ff9b-74e8-4b91-a680-ea9c7fa323fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110114076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4110114076
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3895948076
Short name T31
Test name
Test status
Simulation time 44418921 ps
CPU time 1.13 seconds
Started Jul 21 06:29:22 PM PDT 24
Finished Jul 21 06:29:24 PM PDT 24
Peak memory 208408 kb
Host smart-50b2a67b-de3e-4ca7-baa5-0004474d6a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895948076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3895948076
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2667486771
Short name T97
Test name
Test status
Simulation time 409542314 ps
CPU time 0.98 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:29:25 PM PDT 24
Peak memory 207464 kb
Host smart-c22c4e00-9051-446b-82a6-b6e382271b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667486771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2667486771
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.726742726
Short name T687
Test name
Test status
Simulation time 107533815863 ps
CPU time 24.78 seconds
Started Jul 21 06:29:23 PM PDT 24
Finished Jul 21 06:29:48 PM PDT 24
Peak memory 233152 kb
Host smart-08a7bcd8-2324-4637-9d83-bd1eb7a1026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726742726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.726742726
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1452596813
Short name T974
Test name
Test status
Simulation time 54525298 ps
CPU time 0.75 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 205868 kb
Host smart-d8eb615f-e82f-44d2-b5f3-a557529e27e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452596813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1452596813
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.1808642446
Short name T315
Test name
Test status
Simulation time 2884172055 ps
CPU time 7.25 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 233148 kb
Host smart-1dd9603c-3421-40dc-99a2-cecc31f03e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808642446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.1808642446
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3428085374
Short name T471
Test name
Test status
Simulation time 14873847 ps
CPU time 0.82 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:30:49 PM PDT 24
Peak memory 207092 kb
Host smart-0b313ecb-fa1c-4a44-9b84-8a8623d9e3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428085374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3428085374
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3670486586
Short name T906
Test name
Test status
Simulation time 6584670233 ps
CPU time 111.43 seconds
Started Jul 21 06:30:52 PM PDT 24
Finished Jul 21 06:32:44 PM PDT 24
Peak memory 249628 kb
Host smart-a28d9716-65c7-4053-b384-d9d7482c7b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670486586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3670486586
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3256090056
Short name T591
Test name
Test status
Simulation time 876738959 ps
CPU time 16.7 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:31:07 PM PDT 24
Peak memory 234484 kb
Host smart-9db3e643-4727-4729-9de3-0a222237dcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256090056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3256090056
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3594330763
Short name T197
Test name
Test status
Simulation time 17984246449 ps
CPU time 37.31 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:31:28 PM PDT 24
Peak memory 256324 kb
Host smart-ecfb073a-ec75-4908-bd4f-c34e508a639d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594330763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3594330763
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.452569705
Short name T813
Test name
Test status
Simulation time 1188877191 ps
CPU time 5.03 seconds
Started Jul 21 06:30:52 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 233120 kb
Host smart-b8e8abe7-512e-4cfc-b2d7-df60add641e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452569705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.452569705
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.852088174
Short name T282
Test name
Test status
Simulation time 3142365783 ps
CPU time 26.43 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:31:17 PM PDT 24
Peak memory 240744 kb
Host smart-b050b897-cbbc-4e88-9272-4eb503a0e074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852088174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.852088174
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.450220089
Short name T103
Test name
Test status
Simulation time 10960689813 ps
CPU time 19.81 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:31:11 PM PDT 24
Peak memory 225004 kb
Host smart-24381d98-2b96-46bb-a5f4-cd91f16e8202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450220089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.450220089
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3042257857
Short name T754
Test name
Test status
Simulation time 135468112 ps
CPU time 1.93 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:52 PM PDT 24
Peak memory 223220 kb
Host smart-754c3449-54d2-4934-bc70-23e64fb1da58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042257857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3042257857
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.899860387
Short name T651
Test name
Test status
Simulation time 1732092745 ps
CPU time 6.91 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 222484 kb
Host smart-4942de22-3b27-42ca-bce2-9c082b3a587e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=899860387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.899860387
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2507510942
Short name T221
Test name
Test status
Simulation time 397473392729 ps
CPU time 602.85 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 273928 kb
Host smart-bc560076-8500-4d3f-b54e-f1b382f44271
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507510942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2507510942
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3424119152
Short name T956
Test name
Test status
Simulation time 2227025815 ps
CPU time 12.63 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:31:05 PM PDT 24
Peak memory 216756 kb
Host smart-8bcf67fa-2878-4ffd-8130-f14b3caf1301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424119152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3424119152
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2421288629
Short name T636
Test name
Test status
Simulation time 106333413498 ps
CPU time 20.14 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:31:12 PM PDT 24
Peak memory 216764 kb
Host smart-8c02529c-e9d9-49b5-9f7e-a8a9ee9c4ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421288629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2421288629
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2355849891
Short name T715
Test name
Test status
Simulation time 10328754 ps
CPU time 0.67 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:52 PM PDT 24
Peak memory 206100 kb
Host smart-b895b23f-a840-42af-972f-760177c1e3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355849891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2355849891
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1721063683
Short name T98
Test name
Test status
Simulation time 143702562 ps
CPU time 1.09 seconds
Started Jul 21 06:30:50 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 207464 kb
Host smart-ed520677-4f12-4dd9-a8a3-8cdb69ef9d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721063683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1721063683
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2946178294
Short name T881
Test name
Test status
Simulation time 14799711810 ps
CPU time 21.01 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:31:10 PM PDT 24
Peak memory 233168 kb
Host smart-97e942e3-2e5c-408f-905a-c6a3de50219c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946178294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2946178294
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2925729636
Short name T832
Test name
Test status
Simulation time 12184383 ps
CPU time 0.73 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:30:57 PM PDT 24
Peak memory 206268 kb
Host smart-8aa170df-e508-411f-8dc0-dd802e401e45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925729636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2925729636
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2870258637
Short name T795
Test name
Test status
Simulation time 106617199 ps
CPU time 3.1 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 224884 kb
Host smart-b78d4458-f468-472f-abfb-e9b46ae710ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870258637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2870258637
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2680246248
Short name T958
Test name
Test status
Simulation time 15611832 ps
CPU time 0.82 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:51 PM PDT 24
Peak memory 207088 kb
Host smart-05bcb6d2-0c4e-48b6-8e3d-af77b2804a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680246248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2680246248
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.4119086865
Short name T242
Test name
Test status
Simulation time 1563796765 ps
CPU time 20.71 seconds
Started Jul 21 06:30:54 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 238708 kb
Host smart-d0c78176-45a2-47b2-b349-1e574565cd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119086865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4119086865
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2126757157
Short name T595
Test name
Test status
Simulation time 5867963724 ps
CPU time 38.46 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:31:36 PM PDT 24
Peak memory 261940 kb
Host smart-67d9279c-133b-40c1-94e9-ebc217d747d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126757157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2126757157
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3931915883
Short name T254
Test name
Test status
Simulation time 2862534240 ps
CPU time 34.92 seconds
Started Jul 21 06:30:54 PM PDT 24
Finished Jul 21 06:31:30 PM PDT 24
Peak memory 254784 kb
Host smart-01e95267-bd82-400a-b5a5-e7cd9607cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931915883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3931915883
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1516389546
Short name T688
Test name
Test status
Simulation time 128056736 ps
CPU time 4.66 seconds
Started Jul 21 06:30:52 PM PDT 24
Finished Jul 21 06:30:57 PM PDT 24
Peak memory 227700 kb
Host smart-e01069cd-b8fa-48e4-aeed-c21a7e1d90ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516389546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1516389546
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2855782657
Short name T223
Test name
Test status
Simulation time 15786554744 ps
CPU time 125.05 seconds
Started Jul 21 06:30:52 PM PDT 24
Finished Jul 21 06:32:58 PM PDT 24
Peak memory 236432 kb
Host smart-e5f37584-d5f1-41d9-9cd5-2bc3e63973ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855782657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2855782657
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2408045595
Short name T527
Test name
Test status
Simulation time 3926312717 ps
CPU time 11.11 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:31:03 PM PDT 24
Peak memory 233196 kb
Host smart-49b7ac44-6774-4c34-af7e-2e9878c095b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408045595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2408045595
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1930623031
Short name T268
Test name
Test status
Simulation time 1580329948 ps
CPU time 3.15 seconds
Started Jul 21 06:30:49 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 224968 kb
Host smart-521f4a55-71bf-404d-a3da-1863d2bc0c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930623031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1930623031
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4235893172
Short name T624
Test name
Test status
Simulation time 876568156 ps
CPU time 9.46 seconds
Started Jul 21 06:30:54 PM PDT 24
Finished Jul 21 06:31:04 PM PDT 24
Peak memory 222008 kb
Host smart-0c164905-c8ed-4c36-8f1f-2f904a4bf969
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4235893172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4235893172
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3993721401
Short name T746
Test name
Test status
Simulation time 8064318486 ps
CPU time 91.48 seconds
Started Jul 21 06:30:54 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 256332 kb
Host smart-1c02ba65-4a2b-4226-9ba1-ab475a04c5b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993721401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3993721401
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2385719944
Short name T365
Test name
Test status
Simulation time 7788275454 ps
CPU time 46.92 seconds
Started Jul 21 06:30:52 PM PDT 24
Finished Jul 21 06:31:40 PM PDT 24
Peak memory 215736 kb
Host smart-8d8f9efa-c390-48b8-a6fb-c41562665a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385719944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2385719944
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2599283040
Short name T490
Test name
Test status
Simulation time 19583848 ps
CPU time 0.69 seconds
Started Jul 21 06:30:48 PM PDT 24
Finished Jul 21 06:30:49 PM PDT 24
Peak memory 206168 kb
Host smart-9be445eb-86e5-4e6d-974f-927e8bcab7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599283040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2599283040
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3814392155
Short name T33
Test name
Test status
Simulation time 285302770 ps
CPU time 2.02 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:30:54 PM PDT 24
Peak memory 216732 kb
Host smart-028cd26f-f00c-46c7-95a7-e6e7ff4f6296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814392155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3814392155
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.726383965
Short name T680
Test name
Test status
Simulation time 209860790 ps
CPU time 1.06 seconds
Started Jul 21 06:30:51 PM PDT 24
Finished Jul 21 06:30:53 PM PDT 24
Peak memory 207468 kb
Host smart-8528cd4d-a0ef-4719-b54d-7d4d03e2cea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726383965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.726383965
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2600525614
Short name T533
Test name
Test status
Simulation time 15879089042 ps
CPU time 52 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:31:47 PM PDT 24
Peak memory 249576 kb
Host smart-fa854dfe-04de-4e22-ae28-193247004590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600525614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2600525614
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2649684094
Short name T605
Test name
Test status
Simulation time 13409834 ps
CPU time 0.71 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 205380 kb
Host smart-fd5fef97-ee64-4630-9731-c757609d20ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649684094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2649684094
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3317749802
Short name T907
Test name
Test status
Simulation time 921637598 ps
CPU time 2.73 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 233168 kb
Host smart-61527e8b-6a9e-42bc-ba04-aa3ee2cf51d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317749802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3317749802
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2333079699
Short name T491
Test name
Test status
Simulation time 39057914 ps
CPU time 0.79 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 207092 kb
Host smart-84888a0e-1607-4169-aab6-380c5198095b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333079699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2333079699
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2021126464
Short name T971
Test name
Test status
Simulation time 43248314016 ps
CPU time 77.7 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 234552 kb
Host smart-1b334c7b-c0a5-4394-9813-69c2f67d0e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021126464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2021126464
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3238969165
Short name T238
Test name
Test status
Simulation time 15029689350 ps
CPU time 111.99 seconds
Started Jul 21 06:30:58 PM PDT 24
Finished Jul 21 06:32:51 PM PDT 24
Peak memory 266052 kb
Host smart-593bb788-1f7c-4e93-96a0-1bb8d9ab760e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238969165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3238969165
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3663106837
Short name T59
Test name
Test status
Simulation time 28492042197 ps
CPU time 295.77 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:35:56 PM PDT 24
Peak memory 266056 kb
Host smart-90d240d8-54dd-4bd9-bdcd-e02ac6c7cd06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663106837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3663106837
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.40358593
Short name T790
Test name
Test status
Simulation time 4245583490 ps
CPU time 66.06 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:32:03 PM PDT 24
Peak memory 238616 kb
Host smart-a8d5df4d-3160-4bae-a866-c7095266b410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40358593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.40358593
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3878871476
Short name T946
Test name
Test status
Simulation time 6972996536 ps
CPU time 22.83 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:31:21 PM PDT 24
Peak memory 249620 kb
Host smart-1b36d369-3079-46a8-9c51-8eb1944c1b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878871476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3878871476
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2346623089
Short name T1007
Test name
Test status
Simulation time 144727317 ps
CPU time 4.84 seconds
Started Jul 21 06:30:58 PM PDT 24
Finished Jul 21 06:31:04 PM PDT 24
Peak memory 233104 kb
Host smart-22bf931f-0051-469c-91a8-c77b5ca92a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346623089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2346623089
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3725074827
Short name T504
Test name
Test status
Simulation time 6176737638 ps
CPU time 23.84 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:31:20 PM PDT 24
Peak memory 233128 kb
Host smart-eeaf40b3-e076-47ba-8968-d828db8e9616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725074827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3725074827
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2940643876
Short name T950
Test name
Test status
Simulation time 3379294699 ps
CPU time 5.57 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:31:01 PM PDT 24
Peak memory 225012 kb
Host smart-0a5fb771-7de6-42ba-8ab4-9dd771935b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940643876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2940643876
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3334362173
Short name T573
Test name
Test status
Simulation time 348232934 ps
CPU time 2.57 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 219148 kb
Host smart-a515843c-8310-4b50-88bd-44722d52dfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334362173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3334362173
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.966609395
Short name T169
Test name
Test status
Simulation time 283655964 ps
CPU time 3.34 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:31:02 PM PDT 24
Peak memory 219488 kb
Host smart-c9a960fd-d080-480f-b594-508b64a43fc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=966609395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.966609395
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.4042766363
Short name T354
Test name
Test status
Simulation time 6741365844 ps
CPU time 14.27 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:31:11 PM PDT 24
Peak memory 216788 kb
Host smart-e8942b26-739f-4fd9-b5c5-e77ebf095a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042766363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.4042766363
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.740440566
Short name T765
Test name
Test status
Simulation time 1104035327 ps
CPU time 3.03 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:31:01 PM PDT 24
Peak memory 216704 kb
Host smart-8086659f-8999-4339-af39-b37f49533803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740440566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.740440566
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.323879201
Short name T55
Test name
Test status
Simulation time 12688716 ps
CPU time 0.76 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:30:57 PM PDT 24
Peak memory 206452 kb
Host smart-85016aa3-448e-4d14-b3c5-0732430351e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323879201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.323879201
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3848498117
Short name T546
Test name
Test status
Simulation time 18288935 ps
CPU time 0.74 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 206436 kb
Host smart-f14704cb-2702-476c-967b-eba7afec1b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848498117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3848498117
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1669231024
Short name T461
Test name
Test status
Simulation time 242758880 ps
CPU time 2.36 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:30:58 PM PDT 24
Peak memory 224932 kb
Host smart-f21e3422-7105-4528-933d-035bc8f92957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669231024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1669231024
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2749885436
Short name T402
Test name
Test status
Simulation time 46278088 ps
CPU time 0.74 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:31:02 PM PDT 24
Peak memory 205376 kb
Host smart-e95ada9b-842c-4f8c-a632-999bc76bf8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749885436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2749885436
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.2390553244
Short name T566
Test name
Test status
Simulation time 461115628 ps
CPU time 3.39 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 224972 kb
Host smart-4b63b15a-dd5c-476f-8b33-a931ad0f6153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390553244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.2390553244
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3532995368
Short name T559
Test name
Test status
Simulation time 24536623 ps
CPU time 0.73 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 206064 kb
Host smart-6e761172-f341-4103-a07e-dd78a7240b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532995368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3532995368
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.813702159
Short name T597
Test name
Test status
Simulation time 45280092 ps
CPU time 0.77 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:31:01 PM PDT 24
Peak memory 216276 kb
Host smart-69397e60-39e3-499e-9845-9f3e2fee3de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813702159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.813702159
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.53399818
Short name T359
Test name
Test status
Simulation time 5890869604 ps
CPU time 59.87 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:31:57 PM PDT 24
Peak memory 238392 kb
Host smart-baebbe38-d9b9-437a-837b-79c2a294bed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53399818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.53399818
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3324493068
Short name T200
Test name
Test status
Simulation time 1427233218 ps
CPU time 20.82 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 240772 kb
Host smart-fcbe3308-4d20-42d3-8440-3eb17d0d3fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324493068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3324493068
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1126598821
Short name T652
Test name
Test status
Simulation time 1128338793 ps
CPU time 17.43 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 241292 kb
Host smart-dc4b738c-ca79-4b62-bddc-dad0e02324c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126598821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1126598821
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2827370271
Short name T248
Test name
Test status
Simulation time 1207661013 ps
CPU time 9 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:31:07 PM PDT 24
Peak memory 224936 kb
Host smart-06f0764b-024a-406e-be9a-1991bd161e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827370271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2827370271
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3151162865
Short name T742
Test name
Test status
Simulation time 16653654448 ps
CPU time 33.99 seconds
Started Jul 21 06:30:58 PM PDT 24
Finished Jul 21 06:31:33 PM PDT 24
Peak memory 225036 kb
Host smart-b44dea32-f49c-40ea-ae50-fc6206b2fe2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151162865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3151162865
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.974212175
Short name T548
Test name
Test status
Simulation time 31639276635 ps
CPU time 65.65 seconds
Started Jul 21 06:30:55 PM PDT 24
Finished Jul 21 06:32:01 PM PDT 24
Peak memory 239416 kb
Host smart-65a85a81-b3e0-40e8-b9b3-cfa9dda7ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974212175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.974212175
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1407516057
Short name T634
Test name
Test status
Simulation time 71620270 ps
CPU time 2.47 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:31:03 PM PDT 24
Peak memory 233128 kb
Host smart-8a8db67f-d28b-40e2-b467-727637abe077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407516057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1407516057
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.2639664082
Short name T271
Test name
Test status
Simulation time 9729769533 ps
CPU time 33.32 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:31:30 PM PDT 24
Peak memory 249464 kb
Host smart-28269fd3-8e67-4282-ba48-0259fb50f139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639664082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2639664082
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3401842554
Short name T817
Test name
Test status
Simulation time 159028877 ps
CPU time 4.59 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:31:04 PM PDT 24
Peak memory 223540 kb
Host smart-28bcfb52-7d1f-46fd-bf9c-c15bd0a2228f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3401842554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3401842554
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1384444610
Short name T842
Test name
Test status
Simulation time 20369303836 ps
CPU time 70.89 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:32:12 PM PDT 24
Peak memory 254884 kb
Host smart-f83d826d-8155-409a-9847-beead49e4add
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384444610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1384444610
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.3359172391
Short name T492
Test name
Test status
Simulation time 43810102328 ps
CPU time 34.68 seconds
Started Jul 21 06:30:58 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 216780 kb
Host smart-a7153ec6-840c-489d-8932-a798786dc319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359172391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3359172391
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1412324457
Short name T375
Test name
Test status
Simulation time 2232212177 ps
CPU time 3.02 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:31:01 PM PDT 24
Peak memory 216804 kb
Host smart-64821252-65d4-46c7-9a7c-e9f19468c8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412324457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1412324457
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3208282458
Short name T360
Test name
Test status
Simulation time 105293660 ps
CPU time 1.46 seconds
Started Jul 21 06:30:57 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 216536 kb
Host smart-a9bc1889-b99b-4393-bfe5-9147360bbc52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208282458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3208282458
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.490669083
Short name T552
Test name
Test status
Simulation time 99138431 ps
CPU time 0.84 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:31:01 PM PDT 24
Peak memory 206516 kb
Host smart-0627d500-7946-47f1-810c-64e1e7e0405e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490669083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.490669083
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2439678859
Short name T603
Test name
Test status
Simulation time 98329049 ps
CPU time 2.55 seconds
Started Jul 21 06:30:56 PM PDT 24
Finished Jul 21 06:30:59 PM PDT 24
Peak memory 217180 kb
Host smart-b4411f6c-2835-42e6-9c88-8eecb154adf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439678859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2439678859
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2044710656
Short name T458
Test name
Test status
Simulation time 54676799 ps
CPU time 0.73 seconds
Started Jul 21 06:31:05 PM PDT 24
Finished Jul 21 06:31:06 PM PDT 24
Peak memory 205980 kb
Host smart-5bcc8d4f-0767-4b03-b2be-969c21558147
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044710656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2044710656
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3602669288
Short name T585
Test name
Test status
Simulation time 291491554 ps
CPU time 5.86 seconds
Started Jul 21 06:31:02 PM PDT 24
Finished Jul 21 06:31:08 PM PDT 24
Peak memory 233124 kb
Host smart-01de7f6a-99c5-434a-adde-b23cf98aa007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602669288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3602669288
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1734799770
Short name T66
Test name
Test status
Simulation time 19331783 ps
CPU time 0.81 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:31:03 PM PDT 24
Peak memory 207152 kb
Host smart-0a4ba356-fb2b-48e2-9afb-e0e91b070bde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734799770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1734799770
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2525176562
Short name T290
Test name
Test status
Simulation time 3439130823 ps
CPU time 27.69 seconds
Started Jul 21 06:31:03 PM PDT 24
Finished Jul 21 06:31:31 PM PDT 24
Peak memory 224976 kb
Host smart-3bfdd8a2-1613-49f4-aff1-7626469f8f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525176562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2525176562
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2906192312
Short name T649
Test name
Test status
Simulation time 14668939592 ps
CPU time 96.24 seconds
Started Jul 21 06:31:08 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 241468 kb
Host smart-43a6f9ce-b49b-4e80-aa6d-0895896e00b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906192312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2906192312
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.709086686
Short name T347
Test name
Test status
Simulation time 219724983 ps
CPU time 6.62 seconds
Started Jul 21 06:31:11 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 224832 kb
Host smart-4d167ac7-6cfe-4335-a890-a99148ca0a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709086686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.709086686
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2168404387
Short name T270
Test name
Test status
Simulation time 521985029 ps
CPU time 7.89 seconds
Started Jul 21 06:31:03 PM PDT 24
Finished Jul 21 06:31:11 PM PDT 24
Peak memory 224904 kb
Host smart-d7a321f0-c54c-4f3b-9eeb-aaac1f207638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168404387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2168404387
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1952117920
Short name T147
Test name
Test status
Simulation time 2437145979 ps
CPU time 8.59 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:31:10 PM PDT 24
Peak memory 233236 kb
Host smart-bfad92ae-6d43-4143-846d-237b7f934538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952117920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1952117920
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.3878679290
Short name T391
Test name
Test status
Simulation time 537768482 ps
CPU time 2.16 seconds
Started Jul 21 06:31:03 PM PDT 24
Finished Jul 21 06:31:06 PM PDT 24
Peak memory 224552 kb
Host smart-b6da49ad-28d7-43f4-8020-3baa5b57879d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878679290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.3878679290
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.507031149
Short name T985
Test name
Test status
Simulation time 9967247657 ps
CPU time 11.75 seconds
Started Jul 21 06:30:59 PM PDT 24
Finished Jul 21 06:31:12 PM PDT 24
Peak memory 233160 kb
Host smart-e749dd6d-9c7e-4d8d-8dae-fc3f25bf3ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507031149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.507031149
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3940677152
Short name T317
Test name
Test status
Simulation time 96710626 ps
CPU time 2.94 seconds
Started Jul 21 06:31:09 PM PDT 24
Finished Jul 21 06:31:13 PM PDT 24
Peak memory 233020 kb
Host smart-15a2caaa-51ab-4e0d-8534-5563756552d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940677152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3940677152
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1539051204
Short name T983
Test name
Test status
Simulation time 109739707 ps
CPU time 4.01 seconds
Started Jul 21 06:31:04 PM PDT 24
Finished Jul 21 06:31:08 PM PDT 24
Peak memory 223500 kb
Host smart-64fc9884-1f4b-46df-9592-dd8dd87210df
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1539051204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1539051204
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3822407863
Short name T327
Test name
Test status
Simulation time 145352515500 ps
CPU time 392.78 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 272232 kb
Host smart-87475d9c-0cb3-4320-8a0a-cf91b68101ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822407863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3822407863
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2199295674
Short name T899
Test name
Test status
Simulation time 12257966697 ps
CPU time 14.71 seconds
Started Jul 21 06:31:00 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 220308 kb
Host smart-bd53eca4-52d8-400d-a0d3-eadd05b2ff01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199295674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2199295674
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1474687471
Short name T711
Test name
Test status
Simulation time 6573046686 ps
CPU time 9.85 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:31:12 PM PDT 24
Peak memory 216844 kb
Host smart-cf31e566-14cf-42dc-ac15-c2c0f27307ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474687471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1474687471
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.981614692
Short name T580
Test name
Test status
Simulation time 64791655 ps
CPU time 0.97 seconds
Started Jul 21 06:31:05 PM PDT 24
Finished Jul 21 06:31:06 PM PDT 24
Peak memory 207472 kb
Host smart-0139412d-65e5-4d08-9db4-adbd7fd08f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981614692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.981614692
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.1996017900
Short name T642
Test name
Test status
Simulation time 15671985 ps
CPU time 0.73 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:31:02 PM PDT 24
Peak memory 206436 kb
Host smart-2ed54abc-0adf-4aa6-ab58-adb341ec301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996017900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1996017900
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.3302668683
Short name T446
Test name
Test status
Simulation time 44939827571 ps
CPU time 30.05 seconds
Started Jul 21 06:31:01 PM PDT 24
Finished Jul 21 06:31:32 PM PDT 24
Peak memory 234200 kb
Host smart-27654a96-9f75-4de7-a582-ec4bc027eccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302668683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.3302668683
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2335919155
Short name T602
Test name
Test status
Simulation time 16441264 ps
CPU time 0.71 seconds
Started Jul 21 06:31:05 PM PDT 24
Finished Jul 21 06:31:07 PM PDT 24
Peak memory 205860 kb
Host smart-60436e9d-a9ad-45b6-9d99-c6ec1fe3425d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335919155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2335919155
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3429785851
Short name T265
Test name
Test status
Simulation time 3455750594 ps
CPU time 10.6 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:31:17 PM PDT 24
Peak memory 233144 kb
Host smart-429d815a-076f-4455-b28b-a05b5594b8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429785851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3429785851
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.659783314
Short name T867
Test name
Test status
Simulation time 120432755 ps
CPU time 0.8 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:31:08 PM PDT 24
Peak memory 207380 kb
Host smart-243daed4-e714-4931-a18f-204eaa872aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659783314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.659783314
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1414695073
Short name T596
Test name
Test status
Simulation time 13532140816 ps
CPU time 55.28 seconds
Started Jul 21 06:31:05 PM PDT 24
Finished Jul 21 06:32:01 PM PDT 24
Peak memory 241440 kb
Host smart-d0e7c95d-37e6-4f40-9a4e-35b6e5fc59da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414695073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1414695073
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3656418885
Short name T189
Test name
Test status
Simulation time 13331383865 ps
CPU time 65.95 seconds
Started Jul 21 06:31:07 PM PDT 24
Finished Jul 21 06:32:14 PM PDT 24
Peak memory 257264 kb
Host smart-3113e20d-0d6f-44bf-a906-e3ba7b900224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656418885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3656418885
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3022020360
Short name T644
Test name
Test status
Simulation time 7903506556 ps
CPU time 128.81 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:33:16 PM PDT 24
Peak memory 254756 kb
Host smart-eb26c9e7-65ea-4acd-bdbb-c7dc7bd16256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022020360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3022020360
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2894885709
Short name T450
Test name
Test status
Simulation time 412287014 ps
CPU time 2.86 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:31:09 PM PDT 24
Peak memory 233016 kb
Host smart-3b83207e-557e-4937-9a69-e01d43f9c772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894885709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2894885709
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2559306697
Short name T100
Test name
Test status
Simulation time 10127314222 ps
CPU time 35.74 seconds
Started Jul 21 06:31:07 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 241448 kb
Host smart-8a81f43c-3c2c-4b8e-95f5-ae18ea30135c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559306697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2559306697
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1142318087
Short name T975
Test name
Test status
Simulation time 245224608 ps
CPU time 5.35 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:31:13 PM PDT 24
Peak memory 224908 kb
Host smart-b0db8c29-ae76-4af1-8726-8113adf4f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142318087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1142318087
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3618017964
Short name T462
Test name
Test status
Simulation time 470910757 ps
CPU time 6.96 seconds
Started Jul 21 06:31:07 PM PDT 24
Finished Jul 21 06:31:15 PM PDT 24
Peak memory 233084 kb
Host smart-bf64f386-705c-485d-8a55-cdbc9eff9d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618017964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3618017964
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3663628378
Short name T995
Test name
Test status
Simulation time 3936393892 ps
CPU time 12.63 seconds
Started Jul 21 06:31:04 PM PDT 24
Finished Jul 21 06:31:17 PM PDT 24
Peak memory 233164 kb
Host smart-f763147e-a3c4-4556-a35e-e2050665d50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663628378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3663628378
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.727257076
Short name T530
Test name
Test status
Simulation time 2638652888 ps
CPU time 3.42 seconds
Started Jul 21 06:31:07 PM PDT 24
Finished Jul 21 06:31:12 PM PDT 24
Peak memory 225012 kb
Host smart-8c34f817-f0d4-4dd9-a389-1d74322061b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727257076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.727257076
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1495685944
Short name T622
Test name
Test status
Simulation time 1036373426 ps
CPU time 15.35 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:31:23 PM PDT 24
Peak memory 219372 kb
Host smart-3b4f3949-1162-4e0d-ab25-96412aba59c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1495685944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1495685944
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2557762646
Short name T689
Test name
Test status
Simulation time 26749826082 ps
CPU time 154.98 seconds
Started Jul 21 06:31:06 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 250660 kb
Host smart-dabb19e1-f4a5-413a-8257-2ab11cc4e13f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557762646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2557762646
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2822111886
Short name T970
Test name
Test status
Simulation time 44985846493 ps
CPU time 58.66 seconds
Started Jul 21 06:31:05 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 216712 kb
Host smart-5110f502-4314-4ff0-a5c4-9f78421e0571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822111886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2822111886
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2360178746
Short name T393
Test name
Test status
Simulation time 23294514252 ps
CPU time 9.03 seconds
Started Jul 21 06:31:08 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 216828 kb
Host smart-007caddc-a4db-4b45-aecd-6983fe1d6a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360178746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2360178746
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2011732260
Short name T747
Test name
Test status
Simulation time 24732613 ps
CPU time 1.18 seconds
Started Jul 21 06:31:08 PM PDT 24
Finished Jul 21 06:31:10 PM PDT 24
Peak memory 208324 kb
Host smart-84da8919-ef14-4bc0-9626-903b362dbd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011732260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2011732260
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3439583723
Short name T957
Test name
Test status
Simulation time 368260129 ps
CPU time 0.96 seconds
Started Jul 21 06:31:07 PM PDT 24
Finished Jul 21 06:31:09 PM PDT 24
Peak memory 207436 kb
Host smart-959697c0-8db7-4d94-a333-29395130c3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439583723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3439583723
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.1890454811
Short name T541
Test name
Test status
Simulation time 1611443448 ps
CPU time 8.96 seconds
Started Jul 21 06:31:08 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 236800 kb
Host smart-6ee94100-eeb1-45f8-ba06-0172bf9a3886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890454811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1890454811
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1816445576
Short name T390
Test name
Test status
Simulation time 40945762 ps
CPU time 0.72 seconds
Started Jul 21 06:31:14 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 205912 kb
Host smart-72d27f31-7aff-4e0f-a9cc-0d2b4850627f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816445576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1816445576
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4223711930
Short name T724
Test name
Test status
Simulation time 300344959 ps
CPU time 2.39 seconds
Started Jul 21 06:31:13 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 224492 kb
Host smart-d802e0d2-5aae-4e97-b2da-a23043d7bda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223711930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4223711930
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.864194183
Short name T377
Test name
Test status
Simulation time 17878814 ps
CPU time 0.85 seconds
Started Jul 21 06:31:14 PM PDT 24
Finished Jul 21 06:31:16 PM PDT 24
Peak memory 207068 kb
Host smart-20f8003c-b605-4b37-96a2-537f48ab6f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864194183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.864194183
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1990652412
Short name T522
Test name
Test status
Simulation time 619631953 ps
CPU time 7.49 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:24 PM PDT 24
Peak memory 234232 kb
Host smart-f57ac089-3cf1-4424-a1d8-d69056cdfbd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990652412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1990652412
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3809995695
Short name T945
Test name
Test status
Simulation time 4711236652 ps
CPU time 73.09 seconds
Started Jul 21 06:31:16 PM PDT 24
Finished Jul 21 06:32:31 PM PDT 24
Peak memory 252896 kb
Host smart-8611dc96-016a-4576-9faa-be8f0fd27884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809995695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3809995695
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3515665504
Short name T58
Test name
Test status
Simulation time 7615238181 ps
CPU time 90.55 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:32:47 PM PDT 24
Peak memory 250028 kb
Host smart-84ccd9cb-31a6-4f42-ba2a-7545d647e282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515665504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3515665504
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.274432827
Short name T90
Test name
Test status
Simulation time 31190376482 ps
CPU time 128.66 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:33:24 PM PDT 24
Peak memory 249588 kb
Host smart-d40038a0-47ea-4bf1-b91b-9e7d12507121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274432827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.274432827
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.2006419541
Short name T909
Test name
Test status
Simulation time 151464773 ps
CPU time 5.21 seconds
Started Jul 21 06:31:16 PM PDT 24
Finished Jul 21 06:31:23 PM PDT 24
Peak memory 230076 kb
Host smart-e0c00153-507d-495a-b30e-d43750d48678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006419541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.2006419541
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.689383781
Short name T557
Test name
Test status
Simulation time 856767431 ps
CPU time 2.21 seconds
Started Jul 21 06:31:12 PM PDT 24
Finished Jul 21 06:31:15 PM PDT 24
Peak memory 219036 kb
Host smart-311a8225-39c6-4df5-9d0a-b3f2ac9c06ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689383781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.689383781
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.168510146
Short name T773
Test name
Test status
Simulation time 980322411 ps
CPU time 3.6 seconds
Started Jul 21 06:31:16 PM PDT 24
Finished Jul 21 06:31:22 PM PDT 24
Peak memory 224936 kb
Host smart-3b81d0e9-c863-48e8-8f06-d19b4c34a461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168510146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.168510146
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3272248045
Short name T62
Test name
Test status
Simulation time 12371025400 ps
CPU time 5.38 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:22 PM PDT 24
Peak memory 224860 kb
Host smart-dfa27179-a77e-49a9-9f74-e37a68024776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272248045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3272248045
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.2521297041
Short name T28
Test name
Test status
Simulation time 919326662 ps
CPU time 4.16 seconds
Started Jul 21 06:31:13 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 222984 kb
Host smart-a1187c2e-bda7-4c6f-bd16-2c61780dc280
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2521297041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.2521297041
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.138309676
Short name T175
Test name
Test status
Simulation time 24079384834 ps
CPU time 257.54 seconds
Started Jul 21 06:31:19 PM PDT 24
Finished Jul 21 06:35:37 PM PDT 24
Peak memory 257616 kb
Host smart-7485b782-290f-4f8a-b27d-8865d6ddf561
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138309676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.138309676
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1186460390
Short name T734
Test name
Test status
Simulation time 6056620405 ps
CPU time 15.55 seconds
Started Jul 21 06:31:13 PM PDT 24
Finished Jul 21 06:31:29 PM PDT 24
Peak memory 216800 kb
Host smart-be27fbb7-97e0-4ce7-bdf9-d88dc3524f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186460390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1186460390
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3518501676
Short name T831
Test name
Test status
Simulation time 18807167 ps
CPU time 0.75 seconds
Started Jul 21 06:31:16 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 206188 kb
Host smart-3121bbcf-a23b-4c73-bb60-adb1aaceec57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518501676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3518501676
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.4177178593
Short name T558
Test name
Test status
Simulation time 13693638 ps
CPU time 0.72 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 206468 kb
Host smart-e3c03ccd-4a95-43f2-8e22-17eb97e814a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177178593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4177178593
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3915018392
Short name T442
Test name
Test status
Simulation time 34350873 ps
CPU time 0.83 seconds
Started Jul 21 06:31:17 PM PDT 24
Finished Jul 21 06:31:19 PM PDT 24
Peak memory 206444 kb
Host smart-8b80cf65-ea8c-4bb5-8b68-a49064ceefe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915018392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3915018392
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.4238646219
Short name T308
Test name
Test status
Simulation time 1234270757 ps
CPU time 7.62 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:24 PM PDT 24
Peak memory 225060 kb
Host smart-8cade620-dd63-47dc-80ed-ccfc39eb6c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238646219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.4238646219
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.155696448
Short name T399
Test name
Test status
Simulation time 35777373 ps
CPU time 0.72 seconds
Started Jul 21 06:31:18 PM PDT 24
Finished Jul 21 06:31:20 PM PDT 24
Peak memory 206176 kb
Host smart-9d99290c-e7d2-4880-a442-53ff4f0f7f50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155696448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.155696448
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.440295214
Short name T51
Test name
Test status
Simulation time 242981226 ps
CPU time 2.78 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:31:24 PM PDT 24
Peak memory 224968 kb
Host smart-0298e6cb-3ea7-41c3-8718-8d3236c4bddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440295214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.440295214
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.24557901
Short name T870
Test name
Test status
Simulation time 61447503 ps
CPU time 0.79 seconds
Started Jul 21 06:31:16 PM PDT 24
Finished Jul 21 06:31:19 PM PDT 24
Peak memory 206340 kb
Host smart-e7d73f4a-89b3-4470-886d-b02b198cf6c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24557901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.24557901
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1051121260
Short name T607
Test name
Test status
Simulation time 8202404657 ps
CPU time 147.79 seconds
Started Jul 21 06:31:23 PM PDT 24
Finished Jul 21 06:33:51 PM PDT 24
Peak memory 273268 kb
Host smart-ba6ea45a-f709-4c47-83d4-4629cbec1176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051121260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1051121260
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.3482480911
Short name T594
Test name
Test status
Simulation time 13342525776 ps
CPU time 34.32 seconds
Started Jul 21 06:31:21 PM PDT 24
Finished Jul 21 06:31:56 PM PDT 24
Peak memory 224968 kb
Host smart-7756c9b5-f939-4741-98f2-5a17124dd808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482480911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.3482480911
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.4188763715
Short name T195
Test name
Test status
Simulation time 1510888191 ps
CPU time 14.97 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:31:36 PM PDT 24
Peak memory 235140 kb
Host smart-aede98a5-f8de-4f3f-81e6-642298caddcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188763715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.4188763715
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3148902167
Short name T232
Test name
Test status
Simulation time 302205878 ps
CPU time 3.56 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:31:25 PM PDT 24
Peak memory 224912 kb
Host smart-2a95041e-997f-47ee-b1aa-17b28d9d0169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148902167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3148902167
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3369106467
Short name T219
Test name
Test status
Simulation time 3514308005 ps
CPU time 42.57 seconds
Started Jul 21 06:31:19 PM PDT 24
Finished Jul 21 06:32:03 PM PDT 24
Peak memory 241348 kb
Host smart-c159eee9-e34c-4702-87d7-140721762692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369106467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3369106467
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2692778231
Short name T298
Test name
Test status
Simulation time 1989147804 ps
CPU time 4.7 seconds
Started Jul 21 06:31:14 PM PDT 24
Finished Jul 21 06:31:19 PM PDT 24
Peak memory 224904 kb
Host smart-a2246b0b-45e5-40dc-b7e9-4f325d873649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692778231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2692778231
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1002123088
Short name T871
Test name
Test status
Simulation time 54212840980 ps
CPU time 33.97 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:51 PM PDT 24
Peak memory 233248 kb
Host smart-c2ebcd06-ead2-40be-b88d-841483d09932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002123088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1002123088
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1521112258
Short name T486
Test name
Test status
Simulation time 8463686043 ps
CPU time 9 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:31:30 PM PDT 24
Peak memory 223600 kb
Host smart-a2f13e49-cf71-41c2-912a-33c0a65c2297
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521112258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1521112258
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3801172946
Short name T989
Test name
Test status
Simulation time 21755459344 ps
CPU time 72.99 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:32:34 PM PDT 24
Peak memory 263636 kb
Host smart-5d8e5e14-9ccb-408c-a584-d4a5742bfee3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801172946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3801172946
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3824568311
Short name T352
Test name
Test status
Simulation time 14748473033 ps
CPU time 22.47 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:38 PM PDT 24
Peak memory 217780 kb
Host smart-5bf20413-9b74-4e8b-8281-e35f72865eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824568311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3824568311
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1236031625
Short name T639
Test name
Test status
Simulation time 2565614378 ps
CPU time 6.28 seconds
Started Jul 21 06:31:16 PM PDT 24
Finished Jul 21 06:31:24 PM PDT 24
Peak memory 216708 kb
Host smart-ca7ceec2-a5ec-40c5-acc5-b0c207d0f493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236031625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1236031625
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1518049089
Short name T392
Test name
Test status
Simulation time 215787519 ps
CPU time 2.88 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:19 PM PDT 24
Peak memory 216736 kb
Host smart-99e0c683-b15d-492e-a16b-369677be6163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518049089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1518049089
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.631606945
Short name T666
Test name
Test status
Simulation time 35915685 ps
CPU time 0.95 seconds
Started Jul 21 06:31:15 PM PDT 24
Finished Jul 21 06:31:18 PM PDT 24
Peak memory 207484 kb
Host smart-80a401ef-3e59-4958-a94e-638632a0cc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631606945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.631606945
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1739566583
Short name T940
Test name
Test status
Simulation time 2295088858 ps
CPU time 3.48 seconds
Started Jul 21 06:31:22 PM PDT 24
Finished Jul 21 06:31:26 PM PDT 24
Peak memory 233188 kb
Host smart-18cd8dfb-d29f-481b-b858-4a32ad9524ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739566583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1739566583
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1589718057
Short name T463
Test name
Test status
Simulation time 28656232 ps
CPU time 0.69 seconds
Started Jul 21 06:31:32 PM PDT 24
Finished Jul 21 06:31:33 PM PDT 24
Peak memory 205972 kb
Host smart-f7cb3272-c226-456d-b1da-854e8652edef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589718057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1589718057
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1731286204
Short name T278
Test name
Test status
Simulation time 636863442 ps
CPU time 3.51 seconds
Started Jul 21 06:31:22 PM PDT 24
Finished Jul 21 06:31:26 PM PDT 24
Peak memory 233148 kb
Host smart-7058d504-1230-444d-914c-89a5651cec94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731286204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1731286204
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1053690314
Short name T728
Test name
Test status
Simulation time 17159500 ps
CPU time 0.76 seconds
Started Jul 21 06:31:21 PM PDT 24
Finished Jul 21 06:31:22 PM PDT 24
Peak memory 206388 kb
Host smart-2009ab63-3129-4328-ba91-53aa4ad6c8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053690314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1053690314
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3376032930
Short name T589
Test name
Test status
Simulation time 70302605734 ps
CPU time 256.26 seconds
Started Jul 21 06:31:26 PM PDT 24
Finished Jul 21 06:35:43 PM PDT 24
Peak memory 250708 kb
Host smart-5e7e5d7a-28b5-44a4-8ffb-76aa29d44e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376032930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3376032930
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.155595531
Short name T329
Test name
Test status
Simulation time 6294944230 ps
CPU time 62.33 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:32:34 PM PDT 24
Peak memory 255240 kb
Host smart-65341f71-88f3-4bb6-b83f-518c4ad81627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155595531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.155595531
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3162808355
Short name T690
Test name
Test status
Simulation time 8902395919 ps
CPU time 148.04 seconds
Started Jul 21 06:31:26 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 249652 kb
Host smart-7d7d4afb-ddd4-4f95-bd96-a4d8a0d80a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162808355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3162808355
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1309619282
Short name T262
Test name
Test status
Simulation time 229087982566 ps
CPU time 248.59 seconds
Started Jul 21 06:31:22 PM PDT 24
Finished Jul 21 06:35:31 PM PDT 24
Peak memory 249536 kb
Host smart-b9d485d8-e04a-4a74-8093-65a99d685cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309619282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1309619282
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.2710643678
Short name T48
Test name
Test status
Simulation time 67097848 ps
CPU time 3.06 seconds
Started Jul 21 06:31:22 PM PDT 24
Finished Jul 21 06:31:26 PM PDT 24
Peak memory 233176 kb
Host smart-edb8189b-577d-42ab-b16f-f3a21962e3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710643678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2710643678
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3525225818
Short name T269
Test name
Test status
Simulation time 78016299652 ps
CPU time 137.63 seconds
Started Jul 21 06:31:19 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 235160 kb
Host smart-6e0926b7-fdee-426c-ab22-e68559e63731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525225818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3525225818
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.1332162415
Short name T433
Test name
Test status
Simulation time 273794540 ps
CPU time 2.29 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:31:23 PM PDT 24
Peak memory 224272 kb
Host smart-c4595624-accf-4478-956c-d9b41a54531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332162415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.1332162415
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.633712312
Short name T276
Test name
Test status
Simulation time 1221653703 ps
CPU time 7.42 seconds
Started Jul 21 06:31:24 PM PDT 24
Finished Jul 21 06:31:32 PM PDT 24
Peak memory 232128 kb
Host smart-b53c93a4-cbe4-4228-80fa-e6d4853f2075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633712312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.633712312
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2222681127
Short name T427
Test name
Test status
Simulation time 1004940383 ps
CPU time 12.04 seconds
Started Jul 21 06:31:22 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 222556 kb
Host smart-815e518e-2882-4964-a955-460518c0a9fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2222681127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2222681127
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.3494300747
Short name T987
Test name
Test status
Simulation time 26513341241 ps
CPU time 32.3 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 218160 kb
Host smart-92b230b8-9eef-456c-a803-66791d37db99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494300747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.3494300747
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2388280693
Short name T903
Test name
Test status
Simulation time 19607553826 ps
CPU time 30.5 seconds
Started Jul 21 06:31:24 PM PDT 24
Finished Jul 21 06:31:55 PM PDT 24
Peak memory 215576 kb
Host smart-63810cdc-0176-4cdf-bc96-31ce7f9a8801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388280693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2388280693
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1565230608
Short name T501
Test name
Test status
Simulation time 1380638355 ps
CPU time 6.25 seconds
Started Jul 21 06:31:19 PM PDT 24
Finished Jul 21 06:31:26 PM PDT 24
Peak memory 216712 kb
Host smart-9e66415c-418b-4ce7-88a6-59af651dffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565230608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1565230608
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.1111925352
Short name T785
Test name
Test status
Simulation time 231674221 ps
CPU time 4.35 seconds
Started Jul 21 06:31:19 PM PDT 24
Finished Jul 21 06:31:25 PM PDT 24
Peak memory 216588 kb
Host smart-b9d182db-2aca-4d9f-91d9-10148b87f0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111925352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1111925352
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.39569228
Short name T722
Test name
Test status
Simulation time 67771586 ps
CPU time 0.73 seconds
Started Jul 21 06:31:18 PM PDT 24
Finished Jul 21 06:31:20 PM PDT 24
Peak memory 206440 kb
Host smart-ac75db29-2c33-4452-8c44-ac006a4451de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39569228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.39569228
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2501073556
Short name T921
Test name
Test status
Simulation time 1746863799 ps
CPU time 4.3 seconds
Started Jul 21 06:31:20 PM PDT 24
Finished Jul 21 06:31:26 PM PDT 24
Peak memory 224920 kb
Host smart-760c8025-b236-4165-b196-6d0ce4768713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501073556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2501073556
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2265643746
Short name T467
Test name
Test status
Simulation time 12148350 ps
CPU time 0.79 seconds
Started Jul 21 06:31:33 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 206216 kb
Host smart-0c3e616b-63ef-4616-b636-2e03aa2d1449
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265643746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2265643746
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1066856220
Short name T403
Test name
Test status
Simulation time 4971082322 ps
CPU time 11.66 seconds
Started Jul 21 06:31:25 PM PDT 24
Finished Jul 21 06:31:37 PM PDT 24
Peak memory 233196 kb
Host smart-ca4f419c-9351-4b9a-95ed-5fadd3593c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066856220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1066856220
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3982627403
Short name T426
Test name
Test status
Simulation time 51778382 ps
CPU time 0.78 seconds
Started Jul 21 06:31:25 PM PDT 24
Finished Jul 21 06:31:27 PM PDT 24
Peak memory 206036 kb
Host smart-444f1ef9-74b6-424d-8cb5-b6a4b285f049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982627403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3982627403
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.21818655
Short name T243
Test name
Test status
Simulation time 9037877839 ps
CPU time 74.9 seconds
Started Jul 21 06:31:25 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 250660 kb
Host smart-d47cf56a-4e51-4bb4-a372-ac44cdacde6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21818655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.21818655
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1708584028
Short name T22
Test name
Test status
Simulation time 111255742889 ps
CPU time 116.2 seconds
Started Jul 21 06:31:27 PM PDT 24
Finished Jul 21 06:33:24 PM PDT 24
Peak memory 250344 kb
Host smart-bb0845f3-4f49-44b7-9b9b-1bc639fa9922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708584028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1708584028
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3920481302
Short name T421
Test name
Test status
Simulation time 209531506 ps
CPU time 4.55 seconds
Started Jul 21 06:31:28 PM PDT 24
Finished Jul 21 06:31:33 PM PDT 24
Peak memory 225012 kb
Host smart-82adeb43-801b-49c5-b5ff-950d96302dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920481302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3920481302
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2884245569
Short name T245
Test name
Test status
Simulation time 1381826004 ps
CPU time 26.54 seconds
Started Jul 21 06:31:27 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 252924 kb
Host smart-e5342128-0fd9-4ee0-8ad8-bdd6a470e38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884245569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2884245569
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.817812013
Short name T763
Test name
Test status
Simulation time 1688986050 ps
CPU time 14.74 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:31:47 PM PDT 24
Peak memory 233112 kb
Host smart-f23971a4-da40-4683-b8ba-aeccab288d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817812013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.817812013
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2700780871
Short name T82
Test name
Test status
Simulation time 3851183845 ps
CPU time 28.35 seconds
Started Jul 21 06:31:25 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 233160 kb
Host smart-a3b997ed-8c7a-4885-9546-4995ccb8d776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700780871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2700780871
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1853921825
Short name T294
Test name
Test status
Simulation time 11320755920 ps
CPU time 11.57 seconds
Started Jul 21 06:31:27 PM PDT 24
Finished Jul 21 06:31:40 PM PDT 24
Peak memory 233196 kb
Host smart-00135607-4267-422f-a856-76be3b512f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853921825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1853921825
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.894714285
Short name T240
Test name
Test status
Simulation time 14326307336 ps
CPU time 16.76 seconds
Started Jul 21 06:31:27 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 233308 kb
Host smart-58caad83-e485-4564-be23-b72bd7acb3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894714285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.894714285
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.2113645676
Short name T400
Test name
Test status
Simulation time 2660924331 ps
CPU time 7.88 seconds
Started Jul 21 06:31:27 PM PDT 24
Finished Jul 21 06:31:36 PM PDT 24
Peak memory 223684 kb
Host smart-19ab41f1-fb28-42e1-923f-75f3692c0a56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2113645676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.2113645676
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1231565602
Short name T14
Test name
Test status
Simulation time 33106372690 ps
CPU time 327.82 seconds
Started Jul 21 06:31:28 PM PDT 24
Finished Jul 21 06:36:56 PM PDT 24
Peak memory 256880 kb
Host smart-44d085c8-b910-4205-ae34-a956e9d79412
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231565602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1231565602
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.474261143
Short name T495
Test name
Test status
Simulation time 908426564 ps
CPU time 8.89 seconds
Started Jul 21 06:31:26 PM PDT 24
Finished Jul 21 06:31:35 PM PDT 24
Peak memory 216768 kb
Host smart-4cd133a6-7156-4ac4-8edf-d5e32db81917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474261143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.474261143
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3612494334
Short name T466
Test name
Test status
Simulation time 2606822440 ps
CPU time 5.63 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:31:38 PM PDT 24
Peak memory 216776 kb
Host smart-453ab6f9-8114-459b-9f0d-c6f400a57b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612494334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3612494334
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3374706321
Short name T640
Test name
Test status
Simulation time 12805579 ps
CPU time 0.87 seconds
Started Jul 21 06:31:27 PM PDT 24
Finished Jul 21 06:31:29 PM PDT 24
Peak memory 207512 kb
Host smart-7389d57f-02cb-4839-b93b-f57751cc567c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374706321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3374706321
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3454816799
Short name T445
Test name
Test status
Simulation time 76936757 ps
CPU time 0.95 seconds
Started Jul 21 06:31:25 PM PDT 24
Finished Jul 21 06:31:26 PM PDT 24
Peak memory 207436 kb
Host smart-456ed67e-4d93-48cb-b923-df5c86b15e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454816799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3454816799
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.453680660
Short name T24
Test name
Test status
Simulation time 493437176 ps
CPU time 2.68 seconds
Started Jul 21 06:31:30 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 224952 kb
Host smart-b36680ef-6bd0-430b-93b2-3ac976649d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453680660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.453680660
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3244948794
Short name T512
Test name
Test status
Simulation time 22442711 ps
CPU time 0.76 seconds
Started Jul 21 06:29:28 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 205968 kb
Host smart-1cbeb5ed-f4f3-4ce2-a9cd-94995d2cf2ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244948794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
244948794
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.1306858193
Short name T54
Test name
Test status
Simulation time 461256382 ps
CPU time 4.35 seconds
Started Jul 21 06:29:33 PM PDT 24
Finished Jul 21 06:29:38 PM PDT 24
Peak memory 233076 kb
Host smart-e67ecee4-9163-4538-86eb-abc8417dd22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306858193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1306858193
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.4080514921
Short name T625
Test name
Test status
Simulation time 121865081 ps
CPU time 0.76 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:28 PM PDT 24
Peak memory 206360 kb
Host smart-7c7864b9-fdeb-45a1-a51f-6c59957a619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080514921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.4080514921
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.446878440
Short name T387
Test name
Test status
Simulation time 34857807 ps
CPU time 0.78 seconds
Started Jul 21 06:29:30 PM PDT 24
Finished Jul 21 06:29:31 PM PDT 24
Peak memory 216200 kb
Host smart-ba287d9e-cf10-4d5b-8e2e-f9ecbe9edc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446878440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.446878440
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1773637560
Short name T160
Test name
Test status
Simulation time 9349269096 ps
CPU time 73.88 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:30:42 PM PDT 24
Peak memory 257360 kb
Host smart-63af324f-c837-4b9c-aa19-7dba77a67c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773637560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1773637560
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1239376420
Short name T267
Test name
Test status
Simulation time 6419568817 ps
CPU time 27.89 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:56 PM PDT 24
Peak memory 233248 kb
Host smart-38202962-6cd4-4343-a524-5ddda8c0fb37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239376420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1239376420
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1174540546
Short name T52
Test name
Test status
Simulation time 83060950 ps
CPU time 2.88 seconds
Started Jul 21 06:29:26 PM PDT 24
Finished Jul 21 06:29:30 PM PDT 24
Peak memory 233140 kb
Host smart-a3e51be6-b1d0-48f9-b135-e0e34a29813d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174540546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1174540546
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3339006432
Short name T793
Test name
Test status
Simulation time 2028166676 ps
CPU time 13.07 seconds
Started Jul 21 06:29:28 PM PDT 24
Finished Jul 21 06:29:42 PM PDT 24
Peak memory 239156 kb
Host smart-95cb6c98-56fb-47a8-bd32-0bca6b4165cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339006432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3339006432
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3501517931
Short name T933
Test name
Test status
Simulation time 91340521 ps
CPU time 3.61 seconds
Started Jul 21 06:29:25 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 233132 kb
Host smart-9bd21388-23b1-4fcc-838a-460ef5ee1f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501517931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3501517931
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2823185890
Short name T439
Test name
Test status
Simulation time 3525759286 ps
CPU time 35.73 seconds
Started Jul 21 06:29:30 PM PDT 24
Finished Jul 21 06:30:06 PM PDT 24
Peak memory 241052 kb
Host smart-a089f272-4b73-4153-89f5-357c7cf7218d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823185890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2823185890
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3035451051
Short name T305
Test name
Test status
Simulation time 1063488043 ps
CPU time 8.91 seconds
Started Jul 21 06:29:28 PM PDT 24
Finished Jul 21 06:29:37 PM PDT 24
Peak memory 233140 kb
Host smart-c2ee5b94-8ed1-4327-b46d-18db98b19067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035451051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3035451051
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3710039537
Short name T802
Test name
Test status
Simulation time 5941861556 ps
CPU time 20.16 seconds
Started Jul 21 06:29:32 PM PDT 24
Finished Jul 21 06:29:52 PM PDT 24
Peak memory 249384 kb
Host smart-c422874c-8aee-4949-9cdb-6e865eadd606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710039537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3710039537
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4197237207
Short name T582
Test name
Test status
Simulation time 1033196626 ps
CPU time 14.18 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:42 PM PDT 24
Peak memory 223496 kb
Host smart-6687e1af-a892-4668-9069-d3693129bdd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4197237207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4197237207
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.891476482
Short name T77
Test name
Test status
Simulation time 263456190 ps
CPU time 1.09 seconds
Started Jul 21 06:29:26 PM PDT 24
Finished Jul 21 06:29:27 PM PDT 24
Peak memory 235992 kb
Host smart-e9e82da2-28e9-4d51-876e-b6d9b20ed9dc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891476482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.891476482
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2086632635
Short name T176
Test name
Test status
Simulation time 171834315665 ps
CPU time 420.97 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:36:29 PM PDT 24
Peak memory 257880 kb
Host smart-7f4e790d-d6dd-483a-b662-027233657c56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086632635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2086632635
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1430725208
Short name T821
Test name
Test status
Simulation time 1918110092 ps
CPU time 26.64 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:55 PM PDT 24
Peak memory 216652 kb
Host smart-3e39e97e-9d62-4252-934c-b501372882eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430725208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1430725208
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.41555730
Short name T29
Test name
Test status
Simulation time 27539644 ps
CPU time 0.66 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:29:35 PM PDT 24
Peak memory 206152 kb
Host smart-83493753-6262-40b4-abc8-eb11515bef42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41555730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.41555730
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3502764782
Short name T518
Test name
Test status
Simulation time 23640501 ps
CPU time 1.01 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:28 PM PDT 24
Peak memory 208004 kb
Host smart-d0b0aacb-9f2f-4f2a-9b53-49a31fbba25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502764782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3502764782
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.786230523
Short name T635
Test name
Test status
Simulation time 12565659 ps
CPU time 0.69 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:29 PM PDT 24
Peak memory 206032 kb
Host smart-7594e1b3-54b6-4415-8032-23e1147ca7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786230523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.786230523
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2953185818
Short name T590
Test name
Test status
Simulation time 298311567 ps
CPU time 2.39 seconds
Started Jul 21 06:29:27 PM PDT 24
Finished Jul 21 06:29:30 PM PDT 24
Peak memory 224588 kb
Host smart-41abf194-584b-4dfc-bcdb-44c7b5a488ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953185818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2953185818
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2337120830
Short name T854
Test name
Test status
Simulation time 20839908 ps
CPU time 0.72 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:31:32 PM PDT 24
Peak memory 206300 kb
Host smart-593b6d75-6b17-46a5-968f-47f714f049bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337120830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2337120830
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.706275736
Short name T769
Test name
Test status
Simulation time 1243661676 ps
CPU time 12.61 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 233068 kb
Host smart-de6d0995-640e-490f-b526-51ec49891bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706275736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.706275736
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2434398668
Short name T679
Test name
Test status
Simulation time 51834296 ps
CPU time 0.79 seconds
Started Jul 21 06:31:34 PM PDT 24
Finished Jul 21 06:31:36 PM PDT 24
Peak memory 207388 kb
Host smart-c6ae20f9-85cb-4142-8b01-962f99f83d74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2434398668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2434398668
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1719498341
Short name T759
Test name
Test status
Simulation time 4512237078 ps
CPU time 44.52 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 241600 kb
Host smart-f0532c4c-32df-4adf-9486-b32774ed3c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719498341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1719498341
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.2080702402
Short name T355
Test name
Test status
Simulation time 5331930987 ps
CPU time 15.73 seconds
Started Jul 21 06:31:32 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 218188 kb
Host smart-ff421bb6-4335-4cdc-96e5-0f087c5c7f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080702402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.2080702402
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3620503697
Short name T363
Test name
Test status
Simulation time 17698381505 ps
CPU time 187.11 seconds
Started Jul 21 06:31:32 PM PDT 24
Finished Jul 21 06:34:40 PM PDT 24
Peak memory 263124 kb
Host smart-9a4dae2c-7e5f-4ba6-8082-33bcef6c12f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620503697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3620503697
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3357526532
Short name T479
Test name
Test status
Simulation time 3331744535 ps
CPU time 48.87 seconds
Started Jul 21 06:31:30 PM PDT 24
Finished Jul 21 06:32:20 PM PDT 24
Peak memory 251000 kb
Host smart-e6801929-abe0-4eaf-860b-c11fcb520ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357526532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3357526532
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1707869394
Short name T293
Test name
Test status
Simulation time 117465648608 ps
CPU time 120.79 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 253188 kb
Host smart-78fe2957-09c2-4c5a-9f72-2a64b78e2fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707869394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1707869394
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2156787719
Short name T929
Test name
Test status
Simulation time 461710343 ps
CPU time 4.51 seconds
Started Jul 21 06:31:32 PM PDT 24
Finished Jul 21 06:31:38 PM PDT 24
Peak memory 224904 kb
Host smart-80ce73ae-62ac-4b21-adf4-9c92dc80d7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156787719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2156787719
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.828729273
Short name T850
Test name
Test status
Simulation time 256617772 ps
CPU time 2.73 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:31:35 PM PDT 24
Peak memory 233108 kb
Host smart-1f982d36-422a-45ef-acf2-e7af2766725b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828729273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.828729273
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2900862054
Short name T836
Test name
Test status
Simulation time 236382293 ps
CPU time 3.65 seconds
Started Jul 21 06:31:34 PM PDT 24
Finished Jul 21 06:31:39 PM PDT 24
Peak memory 233164 kb
Host smart-fb57b3ea-7a12-488f-9ce5-b8aa26583e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900862054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2900862054
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1112229106
Short name T592
Test name
Test status
Simulation time 31367515113 ps
CPU time 9.9 seconds
Started Jul 21 06:31:46 PM PDT 24
Finished Jul 21 06:31:58 PM PDT 24
Peak memory 233176 kb
Host smart-8dd90ee9-0875-4309-b499-43a6b12648f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112229106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1112229106
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.800855803
Short name T713
Test name
Test status
Simulation time 559993197 ps
CPU time 5.24 seconds
Started Jul 21 06:31:31 PM PDT 24
Finished Jul 21 06:31:37 PM PDT 24
Peak memory 223468 kb
Host smart-923e635a-4c38-4692-b7c5-fc55c1a8565f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=800855803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.800855803
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.4003253370
Short name T15
Test name
Test status
Simulation time 3601756046 ps
CPU time 21.56 seconds
Started Jul 21 06:31:32 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 224952 kb
Host smart-2e95545a-55fc-4448-bef6-1e52b1f7093b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003253370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.4003253370
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.341779225
Short name T641
Test name
Test status
Simulation time 2807386492 ps
CPU time 16.6 seconds
Started Jul 21 06:31:30 PM PDT 24
Finished Jul 21 06:31:47 PM PDT 24
Peak memory 216696 kb
Host smart-b005a8be-2daa-4c1f-8929-5e9b4664f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341779225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.341779225
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1768599363
Short name T60
Test name
Test status
Simulation time 4549873794 ps
CPU time 6.5 seconds
Started Jul 21 06:31:34 PM PDT 24
Finished Jul 21 06:31:41 PM PDT 24
Peak memory 216760 kb
Host smart-98af72eb-3f31-483b-a69d-cce5b7cfe16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768599363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1768599363
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1230261655
Short name T916
Test name
Test status
Simulation time 31207370 ps
CPU time 0.67 seconds
Started Jul 21 06:31:33 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 206124 kb
Host smart-b08c98da-9883-4ccd-8411-7297270c4ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230261655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1230261655
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.2739373203
Short name T542
Test name
Test status
Simulation time 292178817 ps
CPU time 0.87 seconds
Started Jul 21 06:31:35 PM PDT 24
Finished Jul 21 06:31:36 PM PDT 24
Peak memory 206436 kb
Host smart-3ef7e84f-1acc-4f7d-acb4-f8d7b650cb1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739373203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.2739373203
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.788690463
Short name T388
Test name
Test status
Simulation time 774569936 ps
CPU time 3.56 seconds
Started Jul 21 06:31:35 PM PDT 24
Finished Jul 21 06:31:39 PM PDT 24
Peak memory 233112 kb
Host smart-8480e925-e3b3-46cc-b614-ff6b35c53277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788690463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.788690463
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3449547224
Short name T823
Test name
Test status
Simulation time 35240340 ps
CPU time 0.73 seconds
Started Jul 21 06:31:42 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 205900 kb
Host smart-fc11b1f0-a44a-40f6-80e5-1fb7cc2a260e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449547224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3449547224
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2037681618
Short name T611
Test name
Test status
Simulation time 7658055471 ps
CPU time 10.56 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:31:55 PM PDT 24
Peak memory 233148 kb
Host smart-6f9aea44-0b71-4815-813f-d261e6968fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037681618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2037681618
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3306485076
Short name T26
Test name
Test status
Simulation time 18566529 ps
CPU time 0.77 seconds
Started Jul 21 06:31:33 PM PDT 24
Finished Jul 21 06:31:34 PM PDT 24
Peak memory 207072 kb
Host smart-e3010229-e501-40bd-901a-96a0e81e5b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306485076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3306485076
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.800218164
Short name T203
Test name
Test status
Simulation time 12073779337 ps
CPU time 38.54 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:32:18 PM PDT 24
Peak memory 249608 kb
Host smart-cdf8299b-7b77-40d8-984d-b911dee9d850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800218164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.800218164
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.4176841255
Short name T319
Test name
Test status
Simulation time 44035832676 ps
CPU time 338.9 seconds
Started Jul 21 06:31:42 PM PDT 24
Finished Jul 21 06:37:22 PM PDT 24
Peak memory 265872 kb
Host smart-b52641ac-500d-45ff-8b5b-1dc345250e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176841255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.4176841255
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1867170883
Short name T735
Test name
Test status
Simulation time 20834206678 ps
CPU time 167.06 seconds
Started Jul 21 06:31:42 PM PDT 24
Finished Jul 21 06:34:30 PM PDT 24
Peak memory 250588 kb
Host smart-a043f40f-5aca-4861-8ff8-ac8c0b787622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867170883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1867170883
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2479638410
Short name T555
Test name
Test status
Simulation time 466297601 ps
CPU time 4.33 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:31:43 PM PDT 24
Peak memory 233116 kb
Host smart-1a7d6985-6836-4812-875e-39f721d06de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479638410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2479638410
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3954685282
Short name T500
Test name
Test status
Simulation time 3281154182 ps
CPU time 28.57 seconds
Started Jul 21 06:31:41 PM PDT 24
Finished Jul 21 06:32:10 PM PDT 24
Peak memory 224956 kb
Host smart-7b6fbfeb-9566-4183-a34a-9951576472db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954685282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3954685282
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.501091387
Short name T478
Test name
Test status
Simulation time 6561028298 ps
CPU time 43.71 seconds
Started Jul 21 06:31:37 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 233188 kb
Host smart-430e5189-3a0e-4b7f-8022-fce65116c560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501091387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.501091387
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2707731562
Short name T291
Test name
Test status
Simulation time 162447423 ps
CPU time 2.89 seconds
Started Jul 21 06:31:39 PM PDT 24
Finished Jul 21 06:31:43 PM PDT 24
Peak memory 224980 kb
Host smart-178e8eb3-55cb-428b-a3a3-aadfb80d6b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707731562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2707731562
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2623361803
Short name T67
Test name
Test status
Simulation time 617079511 ps
CPU time 2.33 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:31:47 PM PDT 24
Peak memory 224328 kb
Host smart-571ad918-5bb1-45d0-b292-323ad54050c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623361803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2623361803
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3554258330
Short name T894
Test name
Test status
Simulation time 477348311 ps
CPU time 3.72 seconds
Started Jul 21 06:31:39 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 223624 kb
Host smart-8a26b59c-9a36-4a1e-8225-4f1f2bf2ed36
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554258330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3554258330
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.386551973
Short name T567
Test name
Test status
Simulation time 7204223957 ps
CPU time 61.67 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 240312 kb
Host smart-fce7eb85-d6b9-4a56-a0dd-505a37af8c7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386551973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.386551973
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.3849580657
Short name T429
Test name
Test status
Simulation time 10981395415 ps
CPU time 7.55 seconds
Started Jul 21 06:31:40 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 219928 kb
Host smart-784134c3-630e-4f20-b4b5-17ec1e094133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849580657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.3849580657
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1992186249
Short name T1004
Test name
Test status
Simulation time 1557057320 ps
CPU time 3 seconds
Started Jul 21 06:31:40 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 216676 kb
Host smart-5910bd43-229f-4760-a56f-e1d6908a231b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992186249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1992186249
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1389719813
Short name T751
Test name
Test status
Simulation time 84157494 ps
CPU time 2.98 seconds
Started Jul 21 06:31:39 PM PDT 24
Finished Jul 21 06:31:43 PM PDT 24
Peak memory 216660 kb
Host smart-2ee10e47-7292-42f6-a9a5-99b88c687a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389719813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1389719813
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2156571679
Short name T920
Test name
Test status
Simulation time 176329571 ps
CPU time 0.87 seconds
Started Jul 21 06:31:37 PM PDT 24
Finished Jul 21 06:31:39 PM PDT 24
Peak memory 207476 kb
Host smart-a1571da6-3655-4629-bd98-4e5cd787629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156571679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2156571679
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4287407724
Short name T272
Test name
Test status
Simulation time 712571584 ps
CPU time 5.08 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:31:44 PM PDT 24
Peak memory 224940 kb
Host smart-dc4723ac-fc9a-404b-882e-f2abd5d26f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287407724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4287407724
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.972863908
Short name T30
Test name
Test status
Simulation time 13845699 ps
CPU time 0.71 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:46 PM PDT 24
Peak memory 205348 kb
Host smart-994a9add-42d8-4bf2-80d4-ea605e4d9078
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972863908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.972863908
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.1145285023
Short name T11
Test name
Test status
Simulation time 3248140187 ps
CPU time 5.91 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 233208 kb
Host smart-ce4ef6fc-d162-42e0-8e1c-5fe6cef3fe20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145285023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.1145285023
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1845253244
Short name T991
Test name
Test status
Simulation time 19599056 ps
CPU time 0.81 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:31:39 PM PDT 24
Peak memory 207272 kb
Host smart-aad1605b-6251-4645-9d21-38be34e4de06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845253244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1845253244
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1478483107
Short name T199
Test name
Test status
Simulation time 179998547345 ps
CPU time 352.74 seconds
Started Jul 21 06:31:39 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 254116 kb
Host smart-9f42972c-5090-4e3f-a850-af7bacdc1fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478483107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1478483107
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1943559777
Short name T969
Test name
Test status
Simulation time 18904371438 ps
CPU time 159.91 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:34:25 PM PDT 24
Peak memory 250688 kb
Host smart-f7ed1bba-6203-4976-8210-388c2b0aef6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943559777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1943559777
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2143836652
Short name T348
Test name
Test status
Simulation time 730150480 ps
CPU time 14.3 seconds
Started Jul 21 06:31:40 PM PDT 24
Finished Jul 21 06:31:55 PM PDT 24
Peak memory 232728 kb
Host smart-42aa7f99-2a2d-4df2-b136-c79df78062ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143836652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2143836652
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.1366030372
Short name T332
Test name
Test status
Simulation time 343699300786 ps
CPU time 559.54 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 255824 kb
Host smart-27bd3509-e101-43ff-8847-4f124d54f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366030372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.1366030372
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3160296483
Short name T811
Test name
Test status
Simulation time 2301500663 ps
CPU time 20.72 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:32:00 PM PDT 24
Peak memory 224920 kb
Host smart-ca7c88a2-c096-4328-8a88-ec6c37270ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160296483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3160296483
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3720439571
Short name T434
Test name
Test status
Simulation time 2172191007 ps
CPU time 29.36 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 241120 kb
Host smart-14b8ede5-d9d7-486b-a27e-2b7ec19ab623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720439571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3720439571
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.304646276
Short name T41
Test name
Test status
Simulation time 184119029 ps
CPU time 2.4 seconds
Started Jul 21 06:31:40 PM PDT 24
Finished Jul 21 06:31:43 PM PDT 24
Peak memory 233112 kb
Host smart-e067282b-7a3d-44fb-aed7-5b00cf8590f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304646276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.304646276
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.971930467
Short name T588
Test name
Test status
Simulation time 20334524388 ps
CPU time 7.35 seconds
Started Jul 21 06:31:40 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 233228 kb
Host smart-6d6087d6-bf07-4ca6-a889-5a1237297908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971930467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.971930467
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.4279801393
Short name T862
Test name
Test status
Simulation time 103064033 ps
CPU time 3.96 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:31:49 PM PDT 24
Peak memory 223096 kb
Host smart-fdfbd1d6-fe25-4cea-ab76-d0ca9c52c88b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4279801393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.4279801393
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2420256407
Short name T694
Test name
Test status
Simulation time 7692075707 ps
CPU time 31.06 seconds
Started Jul 21 06:31:42 PM PDT 24
Finished Jul 21 06:32:15 PM PDT 24
Peak memory 216768 kb
Host smart-d13d998a-a9d2-47ca-9286-29da774c2605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420256407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2420256407
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2792578965
Short name T845
Test name
Test status
Simulation time 9359272650 ps
CPU time 6.41 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:31:46 PM PDT 24
Peak memory 217728 kb
Host smart-bf368c8d-14f3-492e-91d4-1a7e6c963d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792578965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2792578965
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4214487049
Short name T741
Test name
Test status
Simulation time 20276509 ps
CPU time 0.99 seconds
Started Jul 21 06:31:38 PM PDT 24
Finished Jul 21 06:31:40 PM PDT 24
Peak memory 207544 kb
Host smart-cc96d41e-0710-48f4-94d5-0a82d433c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214487049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4214487049
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1221523286
Short name T432
Test name
Test status
Simulation time 90049231 ps
CPU time 0.97 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 206468 kb
Host smart-cd385357-4b4a-4b08-af15-3ceee4b1f348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221523286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1221523286
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1417229835
Short name T780
Test name
Test status
Simulation time 125784717 ps
CPU time 2.74 seconds
Started Jul 21 06:31:41 PM PDT 24
Finished Jul 21 06:31:45 PM PDT 24
Peak memory 224872 kb
Host smart-d8dc402c-d4c8-4918-a627-0274221791ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417229835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1417229835
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2439613658
Short name T880
Test name
Test status
Simulation time 36325637 ps
CPU time 0.72 seconds
Started Jul 21 06:31:46 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 205944 kb
Host smart-c24991e8-0dd0-42be-8330-e8cefbea121d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439613658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2439613658
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.638151571
Short name T372
Test name
Test status
Simulation time 11367267208 ps
CPU time 27.98 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:32:15 PM PDT 24
Peak memory 224940 kb
Host smart-779eeb64-ccc7-477f-8da5-d8b9067c7d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638151571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.638151571
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.428003964
Short name T707
Test name
Test status
Simulation time 17239860 ps
CPU time 0.76 seconds
Started Jul 21 06:31:48 PM PDT 24
Finished Jul 21 06:31:49 PM PDT 24
Peak memory 207232 kb
Host smart-960876d1-c9b8-4539-bd7e-f2a827145150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428003964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.428003964
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1702527791
Short name T844
Test name
Test status
Simulation time 2396978323 ps
CPU time 22 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:32:09 PM PDT 24
Peak memory 235192 kb
Host smart-5d5664d0-d1d2-4b6d-ac11-636e3ddd0d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702527791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1702527791
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.4050055976
Short name T620
Test name
Test status
Simulation time 14593622235 ps
CPU time 26.62 seconds
Started Jul 21 06:31:42 PM PDT 24
Finished Jul 21 06:32:10 PM PDT 24
Peak memory 218068 kb
Host smart-a55a2fbf-a25d-44dd-baf2-da1693c59232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050055976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4050055976
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3465540514
Short name T158
Test name
Test status
Simulation time 130365784918 ps
CPU time 234.69 seconds
Started Jul 21 06:31:48 PM PDT 24
Finished Jul 21 06:35:44 PM PDT 24
Peak memory 248660 kb
Host smart-725f080c-1285-4484-90fd-ce38e7fc1115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465540514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3465540514
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1827189670
Short name T887
Test name
Test status
Simulation time 20157335757 ps
CPU time 37.71 seconds
Started Jul 21 06:31:48 PM PDT 24
Finished Jul 21 06:32:27 PM PDT 24
Peak memory 249756 kb
Host smart-e6ec6e9c-d9a0-4fa6-92cb-87844d4e0062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827189670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1827189670
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2747048759
Short name T710
Test name
Test status
Simulation time 50428907351 ps
CPU time 184.24 seconds
Started Jul 21 06:31:47 PM PDT 24
Finished Jul 21 06:34:52 PM PDT 24
Peak memory 255572 kb
Host smart-ac4ab510-f632-4fad-86ef-d76a7f9130fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747048759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2747048759
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.995131312
Short name T692
Test name
Test status
Simulation time 308099022 ps
CPU time 5.93 seconds
Started Jul 21 06:31:46 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 233060 kb
Host smart-22c398d0-f352-4fad-858e-2d469700668f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995131312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.995131312
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2764414809
Short name T748
Test name
Test status
Simulation time 2892426676 ps
CPU time 8.77 seconds
Started Jul 21 06:31:47 PM PDT 24
Finished Jul 21 06:31:57 PM PDT 24
Peak memory 233172 kb
Host smart-ce9f17ef-7e4a-484e-95b4-22e27add0ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764414809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2764414809
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.4262272130
Short name T289
Test name
Test status
Simulation time 9026729172 ps
CPU time 11.48 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:31:56 PM PDT 24
Peak memory 240452 kb
Host smart-11ff7e35-b2d7-44cc-985c-a6baafe910a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262272130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.4262272130
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1949517761
Short name T661
Test name
Test status
Simulation time 6713777598 ps
CPU time 7.56 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 233164 kb
Host smart-ecc4bfa5-885c-4e10-88bd-47005a55b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949517761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1949517761
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2431064464
Short name T678
Test name
Test status
Simulation time 64731713 ps
CPU time 3.67 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:31:50 PM PDT 24
Peak memory 222996 kb
Host smart-c53329b8-43d2-4d00-8f1d-8e47e4ea5d1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2431064464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2431064464
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.710170723
Short name T809
Test name
Test status
Simulation time 164909557838 ps
CPU time 436.87 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 267756 kb
Host smart-c0566d69-ac68-4b43-9383-2589e412489a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710170723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.710170723
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1327530067
Short name T990
Test name
Test status
Simulation time 2999400181 ps
CPU time 17.25 seconds
Started Jul 21 06:31:42 PM PDT 24
Finished Jul 21 06:32:01 PM PDT 24
Peak memory 216744 kb
Host smart-ccf5bc82-3c13-4932-a525-59d9debded9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327530067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1327530067
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2148775537
Short name T1006
Test name
Test status
Simulation time 5322215879 ps
CPU time 16.26 seconds
Started Jul 21 06:31:47 PM PDT 24
Finished Jul 21 06:32:05 PM PDT 24
Peak memory 216856 kb
Host smart-a1af7d51-682e-4da0-9ff2-7fe3376cc4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148775537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2148775537
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.4079483991
Short name T477
Test name
Test status
Simulation time 34946413 ps
CPU time 2.13 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 216692 kb
Host smart-a4e29031-97dd-4c62-b584-9fa23dfb69e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079483991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.4079483991
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.267575416
Short name T798
Test name
Test status
Simulation time 269663564 ps
CPU time 1.04 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:47 PM PDT 24
Peak memory 207572 kb
Host smart-5cf65511-cb42-4f36-80c4-1b998ace7607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267575416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.267575416
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1934638276
Short name T423
Test name
Test status
Simulation time 2278554584 ps
CPU time 3.76 seconds
Started Jul 21 06:31:47 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 224992 kb
Host smart-2cb4d348-7082-407f-8929-b2c017a5d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934638276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1934638276
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.3274172135
Short name T770
Test name
Test status
Simulation time 46204874 ps
CPU time 0.67 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 205376 kb
Host smart-cfc3bb3e-ed48-45a0-820b-4eb2401dc2d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274172135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
3274172135
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.34548080
Short name T407
Test name
Test status
Simulation time 5977080475 ps
CPU time 5.49 seconds
Started Jul 21 06:31:50 PM PDT 24
Finished Jul 21 06:31:56 PM PDT 24
Peak memory 225008 kb
Host smart-b0f0e951-860b-47fb-ba05-58e23635f425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34548080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.34548080
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.872254955
Short name T835
Test name
Test status
Simulation time 51699832 ps
CPU time 0.78 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:31:46 PM PDT 24
Peak memory 207008 kb
Host smart-d44369f6-8a5a-48c8-a091-7283c1173c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872254955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.872254955
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.643095651
Short name T339
Test name
Test status
Simulation time 5847320003 ps
CPU time 68.77 seconds
Started Jul 21 06:31:52 PM PDT 24
Finished Jul 21 06:33:02 PM PDT 24
Peak memory 249572 kb
Host smart-a4d28a03-1f89-4ce3-a6dd-f09104ab1c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643095651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.643095651
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2906512800
Short name T739
Test name
Test status
Simulation time 2800814177 ps
CPU time 59.23 seconds
Started Jul 21 06:31:49 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 250612 kb
Host smart-c7570959-64c4-41c0-a2c7-202ea8f0cbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906512800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2906512800
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1620260921
Short name T213
Test name
Test status
Simulation time 24739349341 ps
CPU time 334.67 seconds
Started Jul 21 06:31:50 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 264384 kb
Host smart-3b47daaa-f82e-4787-92d0-59a1786172b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620260921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1620260921
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.4200471094
Short name T610
Test name
Test status
Simulation time 364549964 ps
CPU time 3.31 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:31:56 PM PDT 24
Peak memory 224940 kb
Host smart-c1aa807e-2b4a-49f3-85ed-902337179e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200471094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.4200471094
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3350833107
Short name T704
Test name
Test status
Simulation time 86937232358 ps
CPU time 143.41 seconds
Started Jul 21 06:31:52 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 252764 kb
Host smart-7468e62a-8354-4153-b7ce-a3badda973a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350833107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3350833107
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.965789384
Short name T631
Test name
Test status
Simulation time 88465278 ps
CPU time 2.85 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 224876 kb
Host smart-09931bbb-9522-47be-a0a4-db5b025c3e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965789384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.965789384
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.576789439
Short name T481
Test name
Test status
Simulation time 6716528485 ps
CPU time 47 seconds
Started Jul 21 06:31:46 PM PDT 24
Finished Jul 21 06:32:34 PM PDT 24
Peak memory 233140 kb
Host smart-284963ca-4a14-43a1-a586-01dd8294b163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576789439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.576789439
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4272844948
Short name T418
Test name
Test status
Simulation time 13336586579 ps
CPU time 14.19 seconds
Started Jul 21 06:31:47 PM PDT 24
Finished Jul 21 06:32:02 PM PDT 24
Peak memory 237880 kb
Host smart-c375af7b-9dcf-4fc8-a05d-ef3d4dc0c25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272844948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4272844948
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1481691437
Short name T285
Test name
Test status
Simulation time 8267934984 ps
CPU time 22.01 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:32:09 PM PDT 24
Peak memory 233156 kb
Host smart-c606e7d7-e9ac-44e6-91d4-8ebd7b78b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481691437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1481691437
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2722659188
Short name T613
Test name
Test status
Simulation time 126889389 ps
CPU time 4.43 seconds
Started Jul 21 06:31:52 PM PDT 24
Finished Jul 21 06:31:57 PM PDT 24
Peak memory 223456 kb
Host smart-04d43c56-5c2a-4d41-baf1-91551013df3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2722659188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2722659188
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1137129979
Short name T39
Test name
Test status
Simulation time 15975630066 ps
CPU time 101.35 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 266068 kb
Host smart-6b2b7aa5-1a58-43b5-b4f5-db52b1ddcdce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137129979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1137129979
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.582472595
Short name T435
Test name
Test status
Simulation time 1654003767 ps
CPU time 4.85 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:50 PM PDT 24
Peak memory 216664 kb
Host smart-0b602b61-7ace-4166-af08-1f891ebd740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582472595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.582472595
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1691579138
Short name T608
Test name
Test status
Simulation time 566827997 ps
CPU time 3.32 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 216612 kb
Host smart-57b62826-1c88-472a-bdf8-f1f0f89cb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691579138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1691579138
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.304365570
Short name T553
Test name
Test status
Simulation time 35749813 ps
CPU time 1.31 seconds
Started Jul 21 06:31:43 PM PDT 24
Finished Jul 21 06:31:46 PM PDT 24
Peak memory 216640 kb
Host smart-2f230e4f-103f-4339-bb10-85b506afe734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304365570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.304365570
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.904988446
Short name T938
Test name
Test status
Simulation time 16268739 ps
CPU time 0.71 seconds
Started Jul 21 06:31:44 PM PDT 24
Finished Jul 21 06:31:46 PM PDT 24
Peak memory 206436 kb
Host smart-baf427da-4ed7-4284-bd4f-12b12ef88a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904988446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.904988446
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.2626447927
Short name T671
Test name
Test status
Simulation time 9582332689 ps
CPU time 31.59 seconds
Started Jul 21 06:31:45 PM PDT 24
Finished Jul 21 06:32:18 PM PDT 24
Peak memory 240356 kb
Host smart-a6f65378-7961-4276-a030-794c53d40c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626447927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.2626447927
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1053921025
Short name T398
Test name
Test status
Simulation time 16961993 ps
CPU time 0.76 seconds
Started Jul 21 06:32:02 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 205912 kb
Host smart-47080ad0-a657-4d42-997e-9c3d95ad9ceb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053921025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1053921025
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.33451697
Short name T545
Test name
Test status
Simulation time 287344546 ps
CPU time 2.79 seconds
Started Jul 21 06:31:52 PM PDT 24
Finished Jul 21 06:31:56 PM PDT 24
Peak memory 224928 kb
Host smart-621248d6-677f-47ca-bafc-7aaeb567d746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33451697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.33451697
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2183615551
Short name T376
Test name
Test status
Simulation time 15159820 ps
CPU time 0.75 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 206100 kb
Host smart-1cbf2911-8eb0-4b73-a6c4-68aa558cf4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183615551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2183615551
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3316985302
Short name T322
Test name
Test status
Simulation time 31367416511 ps
CPU time 98.29 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 233088 kb
Host smart-d56ce3e2-3e1e-4ed6-b3a8-2c04d48184cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316985302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3316985302
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3037273222
Short name T528
Test name
Test status
Simulation time 3767157794 ps
CPU time 17.51 seconds
Started Jul 21 06:31:57 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 218120 kb
Host smart-5e264b93-b1a9-418c-b8df-e251b159fde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037273222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3037273222
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2986652430
Short name T70
Test name
Test status
Simulation time 106859704594 ps
CPU time 233.95 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:35:51 PM PDT 24
Peak memory 257852 kb
Host smart-ed0b1452-ea5a-4a5e-af4a-2c64a26a5168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986652430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2986652430
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2132285212
Short name T1
Test name
Test status
Simulation time 630549872 ps
CPU time 12.17 seconds
Started Jul 21 06:31:50 PM PDT 24
Finished Jul 21 06:32:03 PM PDT 24
Peak memory 233184 kb
Host smart-9a7a5dd8-13e7-4aa1-a583-50f15e0e0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132285212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2132285212
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1578202790
Short name T482
Test name
Test status
Simulation time 42209738052 ps
CPU time 22.93 seconds
Started Jul 21 06:31:58 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 241344 kb
Host smart-e29bffcc-546e-45ce-994e-a47166060d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578202790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1578202790
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2520929638
Short name T247
Test name
Test status
Simulation time 1768609943 ps
CPU time 7.74 seconds
Started Jul 21 06:31:52 PM PDT 24
Finished Jul 21 06:32:01 PM PDT 24
Peak memory 224952 kb
Host smart-16f053bc-0e42-41fc-a846-60a5d02c81ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520929638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2520929638
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2246652162
Short name T279
Test name
Test status
Simulation time 48029777800 ps
CPU time 50.51 seconds
Started Jul 21 06:31:53 PM PDT 24
Finished Jul 21 06:32:44 PM PDT 24
Peak memory 250276 kb
Host smart-5d1d4323-e702-4d68-a6e0-7d9e27269c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246652162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2246652162
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3772829878
Short name T331
Test name
Test status
Simulation time 2566471490 ps
CPU time 6.46 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:31:59 PM PDT 24
Peak memory 241192 kb
Host smart-fc73ddb3-8ff0-4ed6-bf5f-f09d974aeae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772829878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3772829878
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1304105217
Short name T526
Test name
Test status
Simulation time 228886643 ps
CPU time 3 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 233104 kb
Host smart-32ae3232-3339-4ec3-baef-12b970aa83f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304105217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1304105217
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2520701838
Short name T449
Test name
Test status
Simulation time 451817813 ps
CPU time 4.58 seconds
Started Jul 21 06:31:59 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 223008 kb
Host smart-0597c081-2372-4969-ad9d-7ad76f7ce14f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2520701838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2520701838
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3182096007
Short name T16
Test name
Test status
Simulation time 259337743 ps
CPU time 1.23 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:31:58 PM PDT 24
Peak memory 207684 kb
Host smart-e3d0f7e3-ad80-44b6-989b-3eaa01eb3bc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182096007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3182096007
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.818850473
Short name T350
Test name
Test status
Simulation time 16240143901 ps
CPU time 35.6 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:32:28 PM PDT 24
Peak memory 216708 kb
Host smart-1178ee83-368b-4e80-86cd-d8eb4ad43918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818850473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.818850473
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1516571096
Short name T394
Test name
Test status
Simulation time 1266983850 ps
CPU time 3.56 seconds
Started Jul 21 06:31:50 PM PDT 24
Finished Jul 21 06:31:54 PM PDT 24
Peak memory 216688 kb
Host smart-8187b641-dd36-412e-b518-38aeff398ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516571096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1516571096
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1650609361
Short name T583
Test name
Test status
Simulation time 106223640 ps
CPU time 1.36 seconds
Started Jul 21 06:31:50 PM PDT 24
Finished Jul 21 06:31:52 PM PDT 24
Peak memory 216688 kb
Host smart-2dbc0720-2852-44bd-9cd4-b9d8b300488a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650609361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1650609361
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.744973307
Short name T712
Test name
Test status
Simulation time 157621531 ps
CPU time 0.79 seconds
Started Jul 21 06:31:51 PM PDT 24
Finished Jul 21 06:31:53 PM PDT 24
Peak memory 206476 kb
Host smart-7ecffef9-5966-40f7-9efe-af21535b55e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744973307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.744973307
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3602963579
Short name T535
Test name
Test status
Simulation time 422659609 ps
CPU time 6.17 seconds
Started Jul 21 06:31:50 PM PDT 24
Finished Jul 21 06:31:57 PM PDT 24
Peak memory 233108 kb
Host smart-e0125568-8203-4594-ac86-d7c26ae4a275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602963579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3602963579
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1548454170
Short name T506
Test name
Test status
Simulation time 24787503 ps
CPU time 0.75 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:31:58 PM PDT 24
Peak memory 205952 kb
Host smart-961e7d21-f78b-46d1-9aca-14c865debea9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548454170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1548454170
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.697151331
Short name T572
Test name
Test status
Simulation time 61837772 ps
CPU time 2.02 seconds
Started Jul 21 06:31:55 PM PDT 24
Finished Jul 21 06:31:57 PM PDT 24
Peak memory 224852 kb
Host smart-ab9b7ca4-b13c-4a10-8db2-d69ff9ee9dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697151331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.697151331
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1808557104
Short name T505
Test name
Test status
Simulation time 47210747 ps
CPU time 0.77 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:31:58 PM PDT 24
Peak memory 207044 kb
Host smart-6b9f0de4-4449-47f7-bd98-487b0b9a87bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808557104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1808557104
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.718472301
Short name T494
Test name
Test status
Simulation time 1956043461 ps
CPU time 7.5 seconds
Started Jul 21 06:32:02 PM PDT 24
Finished Jul 21 06:32:10 PM PDT 24
Peak memory 224876 kb
Host smart-7d6a1baa-7c71-4428-9b34-9a101f0b486e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718472301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.718472301
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.677340434
Short name T879
Test name
Test status
Simulation time 36627884284 ps
CPU time 350.68 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 256560 kb
Host smart-e74e0632-7a6b-4c13-917c-d1a404fd6482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677340434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.677340434
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2133131711
Short name T947
Test name
Test status
Simulation time 818914535 ps
CPU time 5.23 seconds
Started Jul 21 06:31:57 PM PDT 24
Finished Jul 21 06:32:03 PM PDT 24
Peak memory 224940 kb
Host smart-da19ebeb-5bc8-48cb-9cf9-54b751782bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133131711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2133131711
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3542270753
Short name T911
Test name
Test status
Simulation time 64410339182 ps
CPU time 451.41 seconds
Started Jul 21 06:31:59 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 257764 kb
Host smart-8c184bec-a512-47a9-9e7e-e05b17f85df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542270753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3542270753
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1909601319
Short name T274
Test name
Test status
Simulation time 10987076812 ps
CPU time 25.94 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:32:23 PM PDT 24
Peak memory 220768 kb
Host smart-e2d84b77-c73f-46b1-94f8-cc4e7e547a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909601319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1909601319
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2968601057
Short name T521
Test name
Test status
Simulation time 12326009531 ps
CPU time 20.92 seconds
Started Jul 21 06:32:00 PM PDT 24
Finished Jul 21 06:32:21 PM PDT 24
Peak memory 233172 kb
Host smart-8f0c1a75-2658-40c7-a662-e2f750d4b227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968601057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2968601057
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1526032572
Short name T47
Test name
Test status
Simulation time 1390172593 ps
CPU time 11.63 seconds
Started Jul 21 06:32:02 PM PDT 24
Finished Jul 21 06:32:14 PM PDT 24
Peak memory 240728 kb
Host smart-b9460d6e-f9eb-4676-a11e-396517ceeb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526032572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1526032572
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1981606136
Short name T8
Test name
Test status
Simulation time 2763534786 ps
CPU time 10.78 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:32:07 PM PDT 24
Peak memory 233320 kb
Host smart-5072f522-159f-4be2-b6b6-5d2063064cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981606136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1981606136
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3702620131
Short name T852
Test name
Test status
Simulation time 8191163385 ps
CPU time 19.75 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:32:18 PM PDT 24
Peak memory 219384 kb
Host smart-4e50406a-8c54-4ccb-97a8-54e35bed49c7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3702620131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3702620131
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.626296074
Short name T1000
Test name
Test status
Simulation time 13515057432 ps
CPU time 26.24 seconds
Started Jul 21 06:31:58 PM PDT 24
Finished Jul 21 06:32:25 PM PDT 24
Peak memory 218524 kb
Host smart-20c40c4a-be4c-4419-add7-fc1e7255e052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626296074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.626296074
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3341730420
Short name T944
Test name
Test status
Simulation time 5583023366 ps
CPU time 6.03 seconds
Started Jul 21 06:31:57 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 216656 kb
Host smart-30be7a68-ad7e-4d28-8125-1939aebb2a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341730420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3341730420
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3751526881
Short name T812
Test name
Test status
Simulation time 328759727 ps
CPU time 2.28 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:31:59 PM PDT 24
Peak memory 216648 kb
Host smart-4081048b-1947-4840-9bb7-e537b4092186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751526881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3751526881
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2564612254
Short name T623
Test name
Test status
Simulation time 206281267 ps
CPU time 0.74 seconds
Started Jul 21 06:31:58 PM PDT 24
Finished Jul 21 06:32:00 PM PDT 24
Peak memory 206436 kb
Host smart-70c905f5-200c-4af3-8f05-4d4062620bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564612254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2564612254
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1408403951
Short name T564
Test name
Test status
Simulation time 950330170 ps
CPU time 7.11 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 233024 kb
Host smart-14f8a5b8-ae75-4a3a-971f-9cd3cd27ed03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408403951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1408403951
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1124460333
Short name T953
Test name
Test status
Simulation time 23054048 ps
CPU time 0.73 seconds
Started Jul 21 06:32:04 PM PDT 24
Finished Jul 21 06:32:06 PM PDT 24
Peak memory 205988 kb
Host smart-22e7a234-ab9e-4121-ae25-5b4f285d8acc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124460333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1124460333
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2777382191
Short name T510
Test name
Test status
Simulation time 441476737 ps
CPU time 3.11 seconds
Started Jul 21 06:32:01 PM PDT 24
Finished Jul 21 06:32:05 PM PDT 24
Peak memory 233184 kb
Host smart-1fc33cd7-8d21-4929-84d9-af64cf4bac81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777382191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2777382191
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.236183739
Short name T691
Test name
Test status
Simulation time 14526402 ps
CPU time 0.74 seconds
Started Jul 21 06:31:55 PM PDT 24
Finished Jul 21 06:31:56 PM PDT 24
Peak memory 206004 kb
Host smart-f6302f13-83e4-467d-9f81-87ec39a7a296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236183739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.236183739
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4105172558
Short name T231
Test name
Test status
Simulation time 22392378658 ps
CPU time 146.14 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:34:34 PM PDT 24
Peak memory 239788 kb
Host smart-26d3bf3d-8de9-4e31-b1dc-ab998e8fc066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105172558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4105172558
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.326945959
Short name T336
Test name
Test status
Simulation time 14601610434 ps
CPU time 90.69 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:33:42 PM PDT 24
Peak memory 257852 kb
Host smart-4b956a28-3f4b-4270-bf5f-2a20339fd23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326945959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.326945959
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.761817104
Short name T233
Test name
Test status
Simulation time 3144972907 ps
CPU time 45.17 seconds
Started Jul 21 06:32:03 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 248748 kb
Host smart-640b5163-d852-40cf-b0e5-f2910ca90cf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761817104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.761817104
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3960051839
Short name T415
Test name
Test status
Simulation time 495524885 ps
CPU time 3.25 seconds
Started Jul 21 06:32:05 PM PDT 24
Finished Jul 21 06:32:09 PM PDT 24
Peak memory 233224 kb
Host smart-73b5727e-48e7-4ebc-84e2-aba37d5be078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960051839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3960051839
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1300260223
Short name T309
Test name
Test status
Simulation time 226872708 ps
CPU time 4.38 seconds
Started Jul 21 06:32:04 PM PDT 24
Finished Jul 21 06:32:09 PM PDT 24
Peak memory 224940 kb
Host smart-c5667f3d-24ba-4a1c-8675-25a833a9a0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300260223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1300260223
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1099523427
Short name T146
Test name
Test status
Simulation time 27814074367 ps
CPU time 64.87 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 234516 kb
Host smart-f8e38e68-c6a5-4a6c-a69f-8302fc3fc14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099523427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1099523427
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1599181147
Short name T896
Test name
Test status
Simulation time 47308044382 ps
CPU time 19.26 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:29 PM PDT 24
Peak memory 238860 kb
Host smart-1b72c066-ec12-4e0e-8aa4-5a69da82aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599181147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1599181147
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2634044862
Short name T840
Test name
Test status
Simulation time 13155139726 ps
CPU time 8.59 seconds
Started Jul 21 06:32:01 PM PDT 24
Finished Jul 21 06:32:11 PM PDT 24
Peak memory 224960 kb
Host smart-ad34f4ad-dab2-4134-ab11-02ff1bae4dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634044862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2634044862
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.682108839
Short name T395
Test name
Test status
Simulation time 743800872 ps
CPU time 4.38 seconds
Started Jul 21 06:32:02 PM PDT 24
Finished Jul 21 06:32:07 PM PDT 24
Peak memory 220788 kb
Host smart-443186fa-4f09-499d-82c8-6338e608be29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=682108839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.682108839
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.2364173542
Short name T627
Test name
Test status
Simulation time 9251081581 ps
CPU time 97.71 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:33:48 PM PDT 24
Peak memory 253928 kb
Host smart-05c8c29f-fdbb-4cf6-b592-ac22e546bc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364173542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.2364173542
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.453319364
Short name T810
Test name
Test status
Simulation time 13905816176 ps
CPU time 11.38 seconds
Started Jul 21 06:31:56 PM PDT 24
Finished Jul 21 06:32:09 PM PDT 24
Peak memory 216792 kb
Host smart-7c50a099-4bfd-4aa5-8d95-80498146c5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453319364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.453319364
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.19163506
Short name T875
Test name
Test status
Simulation time 6603010977 ps
CPU time 19.75 seconds
Started Jul 21 06:31:58 PM PDT 24
Finished Jul 21 06:32:18 PM PDT 24
Peak memory 216748 kb
Host smart-645ea073-cc84-4738-9642-ecd677cb34b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19163506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.19163506
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3414870830
Short name T517
Test name
Test status
Simulation time 60472677 ps
CPU time 3.04 seconds
Started Jul 21 06:32:03 PM PDT 24
Finished Jul 21 06:32:07 PM PDT 24
Peak memory 216700 kb
Host smart-d0e504eb-3faf-468a-adb1-c1f7c7c91edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414870830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3414870830
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3033581878
Short name T858
Test name
Test status
Simulation time 125969548 ps
CPU time 0.85 seconds
Started Jul 21 06:31:58 PM PDT 24
Finished Jul 21 06:32:00 PM PDT 24
Peak memory 207488 kb
Host smart-07399ef6-5c7d-4b08-871d-f402cc0faeb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033581878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3033581878
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3368301779
Short name T84
Test name
Test status
Simulation time 2052290571 ps
CPU time 15.09 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:25 PM PDT 24
Peak memory 233276 kb
Host smart-babf0aba-5944-49e1-90a0-2ad0ae87ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368301779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3368301779
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.582056844
Short name T536
Test name
Test status
Simulation time 25958748 ps
CPU time 0.74 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:13 PM PDT 24
Peak memory 205372 kb
Host smart-0faf2711-353d-4a47-91a3-84f0b6179be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582056844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.582056844
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2783303262
Short name T898
Test name
Test status
Simulation time 59124360 ps
CPU time 2.99 seconds
Started Jul 21 06:32:03 PM PDT 24
Finished Jul 21 06:32:07 PM PDT 24
Peak memory 233084 kb
Host smart-9baf2e31-3d5d-41c5-bd5c-70248fe34b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783303262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2783303262
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2641033030
Short name T451
Test name
Test status
Simulation time 63400786 ps
CPU time 0.79 seconds
Started Jul 21 06:32:12 PM PDT 24
Finished Jul 21 06:32:14 PM PDT 24
Peak memory 207100 kb
Host smart-48cc1903-83ef-46d1-980e-d8cc8fe12afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641033030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2641033030
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2754804298
Short name T323
Test name
Test status
Simulation time 371988021 ps
CPU time 8.64 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 234912 kb
Host smart-20c41a96-4e48-4d28-a6d0-704e5612c649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754804298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2754804298
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1131202989
Short name T744
Test name
Test status
Simulation time 15051754891 ps
CPU time 170.95 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 255704 kb
Host smart-7e83e5a7-159a-4ccd-9cb2-649eb189bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131202989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1131202989
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.1930165924
Short name T578
Test name
Test status
Simulation time 1232000353 ps
CPU time 10.74 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 217840 kb
Host smart-029390ff-612d-42be-8bcb-6fd7f267d5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930165924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.1930165924
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3148358632
Short name T345
Test name
Test status
Simulation time 4016023621 ps
CPU time 24.41 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:33 PM PDT 24
Peak memory 241368 kb
Host smart-5ef8af03-14a8-440f-a000-26cd9d61d840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148358632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3148358632
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2135134039
Short name T473
Test name
Test status
Simulation time 23685925545 ps
CPU time 91.06 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 254384 kb
Host smart-7f90fdf3-f054-4991-88b9-343e51faedfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135134039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2135134039
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.2659845390
Short name T922
Test name
Test status
Simulation time 402446265 ps
CPU time 6.5 seconds
Started Jul 21 06:32:02 PM PDT 24
Finished Jul 21 06:32:10 PM PDT 24
Peak memory 224908 kb
Host smart-1d23879f-ccab-42cc-8592-e0d2d7d0c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659845390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.2659845390
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3243935502
Short name T959
Test name
Test status
Simulation time 247652194 ps
CPU time 4.36 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 224888 kb
Host smart-c676ea6f-0cf0-4419-a2b2-3e5be2355e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243935502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3243935502
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.137359403
Short name T296
Test name
Test status
Simulation time 9538392098 ps
CPU time 8.82 seconds
Started Jul 21 06:32:03 PM PDT 24
Finished Jul 21 06:32:13 PM PDT 24
Peak memory 224964 kb
Host smart-1256d6a8-11c4-4c10-a343-3abbb345e7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137359403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap
.137359403
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1876029320
Short name T803
Test name
Test status
Simulation time 241824101 ps
CPU time 2.17 seconds
Started Jul 21 06:32:02 PM PDT 24
Finished Jul 21 06:32:06 PM PDT 24
Peak memory 232772 kb
Host smart-9ab9c47a-f3d3-40ca-aecd-7e3249938e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876029320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1876029320
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3772773888
Short name T982
Test name
Test status
Simulation time 1136954866 ps
CPU time 12.4 seconds
Started Jul 21 06:32:11 PM PDT 24
Finished Jul 21 06:32:25 PM PDT 24
Peak memory 219664 kb
Host smart-552f2450-adcb-441b-977a-365be57b4da6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3772773888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3772773888
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.933522093
Short name T502
Test name
Test status
Simulation time 540548474 ps
CPU time 4.59 seconds
Started Jul 21 06:32:11 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 216900 kb
Host smart-452e863c-6d25-422c-94f9-68230a948fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933522093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.933522093
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3008734440
Short name T369
Test name
Test status
Simulation time 11173670 ps
CPU time 0.71 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:13 PM PDT 24
Peak memory 206248 kb
Host smart-9d231304-63ff-48c2-9570-1e145d067624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008734440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3008734440
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.496346931
Short name T424
Test name
Test status
Simulation time 174560685 ps
CPU time 1.39 seconds
Started Jul 21 06:32:04 PM PDT 24
Finished Jul 21 06:32:06 PM PDT 24
Peak memory 216708 kb
Host smart-bfe5260e-8bc7-419e-837e-f9a1912d94bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496346931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.496346931
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3811007948
Short name T537
Test name
Test status
Simulation time 18511312 ps
CPU time 0.71 seconds
Started Jul 21 06:32:07 PM PDT 24
Finished Jul 21 06:32:09 PM PDT 24
Peak memory 206380 kb
Host smart-83653233-16f7-4db2-8b31-defa68025bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811007948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3811007948
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2997553824
Short name T9
Test name
Test status
Simulation time 3929728905 ps
CPU time 11 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:20 PM PDT 24
Peak memory 239956 kb
Host smart-5c1b2715-3ad9-420f-a3f5-0595cad29387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997553824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2997553824
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.324577582
Short name T673
Test name
Test status
Simulation time 31675673 ps
CPU time 0.7 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:12 PM PDT 24
Peak memory 205848 kb
Host smart-5ce3218b-cbf7-4f7f-b475-e026949857e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324577582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.324577582
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1761173547
Short name T884
Test name
Test status
Simulation time 96984455 ps
CPU time 2.86 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:13 PM PDT 24
Peak memory 233184 kb
Host smart-945873ba-3396-471e-8745-2ec4454b31e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761173547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1761173547
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.4175748765
Short name T777
Test name
Test status
Simulation time 15908905 ps
CPU time 0.88 seconds
Started Jul 21 06:32:11 PM PDT 24
Finished Jul 21 06:32:14 PM PDT 24
Peak memory 206988 kb
Host smart-a2ace6c0-732e-4c3f-bf6d-c391e2ca222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175748765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.4175748765
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3976594364
Short name T925
Test name
Test status
Simulation time 16926745980 ps
CPU time 113.72 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 249708 kb
Host smart-30c1aec6-3da3-4ce6-857e-2c7697face7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976594364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3976594364
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.2157013826
Short name T326
Test name
Test status
Simulation time 25606557941 ps
CPU time 196.05 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:35:29 PM PDT 24
Peak memory 250612 kb
Host smart-12e3634b-09d3-483b-a79a-191e064a43dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157013826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2157013826
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2328662779
Short name T496
Test name
Test status
Simulation time 39103332491 ps
CPU time 138.74 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:34:27 PM PDT 24
Peak memory 249628 kb
Host smart-0013a526-19e1-4359-985e-1681f13a9355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328662779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2328662779
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.1561482830
Short name T766
Test name
Test status
Simulation time 351911603 ps
CPU time 13.27 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 249560 kb
Host smart-a42456ab-354f-4565-989f-7ae7c3834b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561482830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.1561482830
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.406949503
Short name T263
Test name
Test status
Simulation time 3939899870 ps
CPU time 36.39 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 249592 kb
Host smart-decd8a3b-a5cd-4685-a2fb-63a8d8ce0a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406949503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.406949503
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3200266789
Short name T534
Test name
Test status
Simulation time 526099173 ps
CPU time 7.9 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:20 PM PDT 24
Peak memory 233104 kb
Host smart-a7fd73c1-4f85-471b-b8b5-53451fe09fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200266789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3200266789
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1844107636
Short name T670
Test name
Test status
Simulation time 9216851688 ps
CPU time 15.9 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:27 PM PDT 24
Peak memory 236452 kb
Host smart-af691825-64c1-40e4-87bc-53d1b1b01c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844107636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1844107636
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.4166416076
Short name T1005
Test name
Test status
Simulation time 243684474 ps
CPU time 2.34 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:12 PM PDT 24
Peak memory 224188 kb
Host smart-287ec9f2-be90-41a0-b52b-ab315dac9749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166416076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.4166416076
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2995483460
Short name T286
Test name
Test status
Simulation time 6313881473 ps
CPU time 15.6 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 224920 kb
Host smart-799d35d4-18c2-4584-818a-67e129e3eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995483460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2995483460
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3373692753
Short name T860
Test name
Test status
Simulation time 4036297222 ps
CPU time 12.53 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 222720 kb
Host smart-3096315a-86ee-4173-8cdd-b83d1cbedb00
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3373692753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3373692753
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4175194927
Short name T19
Test name
Test status
Simulation time 156824947 ps
CPU time 0.97 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:12 PM PDT 24
Peak memory 207368 kb
Host smart-cdbef057-a2c3-431f-8c58-bcf1d14af764
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175194927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4175194927
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3226904531
Short name T628
Test name
Test status
Simulation time 2907227057 ps
CPU time 5.87 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 216816 kb
Host smart-157265d8-49ef-46e7-824d-efd7a76ae1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226904531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3226904531
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.2445122414
Short name T543
Test name
Test status
Simulation time 1032338332 ps
CPU time 3.29 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:15 PM PDT 24
Peak memory 216708 kb
Host smart-28e972b5-9041-4333-a50f-7ae6681af804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445122414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.2445122414
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3553982566
Short name T714
Test name
Test status
Simulation time 297252247 ps
CPU time 6.22 seconds
Started Jul 21 06:32:10 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 216716 kb
Host smart-e365a983-63af-4c21-b687-62a11c03d278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553982566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3553982566
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3566736611
Short name T654
Test name
Test status
Simulation time 138719510 ps
CPU time 0.85 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:13 PM PDT 24
Peak memory 206436 kb
Host smart-02303dfc-b031-4476-8297-80470b64f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566736611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3566736611
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.2139946641
Short name T301
Test name
Test status
Simulation time 567230272 ps
CPU time 5.15 seconds
Started Jul 21 06:32:08 PM PDT 24
Finished Jul 21 06:32:13 PM PDT 24
Peak memory 233084 kb
Host smart-2d09e15d-7fda-4fd3-a39f-2919467aba30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139946641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.2139946641
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.807945803
Short name T396
Test name
Test status
Simulation time 21911291 ps
CPU time 0.81 seconds
Started Jul 21 06:29:33 PM PDT 24
Finished Jul 21 06:29:35 PM PDT 24
Peak memory 205392 kb
Host smart-37b84f20-6b23-40f1-9a5d-756783839bd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807945803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.807945803
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1278902667
Short name T794
Test name
Test status
Simulation time 1768707598 ps
CPU time 4.88 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:29:46 PM PDT 24
Peak memory 224936 kb
Host smart-7f3d79df-58cd-4c4d-bce8-73d201411c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278902667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1278902667
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3282066449
Short name T799
Test name
Test status
Simulation time 70408470 ps
CPU time 0.77 seconds
Started Jul 21 06:29:30 PM PDT 24
Finished Jul 21 06:29:31 PM PDT 24
Peak memory 207092 kb
Host smart-7677bcc3-1313-4975-be96-00dd6ba94606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282066449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3282066449
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1450070217
Short name T149
Test name
Test status
Simulation time 40616114930 ps
CPU time 133.21 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:31:48 PM PDT 24
Peak memory 254172 kb
Host smart-a7b72328-470c-40d0-87ec-a62eb9fd8a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450070217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1450070217
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2064204843
Short name T685
Test name
Test status
Simulation time 7979794602 ps
CPU time 41.77 seconds
Started Jul 21 06:29:32 PM PDT 24
Finished Jul 21 06:30:14 PM PDT 24
Peak memory 249492 kb
Host smart-64ec7bff-793e-4de5-83bc-12ae0cd72fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064204843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2064204843
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.3196375838
Short name T36
Test name
Test status
Simulation time 4241519315 ps
CPU time 47.73 seconds
Started Jul 21 06:29:32 PM PDT 24
Finished Jul 21 06:30:20 PM PDT 24
Peak memory 251704 kb
Host smart-d4685ce6-2cc1-41d9-925c-dbf740619efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196375838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.3196375838
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1643741069
Short name T441
Test name
Test status
Simulation time 1039198187 ps
CPU time 19.1 seconds
Started Jul 21 06:29:33 PM PDT 24
Finished Jul 21 06:29:53 PM PDT 24
Peak memory 240140 kb
Host smart-1e209e14-a898-41e9-8bae-c2a1555f398d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643741069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1643741069
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3848431218
Short name T230
Test name
Test status
Simulation time 22202244179 ps
CPU time 231.61 seconds
Started Jul 21 06:29:31 PM PDT 24
Finished Jul 21 06:33:23 PM PDT 24
Peak memory 265664 kb
Host smart-427dd1f3-5f9f-4c07-926e-6673ec77e47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848431218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3848431218
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.107127733
Short name T599
Test name
Test status
Simulation time 33574641 ps
CPU time 2.33 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 233144 kb
Host smart-02dba946-06f5-41cb-ac48-96c7a6a0b518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107127733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.107127733
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3147651136
Short name T897
Test name
Test status
Simulation time 5077596921 ps
CPU time 20.35 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:30:01 PM PDT 24
Peak memory 241028 kb
Host smart-3dbac8a7-752c-4325-ac6c-d555d7fe7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147651136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3147651136
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.1291241370
Short name T235
Test name
Test status
Simulation time 6033730146 ps
CPU time 23.98 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 249936 kb
Host smart-71915272-85c1-4345-ac05-55d0b70c5a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291241370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.1291241370
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2820741600
Short name T577
Test name
Test status
Simulation time 145911541 ps
CPU time 4.92 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:29:39 PM PDT 24
Peak memory 236200 kb
Host smart-cde82668-b2f9-4694-87f7-4e5d36adf2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820741600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2820741600
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.3488280136
Short name T859
Test name
Test status
Simulation time 156795667 ps
CPU time 3.69 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 219248 kb
Host smart-da5cccce-1161-471d-aa3f-d3d13f568b84
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3488280136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.3488280136
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4135889128
Short name T80
Test name
Test status
Simulation time 757162744 ps
CPU time 1.07 seconds
Started Jul 21 06:29:32 PM PDT 24
Finished Jul 21 06:29:33 PM PDT 24
Peak memory 235520 kb
Host smart-6f0c72c7-b4dd-430a-b21f-1998cecc78f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135889128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4135889128
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3109550889
Short name T18
Test name
Test status
Simulation time 142302564 ps
CPU time 0.92 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:43 PM PDT 24
Peak memory 206092 kb
Host smart-be0c59a8-84d5-46d0-ba5c-b91121d909f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109550889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3109550889
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2729833714
Short name T756
Test name
Test status
Simulation time 2669777992 ps
CPU time 13.81 seconds
Started Jul 21 06:29:30 PM PDT 24
Finished Jul 21 06:29:44 PM PDT 24
Peak memory 220784 kb
Host smart-f3560860-489a-4e11-b346-2b26c60c060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729833714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2729833714
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.823959325
Short name T493
Test name
Test status
Simulation time 23703096365 ps
CPU time 13.48 seconds
Started Jul 21 06:29:35 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 216704 kb
Host smart-a8babe27-d604-498a-ba98-c6c3c97e6724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823959325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.823959325
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1716001658
Short name T406
Test name
Test status
Simulation time 32420219 ps
CPU time 0.71 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:29:35 PM PDT 24
Peak memory 206080 kb
Host smart-2ff59ac9-fd3c-4816-a258-ef616598b881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716001658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1716001658
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.325965442
Short name T410
Test name
Test status
Simulation time 124541928 ps
CPU time 1.03 seconds
Started Jul 21 06:29:34 PM PDT 24
Finished Jul 21 06:29:35 PM PDT 24
Peak memory 207460 kb
Host smart-e58e2674-86a6-4995-af63-0e02bcdfc13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325965442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.325965442
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2095064034
Short name T706
Test name
Test status
Simulation time 41878859 ps
CPU time 2.44 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 224628 kb
Host smart-5c4e1d9c-a273-42bd-8339-164338322c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095064034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2095064034
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1579659606
Short name T417
Test name
Test status
Simulation time 21815335 ps
CPU time 0.73 seconds
Started Jul 21 06:32:15 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 205968 kb
Host smart-ced97596-8b6b-4892-a5d4-22c85fa9a99b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579659606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1579659606
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.4092816872
Short name T99
Test name
Test status
Simulation time 94799295 ps
CPU time 2.46 seconds
Started Jul 21 06:32:15 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 224940 kb
Host smart-aa149b3f-523f-4ac7-b07a-d4c03f613465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092816872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.4092816872
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.836999775
Short name T568
Test name
Test status
Simulation time 25457783 ps
CPU time 0.77 seconds
Started Jul 21 06:32:09 PM PDT 24
Finished Jul 21 06:32:11 PM PDT 24
Peak memory 206044 kb
Host smart-c30a5823-0beb-4dc9-8d56-821e641ea657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836999775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.836999775
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1868175963
Short name T863
Test name
Test status
Simulation time 27720801290 ps
CPU time 228.45 seconds
Started Jul 21 06:32:19 PM PDT 24
Finished Jul 21 06:36:09 PM PDT 24
Peak memory 255524 kb
Host smart-4376369d-78fa-44d4-a737-db3c72e42fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868175963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1868175963
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2735988647
Short name T626
Test name
Test status
Simulation time 97032914026 ps
CPU time 208.65 seconds
Started Jul 21 06:32:15 PM PDT 24
Finished Jul 21 06:35:45 PM PDT 24
Peak memory 253108 kb
Host smart-25e3b2bc-3feb-4cd2-813a-e55e5b3c88d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735988647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2735988647
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3766743838
Short name T164
Test name
Test status
Simulation time 156977597 ps
CPU time 4.36 seconds
Started Jul 21 06:32:15 PM PDT 24
Finished Jul 21 06:32:21 PM PDT 24
Peak memory 224888 kb
Host smart-128a0bd1-5c93-4029-8180-5e27b4eaedc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766743838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3766743838
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1311720086
Short name T283
Test name
Test status
Simulation time 11741597391 ps
CPU time 80.41 seconds
Started Jul 21 06:32:16 PM PDT 24
Finished Jul 21 06:33:38 PM PDT 24
Peak memory 249604 kb
Host smart-42c7eeba-f46e-4460-b12b-e37e0e91997d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311720086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1311720086
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2361384395
Short name T601
Test name
Test status
Simulation time 957591177 ps
CPU time 9.92 seconds
Started Jul 21 06:32:19 PM PDT 24
Finished Jul 21 06:32:30 PM PDT 24
Peak memory 233112 kb
Host smart-804aa0da-d89e-4a35-b763-e9cf5995046a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361384395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2361384395
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4241327710
Short name T705
Test name
Test status
Simulation time 3275945256 ps
CPU time 10.11 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 224960 kb
Host smart-e273b890-0711-4438-a661-e75fea224458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241327710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4241327710
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2268954540
Short name T999
Test name
Test status
Simulation time 1110754000 ps
CPU time 4.73 seconds
Started Jul 21 06:32:15 PM PDT 24
Finished Jul 21 06:32:21 PM PDT 24
Peak memory 233088 kb
Host smart-6acd151d-e773-40ef-be66-cd6a8f1f9a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268954540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2268954540
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1173029398
Short name T805
Test name
Test status
Simulation time 13980223617 ps
CPU time 9.81 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:31 PM PDT 24
Peak memory 224960 kb
Host smart-449487b4-736a-40ad-8b2f-5718fe0701f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173029398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1173029398
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.456298218
Short name T783
Test name
Test status
Simulation time 6973068231 ps
CPU time 20.81 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:42 PM PDT 24
Peak memory 222524 kb
Host smart-c5dfee3b-aaa1-4037-9523-94aed320ea08
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=456298218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.456298218
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3926892047
Short name T797
Test name
Test status
Simulation time 13458600362 ps
CPU time 114.25 seconds
Started Jul 21 06:32:15 PM PDT 24
Finished Jul 21 06:34:11 PM PDT 24
Peak memory 257760 kb
Host smart-f4a8fe92-2b37-41c8-af71-3f5466909c78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926892047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3926892047
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.687510629
Short name T919
Test name
Test status
Simulation time 4752668497 ps
CPU time 19.13 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:32:35 PM PDT 24
Peak memory 216704 kb
Host smart-5ddba3d3-e98f-42be-a5ea-da663270bb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687510629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.687510629
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2266720355
Short name T738
Test name
Test status
Simulation time 79573498 ps
CPU time 0.87 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 206004 kb
Host smart-15478d75-24a9-4d4f-824d-a9120c8e2c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266720355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2266720355
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2910515022
Short name T148
Test name
Test status
Simulation time 167870341 ps
CPU time 0.77 seconds
Started Jul 21 06:32:19 PM PDT 24
Finished Jul 21 06:32:20 PM PDT 24
Peak memory 206444 kb
Host smart-c9bf6e89-d9e1-4fbb-83a3-cf2bc96b4566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910515022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2910515022
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.872730913
Short name T856
Test name
Test status
Simulation time 1508714317 ps
CPU time 4.31 seconds
Started Jul 21 06:32:13 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 233112 kb
Host smart-f73620d1-7aec-49d7-bdd4-f6c42e9f1cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872730913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.872730913
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2671938366
Short name T88
Test name
Test status
Simulation time 36391458 ps
CPU time 0.72 seconds
Started Jul 21 06:32:19 PM PDT 24
Finished Jul 21 06:32:21 PM PDT 24
Peak memory 205944 kb
Host smart-fd9a8a8a-3133-4e9c-aec2-6b5ef9963268
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671938366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2671938366
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1705577299
Short name T776
Test name
Test status
Simulation time 4063821505 ps
CPU time 8.18 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:32:30 PM PDT 24
Peak memory 233156 kb
Host smart-1c22bdaa-5bad-4558-94c0-db12c0b234b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705577299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1705577299
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2358376926
Short name T682
Test name
Test status
Simulation time 298119407 ps
CPU time 0.81 seconds
Started Jul 21 06:32:17 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 207384 kb
Host smart-47ce8916-ec74-443d-9958-3be2b6bea800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358376926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2358376926
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.2294106747
Short name T185
Test name
Test status
Simulation time 6945923322 ps
CPU time 35.31 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:56 PM PDT 24
Peak memory 251480 kb
Host smart-cac12dbf-bef0-4b56-ba3a-d7834ff17982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294106747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2294106747
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3435117713
Short name T321
Test name
Test status
Simulation time 7988522847 ps
CPU time 169.94 seconds
Started Jul 21 06:32:23 PM PDT 24
Finished Jul 21 06:35:14 PM PDT 24
Peak memory 273240 kb
Host smart-15d458d2-1161-4947-9609-81548a4ea873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435117713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3435117713
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3335066859
Short name T787
Test name
Test status
Simulation time 8064016035 ps
CPU time 74.38 seconds
Started Jul 21 06:32:23 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 249640 kb
Host smart-1b704879-5f9a-4cfc-959a-2e3ab9e0dce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335066859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3335066859
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.396643265
Short name T342
Test name
Test status
Simulation time 336946321 ps
CPU time 8.46 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:32:31 PM PDT 24
Peak memory 236992 kb
Host smart-11dc2f1f-d27c-47f8-8e06-3f6b350a6146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396643265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.396643265
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2682626772
Short name T436
Test name
Test status
Simulation time 1902939642 ps
CPU time 17.68 seconds
Started Jul 21 06:32:19 PM PDT 24
Finished Jul 21 06:32:38 PM PDT 24
Peak memory 237408 kb
Host smart-7f58da43-17e8-415b-86d4-09e2a7c10920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682626772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2682626772
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.4275710691
Short name T698
Test name
Test status
Simulation time 1042739595 ps
CPU time 7.35 seconds
Started Jul 21 06:32:18 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 233100 kb
Host smart-91d6ea77-6fbb-4389-a39d-78e2412c2bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275710691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.4275710691
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2186949889
Short name T732
Test name
Test status
Simulation time 15799977692 ps
CPU time 41.45 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:33:04 PM PDT 24
Peak memory 241028 kb
Host smart-6f743799-d646-4876-bec9-6bee20082062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186949889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2186949889
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2275856777
Short name T295
Test name
Test status
Simulation time 257676686 ps
CPU time 5.77 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:32:22 PM PDT 24
Peak memory 233108 kb
Host smart-51342b1e-47b7-44e5-9b8f-6bb7eb69c1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275856777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2275856777
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.82630407
Short name T260
Test name
Test status
Simulation time 307834977 ps
CPU time 4.75 seconds
Started Jul 21 06:32:17 PM PDT 24
Finished Jul 21 06:32:23 PM PDT 24
Peak memory 224948 kb
Host smart-54354bdd-1780-4a7f-8633-a024f9011266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82630407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.82630407
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2383583132
Short name T464
Test name
Test status
Simulation time 3006411390 ps
CPU time 4.52 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:32:27 PM PDT 24
Peak memory 221356 kb
Host smart-bded7187-bf93-4176-bc39-17ef3ae2e62d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383583132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2383583132
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3672316434
Short name T954
Test name
Test status
Simulation time 21105903834 ps
CPU time 246.24 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:36:28 PM PDT 24
Peak memory 266032 kb
Host smart-93f573d1-8181-4d11-b2a6-e5333203c71d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672316434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3672316434
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1360305726
Short name T905
Test name
Test status
Simulation time 4955302827 ps
CPU time 27.45 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 220156 kb
Host smart-c2342352-6bcc-407d-ac41-6a1aa7034c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360305726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1360305726
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.1889387986
Short name T675
Test name
Test status
Simulation time 6358676963 ps
CPU time 17.82 seconds
Started Jul 21 06:32:13 PM PDT 24
Finished Jul 21 06:32:33 PM PDT 24
Peak memory 216840 kb
Host smart-bea396ac-0b06-41ce-8049-636cd6e0349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889387986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.1889387986
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.628090818
Short name T665
Test name
Test status
Simulation time 69076822 ps
CPU time 1.62 seconds
Started Jul 21 06:32:14 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 216712 kb
Host smart-b700378d-bb95-4c16-8855-de3fcc8755aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628090818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.628090818
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1613228391
Short name T389
Test name
Test status
Simulation time 41527311 ps
CPU time 0.89 seconds
Started Jul 21 06:32:17 PM PDT 24
Finished Jul 21 06:32:19 PM PDT 24
Peak memory 206444 kb
Host smart-134ded6e-4223-4267-953b-7db3615ff2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613228391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1613228391
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.2532548495
Short name T815
Test name
Test status
Simulation time 4547990783 ps
CPU time 16.88 seconds
Started Jul 21 06:32:19 PM PDT 24
Finished Jul 21 06:32:37 PM PDT 24
Peak memory 239696 kb
Host smart-f14f7ccf-5680-4f9f-8026-4c9e3177882c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532548495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2532548495
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2278456530
Short name T847
Test name
Test status
Simulation time 16025316 ps
CPU time 0.72 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:29 PM PDT 24
Peak memory 205376 kb
Host smart-4ec7fb84-ec87-44b8-8012-19aff1d3e024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278456530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2278456530
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2995633008
Short name T604
Test name
Test status
Simulation time 35394022 ps
CPU time 2.2 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:31 PM PDT 24
Peak memory 224816 kb
Host smart-6346eae8-f7d9-4507-95e6-fe5a071c01a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995633008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2995633008
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3479865756
Short name T743
Test name
Test status
Simulation time 31840693 ps
CPU time 0.82 seconds
Started Jul 21 06:32:22 PM PDT 24
Finished Jul 21 06:32:23 PM PDT 24
Peak memory 207092 kb
Host smart-e6aaee1e-353c-4d3e-9575-941dcc9342a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479865756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3479865756
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.96647197
Short name T943
Test name
Test status
Simulation time 9959609676 ps
CPU time 95.09 seconds
Started Jul 21 06:32:30 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 249776 kb
Host smart-270f9ed8-aa02-43ca-b646-224acfc54218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96647197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.96647197
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1032959332
Short name T227
Test name
Test status
Simulation time 185490007456 ps
CPU time 469.48 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:40:17 PM PDT 24
Peak memory 266052 kb
Host smart-a8cb70b3-87c8-4e78-b41a-455581809ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032959332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1032959332
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1801199919
Short name T96
Test name
Test status
Simulation time 22410989624 ps
CPU time 204.91 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:35:53 PM PDT 24
Peak memory 241436 kb
Host smart-0b3aed7f-be32-4c90-930b-44a490ffd4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801199919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1801199919
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1883567363
Short name T725
Test name
Test status
Simulation time 57752308 ps
CPU time 2.18 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:31 PM PDT 24
Peak memory 224864 kb
Host smart-f0dcdbbe-42d8-4653-8128-22b9230b794a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883567363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1883567363
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.930629558
Short name T538
Test name
Test status
Simulation time 2301201023 ps
CPU time 40.46 seconds
Started Jul 21 06:32:26 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 241436 kb
Host smart-506c9ed2-2df9-4ed5-82ab-fbb8bb704321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930629558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.930629558
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.3125354205
Short name T303
Test name
Test status
Simulation time 11237382786 ps
CPU time 28.18 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 224956 kb
Host smart-4db9aed7-293f-431c-8ce6-c5059e6cf2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125354205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3125354205
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2313311403
Short name T753
Test name
Test status
Simulation time 2912151423 ps
CPU time 22.27 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 233236 kb
Host smart-d3831f1b-bebe-4909-bd26-509f6d448898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313311403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2313311403
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.559267753
Short name T25
Test name
Test status
Simulation time 6623858480 ps
CPU time 14.59 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:32:37 PM PDT 24
Peak memory 224956 kb
Host smart-0d24b488-5474-4f19-b793-145d64fee5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559267753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.559267753
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1339299579
Short name T882
Test name
Test status
Simulation time 1773237874 ps
CPU time 6.67 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:32:28 PM PDT 24
Peak memory 233040 kb
Host smart-a6795f66-c341-43fd-be51-fe27bcb5f514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339299579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1339299579
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.443838437
Short name T827
Test name
Test status
Simulation time 926761259 ps
CPU time 4.41 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:33 PM PDT 24
Peak memory 219852 kb
Host smart-cf3b786f-61c5-457a-90cc-65f10b34b2bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=443838437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.443838437
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.254111135
Short name T658
Test name
Test status
Simulation time 36834543 ps
CPU time 1 seconds
Started Jul 21 06:32:26 PM PDT 24
Finished Jul 21 06:32:28 PM PDT 24
Peak memory 208180 kb
Host smart-010f8f61-f1ea-42a3-8c19-76cc7382d17e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254111135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.254111135
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2598783784
Short name T547
Test name
Test status
Simulation time 341772006 ps
CPU time 5.43 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:26 PM PDT 24
Peak memory 216952 kb
Host smart-48ed2412-d1dc-4bab-9f3d-5252a2c10d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598783784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2598783784
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.981252026
Short name T935
Test name
Test status
Simulation time 55319556 ps
CPU time 0.7 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:21 PM PDT 24
Peak memory 206100 kb
Host smart-4bbdef72-4b91-4d8e-b312-bd6efe7c594f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981252026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.981252026
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.115910388
Short name T539
Test name
Test status
Simulation time 1049284913 ps
CPU time 2.67 seconds
Started Jul 21 06:32:20 PM PDT 24
Finished Jul 21 06:32:23 PM PDT 24
Peak memory 216660 kb
Host smart-a974b4c3-4340-4328-b6e0-d2dba38edf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115910388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.115910388
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.195427511
Short name T1003
Test name
Test status
Simulation time 11674957 ps
CPU time 0.72 seconds
Started Jul 21 06:32:21 PM PDT 24
Finished Jul 21 06:32:23 PM PDT 24
Peak memory 206072 kb
Host smart-f3f5c46b-e1a4-4b67-83a0-e9d41348cbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195427511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.195427511
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2350032467
Short name T476
Test name
Test status
Simulation time 22007505802 ps
CPU time 16.75 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 241236 kb
Host smart-db4b1650-fafe-4cdc-a358-880ead4740ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350032467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2350032467
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3941092422
Short name T72
Test name
Test status
Simulation time 141433222 ps
CPU time 0.73 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:32:28 PM PDT 24
Peak memory 205376 kb
Host smart-1489a5de-c0d1-4f30-8e67-c8cc17c68a85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941092422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3941092422
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.361450277
Short name T973
Test name
Test status
Simulation time 529831579 ps
CPU time 3.74 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:33 PM PDT 24
Peak memory 233100 kb
Host smart-e8600504-0440-4d6b-ad52-533b7e29a9ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361450277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.361450277
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2809434945
Short name T371
Test name
Test status
Simulation time 57571874 ps
CPU time 0.79 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:32:29 PM PDT 24
Peak memory 207460 kb
Host smart-b9ad2301-1742-44f0-87fb-da66dc65185c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809434945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2809434945
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2674392968
Short name T700
Test name
Test status
Simulation time 7827562950 ps
CPU time 71.66 seconds
Started Jul 21 06:32:29 PM PDT 24
Finished Jul 21 06:33:42 PM PDT 24
Peak memory 250512 kb
Host smart-938e83ad-6a44-44bd-b781-4f864f75b895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674392968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2674392968
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2400343457
Short name T56
Test name
Test status
Simulation time 17808603134 ps
CPU time 184.92 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:35:34 PM PDT 24
Peak memory 252968 kb
Host smart-ecbd8de8-ac21-44db-8681-3266748518ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400343457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2400343457
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3035036351
Short name T723
Test name
Test status
Simulation time 40836137034 ps
CPU time 153.46 seconds
Started Jul 21 06:32:26 PM PDT 24
Finished Jul 21 06:35:00 PM PDT 24
Peak memory 249600 kb
Host smart-045b8095-6f70-4fad-bbd5-b831f9f69f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035036351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3035036351
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3997382705
Short name T699
Test name
Test status
Simulation time 54696292 ps
CPU time 2.8 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:32 PM PDT 24
Peak memory 233176 kb
Host smart-b14a5a53-cbc9-4422-97da-09ef45ad3169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997382705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3997382705
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.973910874
Short name T237
Test name
Test status
Simulation time 54291644028 ps
CPU time 180.01 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 253708 kb
Host smart-721d8c98-6c7b-45dd-a3c6-2ef6772c6975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973910874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.973910874
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1022076386
Short name T720
Test name
Test status
Simulation time 814414426 ps
CPU time 9.82 seconds
Started Jul 21 06:32:26 PM PDT 24
Finished Jul 21 06:32:37 PM PDT 24
Peak memory 224984 kb
Host smart-20c076e8-ab72-4f3b-ab6c-a2aeb29d00e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022076386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1022076386
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2312436138
Short name T697
Test name
Test status
Simulation time 5992313643 ps
CPU time 60.28 seconds
Started Jul 21 06:32:30 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 249536 kb
Host smart-d2a31f6e-e457-4b8a-9fe5-abbb633af54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312436138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2312436138
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3876419575
Short name T288
Test name
Test status
Simulation time 2181257653 ps
CPU time 5.58 seconds
Started Jul 21 06:32:29 PM PDT 24
Finished Jul 21 06:32:35 PM PDT 24
Peak memory 240528 kb
Host smart-1b07397a-307a-4f11-941c-c0b515b9b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876419575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3876419575
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1957612696
Short name T273
Test name
Test status
Simulation time 39699399384 ps
CPU time 27.93 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:32:56 PM PDT 24
Peak memory 250848 kb
Host smart-69338381-4ee3-4e61-9145-dd7ce1d5af2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957612696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1957612696
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.3240786496
Short name T167
Test name
Test status
Simulation time 3928818104 ps
CPU time 11.85 seconds
Started Jul 21 06:32:26 PM PDT 24
Finished Jul 21 06:32:38 PM PDT 24
Peak memory 222572 kb
Host smart-19002ee2-dd57-4244-bfce-8a473f99f776
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3240786496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.3240786496
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1387038850
Short name T886
Test name
Test status
Simulation time 5708386550 ps
CPU time 127.15 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:34:34 PM PDT 24
Peak memory 274252 kb
Host smart-3409020d-ce3a-47a8-9dea-dd171eb80e39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387038850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1387038850
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3842668002
Short name T976
Test name
Test status
Simulation time 891848338 ps
CPU time 2.92 seconds
Started Jul 21 06:32:26 PM PDT 24
Finished Jul 21 06:32:29 PM PDT 24
Peak memory 219200 kb
Host smart-6ec7f02f-f0f6-4598-aabe-5c86cd4f0190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842668002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3842668002
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.206513791
Short name T683
Test name
Test status
Simulation time 9571737567 ps
CPU time 16.81 seconds
Started Jul 21 06:32:28 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 216688 kb
Host smart-69c9c206-a8da-4eb0-a0da-1c47827e1228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206513791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.206513791
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2242549200
Short name T556
Test name
Test status
Simulation time 13082319 ps
CPU time 0.74 seconds
Started Jul 21 06:32:29 PM PDT 24
Finished Jul 21 06:32:30 PM PDT 24
Peak memory 206468 kb
Host smart-ccf0a6aa-e741-4c4e-8c84-7eabfb64c5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242549200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2242549200
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3945166497
Short name T575
Test name
Test status
Simulation time 72342023 ps
CPU time 0.83 seconds
Started Jul 21 06:32:29 PM PDT 24
Finished Jul 21 06:32:30 PM PDT 24
Peak memory 206464 kb
Host smart-e0f59416-da8a-4ac3-9ee7-93ff2a34ace5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945166497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3945166497
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1971224366
Short name T657
Test name
Test status
Simulation time 955542774 ps
CPU time 7.76 seconds
Started Jul 21 06:32:27 PM PDT 24
Finished Jul 21 06:32:35 PM PDT 24
Peak memory 224860 kb
Host smart-100b71ad-e01a-41d4-b73d-86783bc89f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971224366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1971224366
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2697741816
Short name T829
Test name
Test status
Simulation time 10993536 ps
CPU time 0.71 seconds
Started Jul 21 06:32:38 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 205376 kb
Host smart-54e33375-ac8d-41be-812f-c31af678901f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697741816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2697741816
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3521968335
Short name T287
Test name
Test status
Simulation time 1013534946 ps
CPU time 5.01 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:39 PM PDT 24
Peak memory 224928 kb
Host smart-7cf2200c-c065-418c-b5f8-7c40f0c8fd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521968335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3521968335
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1765653807
Short name T918
Test name
Test status
Simulation time 70704912 ps
CPU time 0.82 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:32:36 PM PDT 24
Peak memory 207068 kb
Host smart-e37b5024-ea58-4a29-994d-50c1ff8daa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765653807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1765653807
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1078813291
Short name T764
Test name
Test status
Simulation time 1844985933 ps
CPU time 44.55 seconds
Started Jul 21 06:32:35 PM PDT 24
Finished Jul 21 06:33:20 PM PDT 24
Peak memory 240060 kb
Host smart-cebcd17c-55ea-432b-abc9-b7d1c9dec5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078813291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1078813291
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.4086383829
Short name T324
Test name
Test status
Simulation time 60236548286 ps
CPU time 531.65 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:41:27 PM PDT 24
Peak memory 262748 kb
Host smart-d22733a9-4a56-490b-9db2-68f18f4fe70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086383829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.4086383829
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.346339759
Short name T65
Test name
Test status
Simulation time 101834416628 ps
CPU time 314.64 seconds
Started Jul 21 06:32:37 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 259544 kb
Host smart-4d12abc6-c2d8-4102-b61e-838ac8715d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346339759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.346339759
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.850153836
Short name T784
Test name
Test status
Simulation time 23960472747 ps
CPU time 82.63 seconds
Started Jul 21 06:32:32 PM PDT 24
Finished Jul 21 06:33:56 PM PDT 24
Peak memory 233192 kb
Host smart-84552a54-ebc3-4e3d-a873-5721acf2fb3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850153836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.850153836
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2967160857
Short name T520
Test name
Test status
Simulation time 4397502603 ps
CPU time 23.65 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:32:59 PM PDT 24
Peak memory 237484 kb
Host smart-2041dab0-e8ae-4f3d-a869-a8b2c41ba42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967160857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2967160857
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3723145364
Short name T980
Test name
Test status
Simulation time 122819185 ps
CPU time 4.18 seconds
Started Jul 21 06:32:37 PM PDT 24
Finished Jul 21 06:32:42 PM PDT 24
Peak memory 233164 kb
Host smart-5fd5bef3-1e1f-45e0-8590-39b7fc8edd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723145364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3723145364
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1928666416
Short name T586
Test name
Test status
Simulation time 1427281242 ps
CPU time 18.15 seconds
Started Jul 21 06:32:32 PM PDT 24
Finished Jul 21 06:32:50 PM PDT 24
Peak memory 250948 kb
Host smart-a6dfdb90-215b-4096-9292-84bf380de064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928666416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1928666416
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.1773881575
Short name T648
Test name
Test status
Simulation time 508513513 ps
CPU time 3.46 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:32:39 PM PDT 24
Peak memory 224884 kb
Host smart-3dd8f166-e4c0-4ee4-9f5f-a00318aa55fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773881575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.1773881575
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.2678520199
Short name T460
Test name
Test status
Simulation time 6695926505 ps
CPU time 4.13 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:38 PM PDT 24
Peak memory 233216 kb
Host smart-2ac79877-37f6-4eea-a99a-01f491855578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678520199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2678520199
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4116547090
Short name T767
Test name
Test status
Simulation time 815148310 ps
CPU time 9.81 seconds
Started Jul 21 06:32:35 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 222468 kb
Host smart-365e9cb5-bc3e-4540-b812-382a8334c813
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4116547090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4116547090
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2440084354
Short name T988
Test name
Test status
Simulation time 19155074131 ps
CPU time 81.4 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 237892 kb
Host smart-a0973872-055f-4802-b15f-9c4d060d3188
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440084354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2440084354
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2891421812
Short name T667
Test name
Test status
Simulation time 3865098586 ps
CPU time 24.19 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:58 PM PDT 24
Peak memory 217020 kb
Host smart-9aff87f9-5931-4a6e-9b88-8dcd58c48ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891421812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2891421812
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1280132507
Short name T662
Test name
Test status
Simulation time 28890489888 ps
CPU time 9.09 seconds
Started Jul 21 06:32:36 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 216780 kb
Host smart-e88654a3-6eac-4712-8d77-073184d495d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280132507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1280132507
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2110646596
Short name T145
Test name
Test status
Simulation time 11699802 ps
CPU time 0.7 seconds
Started Jul 21 06:32:35 PM PDT 24
Finished Jul 21 06:32:36 PM PDT 24
Peak memory 206032 kb
Host smart-c0d3aa17-7fa0-489c-8522-1cb782e58ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110646596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2110646596
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1505472762
Short name T32
Test name
Test status
Simulation time 32346385 ps
CPU time 0.79 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 206272 kb
Host smart-c5ddb023-a9ed-404b-ba73-3875b199446a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505472762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1505472762
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.213637973
Short name T986
Test name
Test status
Simulation time 25535452500 ps
CPU time 21.99 seconds
Started Jul 21 06:32:32 PM PDT 24
Finished Jul 21 06:32:55 PM PDT 24
Peak memory 233152 kb
Host smart-9d3f308e-e2ae-4e48-820a-6af5d66a0ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213637973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.213637973
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3749156056
Short name T674
Test name
Test status
Simulation time 16285347 ps
CPU time 0.68 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:34 PM PDT 24
Peak memory 205360 kb
Host smart-5874bbbb-4c88-494f-85f2-5056bbf0280e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749156056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3749156056
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.2400609190
Short name T307
Test name
Test status
Simulation time 802996446 ps
CPU time 8.21 seconds
Started Jul 21 06:32:32 PM PDT 24
Finished Jul 21 06:32:42 PM PDT 24
Peak memory 233136 kb
Host smart-c0a6b29a-47bd-4454-8840-5bd9c506b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400609190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.2400609190
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.163907170
Short name T472
Test name
Test status
Simulation time 34366935 ps
CPU time 0.78 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 206032 kb
Host smart-8c990182-15f2-4bd5-bba4-8cdcf0e8dede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163907170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.163907170
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2553629840
Short name T64
Test name
Test status
Simulation time 22740160189 ps
CPU time 189.69 seconds
Started Jul 21 06:32:32 PM PDT 24
Finished Jul 21 06:35:43 PM PDT 24
Peak memory 249612 kb
Host smart-b1d89d61-4d5b-4ec1-9da6-704865255862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553629840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2553629840
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2767303976
Short name T37
Test name
Test status
Simulation time 33556555503 ps
CPU time 166.91 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 251324 kb
Host smart-06fdce07-4297-4c45-8851-cff6f0652386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767303976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2767303976
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2027110315
Short name T789
Test name
Test status
Simulation time 1332355184 ps
CPU time 7.18 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 224776 kb
Host smart-48ba32e8-b8b6-44ab-9b6d-294ac3b0ecf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027110315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2027110315
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3481806627
Short name T349
Test name
Test status
Simulation time 411849149 ps
CPU time 10.52 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:51 PM PDT 24
Peak memory 233096 kb
Host smart-59e6b384-cd85-4120-8227-8e2b3bae12ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481806627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3481806627
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2986961489
Short name T480
Test name
Test status
Simulation time 2386096449 ps
CPU time 33.85 seconds
Started Jul 21 06:32:49 PM PDT 24
Finished Jul 21 06:33:25 PM PDT 24
Peak memory 253876 kb
Host smart-9d3bbebf-d704-4088-bd02-87e33117a7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986961489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2986961489
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.384120364
Short name T752
Test name
Test status
Simulation time 167632420 ps
CPU time 3.68 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:32:39 PM PDT 24
Peak memory 224968 kb
Host smart-5d7ffa09-c14e-4d0b-83fb-0d52b7d3ac17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384120364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.384120364
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1458259787
Short name T280
Test name
Test status
Simulation time 11702043381 ps
CPU time 106.92 seconds
Started Jul 21 06:32:35 PM PDT 24
Finished Jul 21 06:34:22 PM PDT 24
Peak memory 241004 kb
Host smart-d614b93a-1a9e-46d2-8732-8fb5a12705bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458259787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1458259787
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.639649250
Short name T1009
Test name
Test status
Simulation time 2363483975 ps
CPU time 9.2 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 241120 kb
Host smart-ff5242bd-c2e2-44cd-baf4-84df12bfb861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639649250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.639649250
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1145948768
Short name T408
Test name
Test status
Simulation time 668761639 ps
CPU time 4.04 seconds
Started Jul 21 06:32:38 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 233124 kb
Host smart-ac62c0c0-af9f-4d8c-a35e-50a184da61c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145948768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1145948768
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1568275450
Short name T659
Test name
Test status
Simulation time 96309604 ps
CPU time 3.58 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:37 PM PDT 24
Peak memory 220808 kb
Host smart-0a261c53-e804-4b8c-8f83-06f0d7834cc1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1568275450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1568275450
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.1356369106
Short name T340
Test name
Test status
Simulation time 3590198027 ps
CPU time 88.18 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:34:02 PM PDT 24
Peak memory 269412 kb
Host smart-f00469f5-72cc-4250-8330-1545c0cf0955
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356369106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.1356369106
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.187248396
Short name T488
Test name
Test status
Simulation time 8675954384 ps
CPU time 36.38 seconds
Started Jul 21 06:32:32 PM PDT 24
Finished Jul 21 06:33:10 PM PDT 24
Peak memory 216708 kb
Host smart-e49a4549-7149-472d-a695-1d7968d29e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187248396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.187248396
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.460434957
Short name T409
Test name
Test status
Simulation time 3236764541 ps
CPU time 4.92 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:32:40 PM PDT 24
Peak memory 216600 kb
Host smart-f067fb7c-a24c-4579-8a6f-d606e93952bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460434957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.460434957
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1610899261
Short name T570
Test name
Test status
Simulation time 45932146 ps
CPU time 2.21 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:42 PM PDT 24
Peak memory 216488 kb
Host smart-78dd0073-c3df-425b-b72c-a6224fee54a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610899261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1610899261
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.342368851
Short name T489
Test name
Test status
Simulation time 155780022 ps
CPU time 0.88 seconds
Started Jul 21 06:32:34 PM PDT 24
Finished Jul 21 06:32:36 PM PDT 24
Peak memory 207472 kb
Host smart-3e02c680-2356-4252-8fa1-3c42b6b1d53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342368851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.342368851
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.449979951
Short name T241
Test name
Test status
Simulation time 7813896798 ps
CPU time 3.87 seconds
Started Jul 21 06:32:33 PM PDT 24
Finished Jul 21 06:32:38 PM PDT 24
Peak memory 225016 kb
Host smart-ef2684c8-8fbf-4d2e-8350-09727221a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449979951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.449979951
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1203740163
Short name T967
Test name
Test status
Simulation time 15096897 ps
CPU time 0.81 seconds
Started Jul 21 06:32:41 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 205984 kb
Host smart-fbecece3-a1f5-4f58-91fb-e4815a8ae7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203740163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1203740163
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2979369606
Short name T422
Test name
Test status
Simulation time 1006880923 ps
CPU time 9.26 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:32:51 PM PDT 24
Peak memory 224884 kb
Host smart-4c8e13a7-3a2e-4d79-bc9d-da9f53b5aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979369606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2979369606
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2563983511
Short name T397
Test name
Test status
Simulation time 90274819 ps
CPU time 0.76 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:47 PM PDT 24
Peak memory 206048 kb
Host smart-02e0a0f6-020d-4ca3-98c7-e5e64e19d100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563983511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2563983511
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.200250412
Short name T225
Test name
Test status
Simulation time 2232488186 ps
CPU time 41.21 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:33:22 PM PDT 24
Peak memory 249612 kb
Host smart-32bc8b3c-19e9-4bdd-adc8-87952ff41c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200250412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.200250412
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1059899646
Short name T800
Test name
Test status
Simulation time 9451726122 ps
CPU time 138.26 seconds
Started Jul 21 06:32:37 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 263592 kb
Host smart-f0906ab6-4a6d-4c40-9b30-c0d2c2fc44a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059899646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1059899646
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.852898500
Short name T351
Test name
Test status
Simulation time 370129806 ps
CPU time 5.48 seconds
Started Jul 21 06:32:38 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 218240 kb
Host smart-01426f19-0300-48cc-93c5-14b5a8523063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852898500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.852898500
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3846720577
Short name T341
Test name
Test status
Simulation time 4806286920 ps
CPU time 23.94 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 225052 kb
Host smart-84e65cf0-d6c2-43d9-b34c-3e397d534804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846720577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3846720577
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2876279489
Short name T264
Test name
Test status
Simulation time 1059579392 ps
CPU time 23.63 seconds
Started Jul 21 06:32:41 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 249608 kb
Host smart-55dfb559-9af6-4c41-aafb-d39dc8092e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876279489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2876279489
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3069215433
Short name T668
Test name
Test status
Simulation time 160361029 ps
CPU time 3.38 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:44 PM PDT 24
Peak memory 224856 kb
Host smart-2e6316fe-92c0-4d34-a9ec-5a7864c9c498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069215433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3069215433
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1311008399
Short name T204
Test name
Test status
Simulation time 2250596412 ps
CPU time 10.23 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:50 PM PDT 24
Peak memory 233192 kb
Host smart-c62d331b-df4d-45cb-a3a5-c609858d82ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311008399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1311008399
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3695363652
Short name T908
Test name
Test status
Simulation time 9005158423 ps
CPU time 7.19 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 224972 kb
Host smart-1e62a335-f97c-4ec6-9f8a-fe986af41b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695363652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3695363652
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.710306856
Short name T618
Test name
Test status
Simulation time 2249888278 ps
CPU time 7.2 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 233284 kb
Host smart-69158943-caba-462c-854d-e33937b1d03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710306856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.710306856
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.70158325
Short name T581
Test name
Test status
Simulation time 943350014 ps
CPU time 6.23 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 223572 kb
Host smart-d3230cbb-d7ee-481f-9163-866013c4a7c6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=70158325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direc
t.70158325
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2320566781
Short name T824
Test name
Test status
Simulation time 8371934513 ps
CPU time 178.58 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:35:40 PM PDT 24
Peak memory 263580 kb
Host smart-c6d15afd-8869-46b6-aa80-eddca51bf278
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320566781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2320566781
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1129951902
Short name T915
Test name
Test status
Simulation time 46396359821 ps
CPU time 38.81 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 216720 kb
Host smart-3d748e63-78d9-472b-a3a4-1e334ef738cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129951902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1129951902
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3905161542
Short name T876
Test name
Test status
Simulation time 2011606184 ps
CPU time 10.75 seconds
Started Jul 21 06:32:38 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 216716 kb
Host smart-71d53852-67f0-4748-bc7b-641241068af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905161542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3905161542
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1655237606
Short name T733
Test name
Test status
Simulation time 19920494 ps
CPU time 0.98 seconds
Started Jul 21 06:32:42 PM PDT 24
Finished Jul 21 06:32:44 PM PDT 24
Peak memory 207440 kb
Host smart-090d15ab-e714-4115-8fce-f20440f8b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655237606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1655237606
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2649693081
Short name T401
Test name
Test status
Simulation time 40914008 ps
CPU time 0.76 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:32:42 PM PDT 24
Peak memory 206444 kb
Host smart-eb7a98a5-274c-46f5-a6f6-c3ad3c1a4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649693081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2649693081
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.257095879
Short name T10
Test name
Test status
Simulation time 467069910 ps
CPU time 5.97 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:51 PM PDT 24
Peak memory 236944 kb
Host smart-56df212d-4cd5-4c9e-bcb2-31c250c6eee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257095879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.257095879
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3894737803
Short name T963
Test name
Test status
Simulation time 51497088 ps
CPU time 0.7 seconds
Started Jul 21 06:32:46 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 205936 kb
Host smart-1b77ee66-48fa-4b9e-ad38-bb5c0b3a0440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894737803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3894737803
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1435241712
Short name T849
Test name
Test status
Simulation time 5036393358 ps
CPU time 3.43 seconds
Started Jul 21 06:32:48 PM PDT 24
Finished Jul 21 06:32:54 PM PDT 24
Peak memory 233128 kb
Host smart-a24fc7a1-ef58-4f23-93b7-5a1c74b8db44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435241712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1435241712
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3440578517
Short name T934
Test name
Test status
Simulation time 37817591 ps
CPU time 0.77 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:47 PM PDT 24
Peak memory 206048 kb
Host smart-e3042f54-f9fb-4d32-86e7-cb8574666a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440578517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3440578517
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.524805395
Short name T207
Test name
Test status
Simulation time 20279599655 ps
CPU time 135.67 seconds
Started Jul 21 06:32:47 PM PDT 24
Finished Jul 21 06:35:05 PM PDT 24
Peak memory 252164 kb
Host smart-1a264e77-57c9-4687-baea-1a8a21eb875c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524805395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.524805395
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2949865284
Short name T300
Test name
Test status
Simulation time 123057804071 ps
CPU time 135.1 seconds
Started Jul 21 06:32:48 PM PDT 24
Finished Jul 21 06:35:05 PM PDT 24
Peak memory 240412 kb
Host smart-f7e7b857-18df-4017-a354-fdb9cba3fa59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949865284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2949865284
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3700698480
Short name T877
Test name
Test status
Simulation time 3429975089 ps
CPU time 78.56 seconds
Started Jul 21 06:32:46 PM PDT 24
Finished Jul 21 06:34:07 PM PDT 24
Peak memory 257152 kb
Host smart-26a04a2b-5a21-4b89-b315-8daace5faede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700698480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3700698480
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3353883927
Short name T912
Test name
Test status
Simulation time 444708948 ps
CPU time 11.98 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:58 PM PDT 24
Peak memory 241260 kb
Host smart-b939f5be-ea3c-4597-b31d-c2a6289a2461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353883927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3353883927
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2251306976
Short name T901
Test name
Test status
Simulation time 88913675408 ps
CPU time 328.73 seconds
Started Jul 21 06:32:47 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 266872 kb
Host smart-fee438af-f1f9-46e9-a98f-f4b27e8fa33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251306976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2251306976
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.402565730
Short name T447
Test name
Test status
Simulation time 905918586 ps
CPU time 5.94 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:47 PM PDT 24
Peak memory 233108 kb
Host smart-1a363a0f-852e-43de-8359-8a33e8bd5d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402565730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.402565730
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2971264932
Short name T382
Test name
Test status
Simulation time 31229027 ps
CPU time 2.45 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 232716 kb
Host smart-4a082510-6db3-47ce-9929-12b474ae3f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971264932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2971264932
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3632922438
Short name T964
Test name
Test status
Simulation time 4464835532 ps
CPU time 4.66 seconds
Started Jul 21 06:32:42 PM PDT 24
Finished Jul 21 06:32:47 PM PDT 24
Peak memory 224908 kb
Host smart-b1861e17-2476-49f4-8068-4c5b2d1a77c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632922438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3632922438
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1737994577
Short name T210
Test name
Test status
Simulation time 1979574329 ps
CPU time 4.09 seconds
Started Jul 21 06:32:38 PM PDT 24
Finished Jul 21 06:32:44 PM PDT 24
Peak memory 233096 kb
Host smart-adb03f77-f2d3-430d-899e-ecd922668adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737994577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1737994577
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.3517862629
Short name T774
Test name
Test status
Simulation time 1625167387 ps
CPU time 8.29 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:54 PM PDT 24
Peak memory 222992 kb
Host smart-07797ef4-5ee6-4bea-b762-07e36d842060
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3517862629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.3517862629
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.509664209
Short name T159
Test name
Test status
Simulation time 3052980691 ps
CPU time 70.94 seconds
Started Jul 21 06:32:49 PM PDT 24
Finished Jul 21 06:34:02 PM PDT 24
Peak memory 249684 kb
Host smart-c10a856a-7c46-4b10-a62b-f891e2293a3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509664209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.509664209
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2828150183
Short name T647
Test name
Test status
Simulation time 2154347726 ps
CPU time 13.52 seconds
Started Jul 21 06:32:41 PM PDT 24
Finished Jul 21 06:32:55 PM PDT 24
Peak memory 216780 kb
Host smart-c2fe236b-2df5-476b-a31f-21eb3aade062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828150183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2828150183
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.3681990744
Short name T843
Test name
Test status
Simulation time 9638350621 ps
CPU time 3 seconds
Started Jul 21 06:32:40 PM PDT 24
Finished Jul 21 06:32:44 PM PDT 24
Peak memory 216616 kb
Host smart-070f0236-4593-4348-a47b-ebaa6c56e104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681990744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.3681990744
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1719060285
Short name T571
Test name
Test status
Simulation time 33031886 ps
CPU time 1.15 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:47 PM PDT 24
Peak memory 208060 kb
Host smart-672b45ae-b089-4b3e-a71a-56409f5992dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719060285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1719060285
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.35921512
Short name T804
Test name
Test status
Simulation time 61899773 ps
CPU time 0.76 seconds
Started Jul 21 06:32:39 PM PDT 24
Finished Jul 21 06:32:41 PM PDT 24
Peak memory 206480 kb
Host smart-01384765-e887-420d-8f78-9a551486274a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35921512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.35921512
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3881515968
Short name T469
Test name
Test status
Simulation time 76697955 ps
CPU time 2.38 seconds
Started Jul 21 06:32:45 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 234552 kb
Host smart-4d41431d-de42-4f78-89f6-817d74983d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881515968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3881515968
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.4107623966
Short name T736
Test name
Test status
Simulation time 11690401 ps
CPU time 0.7 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:32:59 PM PDT 24
Peak memory 205920 kb
Host smart-16c04d46-ac0a-410d-a6a1-6d39de923479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107623966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
4107623966
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1915389465
Short name T457
Test name
Test status
Simulation time 416379918 ps
CPU time 3.46 seconds
Started Jul 21 06:32:48 PM PDT 24
Finished Jul 21 06:32:53 PM PDT 24
Peak memory 233212 kb
Host smart-b0a7075e-91ea-49ff-b43c-a66aa87fdde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915389465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1915389465
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1852210837
Short name T484
Test name
Test status
Simulation time 35618122 ps
CPU time 0.79 seconds
Started Jul 21 06:32:49 PM PDT 24
Finished Jul 21 06:32:52 PM PDT 24
Peak memory 206060 kb
Host smart-4bc806ad-899b-45cb-9fb7-6145af226602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852210837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1852210837
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2929154439
Short name T891
Test name
Test status
Simulation time 255511983143 ps
CPU time 108.48 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:34:47 PM PDT 24
Peak memory 239740 kb
Host smart-24132532-8f3f-401d-ac53-41471d37555f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929154439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2929154439
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3491106118
Short name T621
Test name
Test status
Simulation time 154890156401 ps
CPU time 58.13 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:57 PM PDT 24
Peak memory 217824 kb
Host smart-c4214a8e-8cd9-4132-b739-89b0d4bea686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491106118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3491106118
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2600115190
Short name T554
Test name
Test status
Simulation time 20670137919 ps
CPU time 18.81 seconds
Started Jul 21 06:32:57 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 225068 kb
Host smart-e879b5c7-59e1-40b4-b38d-7084b9155b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600115190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2600115190
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3518617900
Short name T343
Test name
Test status
Simulation time 2022379813 ps
CPU time 22.14 seconds
Started Jul 21 06:32:48 PM PDT 24
Finished Jul 21 06:33:12 PM PDT 24
Peak memory 234764 kb
Host smart-be0ec62a-38f3-45eb-83e4-cfdbad664b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518617900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3518617900
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2202616607
Short name T531
Test name
Test status
Simulation time 14727016558 ps
CPU time 34.66 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 249580 kb
Host smart-40f1cc64-7a15-4759-b75c-5011f987aeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202616607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2202616607
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.391156099
Short name T85
Test name
Test status
Simulation time 165363813 ps
CPU time 4.49 seconds
Started Jul 21 06:32:49 PM PDT 24
Finished Jul 21 06:32:56 PM PDT 24
Peak memory 233164 kb
Host smart-67670a73-b12d-4826-b7f7-e186c51256fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391156099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.391156099
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1376673274
Short name T218
Test name
Test status
Simulation time 23102168235 ps
CPU time 78.16 seconds
Started Jul 21 06:32:47 PM PDT 24
Finished Jul 21 06:34:07 PM PDT 24
Peak memory 233260 kb
Host smart-18caef39-fb3a-4c88-9425-4e8965172308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376673274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1376673274
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.475588936
Short name T992
Test name
Test status
Simulation time 2104620396 ps
CPU time 7.94 seconds
Started Jul 21 06:32:46 PM PDT 24
Finished Jul 21 06:32:55 PM PDT 24
Peak memory 225032 kb
Host smart-8f298942-d17e-4108-b4b2-3c1241dbdac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475588936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.475588936
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1448511511
Short name T63
Test name
Test status
Simulation time 4896643388 ps
CPU time 13.61 seconds
Started Jul 21 06:32:49 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 233160 kb
Host smart-aef10f19-bd24-4757-b097-8a641b8cc813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448511511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1448511511
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.3020555285
Short name T878
Test name
Test status
Simulation time 814759452 ps
CPU time 4.21 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:02 PM PDT 24
Peak memory 219368 kb
Host smart-f1c62196-a664-4635-88df-6c21c9185e9f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3020555285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.3020555285
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3719479304
Short name T750
Test name
Test status
Simulation time 51333763 ps
CPU time 0.91 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:32:59 PM PDT 24
Peak memory 207164 kb
Host smart-12fd05e2-7f2a-4a3e-8bf5-57f6069cebf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719479304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3719479304
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2579945057
Short name T475
Test name
Test status
Simulation time 14461020 ps
CPU time 0.73 seconds
Started Jul 21 06:32:46 PM PDT 24
Finished Jul 21 06:32:48 PM PDT 24
Peak memory 206160 kb
Host smart-24561f2a-d77c-4057-83fa-984dcf15d3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579945057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2579945057
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.388528193
Short name T820
Test name
Test status
Simulation time 20281221 ps
CPU time 0.71 seconds
Started Jul 21 06:32:46 PM PDT 24
Finished Jul 21 06:32:49 PM PDT 24
Peak memory 206184 kb
Host smart-6691a712-1c9b-4691-b466-425d937426c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388528193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.388528193
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.516610139
Short name T414
Test name
Test status
Simulation time 270172772 ps
CPU time 8.7 seconds
Started Jul 21 06:32:47 PM PDT 24
Finished Jul 21 06:32:57 PM PDT 24
Peak memory 216740 kb
Host smart-9466a991-8780-4098-8942-f9491c038ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516610139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.516610139
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1037032621
Short name T144
Test name
Test status
Simulation time 16464892 ps
CPU time 0.79 seconds
Started Jul 21 06:32:47 PM PDT 24
Finished Jul 21 06:32:50 PM PDT 24
Peak memory 206432 kb
Host smart-e565a33a-1228-4ec3-b902-70f10268276d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037032621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1037032621
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.915458926
Short name T69
Test name
Test status
Simulation time 92569746 ps
CPU time 2.85 seconds
Started Jul 21 06:32:48 PM PDT 24
Finished Jul 21 06:32:53 PM PDT 24
Peak memory 233292 kb
Host smart-b624b2c0-2575-44a2-9e6f-6cd0203df07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915458926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.915458926
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2686389866
Short name T749
Test name
Test status
Simulation time 66543742 ps
CPU time 0.68 seconds
Started Jul 21 06:32:55 PM PDT 24
Finished Jul 21 06:32:56 PM PDT 24
Peak memory 205948 kb
Host smart-c6dbc3a6-94b3-41a0-a75e-e03d943b3b19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686389866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2686389866
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.621255852
Short name T979
Test name
Test status
Simulation time 91610065 ps
CPU time 2.55 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 233140 kb
Host smart-ec416542-c1da-48d4-8a62-75ef340f3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621255852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.621255852
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.901454996
Short name T465
Test name
Test status
Simulation time 16284982 ps
CPU time 0.78 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:32:58 PM PDT 24
Peak memory 207316 kb
Host smart-1c6ff01c-01bb-4335-b4a9-9196fd74aa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901454996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.901454996
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1100026022
Short name T222
Test name
Test status
Simulation time 32753071711 ps
CPU time 171.82 seconds
Started Jul 21 06:32:57 PM PDT 24
Finished Jul 21 06:35:50 PM PDT 24
Peak memory 249588 kb
Host smart-02abf666-fc69-4e7a-80bc-719882cf1d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100026022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1100026022
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1126930637
Short name T50
Test name
Test status
Simulation time 94121416697 ps
CPU time 226.22 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:36:50 PM PDT 24
Peak memory 253740 kb
Host smart-94c4b787-4e3c-4781-bcdd-58d4226d54da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126930637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1126930637
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3499136711
Short name T716
Test name
Test status
Simulation time 3211057299 ps
CPU time 22.07 seconds
Started Jul 21 06:32:59 PM PDT 24
Finished Jul 21 06:33:24 PM PDT 24
Peak memory 236676 kb
Host smart-ff793378-99a5-4f85-a422-574ec12ba6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499136711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3499136711
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2706275783
Short name T346
Test name
Test status
Simulation time 500458689 ps
CPU time 8.94 seconds
Started Jul 21 06:32:55 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 233156 kb
Host smart-f37e46e3-a1f3-47e4-aba3-70cc8cb5e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706275783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2706275783
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.723828180
Short name T306
Test name
Test status
Simulation time 2063339051 ps
CPU time 6.2 seconds
Started Jul 21 06:32:57 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 233120 kb
Host smart-46f0532d-dc0e-412d-8eea-ae7930bde405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723828180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.723828180
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1410254034
Short name T760
Test name
Test status
Simulation time 84588191500 ps
CPU time 77.33 seconds
Started Jul 21 06:32:59 PM PDT 24
Finished Jul 21 06:34:19 PM PDT 24
Peak memory 241376 kb
Host smart-4da1e6f5-7127-4434-b1bf-91e559163098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410254034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1410254034
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.545099401
Short name T311
Test name
Test status
Simulation time 404618703 ps
CPU time 2.97 seconds
Started Jul 21 06:32:55 PM PDT 24
Finished Jul 21 06:32:59 PM PDT 24
Peak memory 224920 kb
Host smart-d2f3d47d-1a0f-4071-b25a-ddbdf8ad1a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545099401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap
.545099401
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3975555191
Short name T380
Test name
Test status
Simulation time 146595273 ps
CPU time 2.54 seconds
Started Jul 21 06:32:59 PM PDT 24
Finished Jul 21 06:33:03 PM PDT 24
Peak memory 224596 kb
Host smart-24382054-367d-4a58-a9f2-15cd25471feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975555191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3975555191
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1316924560
Short name T998
Test name
Test status
Simulation time 387546623 ps
CPU time 6.52 seconds
Started Jul 21 06:32:58 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 222476 kb
Host smart-374b2f44-f200-431b-9eb7-2a047f15829b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1316924560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1316924560
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4258043009
Short name T313
Test name
Test status
Simulation time 122311298315 ps
CPU time 231.6 seconds
Started Jul 21 06:32:58 PM PDT 24
Finished Jul 21 06:36:52 PM PDT 24
Peak memory 252144 kb
Host smart-09574880-a313-4264-8c2e-23840240ee9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258043009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4258043009
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2514339281
Short name T757
Test name
Test status
Simulation time 5220253468 ps
CPU time 14.03 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:12 PM PDT 24
Peak memory 216640 kb
Host smart-5d07ed0e-4a02-425f-b5af-12a68f768bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514339281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2514339281
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.537674863
Short name T612
Test name
Test status
Simulation time 3333766215 ps
CPU time 4.28 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:01 PM PDT 24
Peak memory 216692 kb
Host smart-00b9b9cf-687f-4c5b-a72c-f4fe9691ac3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537674863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.537674863
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.575266341
Short name T873
Test name
Test status
Simulation time 149823736 ps
CPU time 1.14 seconds
Started Jul 21 06:32:57 PM PDT 24
Finished Jul 21 06:33:01 PM PDT 24
Peak memory 216568 kb
Host smart-3b424896-a557-4265-a46a-76a170d4af73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575266341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.575266341
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.2647978087
Short name T972
Test name
Test status
Simulation time 73743280 ps
CPU time 0.76 seconds
Started Jul 21 06:32:57 PM PDT 24
Finished Jul 21 06:33:00 PM PDT 24
Peak memory 206476 kb
Host smart-2de8fb69-e2cc-46fd-8049-fbda2831dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647978087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2647978087
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4122921352
Short name T220
Test name
Test status
Simulation time 418522821 ps
CPU time 3.77 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 233056 kb
Host smart-9489bc0a-7606-4fa6-8474-34f0e35b951c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122921352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4122921352
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3716693918
Short name T373
Test name
Test status
Simulation time 17172631 ps
CPU time 0.72 seconds
Started Jul 21 06:29:43 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 205996 kb
Host smart-9fc2f102-97cd-4300-85a8-a6ef622a22b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716693918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
716693918
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1376098442
Short name T170
Test name
Test status
Simulation time 1117067555 ps
CPU time 7.6 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:29:51 PM PDT 24
Peak memory 233144 kb
Host smart-02a0bbda-aa5d-4dc4-a25b-bf8ed985ff6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376098442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1376098442
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1250218131
Short name T593
Test name
Test status
Simulation time 59367302 ps
CPU time 0.77 seconds
Started Jul 21 06:29:32 PM PDT 24
Finished Jul 21 06:29:34 PM PDT 24
Peak memory 206008 kb
Host smart-7e04017f-25d1-4f36-820e-49dc1f0f2398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250218131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1250218131
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.418383743
Short name T761
Test name
Test status
Simulation time 2526291719 ps
CPU time 53.59 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:30:35 PM PDT 24
Peak memory 253736 kb
Host smart-7d88e7b1-2589-49c6-a92d-ca723cb7ea83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418383743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.418383743
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3732079051
Short name T367
Test name
Test status
Simulation time 98926020591 ps
CPU time 153.33 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 252820 kb
Host smart-3791f0be-3534-422c-9f39-7645a19a6ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732079051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3732079051
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1436449400
Short name T253
Test name
Test status
Simulation time 2073561018 ps
CPU time 23.57 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:30:05 PM PDT 24
Peak memory 249652 kb
Host smart-9339942d-4f1a-47ae-9cfc-c0b1e9cd93ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436449400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1436449400
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.237724854
Short name T709
Test name
Test status
Simulation time 4103579509 ps
CPU time 16.65 seconds
Started Jul 21 06:29:44 PM PDT 24
Finished Jul 21 06:30:02 PM PDT 24
Peak memory 235872 kb
Host smart-28a5cb2b-283a-4ac6-b73f-d59dcb509f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237724854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.237724854
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3194523419
Short name T828
Test name
Test status
Simulation time 6556860484 ps
CPU time 61.81 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:30:50 PM PDT 24
Peak memory 265804 kb
Host smart-8573e834-f141-4e45-b4a5-6e290070e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194523419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3194523419
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2778224423
Short name T664
Test name
Test status
Simulation time 318083843 ps
CPU time 4.73 seconds
Started Jul 21 06:29:43 PM PDT 24
Finished Jul 21 06:29:48 PM PDT 24
Peak memory 233164 kb
Host smart-2302f153-1b91-477a-ad04-5d5074b5d869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778224423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2778224423
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2405735703
Short name T312
Test name
Test status
Simulation time 20205145764 ps
CPU time 32.41 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:30:12 PM PDT 24
Peak memory 240900 kb
Host smart-78d6e35f-b7be-4b90-8528-295808661393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405735703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2405735703
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.966221013
Short name T337
Test name
Test status
Simulation time 24489937060 ps
CPU time 25.63 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:30:09 PM PDT 24
Peak memory 240636 kb
Host smart-3709578b-05b1-40ff-8261-bcae29802e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966221013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
966221013
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.3130967806
Short name T318
Test name
Test status
Simulation time 1871203494 ps
CPU time 5.63 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:48 PM PDT 24
Peak memory 233144 kb
Host smart-0b20d476-22b3-4e10-8cfc-471b92d34840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130967806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.3130967806
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2374511836
Short name T737
Test name
Test status
Simulation time 188974450 ps
CPU time 3.68 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:46 PM PDT 24
Peak memory 223144 kb
Host smart-783b8d59-7afa-4c56-a450-a97d94543968
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2374511836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2374511836
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1486053979
Short name T151
Test name
Test status
Simulation time 146790979 ps
CPU time 1.01 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:29:42 PM PDT 24
Peak memory 207360 kb
Host smart-b027f9af-b0f5-4834-9aab-54d60259d6f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486053979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1486053979
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.189717700
Short name T808
Test name
Test status
Simulation time 4243915022 ps
CPU time 33.13 seconds
Started Jul 21 06:29:44 PM PDT 24
Finished Jul 21 06:30:17 PM PDT 24
Peak memory 221344 kb
Host smart-6b0d6fe8-01f7-42b0-aca9-554c9d1c51ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189717700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.189717700
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2546712895
Short name T516
Test name
Test status
Simulation time 2280946619 ps
CPU time 3.35 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:29:52 PM PDT 24
Peak memory 216724 kb
Host smart-2c261ae3-cca1-46f8-b511-41a7d3332b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546712895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2546712895
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2468491050
Short name T565
Test name
Test status
Simulation time 92763855 ps
CPU time 0.74 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:43 PM PDT 24
Peak memory 206076 kb
Host smart-ab6ea149-a9aa-492d-b8f4-2206d23d8f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468491050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2468491050
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3100608548
Short name T419
Test name
Test status
Simulation time 147003787 ps
CPU time 0.78 seconds
Started Jul 21 06:29:43 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 206456 kb
Host smart-bba42eb4-942f-4c41-aaef-6f355a823853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100608548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3100608548
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.284052666
Short name T3
Test name
Test status
Simulation time 667620510 ps
CPU time 2.66 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:45 PM PDT 24
Peak memory 224964 kb
Host smart-009d0b2c-2340-4d31-9c96-2dc1ba0e8347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284052666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.284052666
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.538814730
Short name T560
Test name
Test status
Simulation time 46748081 ps
CPU time 0.71 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 205848 kb
Host smart-48c77cfb-4303-4513-8bb0-09d59726230f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538814730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.538814730
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3408472384
Short name T686
Test name
Test status
Simulation time 454650573 ps
CPU time 3.42 seconds
Started Jul 21 06:29:45 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 233148 kb
Host smart-9159ca1d-b1ca-418a-9b5f-e2e768b1b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408472384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3408472384
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1452204135
Short name T508
Test name
Test status
Simulation time 25970967 ps
CPU time 0.78 seconds
Started Jul 21 06:29:41 PM PDT 24
Finished Jul 21 06:29:43 PM PDT 24
Peak memory 207048 kb
Host smart-26c4a428-08cc-4cc2-aaab-de40f9589c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452204135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1452204135
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.580274046
Short name T211
Test name
Test status
Simulation time 58549727608 ps
CPU time 404.09 seconds
Started Jul 21 06:29:48 PM PDT 24
Finished Jul 21 06:36:33 PM PDT 24
Peak memory 264272 kb
Host smart-8cbf82b8-4f29-4f77-90f5-cbb1b855c8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580274046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.580274046
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.635014780
Short name T215
Test name
Test status
Simulation time 18858432468 ps
CPU time 85.19 seconds
Started Jul 21 06:29:45 PM PDT 24
Finished Jul 21 06:31:11 PM PDT 24
Peak memory 265764 kb
Host smart-b73683f5-9c9b-4120-a269-0981fa2ab356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635014780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.635014780
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3016846496
Short name T978
Test name
Test status
Simulation time 27389914008 ps
CPU time 120.08 seconds
Started Jul 21 06:29:49 PM PDT 24
Finished Jul 21 06:31:50 PM PDT 24
Peak memory 264512 kb
Host smart-b1ab51ce-783b-4062-b8b2-59ef1d76d306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016846496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3016846496
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1456141257
Short name T872
Test name
Test status
Simulation time 704677503 ps
CPU time 6.75 seconds
Started Jul 21 06:29:49 PM PDT 24
Finished Jul 21 06:29:56 PM PDT 24
Peak memory 233112 kb
Host smart-21f71718-5a14-4a0a-b6d1-5d6c5624f88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456141257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1456141257
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2426474859
Short name T335
Test name
Test status
Simulation time 9440937693 ps
CPU time 95.01 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:31:23 PM PDT 24
Peak memory 264712 kb
Host smart-3ded46e7-1c48-4264-afd5-c98ee048e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426474859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2426474859
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2327929778
Short name T455
Test name
Test status
Simulation time 1239488103 ps
CPU time 7.85 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 233104 kb
Host smart-c2eb9dfa-b343-4cab-ae2d-f42067e766f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327929778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2327929778
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3753516561
Short name T202
Test name
Test status
Simulation time 2093102597 ps
CPU time 15.42 seconds
Started Jul 21 06:29:44 PM PDT 24
Finished Jul 21 06:30:00 PM PDT 24
Peak memory 233148 kb
Host smart-8a4dff42-285e-46b8-8dbf-d0a746d4ec8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753516561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3753516561
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.268830190
Short name T261
Test name
Test status
Simulation time 178691205 ps
CPU time 2.85 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:29:46 PM PDT 24
Peak memory 224924 kb
Host smart-ab537fcb-00e3-4b97-b7a8-e089b20d2ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268830190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
268830190
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3451633617
Short name T239
Test name
Test status
Simulation time 7203936913 ps
CPU time 7.15 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:29:50 PM PDT 24
Peak memory 233092 kb
Host smart-1611226e-5f7e-4776-a267-51b1d173e11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451633617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3451633617
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.217907962
Short name T775
Test name
Test status
Simulation time 3207319829 ps
CPU time 18.27 seconds
Started Jul 21 06:29:48 PM PDT 24
Finished Jul 21 06:30:07 PM PDT 24
Peak memory 219932 kb
Host smart-d855af5d-1fde-4762-b044-ec97481b7188
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=217907962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.217907962
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.548892751
Short name T913
Test name
Test status
Simulation time 68914573 ps
CPU time 1.14 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:29:51 PM PDT 24
Peak memory 207336 kb
Host smart-9cd2a7f8-3fcf-4811-8f68-d085ee2221b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548892751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.548892751
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1192677430
Short name T364
Test name
Test status
Simulation time 2347214376 ps
CPU time 4.32 seconds
Started Jul 21 06:29:44 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 216684 kb
Host smart-77d0a5bc-b50b-4c0f-92a3-77acc7b1c7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192677430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1192677430
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2862890127
Short name T968
Test name
Test status
Simulation time 3297624489 ps
CPU time 8.23 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 216696 kb
Host smart-54100072-977a-4426-a6e8-9bc4d321bf57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862890127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2862890127
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3380274438
Short name T448
Test name
Test status
Simulation time 463620292 ps
CPU time 1.97 seconds
Started Jul 21 06:29:40 PM PDT 24
Finished Jul 21 06:29:43 PM PDT 24
Peak memory 216696 kb
Host smart-6a66d25e-8830-4585-a2be-89bf052c10b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380274438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3380274438
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2692554926
Short name T932
Test name
Test status
Simulation time 46957483 ps
CPU time 0.87 seconds
Started Jul 21 06:29:42 PM PDT 24
Finished Jul 21 06:29:44 PM PDT 24
Peak memory 206480 kb
Host smart-28b3c06b-f150-495d-a55f-cf4fbec96779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692554926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2692554926
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3384835679
Short name T853
Test name
Test status
Simulation time 24946821169 ps
CPU time 37.88 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:30:26 PM PDT 24
Peak memory 234412 kb
Host smart-fdd3f662-66ea-47d0-b2ee-f3f14a937e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384835679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3384835679
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3259447030
Short name T83
Test name
Test status
Simulation time 41003595 ps
CPU time 0.72 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:29:53 PM PDT 24
Peak memory 205920 kb
Host smart-761c5e0a-b349-4c50-9666-919a70a30580
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259447030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
259447030
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.707970724
Short name T965
Test name
Test status
Simulation time 666171600 ps
CPU time 7.81 seconds
Started Jul 21 06:29:46 PM PDT 24
Finished Jul 21 06:29:54 PM PDT 24
Peak memory 233116 kb
Host smart-16b258a6-a83f-4fc0-b76f-365ba4b50816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707970724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.707970724
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3619393854
Short name T731
Test name
Test status
Simulation time 42707837 ps
CPU time 0.77 seconds
Started Jul 21 06:29:46 PM PDT 24
Finished Jul 21 06:29:49 PM PDT 24
Peak memory 207452 kb
Host smart-24df2958-0d88-4aef-91d5-834540791d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619393854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3619393854
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3763054576
Short name T672
Test name
Test status
Simulation time 8782704507 ps
CPU time 58.75 seconds
Started Jul 21 06:29:46 PM PDT 24
Finished Jul 21 06:30:45 PM PDT 24
Peak memory 252900 kb
Host smart-bf81e8fa-3f84-4b5c-ac2e-5a1fe6ff7f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763054576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3763054576
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.530574099
Short name T996
Test name
Test status
Simulation time 2546285251 ps
CPU time 30.74 seconds
Started Jul 21 06:29:48 PM PDT 24
Finished Jul 21 06:30:20 PM PDT 24
Peak memory 251624 kb
Host smart-f1c870ac-fc3e-4d46-aa85-bf86cf8c7fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530574099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.530574099
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3371213781
Short name T438
Test name
Test status
Simulation time 25860954638 ps
CPU time 88.67 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:31:17 PM PDT 24
Peak memory 250628 kb
Host smart-1a0e636b-7e98-4cf7-9175-c7c382c17a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371213781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3371213781
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.561007845
Short name T630
Test name
Test status
Simulation time 94061380 ps
CPU time 3.22 seconds
Started Jul 21 06:29:46 PM PDT 24
Finished Jul 21 06:29:50 PM PDT 24
Peak memory 233172 kb
Host smart-95613215-86f2-43f0-addb-14f342af25c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561007845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.561007845
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3500866344
Short name T378
Test name
Test status
Simulation time 5202203548 ps
CPU time 42.9 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:30:33 PM PDT 24
Peak memory 239928 kb
Host smart-ef31661a-3643-41ae-81a6-d3d783f5e3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500866344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3500866344
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4217617584
Short name T266
Test name
Test status
Simulation time 479003144 ps
CPU time 4.26 seconds
Started Jul 21 06:29:45 PM PDT 24
Finished Jul 21 06:29:50 PM PDT 24
Peak memory 224808 kb
Host smart-25716796-603a-4a91-b229-fe082d5764d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217617584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4217617584
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1672700756
Short name T924
Test name
Test status
Simulation time 1675228829 ps
CPU time 28.21 seconds
Started Jul 21 06:29:48 PM PDT 24
Finished Jul 21 06:30:17 PM PDT 24
Peak memory 233424 kb
Host smart-d5a1ad6c-810a-4d36-90b4-d7cd940a6d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672700756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1672700756
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4277858859
Short name T425
Test name
Test status
Simulation time 122124958 ps
CPU time 2.56 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:29:51 PM PDT 24
Peak memory 232740 kb
Host smart-d0581c84-4469-4912-a7eb-00ff92161029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277858859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4277858859
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1354744707
Short name T917
Test name
Test status
Simulation time 15722389579 ps
CPU time 25.57 seconds
Started Jul 21 06:29:46 PM PDT 24
Finished Jul 21 06:30:12 PM PDT 24
Peak memory 237888 kb
Host smart-702b0bac-8ed9-4dec-a02b-72884bd876b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354744707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1354744707
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2274330939
Short name T900
Test name
Test status
Simulation time 135604385 ps
CPU time 3.79 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:29:54 PM PDT 24
Peak memory 223464 kb
Host smart-b0aef04b-9ba6-42e0-8097-8bc9cfe31b1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2274330939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2274330939
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.50545861
Short name T292
Test name
Test status
Simulation time 13605707905 ps
CPU time 161.53 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:32:30 PM PDT 24
Peak memory 251712 kb
Host smart-5125c8e5-9933-4a8e-9c7f-7d467849dd06
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50545861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_
all.50545861
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.963022529
Short name T660
Test name
Test status
Simulation time 2926239508 ps
CPU time 25.99 seconds
Started Jul 21 06:29:45 PM PDT 24
Finished Jul 21 06:30:12 PM PDT 24
Peak memory 216912 kb
Host smart-539e2db6-3f23-4b57-ad8e-dd954c8582f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963022529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.963022529
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.208857654
Short name T385
Test name
Test status
Simulation time 3202004402 ps
CPU time 13.79 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:30:02 PM PDT 24
Peak memory 216632 kb
Host smart-32293213-e0ea-4d8c-b481-5aef1eb46b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208857654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.208857654
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.571258395
Short name T910
Test name
Test status
Simulation time 44157696 ps
CPU time 1.69 seconds
Started Jul 21 06:29:45 PM PDT 24
Finished Jul 21 06:29:47 PM PDT 24
Peak memory 216720 kb
Host smart-426b86eb-c8c3-452c-a323-555d2d1574dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571258395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.571258395
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.4141626018
Short name T383
Test name
Test status
Simulation time 68933921 ps
CPU time 0.81 seconds
Started Jul 21 06:29:48 PM PDT 24
Finished Jul 21 06:29:50 PM PDT 24
Peak memory 206432 kb
Host smart-d2cf4d61-e1b6-49ed-af32-55659d4721d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141626018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.4141626018
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3479186373
Short name T40
Test name
Test status
Simulation time 7826227264 ps
CPU time 27.61 seconds
Started Jul 21 06:29:47 PM PDT 24
Finished Jul 21 06:30:16 PM PDT 24
Peak memory 240732 kb
Host smart-c02f4eed-5469-4645-ac6f-e4948672d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479186373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3479186373
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.812323467
Short name T866
Test name
Test status
Simulation time 33354979 ps
CPU time 0.7 seconds
Started Jul 21 06:29:52 PM PDT 24
Finished Jul 21 06:29:53 PM PDT 24
Peak memory 205952 kb
Host smart-b6bcb2c7-bb41-47d4-b97c-e244aaafedd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812323467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.812323467
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.213140771
Short name T483
Test name
Test status
Simulation time 1643169621 ps
CPU time 6.33 seconds
Started Jul 21 06:29:52 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 233164 kb
Host smart-518eea0a-c9fa-4fc4-8622-ea444e482cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213140771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.213140771
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.657870463
Short name T994
Test name
Test status
Simulation time 35996462 ps
CPU time 0.82 seconds
Started Jul 21 06:29:56 PM PDT 24
Finished Jul 21 06:29:57 PM PDT 24
Peak memory 207080 kb
Host smart-84e2d2f6-a5cd-4556-b861-c9286238d22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657870463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.657870463
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.242979750
Short name T727
Test name
Test status
Simulation time 5038955697 ps
CPU time 48.07 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:30:40 PM PDT 24
Peak memory 255356 kb
Host smart-ce3752ae-8719-4a2f-a5fc-3087da4cb74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242979750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.242979750
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.174684838
Short name T208
Test name
Test status
Simulation time 16515917483 ps
CPU time 83.6 seconds
Started Jul 21 06:29:53 PM PDT 24
Finished Jul 21 06:31:17 PM PDT 24
Peak memory 251220 kb
Host smart-bbd53c0d-999f-408f-9ce8-68e0f4516968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174684838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.174684838
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.293147455
Short name T977
Test name
Test status
Simulation time 120782565 ps
CPU time 3.41 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:29:54 PM PDT 24
Peak memory 224912 kb
Host smart-356f6f44-0f72-42b1-9da2-53613dc619d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293147455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.293147455
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1674884120
Short name T275
Test name
Test status
Simulation time 1659018829 ps
CPU time 18.02 seconds
Started Jul 21 06:29:52 PM PDT 24
Finished Jul 21 06:30:10 PM PDT 24
Peak memory 224944 kb
Host smart-15756459-1a2f-4921-b225-186857755778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674884120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1674884120
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.172151822
Short name T529
Test name
Test status
Simulation time 221613316 ps
CPU time 2.51 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:29:53 PM PDT 24
Peak memory 224856 kb
Host smart-430592a3-59a1-4a54-989b-efb2de1d674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172151822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.172151822
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3223201226
Short name T384
Test name
Test status
Simulation time 154370795 ps
CPU time 3.07 seconds
Started Jul 21 06:29:53 PM PDT 24
Finished Jul 21 06:29:56 PM PDT 24
Peak memory 233152 kb
Host smart-cbe6f0e7-c121-4a3f-acda-081172286609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223201226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3223201226
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3559793007
Short name T102
Test name
Test status
Simulation time 274557664 ps
CPU time 2.96 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:29:54 PM PDT 24
Peak memory 225068 kb
Host smart-8cd64d6a-13de-411c-afe1-5e39d169ecaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559793007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3559793007
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.439920451
Short name T927
Test name
Test status
Simulation time 151047004 ps
CPU time 4.03 seconds
Started Jul 21 06:29:50 PM PDT 24
Finished Jul 21 06:29:54 PM PDT 24
Peak memory 219692 kb
Host smart-c786077a-711e-4b1f-ae0c-e5f98fe18321
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=439920451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.439920451
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2912141397
Short name T768
Test name
Test status
Simulation time 3754750405 ps
CPU time 14.19 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:30:05 PM PDT 24
Peak memory 216712 kb
Host smart-2d0d8a4f-d732-4e9e-860e-81d511a976b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912141397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2912141397
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.341163385
Short name T718
Test name
Test status
Simulation time 2344994662 ps
CPU time 7.55 seconds
Started Jul 21 06:29:52 PM PDT 24
Finished Jul 21 06:30:00 PM PDT 24
Peak memory 216684 kb
Host smart-9eb5d918-f03e-460f-93a2-548cc0c64aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341163385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.341163385
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.551562394
Short name T437
Test name
Test status
Simulation time 52226672 ps
CPU time 0.88 seconds
Started Jul 21 06:29:51 PM PDT 24
Finished Jul 21 06:29:52 PM PDT 24
Peak memory 208316 kb
Host smart-17161ef2-e2b6-4555-80b4-ba6eab24a30f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551562394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.551562394
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.937080246
Short name T895
Test name
Test status
Simulation time 13898278 ps
CPU time 0.79 seconds
Started Jul 21 06:29:56 PM PDT 24
Finished Jul 21 06:29:58 PM PDT 24
Peak memory 206104 kb
Host smart-4450d26c-0e0d-46c3-8544-3d39cf8e9fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937080246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.937080246
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.3314315217
Short name T284
Test name
Test status
Simulation time 2368645691 ps
CPU time 15.87 seconds
Started Jul 21 06:29:52 PM PDT 24
Finished Jul 21 06:30:08 PM PDT 24
Peak memory 233152 kb
Host smart-fdfa3f4e-8057-4869-b2ef-34ca4b0f6575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314315217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.3314315217
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1954695776
Short name T525
Test name
Test status
Simulation time 14022351 ps
CPU time 0.8 seconds
Started Jul 21 06:29:59 PM PDT 24
Finished Jul 21 06:30:00 PM PDT 24
Peak memory 206212 kb
Host smart-ab4f002d-856a-41f9-a38e-10476a94b53c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954695776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
954695776
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.994534003
Short name T638
Test name
Test status
Simulation time 847748693 ps
CPU time 6.58 seconds
Started Jul 21 06:29:56 PM PDT 24
Finished Jul 21 06:30:03 PM PDT 24
Peak memory 233164 kb
Host smart-128fef1f-b654-4277-ac0f-fa76eb30e69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994534003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.994534003
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3667900243
Short name T386
Test name
Test status
Simulation time 53511110 ps
CPU time 0.78 seconds
Started Jul 21 06:29:59 PM PDT 24
Finished Jul 21 06:30:00 PM PDT 24
Peak memory 205988 kb
Host smart-803a5f07-ccf4-46f5-ad56-22e9c89733f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667900243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3667900243
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3384621043
Short name T930
Test name
Test status
Simulation time 732960649 ps
CPU time 4.3 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:30:03 PM PDT 24
Peak memory 224916 kb
Host smart-5ff6a5c9-6305-4f34-b4be-21b2d65d6246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384621043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3384621043
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2700998847
Short name T155
Test name
Test status
Simulation time 82377422570 ps
CPU time 243.9 seconds
Started Jul 21 06:30:03 PM PDT 24
Finished Jul 21 06:34:07 PM PDT 24
Peak memory 257840 kb
Host smart-bab4881a-8751-494f-8dc8-8109ed258b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700998847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2700998847
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3113184268
Short name T474
Test name
Test status
Simulation time 21555684379 ps
CPU time 42.45 seconds
Started Jul 21 06:29:59 PM PDT 24
Finished Jul 21 06:30:42 PM PDT 24
Peak memory 239520 kb
Host smart-2864cb9f-c796-49ca-85b2-0a4af1b2c174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113184268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3113184268
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2666005073
Short name T166
Test name
Test status
Simulation time 979658603 ps
CPU time 12.43 seconds
Started Jul 21 06:30:00 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 233140 kb
Host smart-02303059-6187-4389-93ad-71e8ec04ef94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666005073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2666005073
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1335962987
Short name T941
Test name
Test status
Simulation time 75098697553 ps
CPU time 124.76 seconds
Started Jul 21 06:29:59 PM PDT 24
Finished Jul 21 06:32:04 PM PDT 24
Peak memory 238084 kb
Host smart-770513e2-8746-45b3-a627-8f0cfd43aa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335962987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1335962987
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2939974835
Short name T104
Test name
Test status
Simulation time 346329427 ps
CPU time 6.64 seconds
Started Jul 21 06:30:02 PM PDT 24
Finished Jul 21 06:30:09 PM PDT 24
Peak memory 233096 kb
Host smart-73f86e2d-1b03-4ea3-8fbc-c581e47b34e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939974835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2939974835
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1968117096
Short name T745
Test name
Test status
Simulation time 3779690746 ps
CPU time 35.75 seconds
Started Jul 21 06:30:00 PM PDT 24
Finished Jul 21 06:30:36 PM PDT 24
Peak memory 241296 kb
Host smart-08389eb3-f8a3-4bed-9a11-358538abb1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968117096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1968117096
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.330279359
Short name T955
Test name
Test status
Simulation time 801210125 ps
CPU time 4.22 seconds
Started Jul 21 06:29:56 PM PDT 24
Finished Jul 21 06:30:01 PM PDT 24
Peak memory 224932 kb
Host smart-b339986d-e4b6-43f8-944a-e0c7b801f426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330279359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
330279359
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2716497178
Short name T818
Test name
Test status
Simulation time 11177221327 ps
CPU time 31.95 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:30:30 PM PDT 24
Peak memory 249200 kb
Host smart-8de69ba1-5c0d-46f6-90d1-0d2b530dde99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716497178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2716497178
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3554309964
Short name T405
Test name
Test status
Simulation time 325778834 ps
CPU time 4.15 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:30:02 PM PDT 24
Peak memory 219220 kb
Host smart-4ee3a5d9-e1fb-4525-926a-f56b2fc0e2fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3554309964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3554309964
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1894272733
Short name T532
Test name
Test status
Simulation time 73116242348 ps
CPU time 322.18 seconds
Started Jul 21 06:29:59 PM PDT 24
Finished Jul 21 06:35:22 PM PDT 24
Peak memory 256840 kb
Host smart-017856b1-1fbd-48f6-9a5e-18d21e3b66e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894272733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1894272733
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.480385625
Short name T357
Test name
Test status
Simulation time 8910762614 ps
CPU time 11.1 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:30:09 PM PDT 24
Peak memory 216740 kb
Host smart-db782c9a-86b7-417d-b67c-1d131d63ef95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480385625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.480385625
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2190129235
Short name T431
Test name
Test status
Simulation time 2469140520 ps
CPU time 9.25 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:30:06 PM PDT 24
Peak memory 216696 kb
Host smart-84667501-d77f-4a6f-8376-8102e6bb924a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190129235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2190129235
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2337489317
Short name T374
Test name
Test status
Simulation time 42196553 ps
CPU time 1.01 seconds
Started Jul 21 06:29:57 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 208360 kb
Host smart-d90fcee5-f278-4a0f-a050-c95ecbbf38b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337489317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2337489317
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1095308008
Short name T846
Test name
Test status
Simulation time 84142154 ps
CPU time 0.85 seconds
Started Jul 21 06:29:58 PM PDT 24
Finished Jul 21 06:29:59 PM PDT 24
Peak memory 206424 kb
Host smart-f5c36009-ad7f-4ae2-80f8-ecab241dabc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095308008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1095308008
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3522259701
Short name T314
Test name
Test status
Simulation time 2979659862 ps
CPU time 13.75 seconds
Started Jul 21 06:29:59 PM PDT 24
Finished Jul 21 06:30:13 PM PDT 24
Peak memory 224900 kb
Host smart-b1025b57-9db8-412c-8800-4f0857820bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522259701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3522259701
Directory /workspace/9.spi_device_upload/latest
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