Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2296008	1			T1	1		T3	1		T4	1
all_values[1]	2296008	1			T1	1		T3	1		T4	1
all_values[2]	2296008	1			T1	1		T3	1		T4	1
all_values[3]	2296008	1			T1	1		T3	1		T4	1
all_values[4]	2296008	1			T1	1		T3	1		T4	1
all_values[5]	2296008	1			T1	1		T3	1		T4	1
all_values[6]	2296008	1			T1	1		T3	1		T4	1
all_values[7]	2296008	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17808371

1

T1

8

T3

8

T4

8

auto[1]

559693

1

T14

70

T16

10471

T17

43

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18342552

1

T1

8

T3

8

T4

8

auto[1]

25512

1

T12

320

T31

76

T32

79

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2223293	1			T1	1		T3	1		T4	1
all_values[0]	auto[0]	auto[1]	11716	1			T12	170		T31	61		T32	41
all_values[0]	auto[1]	auto[0]	60396	1			T14	2		T16	1733		T17	3
all_values[0]	auto[1]	auto[1]	603	1			T14	4		T16	6		T17	1
all_values[1]	auto[0]	auto[0]	2272452	1			T1	1		T3	1		T4	1
all_values[1]	auto[0]	auto[1]	7718	1			T12	134		T31	13		T32	38
all_values[1]	auto[1]	auto[0]	15625	1			T14	7		T16	1732		T17	2
all_values[1]	auto[1]	auto[1]	213	1			T14	3		T16	10		T17	5
all_values[2]	auto[0]	auto[0]	2201949	1			T1	1		T3	1		T4	1
all_values[2]	auto[0]	auto[1]	2947	1			T12	16		T31	2		T14	6
all_values[2]	auto[1]	auto[0]	90757	1			T14	6		T16	1730		T17	1
all_values[2]	auto[1]	auto[1]	355	1			T14	3		T16	6		T17	3
all_values[3]	auto[0]	auto[0]	2200014	1			T1	1		T3	1		T4	1
all_values[3]	auto[0]	auto[1]	221	1			T14	3		T16	9		T17	2
all_values[3]	auto[1]	auto[0]	95551	1			T14	4		T16	1730		T17	4
all_values[3]	auto[1]	auto[1]	222	1			T14	6		T16	10		T17	1
all_values[4]	auto[0]	auto[0]	2265835	1			T1	1		T3	1		T4	1
all_values[4]	auto[0]	auto[1]	192	1			T14	2		T16	9		T17	2
all_values[4]	auto[1]	auto[0]	29784	1			T14	12		T16	1731		T17	3
all_values[4]	auto[1]	auto[1]	197	1			T14	2		T16	4		T17	1
all_values[5]	auto[0]	auto[0]	2140804	1			T1	1		T3	1		T4	1
all_values[5]	auto[0]	auto[1]	183	1			T14	6		T16	4		T17	4
all_values[5]	auto[1]	auto[0]	154861	1			T14	2		T16	1733		T17	4
all_values[5]	auto[1]	auto[1]	160	1			T14	1		T16	6		T17	1
all_values[6]	auto[0]	auto[0]	2250120	1			T1	1		T3	1		T4	1
all_values[6]	auto[0]	auto[1]	190	1			T14	1		T16	11		T17	2
all_values[6]	auto[1]	auto[0]	45496	1			T14	7		T16	4		T17	3
all_values[6]	auto[1]	auto[1]	202	1			T14	3		T16	12		T17	5
all_values[7]	auto[0]	auto[0]	2230543	1			T1	1		T3	1		T4	1
all_values[7]	auto[0]	auto[1]	194	1			T14	1		T16	6		T17	4
all_values[7]	auto[1]	auto[0]	65072	1			T14	6		T16	17		T17	4
all_values[7]	auto[1]	auto[1]	199	1			T14	2		T16	7		T17	2