Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34395	1			T5	151		T6	2		T10	125
auto[SpiFlashAddrCfg]	7584	1			T1	8		T3	4		T5	20
auto[SpiFlashAddr3b]	8752	1			T1	4		T5	27		T6	2
auto[SpiFlashAddr4b]	7598	1			T1	4		T5	28		T6	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33513

1

T1

16

T3

4

T5

127

auto[1]

24816

1

T5

99

T6

14

T10

85

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31138

1

T1

4

T5

93

T6

10

auto[1]

27191

1

T1

12

T3

4

T5

133

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	38971	1			T1	8		T5	180		T6	10
values[1]	1042	1			T5	4		T10	1		T11	1
values[2]	1471	1			T5	5		T10	1		T11	9
values[3]	1458	1			T5	2		T10	2		T11	8
values[4]	1477	1			T6	2		T10	7		T11	11
values[5]	1413	1			T5	4		T6	2		T10	8
values[6]	1422	1			T3	2		T5	3		T10	2
values[7]	1442	1			T5	1		T10	8		T11	10
values[8]	9633	1			T1	8		T3	2		T5	27

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28663

1

T1

16

T3

4

T6

14

auto[1]

29666

1

T5

226

T10

188

T31

215

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55190

1

T1

16

T3

4

T5

205

write

3139

1

T5

21

T6

2

T10

8

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18767

1

T1

4

T3

2

T5

58

valids[0x1]

39562

1

T1

12

T3

2

T5

168

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1553	1			T5	5		T6	2		T10	8
internal_process_ops[0x5a]	1559	1			T5	3		T10	6		T11	6
internal_process_ops[0x05]	20880	1			T5	99		T10	72		T11	203
internal_process_ops[0x35]	1506	1			T5	2		T10	7		T11	10
internal_process_ops[0x15]	1524	1			T5	4		T10	5		T11	10
internal_process_ops[0x03]	1039	1			T1	8		T5	5		T11	7
internal_process_ops[0x0b]	1040	1			T1	4		T3	2		T5	1
internal_process_ops[0x3b]	1007	1			T5	1		T10	3		T11	6
internal_process_ops[0x6b]	1018	1			T1	4		T6	2		T10	1
internal_process_ops[0xbb]	1022	1			T3	2		T5	3		T10	2
internal_process_ops[0xeb]	1018	1			T10	1		T11	3		T12	13

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56809

1

T1

16

T3

4

T5

209

auto[1]

1520

1

T5

17

T6

2

T10

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56049

1

T1

16

T3

4

T5

211

auto[1]

2280

1

T5

15

T10

9

T11

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9810

1

T11

181

T12

94

T41

68

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5573

1

T6

2

T11

93

T12

64

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1972

1

T1

8

T3

4

T11

27

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1797

1

T6

6

T11

18

T12

29

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2305

1

T1

4

T11

35

T12

33

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1997

1

T6

2

T11

25

T12

28

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2003

1

T1

4

T11

11

T12

30

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1752

1

T6

2

T11

12

T12

23

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

146

1

T11

1

T12

3

T41

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

65

1

T12

1

T41

1

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T12

2

T41

2

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

99

1

T12

3

T41

3

T14

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

97

1

T11

1

T42

1

T14

5

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T11

2

T14

1

T100

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

82

1

T14

2

T24

2

T100

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

72

1

T6

2

T12

5

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T11

2

T41

1

T14

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

102

1

T11

1

T41

1

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

62

1

T11

1

T12

2

T41

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

110

1

T11

2

T24

3

T30

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

103

1

T11

2

T41

3

T24

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

79

1

T11

1

T14

2

T24

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

66

1

T41

1

T14

2

T24

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

97

1

T11

1

T12

1

T13

4

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10859

1

T5

86

T10

64

T31

69

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7319

1

T5

58

T10

61

T31

25

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1590

1

T5

7

T10

15

T31

15

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1495

1

T5

8

T10

6

T31

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1882

1

T5

11

T10

12

T31

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1788

1

T5

12

T10

6

T31

11

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1488

1

T5

12

T10

11

T31

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1560

1

T5

11

T10

5

T31

20

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

110

1

T5

1

T31

2

T15

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

105

1

T5

2

T31

1

T90

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

112

1

T31

3

T43

1

T84

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

106

1

T5

4

T31

2

T32

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

85

1

T5

2

T31

4

T32

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

96

1

T31

1

T15

1

T83

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

99

1

T10

3

T32

1

T90

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

129

1

T5

3

T43

2

T161

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

127

1

T83

2

T43

2

T162

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

87

1

T5

3

T15

1

T83

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

102

1

T5

1

T31

2

T32

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

77

1

T32

1

T15

2

T83

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T10

1

T31

3

T32

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

105

1

T5

3

T43

3

T84

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T10

2

T160

1

T163

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

121

1

T5

2

T10

2

T31

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3591	1			T11	39		T12	47		T13	2
auto[0]	values[0]	valids[0x1]	14536	1			T1	8		T6	10		T11	263
auto[0]	values[1]	valids[0x1]	512	1			T11	1		T12	14		T41	6
auto[0]	values[2]	valids[0x0]	514	1			T11	5		T12	11		T13	2
auto[0]	values[2]	valids[0x1]	276	1			T11	4		T12	2		T41	4
auto[0]	values[3]	valids[0x0]	559	1			T11	4		T12	8		T41	3
auto[0]	values[3]	valids[0x1]	284	1			T11	4		T12	3		T41	1
auto[0]	values[4]	valids[0x0]	451	1			T6	2		T11	5		T12	9
auto[0]	values[4]	valids[0x1]	304	1			T11	6		T12	8		T41	2
auto[0]	values[5]	valids[0x0]	503	1			T6	2		T11	4		T12	11
auto[0]	values[5]	valids[0x1]	236	1			T11	4		T12	5		T41	1
auto[0]	values[6]	valids[0x0]	491	1			T11	6		T12	3		T41	5
auto[0]	values[6]	valids[0x1]	311	1			T3	2		T11	3		T12	5
auto[0]	values[7]	valids[0x0]	543	1			T11	7		T12	3		T41	7
auto[0]	values[7]	valids[0x1]	284	1			T11	3		T12	5		T13	2
auto[0]	values[8]	valids[0x0]	3296	1			T1	4		T3	2		T11	31
auto[0]	values[8]	valids[0x1]	1972	1			T1	4		T11	27		T12	25
auto[1]	values[0]	valids[0x0]	3926	1			T5	36		T10	36		T31	34
auto[1]	values[0]	valids[0x1]	16918	1			T5	144		T10	105		T31	102
auto[1]	values[1]	valids[0x1]	530	1			T5	4		T10	1		T31	2
auto[1]	values[2]	valids[0x0]	423	1			T5	1		T10	1		T31	1
auto[1]	values[2]	valids[0x1]	258	1			T5	4		T31	1		T32	1
auto[1]	values[3]	valids[0x0]	357	1			T10	2		T31	6		T32	1
auto[1]	values[3]	valids[0x1]	258	1			T5	2		T31	2		T90	1
auto[1]	values[4]	valids[0x0]	438	1			T10	3		T31	4		T90	3
auto[1]	values[4]	valids[0x1]	284	1			T10	4		T31	2		T15	1
auto[1]	values[5]	valids[0x0]	393	1			T5	3		T10	1		T31	2
auto[1]	values[5]	valids[0x1]	281	1			T5	1		T10	7		T31	2
auto[1]	values[6]	valids[0x0]	354	1			T10	1		T31	4		T32	3
auto[1]	values[6]	valids[0x1]	266	1			T5	3		T10	1		T31	2
auto[1]	values[7]	valids[0x0]	351	1			T5	1		T10	6		T31	1
auto[1]	values[7]	valids[0x1]	264	1			T10	2		T31	5		T15	2
auto[1]	values[8]	valids[0x0]	2577	1			T5	17		T10	10		T31	31
auto[1]	values[8]	valids[0x1]	1788	1			T5	10		T10	8		T31	14