Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3351496

1

T1

92335

T3

32

T5

7498

auto[1]

34300

1

T5

86

T10

68

T11

196

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058755

1

T1

92335

T3

32

T5

59

auto[1]

2327041

1

T5

7525

T10

3247

T11

15719

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	652023	1			T1	23138		T3	1		T5	1000
auto[524288:1048575]	369716	1			T1	585		T5	959		T10	1871
auto[1048576:1572863]	405332	1			T1	11139		T3	2		T5	1879
auto[1572864:2097151]	375383	1			T1	2636		T3	29		T5	130
auto[2097152:2621439]	399301	1			T1	1111		T5	3026		T10	1
auto[2621440:3145727]	420248	1			T1	18852		T5	2		T10	14
auto[3145728:3670015]	368766	1			T1	32256		T5	263		T10	10
auto[3670016:4194303]	395027	1			T1	2618		T5	325		T10	17

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2363343

1

T1

98

T3

8

T5

7568

auto[1]

1022453

1

T1

92237

T3

24

T5

16

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2989059

1

T1

92335

T3

32

T5

5771

auto[1]

396737

1

T5

1813

T10

267

T11

11593

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	219899	1			T1	23138		T3	1		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	380102	1			T10	375		T12	137		T41	590
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	111087	1			T1	585		T5	2		T10	11
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	206773	1			T5	433		T10	1847		T11	1155
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	135169	1			T1	11139		T3	2		T5	3
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	209146	1			T5	1615		T10	257		T11	1
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	67737	1			T1	2636		T3	29		T5	2
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	247983	1			T5	128		T10	447		T11	1712
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	136671	1			T1	1111		T5	13		T10	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	193482	1			T5	2992		T12	135		T14	448
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	130657	1			T1	18852		T5	2		T10	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	245967	1			T10	1		T11	1		T12	1
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	105734	1			T1	32256		T5	1		T10	2
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	222650	1			T5	257		T10	3		T11	646
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	141429	1			T1	2618		T5	4		T10	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	205432	1			T5	258		T10	1		T11	512
auto[0]	auto[1]	auto[0:524287]	auto[0]	1073	1			T5	1		T10	3		T41	21
auto[0]	auto[1]	auto[0:524287]	auto[1]	45410	1			T5	995		T10	256		T11	151
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	612	1			T5	4		T41	21		T31	5
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46936	1			T5	513		T41	42		T31	769
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	457	1			T5	3		T11	6		T12	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	56909	1			T5	258		T11	2458		T24	2535
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	595	1			T10	1		T11	1		T31	7
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	54090	1			T31	3379		T30	256		T90	128
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	653	1			T11	1		T41	21		T24	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	64388	1			T11	256		T41	3		T32	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	495	1			T10	3		T11	4		T12	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	38544	1			T10	1		T11	3840		T41	2497
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1887	1			T11	6		T12	4		T41	9
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	34823	1			T11	3776		T12	256		T41	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	637	1			T5	8		T11	8		T24	6
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44069	1			T5	5		T11	1026		T24	2377
auto[1]	auto[0]	auto[0:524287]	auto[0]	484	1			T10	3		T12	2		T31	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	4499	1			T10	23		T12	2		T31	2
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	417	1			T5	1		T10	1		T12	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2986	1			T5	3		T10	12		T12	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	408	1			T10	1		T11	1		T12	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2677	1			T10	7		T11	14		T12	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	358	1			T11	3		T12	1		T41	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	4080	1			T11	90		T12	14		T41	746
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	377	1			T5	4		T12	2		T41	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3188	1			T5	17		T12	18		T24	101
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	390	1			T10	1		T11	1		T12	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	3271	1			T10	2		T11	4		T12	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	355	1			T5	1		T10	1		T11	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2766	1			T5	4		T10	4		T11	22
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	395	1			T5	2		T10	1		T12	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2490	1			T5	28		T10	9		T12	9
auto[1]	auto[1]	auto[0:524287]	auto[0]	108	1			T5	1		T41	2		T184	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	448	1			T5	2		T84	11		T234	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	95	1			T5	1		T41	10		T31	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	810	1			T5	2		T31	4		T83	7
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	77	1			T15	1		T16	1		T85	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	489	1			T15	7		T16	24		T85	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	90	1			T184	1		T84	1		T17	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	450	1			T184	2		T84	12		T17	76
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	98	1			T41	9		T161	1		T137	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	444	1			T161	15		T137	1		T19	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	99	1			T10	1		T11	1		T31	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	825	1			T10	2		T11	1		T31	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	124	1			T11	2		T15	1		T83	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	427	1			T11	37		T15	8		T83	5
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	88	1			T5	5		T11	2		T24	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	487	1			T5	15		T11	17		T24	12

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1939831	1			T1	98		T3	8		T5	5709
auto[0]	auto[0]	auto[1]	1020087	1			T1	92237		T3	24		T5	2
auto[0]	auto[1]	auto[0]	389850	1			T5	1784		T10	263		T11	11529
auto[0]	auto[1]	auto[1]	1728	1			T5	3		T10	1		T11	4
auto[1]	auto[0]	auto[0]	28631	1			T5	54		T10	63		T11	134
auto[1]	auto[0]	auto[1]	510	1			T5	6		T10	2		T11	2
auto[1]	auto[1]	auto[0]	5031	1			T5	21		T10	2		T11	58
auto[1]	auto[1]	auto[1]	128	1			T5	5		T10	1		T11	2