Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2296008	1			T1	1		T3	1		T4	1
all_pins[1]	2296008	1			T1	1		T3	1		T4	1
all_pins[2]	2296008	1			T1	1		T3	1		T4	1
all_pins[3]	2296008	1			T1	1		T3	1		T4	1
all_pins[4]	2296008	1			T1	1		T3	1		T4	1
all_pins[5]	2296008	1			T1	1		T3	1		T4	1
all_pins[6]	2296008	1			T1	1		T3	1		T4	1
all_pins[7]	2296008	1			T1	1		T3	1		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18318553	1			T1	8		T3	8		T4	8
values[0x1]	49511	1			T14	24		T16	96		T17	19
transitions[0x0=>0x1]	48180	1			T14	23		T16	61		T17	15
transitions[0x1=>0x0]	48191	1			T14	23		T16	61		T17	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2295322	1			T1	1		T3	1		T4	1
all_pins[0]	values[0x1]	686	1			T14	4		T16	24		T17	1
all_pins[0]	transitions[0x0=>0x1]	590	1			T14	4		T16	10		T17	1
all_pins[0]	transitions[0x1=>0x0]	130	1			T14	3		T16	7		T17	5
all_pins[1]	values[0x0]	2295782	1			T1	1		T3	1		T4	1
all_pins[1]	values[0x1]	226	1			T14	3		T16	21		T17	5
all_pins[1]	transitions[0x0=>0x1]	178	1			T14	3		T16	12		T17	4
all_pins[1]	transitions[0x1=>0x0]	340	1			T14	3		T16	3		T17	2
all_pins[2]	values[0x0]	2295620	1			T1	1		T3	1		T4	1
all_pins[2]	values[0x1]	388	1			T14	3		T16	12		T17	3
all_pins[2]	transitions[0x0=>0x1]	335	1			T14	3		T16	10		T17	2
all_pins[2]	transitions[0x1=>0x0]	169	1			T14	6		T16	8		T19	2
all_pins[3]	values[0x0]	2295786	1			T1	1		T3	1		T4	1
all_pins[3]	values[0x1]	222	1			T14	6		T16	10		T17	1
all_pins[3]	transitions[0x0=>0x1]	167	1			T14	6		T16	8		T17	1
all_pins[3]	transitions[0x1=>0x0]	142	1			T14	2		T16	2		T17	1
all_pins[4]	values[0x0]	2295811	1			T1	1		T3	1		T4	1
all_pins[4]	values[0x1]	197	1			T14	2		T16	4		T17	1
all_pins[4]	transitions[0x0=>0x1]	161	1			T14	2		T16	3		T17	1
all_pins[4]	transitions[0x1=>0x0]	2238	1			T14	1		T16	5		T17	1
all_pins[5]	values[0x0]	2293734	1			T1	1		T3	1		T4	1
all_pins[5]	values[0x1]	2274	1			T14	1		T16	6		T17	1
all_pins[5]	transitions[0x0=>0x1]	1341	1			T14	1		T16	2		T18	1
all_pins[5]	transitions[0x1=>0x0]	44386	1			T14	3		T16	8		T17	4
all_pins[6]	values[0x0]	2250689	1			T1	1		T3	1		T4	1
all_pins[6]	values[0x1]	45319	1			T14	3		T16	12		T17	5
all_pins[6]	transitions[0x0=>0x1]	45269	1			T14	2		T16	10		T17	4
all_pins[6]	transitions[0x1=>0x0]	149	1			T14	1		T16	5		T17	1
all_pins[7]	values[0x0]	2295809	1			T1	1		T3	1		T4	1
all_pins[7]	values[0x1]	199	1			T14	2		T16	7		T17	2
all_pins[7]	transitions[0x0=>0x1]	139	1			T14	2		T16	6		T17	2
all_pins[7]	transitions[0x1=>0x0]	637	1			T14	4		T16	23		T17	1