Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16865

1

T1

16

T3

4

T11

264

auto[1]

11798

1

T6

14

T11

152

T12

157

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3499	1			T11	74		T12	20		T41	20
values[1]	3476	1			T11	31		T12	69		T41	40
values[2]	3313	1			T11	97		T12	20		T46	14
values[3]	3770	1			T11	154		T12	113		T41	40
values[4]	3739	1			T1	16		T11	20		T12	40
values[5]	3793	1			T6	14		T12	23		T14	66
values[6]	3481	1			T11	40		T12	20		T41	60
values[7]	3592	1			T3	4		T12	42		T13	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4135	1			T12	94		T41	60		T45	12
values[1]	3505	1			T6	14		T11	74		T12	43
values[2]	3818	1			T11	98		T47	2		T14	177
values[3]	3530	1			T11	20		T12	79		T41	60
values[4]	3424	1			T11	22		T12	47		T41	20
values[5]	3055	1			T1	16		T12	22		T103	26
values[6]	3665	1			T11	20		T12	42		T41	20
values[7]	3531	1			T3	4		T11	182		T12	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	230	1			T41	10		T184	10		T136	8
auto[0]	values[0]	values[1]	274	1			T11	65		T190	11		T215	6
auto[0]	values[0]	values[2]	188	1			T180	12		T190	15		T183	18
auto[0]	values[0]	values[3]	328	1			T30	11		T173	12		T227	24
auto[0]	values[0]	values[4]	190	1			T14	9		T25	16		T184	22
auto[0]	values[0]	values[5]	139	1			T212	25		T224	7		T235	11
auto[0]	values[0]	values[6]	191	1			T236	8		T213	10		T237	2
auto[0]	values[0]	values[7]	383	1			T12	14		T100	8		T137	17
auto[0]	values[1]	values[0]	284	1			T12	9		T137	18		T183	10
auto[0]	values[1]	values[1]	254	1			T14	86		T190	10		T191	22
auto[0]	values[1]	values[2]	270	1			T14	32		T180	11		T185	12
auto[0]	values[1]	values[3]	231	1			T41	24		T30	6		T200	12
auto[0]	values[1]	values[4]	231	1			T12	12		T175	6		T238	6
auto[0]	values[1]	values[5]	225	1			T24	31		T30	12		T101	12
auto[0]	values[1]	values[6]	203	1			T12	11		T100	7		T239	4
auto[0]	values[1]	values[7]	199	1			T11	29		T191	11		T240	67
auto[0]	values[2]	values[0]	273	1			T12	11		T24	9		T205	6
auto[0]	values[2]	values[1]	279	1			T46	14		T24	14		T30	11
auto[0]	values[2]	values[2]	196	1			T11	50		T14	9		T180	4
auto[0]	values[2]	values[3]	272	1			T184	18		T211	10		T210	4
auto[0]	values[2]	values[4]	331	1			T11	13		T24	16		T233	14
auto[0]	values[2]	values[5]	168	1			T189	10		T241	8		T242	8
auto[0]	values[2]	values[6]	203	1			T173	13		T213	17		T57	8
auto[0]	values[2]	values[7]	203	1			T11	14		T204	4		T39	16
auto[0]	values[3]	values[0]	300	1			T12	18		T50	11		T243	22
auto[0]	values[3]	values[1]	227	1			T42	25		T184	17		T137	16
auto[0]	values[3]	values[2]	310	1			T11	35		T47	2		T14	83
auto[0]	values[3]	values[3]	334	1			T12	47		T30	13		T244	4
auto[0]	values[3]	values[4]	272	1			T245	11		T39	10		T190	11
auto[0]	values[3]	values[5]	264	1			T174	8		T184	18		T136	17
auto[0]	values[3]	values[6]	206	1			T41	10		T202	6		T39	14
auto[0]	values[3]	values[7]	282	1			T11	22		T41	14		T137	15
auto[0]	values[4]	values[0]	410	1			T14	11		T24	11		T184	11
auto[0]	values[4]	values[1]	215	1			T48	8		T100	12		T101	8
auto[0]	values[4]	values[2]	450	1			T24	15		T137	15		T219	23
auto[0]	values[4]	values[3]	299	1			T11	14		T12	14		T230	12
auto[0]	values[4]	values[4]	181	1			T12	9		T30	12		T100	13
auto[0]	values[4]	values[5]	242	1			T1	16		T98	10		T101	12
auto[0]	values[4]	values[6]	282	1			T14	112		T195	13		T207	10
auto[0]	values[4]	values[7]	222	1			T100	10		T39	18		T190	13
auto[0]	values[5]	values[0]	423	1			T24	40		T219	9		T212	15
auto[0]	values[5]	values[1]	252	1			T12	12		T24	19		T30	34
auto[0]	values[5]	values[2]	488	1			T24	24		T203	24		T137	12
auto[0]	values[5]	values[3]	230	1			T100	13		T137	6		T197	12
auto[0]	values[5]	values[4]	249	1			T184	18		T246	14		T137	16
auto[0]	values[5]	values[5]	269	1			T190	4		T247	8		T248	10
auto[0]	values[5]	values[6]	193	1			T30	11		T173	21		T245	10
auto[0]	values[5]	values[7]	269	1			T14	15		T249	2		T184	10
auto[0]	values[6]	values[0]	165	1			T41	10		T100	13		T184	11
auto[0]	values[6]	values[1]	291	1			T12	16		T41	15		T250	12
auto[0]	values[6]	values[2]	266	1			T181	10		T136	12		T251	54
auto[0]	values[6]	values[3]	226	1			T41	12		T24	11		T30	9
auto[0]	values[6]	values[4]	205	1			T173	12		T184	27		T136	9
auto[0]	values[6]	values[5]	266	1			T252	18		T58	6		T185	11
auto[0]	values[6]	values[6]	410	1			T11	9		T14	9		T24	13
auto[0]	values[6]	values[7]	307	1			T11	13		T42	9		T253	12
auto[0]	values[7]	values[0]	200	1			T41	10		T45	12		T24	21
auto[0]	values[7]	values[1]	218	1			T26	12		T38	26		T254	22
auto[0]	values[7]	values[2]	367	1			T30	7		T219	11		T255	12
auto[0]	values[7]	values[3]	273	1			T42	43		T136	14		T175	12
auto[0]	values[7]	values[4]	247	1			T41	16		T14	63		T212	10
auto[0]	values[7]	values[5]	210	1			T12	8		T14	12		T197	12
auto[0]	values[7]	values[6]	371	1			T12	9		T42	12		T256	45
auto[0]	values[7]	values[7]	229	1			T3	4		T14	25		T180	14
auto[1]	values[0]	values[0]	226	1			T41	10		T184	12		T136	80
auto[1]	values[0]	values[1]	142	1			T11	9		T190	9		T226	8
auto[1]	values[0]	values[2]	105	1			T180	8		T190	5		T183	2
auto[1]	values[0]	values[3]	150	1			T30	12		T173	8		T136	5
auto[1]	values[0]	values[4]	213	1			T14	11		T184	4		T213	15
auto[1]	values[0]	values[5]	168	1			T228	24		T212	38		T224	13
auto[1]	values[0]	values[6]	246	1			T213	10		T195	10		T101	8
auto[1]	values[0]	values[7]	326	1			T12	6		T100	12		T137	3
auto[1]	values[1]	values[0]	523	1			T12	11		T104	14		T137	7
auto[1]	values[1]	values[1]	170	1			T14	5		T190	10		T191	18
auto[1]	values[1]	values[2]	125	1			T14	19		T180	11		T257	8
auto[1]	values[1]	values[3]	164	1			T41	16		T30	44		T173	18
auto[1]	values[1]	values[4]	235	1			T12	15		T258	20		T175	14
auto[1]	values[1]	values[5]	150	1			T103	26		T24	3		T30	8
auto[1]	values[1]	values[6]	132	1			T12	11		T100	13		T136	25
auto[1]	values[1]	values[7]	80	1			T11	2		T191	9		T240	9
auto[1]	values[2]	values[0]	224	1			T12	9		T24	11		T179	10
auto[1]	values[2]	values[1]	219	1			T24	6		T30	58		T173	5
auto[1]	values[2]	values[2]	131	1			T11	5		T14	27		T180	16
auto[1]	values[2]	values[3]	173	1			T184	5		T259	8		T211	10
auto[1]	values[2]	values[4]	198	1			T11	9		T24	65		T221	19
auto[1]	values[2]	values[5]	162	1			T260	28		T224	7		T261	18
auto[1]	values[2]	values[6]	173	1			T214	14		T173	7		T213	4
auto[1]	values[2]	values[7]	108	1			T11	6		T39	4		T212	9
auto[1]	values[3]	values[0]	167	1			T12	36		T50	9		T100	6
auto[1]	values[3]	values[1]	210	1			T42	66		T184	6		T137	12
auto[1]	values[3]	values[2]	171	1			T11	8		T14	7		T218	9
auto[1]	values[3]	values[3]	248	1			T12	12		T30	14		T136	8
auto[1]	values[3]	values[4]	121	1			T245	9		T39	11		T190	9
auto[1]	values[3]	values[5]	108	1			T44	8		T184	4		T136	4
auto[1]	values[3]	values[6]	337	1			T41	10		T39	6		T191	10
auto[1]	values[3]	values[7]	213	1			T11	89		T41	6		T137	7
auto[1]	values[4]	values[0]	240	1			T14	73		T24	9		T184	10
auto[1]	values[4]	values[1]	205	1			T100	8		T101	12		T39	7
auto[1]	values[4]	values[2]	223	1			T24	5		T198	14		T137	7
auto[1]	values[4]	values[3]	143	1			T11	6		T12	6		T136	12
auto[1]	values[4]	values[4]	148	1			T12	11		T30	24		T100	7
auto[1]	values[4]	values[5]	188	1			T101	8		T175	10		T191	3
auto[1]	values[4]	values[6]	70	1			T14	13		T262	4		T195	7
auto[1]	values[4]	values[7]	221	1			T100	10		T82	18		T39	9
auto[1]	values[5]	values[0]	167	1			T24	11		T219	11		T212	8
auto[1]	values[5]	values[1]	208	1			T6	14		T12	11		T24	107
auto[1]	values[5]	values[2]	199	1			T24	6		T137	11		T191	14
auto[1]	values[5]	values[3]	109	1			T100	7		T137	14		T197	8
auto[1]	values[5]	values[4]	241	1			T184	5		T137	7		T212	6
auto[1]	values[5]	values[5]	176	1			T190	16		T263	7		T264	24
auto[1]	values[5]	values[6]	156	1			T30	9		T173	19		T245	16
auto[1]	values[5]	values[7]	164	1			T14	51		T184	10		T222	20
auto[1]	values[6]	values[0]	118	1			T41	10		T100	7		T184	9
auto[1]	values[6]	values[1]	164	1			T12	4		T41	5		T136	8
auto[1]	values[6]	values[2]	198	1			T136	8		T183	8		T192	18
auto[1]	values[6]	values[3]	117	1			T41	8		T24	12		T30	11
auto[1]	values[6]	values[4]	166	1			T265	2		T173	8		T184	17
auto[1]	values[6]	values[5]	106	1			T266	12		T185	9		T267	9
auto[1]	values[6]	values[6]	254	1			T11	11		T14	44		T24	7
auto[1]	values[6]	values[7]	222	1			T11	7		T42	11		T100	14
auto[1]	values[7]	values[0]	185	1			T41	10		T24	19		T30	8
auto[1]	values[7]	values[1]	177	1			T136	9		T221	14		T175	5
auto[1]	values[7]	values[2]	131	1			T30	13		T219	9		T185	7
auto[1]	values[7]	values[3]	233	1			T42	2		T136	7		T175	8
auto[1]	values[7]	values[4]	196	1			T41	4		T14	12		T212	27
auto[1]	values[7]	values[5]	214	1			T12	14		T14	79		T197	8
auto[1]	values[7]	values[6]	238	1			T12	11		T42	8		T100	15
auto[1]	values[7]	values[7]	103	1			T13	16		T14	5		T180	10