Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	437	1			T1	6		T11	3		T12	4
auto[ReadAddrCrossIntoMailbox]	259	1			T1	4		T11	2		T12	3
auto[ReadAddrCrossOutOfMailbox]	316	1			T1	2		T11	2		T12	2
auto[ReadAddrCrossAllMailbox]	211	1			T11	3		T12	6		T41	1
auto[ReadAddrOutsideMailbox]	3306	1			T1	4		T3	4		T6	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2224

1

T1

8

T3

2

T6

1

auto[1]

2305

1

T1

8

T3

2

T6

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	787	1			T1	8		T11	7		T12	9
read_ops[0x0b]	771	1			T1	4		T3	2		T11	12
read_ops[0x3b]	741	1			T11	6		T12	14		T41	5
read_ops[0x6b]	732	1			T1	4		T6	2		T11	7
read_ops[0xbb]	751	1			T3	2		T11	8		T12	15
read_ops[0xeb]	747	1			T11	3		T12	13		T41	6

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	39	1			T1	1		T24	1		T137	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T1	1		T11	1		T173	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T1	1		T218	1		T39	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T1	1		T42	2		T180	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T137	1		T222	1		T183	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T101	1		T212	1		T183	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T11	1		T12	2		T24	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T11	2		T14	1		T24	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T1	2		T11	1		T12	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	316	1			T1	2		T11	2		T12	4
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	29	1			T1	1		T12	1		T42	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T1	1		T11	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T11	1		T42	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T100	3		T57	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	25	1			T1	1		T11	1		T45	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	39	1			T1	1		T11	1		T45	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T213	1		T101	1		T222	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	29	1			T180	1		T137	3		T195	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	264	1			T3	1		T11	3		T12	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	295	1			T3	1		T11	5		T12	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T173	2		T137	1		T221	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	44	1			T42	1		T137	1		T101	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T14	1		T137	2		T39	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T12	1		T42	1		T218	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T12	1		T136	1		T137	3
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T218	1		T217	2		T191	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T12	1		T14	1		T197	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T41	1		T184	1		T229	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	283	1			T11	2		T12	2		T46	2
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	262	1			T11	4		T12	9		T41	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T1	1		T42	1		T184	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	39	1			T1	1		T12	2		T41	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T1	1		T12	1		T45	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T1	1		T11	1		T45	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T101	1		T197	1		T212	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T137	1		T219	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T24	1		T190	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T12	1		T42	1		T14	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T6	1		T12	4		T13	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	247	1			T6	1		T11	6		T12	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T42	3		T14	1		T268	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T11	1		T12	1		T24	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T12	1		T136	1		T190	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T137	1		T101	1		T183	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T41	1		T14	1		T30	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T173	2		T184	1		T137	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T222	1		T191	2		T263	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	10	1			T137	1		T183	1		T191	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T3	1		T11	4		T12	5
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	259	1			T3	1		T11	3		T12	8
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T47	1		T180	1		T173	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T47	1		T14	1		T100	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T184	1		T205	1		T218	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T24	1		T180	1		T184	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T12	1		T173	1		T205	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	31	1			T41	1		T205	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T12	2		T24	1		T137	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T42	1		T137	2		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T11	1		T12	5		T41	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T11	2		T12	5		T41	4