Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3599	1			T12	42		T41	40		T45	12
values[1]	4123	1			T11	94		T12	34		T41	40
values[2]	3191	1			T11	71		T12	20		T47	2
values[3]	3778	1			T1	16		T3	4		T11	146
values[4]	3191	1			T12	109		T41	20		T103	26
values[5]	3284	1			T11	20		T12	79		T41	20
values[6]	3901	1			T6	14		T11	65		T12	20
values[7]	3596	1			T11	20		T12	43		T41	60

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3547	1			T11	20		T12	44		T24	60
values[1]	3791	1			T11	209		T41	20		T45	12
values[2]	3222	1			T1	16		T12	20		T41	40
values[3]	3803	1			T12	43		T41	20		T47	2
values[4]	3953	1			T11	42		T12	54		T13	16
values[5]	3252	1			T3	4		T6	14		T11	31
values[6]	3596	1			T11	20		T12	107		T41	40
values[7]	3499	1			T11	94		T12	79		T41	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27969

1

T1

16

T3

4

T6

12

auto[1]

694

1

T6

2

T11

7

T12

10

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	300	1			T12	21		T227	24		T39	26
auto[0]	values[0]	values[1]	423	1			T45	12		T24	20		T198	14
auto[0]	values[0]	values[2]	280	1			T41	39		T100	37		T190	18
auto[0]	values[0]	values[3]	537	1			T14	20		T100	20		T197	20
auto[0]	values[0]	values[4]	573	1			T42	59		T24	20		T269	14
auto[0]	values[0]	values[5]	606	1			T179	10		T136	122		T175	71
auto[0]	values[0]	values[6]	407	1			T246	14		T101	20		T190	20
auto[0]	values[0]	values[7]	403	1			T12	19		T30	23		T180	20
auto[0]	values[1]	values[0]	325	1			T24	20		T38	26		T39	20
auto[0]	values[1]	values[1]	854	1			T200	12		T219	19		T212	43
auto[0]	values[1]	values[2]	604	1			T173	20		T191	20		T52	20
auto[0]	values[1]	values[3]	467	1			T41	20		T180	24		T101	33
auto[0]	values[1]	values[4]	475	1			T12	32		T41	20		T14	89
auto[0]	values[1]	values[5]	357	1			T98	10		T204	4		T233	14
auto[0]	values[1]	values[6]	405	1			T39	21		T175	34		T270	12
auto[0]	values[1]	values[7]	544	1			T11	93		T221	21		T175	35
auto[0]	values[2]	values[0]	530	1			T11	20		T30	34		T175	19
auto[0]	values[2]	values[1]	635	1			T25	16		T44	6		T184	22
auto[0]	values[2]	values[2]	231	1			T262	2		T184	23		T178	20
auto[0]	values[2]	values[3]	369	1			T47	2		T24	70		T100	19
auto[0]	values[2]	values[4]	233	1			T11	20		T213	20		T219	20
auto[0]	values[2]	values[5]	440	1			T11	30		T14	83		T202	6
auto[0]	values[2]	values[6]	417	1			T12	19		T30	19		T100	20
auto[0]	values[2]	values[7]	243	1			T30	20		T173	20		T137	21
auto[0]	values[3]	values[0]	540	1			T173	20		T137	20		T258	16
auto[0]	values[3]	values[1]	486	1			T11	144		T218	23		T39	27
auto[0]	values[3]	values[2]	442	1			T1	16		T24	104		T184	24
auto[0]	values[3]	values[3]	507	1			T14	124		T219	20		T190	19
auto[0]	values[3]	values[4]	378	1			T239	4		T136	20		T137	21
auto[0]	values[3]	values[5]	556	1			T3	4		T30	27		T137	20
auto[0]	values[3]	values[6]	426	1			T41	18		T30	20		T271	12
auto[0]	values[3]	values[7]	354	1			T184	19		T221	23		T232	6
auto[0]	values[4]	values[0]	451	1			T12	21		T253	12		T184	20
auto[0]	values[4]	values[1]	319	1			T24	20		T184	22		T101	20
auto[0]	values[4]	values[2]	396	1			T12	20		T137	26		T219	40
auto[0]	values[4]	values[3]	209	1			T212	19		T57	19		T272	21
auto[0]	values[4]	values[4]	464	1			T12	20		T103	26		T14	74
auto[0]	values[4]	values[5]	344	1			T184	20		T101	19		T219	19
auto[0]	values[4]	values[6]	451	1			T12	46		T42	45		T100	18
auto[0]	values[4]	values[7]	485	1			T41	20		T42	19		T100	20
auto[0]	values[5]	values[0]	340	1			T100	20		T213	18		T137	20
auto[0]	values[5]	values[1]	301	1			T11	20		T180	19		T173	17
auto[0]	values[5]	values[2]	264	1			T24	23		T236	8		T273	2
auto[0]	values[5]	values[3]	469	1			T14	118		T173	20		T249	2
auto[0]	values[5]	values[4]	448	1			T219	19		T82	10		T175	44
auto[0]	values[5]	values[5]	336	1			T137	22		T195	20		T267	20
auto[0]	values[5]	values[6]	429	1			T12	19		T41	20		T14	90
auto[0]	values[5]	values[7]	598	1			T12	59		T14	31		T104	14
auto[0]	values[6]	values[0]	493	1			T24	38		T256	45		T101	19
auto[0]	values[6]	values[1]	412	1			T11	42		T46	14		T136	21
auto[0]	values[6]	values[2]	559	1			T24	34		T26	12		T225	12
auto[0]	values[6]	values[3]	464	1			T14	65		T30	46		T184	20
auto[0]	values[6]	values[4]	749	1			T11	21		T13	12		T42	20
auto[0]	values[6]	values[5]	335	1			T6	12		T230	12		T243	22
auto[0]	values[6]	values[6]	419	1			T12	19		T14	110		T173	20
auto[0]	values[6]	values[7]	377	1			T24	20		T30	20		T212	20
auto[0]	values[7]	values[0]	463	1			T30	66		T50	20		T100	19
auto[0]	values[7]	values[1]	289	1			T41	18		T42	29		T184	23
auto[0]	values[7]	values[2]	358	1			T30	49		T197	19		T210	4
auto[0]	values[7]	values[3]	694	1			T12	42		T24	81		T100	16
auto[0]	values[7]	values[4]	523	1			T41	20		T184	20		T52	80
auto[0]	values[7]	values[5]	202	1			T41	20		T268	16		T188	20
auto[0]	values[7]	values[6]	567	1			T11	19		T174	8		T24	30
auto[0]	values[7]	values[7]	414	1			T48	8		T205	6		T203	24
auto[1]	values[0]	values[0]	7	1			T12	1		T39	4		T274	1
auto[1]	values[0]	values[1]	6	1			T219	2		T275	2		T276	2
auto[1]	values[0]	values[2]	11	1			T41	1		T100	3		T190	2
auto[1]	values[0]	values[3]	8	1			T186	1		T188	3		T277	2
auto[1]	values[0]	values[4]	9	1			T42	3		T39	1		T52	1
auto[1]	values[0]	values[5]	10	1			T136	1		T175	1		T278	1
auto[1]	values[0]	values[6]	10	1			T222	1		T191	5		T240	1
auto[1]	values[0]	values[7]	9	1			T12	1		T213	3		T192	1
auto[1]	values[1]	values[0]	9	1			T260	3		T188	1		T194	2
auto[1]	values[1]	values[1]	13	1			T219	1		T191	1		T211	3
auto[1]	values[1]	values[2]	14	1			T260	4		T240	2		T235	1
auto[1]	values[1]	values[3]	14	1			T101	7		T186	1		T138	3
auto[1]	values[1]	values[4]	13	1			T12	2		T14	2		T173	2
auto[1]	values[1]	values[5]	15	1			T192	2		T279	4		T280	3
auto[1]	values[1]	values[6]	3	1			T175	1		T280	2		-	-
auto[1]	values[1]	values[7]	11	1			T11	1		T190	5		T277	4
auto[1]	values[2]	values[0]	17	1			T30	2		T175	1		T212	4
auto[1]	values[2]	values[1]	13	1			T44	2		T136	2		T137	1
auto[1]	values[2]	values[2]	11	1			T262	2		T178	3		T281	2
auto[1]	values[2]	values[3]	3	1			T24	1		T100	1		T282	1
auto[1]	values[2]	values[4]	5	1			T213	1		T211	1		T138	1
auto[1]	values[2]	values[5]	12	1			T11	1		T14	1		T261	1
auto[1]	values[2]	values[6]	19	1			T12	1		T30	1		T173	1
auto[1]	values[2]	values[7]	13	1			T137	1		T190	2		T183	3
auto[1]	values[3]	values[0]	13	1			T258	4		T187	2		T283	3
auto[1]	values[3]	values[1]	8	1			T11	2		T221	1		T284	3
auto[1]	values[3]	values[2]	13	1			T24	2		T184	2		T231	2
auto[1]	values[3]	values[3]	11	1			T14	1		T190	1		T235	3
auto[1]	values[3]	values[4]	22	1			T136	1		T137	2		T207	8
auto[1]	values[3]	values[5]	8	1			T137	2		T183	1		T188	1
auto[1]	values[3]	values[6]	10	1			T41	2		T271	4		T211	1
auto[1]	values[3]	values[7]	4	1			T184	1		T191	1		T231	1
auto[1]	values[4]	values[0]	17	1			T12	1		T184	1		T245	1
auto[1]	values[4]	values[1]	7	1			T240	2		T231	2		T284	1
auto[1]	values[4]	values[2]	3	1			T137	2		T235	1		-	-
auto[1]	values[4]	values[3]	12	1			T212	1		T57	1		T272	2
auto[1]	values[4]	values[4]	10	1			T14	1		T285	4		T263	2
auto[1]	values[4]	values[5]	5	1			T101	1		T219	1		T39	2
auto[1]	values[4]	values[6]	13	1			T12	1		T100	2		T173	1
auto[1]	values[4]	values[7]	5	1			T42	1		T187	1		T286	3
auto[1]	values[5]	values[0]	16	1			T213	2		T212	3		T287	6
auto[1]	values[5]	values[1]	11	1			T180	1		T173	3		T221	1
auto[1]	values[5]	values[2]	10	1			T278	1		T224	1		T288	3
auto[1]	values[5]	values[3]	14	1			T14	1		T289	4		T278	2
auto[1]	values[5]	values[4]	22	1			T219	1		T82	8		T175	3
auto[1]	values[5]	values[5]	7	1			T54	3		T290	3		T291	1
auto[1]	values[5]	values[6]	4	1			T12	1		T101	1		T192	2
auto[1]	values[5]	values[7]	15	1			T175	1		T292	4		T231	2
auto[1]	values[6]	values[0]	11	1			T24	2		T101	1		T188	2
auto[1]	values[6]	values[1]	7	1			T11	1		T136	4		T288	1
auto[1]	values[6]	values[2]	12	1			T240	1		T231	1		T274	2
auto[1]	values[6]	values[3]	11	1			T14	1		T30	1		T136	3
auto[1]	values[6]	values[4]	24	1			T11	1		T13	4		T39	1
auto[1]	values[6]	values[5]	14	1			T6	2		T222	3		T293	3
auto[1]	values[6]	values[6]	6	1			T12	1		T14	1		T207	1
auto[1]	values[6]	values[7]	8	1			T216	1		T294	1		T281	1
auto[1]	values[7]	values[0]	15	1			T30	3		T100	1		T294	1
auto[1]	values[7]	values[1]	7	1			T41	2		T101	1		T278	1
auto[1]	values[7]	values[2]	14	1			T30	1		T197	1		T224	2
auto[1]	values[7]	values[3]	14	1			T12	1		T100	4		T213	1
auto[1]	values[7]	values[4]	5	1			T184	2		T188	2		T201	1
auto[1]	values[7]	values[5]	5	1			T295	1		T194	3		T296	1
auto[1]	values[7]	values[6]	10	1			T11	1		T30	1		T216	1
auto[1]	values[7]	values[7]	16	1			T195	2		T221	2		T185	2