Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	830	1			T14	14		T16	31		T17	10
all_values[1]	830	1			T14	14		T16	31		T17	10
all_values[2]	830	1			T14	14		T16	31		T17	10
all_values[3]	830	1			T14	14		T16	31		T17	10
all_values[4]	830	1			T14	14		T16	31		T17	10
all_values[5]	830	1			T14	14		T16	31		T17	10
all_values[6]	830	1			T14	14		T16	31		T17	10
all_values[7]	830	1			T14	14		T16	31		T17	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3551

1

T14

57

T16

108

T17

38

auto[1]

3089

1

T14

55

T16

140

T17

42

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2704

1

T14

48

T16

116

T17

31

auto[1]

3936

1

T14

64

T16

132

T17

49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3841

1

T14

66

T16

155

T17

44

auto[1]

2799

1

T14

46

T16

93

T17

36

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	185	1			T14	3		T16	11		T17	3
all_values[0]	auto[0]	auto[0]	auto[1]	67	1			T14	3		T17	1		T19	3
all_values[0]	auto[0]	auto[1]	auto[0]	147	1			T14	1		T16	12		T17	4
all_values[0]	auto[0]	auto[1]	auto[1]	73	1			T14	1		T16	1		T18	3
all_values[0]	auto[1]	auto[0]	auto[1]	186	1			T14	4		T16	2		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	172	1			T14	2		T16	5		T18	1
all_values[1]	auto[0]	auto[0]	auto[0]	176	1			T14	2		T16	3		T19	4
all_values[1]	auto[0]	auto[0]	auto[1]	71	1			T14	1		T16	2		T17	2
all_values[1]	auto[0]	auto[1]	auto[0]	149	1			T14	3		T16	10		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T14	1		T16	2		T17	2
all_values[1]	auto[1]	auto[0]	auto[1]	182	1			T14	2		T16	5		T17	2
all_values[1]	auto[1]	auto[1]	auto[1]	172	1			T14	5		T16	9		T17	3
all_values[2]	auto[0]	auto[0]	auto[0]	190	1			T14	2		T16	8		T17	1
all_values[2]	auto[0]	auto[0]	auto[1]	81	1			T14	4		T16	2		T17	3
all_values[2]	auto[0]	auto[1]	auto[0]	165	1			T14	3		T16	7		T17	1
all_values[2]	auto[0]	auto[1]	auto[1]	77	1			T14	1		T16	1		T17	1
all_values[2]	auto[1]	auto[0]	auto[1]	176	1			T14	1		T16	5		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	141	1			T14	3		T16	8		T17	3
all_values[3]	auto[0]	auto[0]	auto[0]	137	1			T14	1		T16	5		T17	3
all_values[3]	auto[0]	auto[0]	auto[1]	96	1			T16	3		T17	1		T19	4
all_values[3]	auto[0]	auto[1]	auto[0]	126	1			T14	3		T16	6		T17	3
all_values[3]	auto[0]	auto[1]	auto[1]	92	1			T14	3		T16	6		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	233	1			T14	3		T16	7		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	146	1			T14	4		T16	4		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	161	1			T14	1		T16	3		T17	3
all_values[4]	auto[0]	auto[0]	auto[1]	80	1			T14	1		T16	4		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	148	1			T14	5		T16	11		T17	3
all_values[4]	auto[0]	auto[1]	auto[1]	81	1			T14	2		T16	2		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	194	1			T14	2		T16	5		T17	1
all_values[4]	auto[1]	auto[1]	auto[1]	166	1			T14	3		T16	6		T17	2
all_values[5]	auto[0]	auto[0]	auto[0]	257	1			T14	5		T16	11		T17	2
all_values[5]	auto[0]	auto[1]	auto[0]	230	1			T14	2		T16	10		T17	3
all_values[5]	auto[1]	auto[0]	auto[1]	194	1			T14	6		T16	6		T17	4
all_values[5]	auto[1]	auto[1]	auto[1]	149	1			T14	1		T16	4		T17	1
all_values[6]	auto[0]	auto[0]	auto[0]	185	1			T14	5		T16	3		T18	2
all_values[6]	auto[0]	auto[0]	auto[1]	78	1			T16	6		T19	5		T20	4
all_values[6]	auto[0]	auto[1]	auto[0]	136	1			T14	2		T16	2		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	96	1			T14	1		T16	4		T17	1
all_values[6]	auto[1]	auto[0]	auto[1]	174	1			T14	3		T16	7		T17	1
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T14	3		T16	9		T17	7
all_values[7]	auto[0]	auto[0]	auto[0]	173	1			T14	6		T16	4		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T16	2		T17	1		T18	1
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T14	4		T16	10		T17	2
all_values[7]	auto[0]	auto[1]	auto[1]	86	1			T16	4		T19	3		T20	1
all_values[7]	auto[1]	auto[0]	auto[1]	196	1			T14	2		T16	4		T17	4
all_values[7]	auto[1]	auto[1]	auto[1]	157	1			T14	2		T16	7		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal