Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1733

1

T4

3

T12

12

T31

5

auto[1]

1717

1

T4

10

T12

8

T31

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1870

1

T12

20

T31

20

T32

6

auto[1]

1580

1

T4

13

T33

7

T90

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2723

1

T4

13

T12

17

T31

11

auto[1]

727

1

T12

3

T31

9

T32

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	730	1			T4	4		T12	3		T31	1
valid[1]	705	1			T4	2		T12	5		T31	5
valid[2]	653	1			T4	1		T12	7		T31	4
valid[3]	663	1			T4	2		T31	2		T32	2
valid[4]	699	1			T4	4		T12	5		T31	8

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	115	1			T12	2		T32	2		T14	1
auto[0]	auto[0]	valid[0]	auto[1]	179	1			T4	1		T93	2		T94	1
auto[0]	auto[0]	valid[1]	auto[0]	137	1			T12	2		T36	1		T49	1
auto[0]	auto[0]	valid[1]	auto[1]	139	1			T4	1		T33	1		T90	1
auto[0]	auto[0]	valid[2]	auto[0]	99	1			T12	4		T31	1		T83	1
auto[0]	auto[0]	valid[2]	auto[1]	165	1			T33	2		T90	1		T93	1
auto[0]	auto[0]	valid[3]	auto[0]	101	1			T35	1		T321	1		T15	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T93	2		T94	1		T95	2
auto[0]	auto[0]	valid[4]	auto[0]	116	1			T12	2		T35	2		T50	1
auto[0]	auto[0]	valid[4]	auto[1]	158	1			T4	1		T33	1		T93	3
auto[0]	auto[1]	valid[0]	auto[0]	120	1			T12	1		T31	1		T35	1
auto[0]	auto[1]	valid[0]	auto[1]	172	1			T4	3		T90	1		T93	1
auto[0]	auto[1]	valid[1]	auto[0]	122	1			T12	2		T31	2		T32	1
auto[0]	auto[1]	valid[1]	auto[1]	149	1			T4	1		T93	2		T94	1
auto[0]	auto[1]	valid[2]	auto[0]	110	1			T12	1		T31	2		T35	1
auto[0]	auto[1]	valid[2]	auto[1]	149	1			T4	1		T33	1		T90	1
auto[0]	auto[1]	valid[3]	auto[0]	107	1			T31	1		T32	2		T35	2
auto[0]	auto[1]	valid[3]	auto[1]	157	1			T4	2		T93	1		T95	1
auto[0]	auto[1]	valid[4]	auto[0]	116	1			T12	3		T31	4		T35	2
auto[0]	auto[1]	valid[4]	auto[1]	152	1			T4	3		T33	2		T94	1
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T14	1		T36	1		T50	1
auto[1]	auto[0]	valid[1]	auto[0]	77	1			T12	1		T31	1		T49	1
auto[1]	auto[0]	valid[2]	auto[0]	63	1			T12	1		T31	1		T36	1
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T31	1		T184	1		T245	1
auto[1]	auto[0]	valid[4]	auto[0]	79	1			T31	1		T34	1		T35	1
auto[1]	auto[1]	valid[0]	auto[0]	68	1			T35	2		T36	1		T49	1
auto[1]	auto[1]	valid[1]	auto[0]	81	1			T31	2		T14	1		T50	1
auto[1]	auto[1]	valid[2]	auto[0]	67	1			T12	1		T14	1		T50	1
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T35	1		T180	1		T184	2
auto[1]	auto[1]	valid[4]	auto[0]	78	1			T31	3		T32	1		T30	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal