Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46129

1

T12

479

T31

488

T32

121

auto[1]

16418

1

T4

13

T33

7

T14

13

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45803

1

T4

13

T12

331

T31

326

auto[1]

16744

1

T12

148

T31

162

T32

37

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32358	1			T4	13		T12	265		T31	238
others[1]	5300	1			T12	40		T31	46		T32	11
others[2]	5211	1			T12	42		T31	37		T32	6
others[3]	5949	1			T12	35		T31	52		T32	14
interest[1]	3486	1			T12	26		T31	25		T32	6
interest[4]	21251	1			T4	13		T12	176		T31	167
interest[64]	10243	1			T12	71		T31	90		T32	21

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15104	1			T12	188		T31	165		T32	39
auto[0]	auto[0]	others[1]	2511	1			T12	28		T31	28		T32	10
auto[0]	auto[0]	others[2]	2467	1			T12	25		T31	25		T32	5
auto[0]	auto[0]	others[3]	2760	1			T12	25		T31	30		T32	9
auto[0]	auto[0]	interest[1]	1664	1			T12	17		T31	17		T32	5
auto[0]	auto[0]	interest[4]	9890	1			T12	123		T31	112		T32	20
auto[0]	auto[0]	interest[64]	4879	1			T12	48		T31	61		T32	16
auto[0]	auto[1]	others[0]	8623	1			T4	13		T33	7		T14	9
auto[0]	auto[1]	others[1]	1384	1			T14	2		T49	2		T90	2
auto[0]	auto[1]	others[2]	1352	1			T49	6		T90	4		T91	9
auto[0]	auto[1]	others[3]	1539	1			T30	1		T49	8		T90	7
auto[0]	auto[1]	interest[1]	892	1			T49	3		T90	2		T180	3
auto[0]	auto[1]	interest[4]	5803	1			T4	13		T33	7		T14	6
auto[0]	auto[1]	interest[64]	2628	1			T14	2		T49	4		T90	5
auto[1]	auto[0]	others[0]	8631	1			T12	77		T31	73		T32	24
auto[1]	auto[0]	others[1]	1405	1			T12	12		T31	18		T32	1
auto[1]	auto[0]	others[2]	1392	1			T12	17		T31	12		T32	1
auto[1]	auto[0]	others[3]	1650	1			T12	10		T31	22		T32	5
auto[1]	auto[0]	interest[1]	930	1			T12	9		T31	8		T32	1
auto[1]	auto[0]	interest[4]	5558	1			T12	53		T31	55		T32	13
auto[1]	auto[0]	interest[64]	2736	1			T12	23		T31	29		T32	5

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal