Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 94.01 98.62 89.36 97.21 95.45 99.21


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
T1031 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1368719615 Jul 22 05:41:03 PM PDT 24 Jul 22 05:41:05 PM PDT 24 37711153 ps
T121 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2535385133 Jul 22 05:41:02 PM PDT 24 Jul 22 05:41:07 PM PDT 24 169568986 ps
T88 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1688049858 Jul 22 05:44:38 PM PDT 24 Jul 22 05:44:40 PM PDT 24 44749886 ps
T89 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2525009861 Jul 22 05:41:15 PM PDT 24 Jul 22 05:41:19 PM PDT 24 138527624 ps
T1032 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.934526430 Jul 22 05:41:28 PM PDT 24 Jul 22 05:41:29 PM PDT 24 14987048 ps
T164 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3523454958 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:24 PM PDT 24 275119032 ps
T150 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.62184513 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:40 PM PDT 24 675254682 ps
T117 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3125494398 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:34 PM PDT 24 145724472 ps
T1033 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3472501721 Jul 22 05:41:44 PM PDT 24 Jul 22 05:41:45 PM PDT 24 15932005 ps
T1034 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.252308161 Jul 22 05:41:29 PM PDT 24 Jul 22 05:41:30 PM PDT 24 13850165 ps
T1035 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.930433959 Jul 22 05:43:31 PM PDT 24 Jul 22 05:43:33 PM PDT 24 54865844 ps
T1036 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2026454186 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:31 PM PDT 24 33148059 ps
T1037 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.438196597 Jul 22 05:41:37 PM PDT 24 Jul 22 05:41:39 PM PDT 24 24556460 ps
T167 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3398001210 Jul 22 05:44:42 PM PDT 24 Jul 22 05:44:50 PM PDT 24 971618063 ps
T110 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.384710702 Jul 22 05:41:24 PM PDT 24 Jul 22 05:41:28 PM PDT 24 128296779 ps
T1038 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2424806994 Jul 22 05:44:47 PM PDT 24 Jul 22 05:44:48 PM PDT 24 27910389 ps
T111 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3325468513 Jul 22 05:44:38 PM PDT 24 Jul 22 05:44:41 PM PDT 24 95032943 ps
T1039 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1547919994 Jul 22 05:41:22 PM PDT 24 Jul 22 05:41:25 PM PDT 24 29258969 ps
T118 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2464308731 Jul 22 05:41:20 PM PDT 24 Jul 22 05:41:25 PM PDT 24 130027088 ps
T1040 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2453287382 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:33 PM PDT 24 69290289 ps
T151 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3951449986 Jul 22 05:41:21 PM PDT 24 Jul 22 05:41:26 PM PDT 24 195003848 ps
T1041 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1418474468 Jul 22 05:41:13 PM PDT 24 Jul 22 05:41:16 PM PDT 24 12217096 ps
T168 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1309766253 Jul 22 05:41:02 PM PDT 24 Jul 22 05:41:11 PM PDT 24 402866007 ps
T152 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2565897340 Jul 22 05:41:17 PM PDT 24 Jul 22 05:41:23 PM PDT 24 153602753 ps
T1042 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.854173868 Jul 22 05:41:32 PM PDT 24 Jul 22 05:41:34 PM PDT 24 61276817 ps
T130 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1988260223 Jul 22 05:41:01 PM PDT 24 Jul 22 05:41:17 PM PDT 24 1601227808 ps
T153 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1933589820 Jul 22 05:41:02 PM PDT 24 Jul 22 05:41:18 PM PDT 24 4393366104 ps
T1043 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3610228738 Jul 22 05:41:13 PM PDT 24 Jul 22 05:41:16 PM PDT 24 12207859 ps
T1044 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.378744468 Jul 22 05:41:12 PM PDT 24 Jul 22 05:41:15 PM PDT 24 106900770 ps
T165 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3659685036 Jul 22 05:41:32 PM PDT 24 Jul 22 05:41:56 PM PDT 24 1721602668 ps
T132 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2623566990 Jul 22 05:41:18 PM PDT 24 Jul 22 05:41:21 PM PDT 24 142714906 ps
T133 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.445271848 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:34 PM PDT 24 301503380 ps
T134 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1691947766 Jul 22 05:44:41 PM PDT 24 Jul 22 05:44:43 PM PDT 24 385805263 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4071056133 Jul 22 05:41:02 PM PDT 24 Jul 22 05:41:06 PM PDT 24 224305652 ps
T1046 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3769037548 Jul 22 05:41:40 PM PDT 24 Jul 22 05:41:41 PM PDT 24 19953988 ps
T1047 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3836827495 Jul 22 05:42:21 PM PDT 24 Jul 22 05:42:23 PM PDT 24 264649284 ps
T114 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2774798275 Jul 22 05:41:21 PM PDT 24 Jul 22 05:41:26 PM PDT 24 137847078 ps
T1048 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2151389613 Jul 22 05:41:02 PM PDT 24 Jul 22 05:41:11 PM PDT 24 1524342360 ps
T154 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3506244519 Jul 22 05:41:38 PM PDT 24 Jul 22 05:41:42 PM PDT 24 125320847 ps
T166 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2818357796 Jul 22 05:41:18 PM PDT 24 Jul 22 05:41:34 PM PDT 24 3640054288 ps
T116 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3647042487 Jul 22 05:41:11 PM PDT 24 Jul 22 05:41:15 PM PDT 24 239800279 ps
T115 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.803218919 Jul 22 05:41:20 PM PDT 24 Jul 22 05:41:25 PM PDT 24 271444766 ps
T1049 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3506742216 Jul 22 05:41:23 PM PDT 24 Jul 22 05:41:24 PM PDT 24 16362511 ps
T1050 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1908281591 Jul 22 05:41:20 PM PDT 24 Jul 22 05:41:23 PM PDT 24 57571195 ps
T1051 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.117302979 Jul 22 05:41:02 PM PDT 24 Jul 22 05:41:05 PM PDT 24 67821581 ps
T1052 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.364448280 Jul 22 05:41:12 PM PDT 24 Jul 22 05:41:22 PM PDT 24 1303674190 ps
T1053 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1968870049 Jul 22 05:41:45 PM PDT 24 Jul 22 05:41:46 PM PDT 24 139583840 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3649117688 Jul 22 05:41:03 PM PDT 24 Jul 22 05:41:05 PM PDT 24 40820459 ps
T1055 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.646546245 Jul 22 05:41:01 PM PDT 24 Jul 22 05:41:04 PM PDT 24 678106993 ps
T1056 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3360568762 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:37 PM PDT 24 117876819 ps
T1057 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3647877958 Jul 22 05:41:46 PM PDT 24 Jul 22 05:41:48 PM PDT 24 24671071 ps
T1058 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2375413579 Jul 22 05:41:23 PM PDT 24 Jul 22 05:41:26 PM PDT 24 39866754 ps
T1059 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.415460372 Jul 22 05:41:05 PM PDT 24 Jul 22 05:41:07 PM PDT 24 44033006 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1943766903 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:19 PM PDT 24 93295645 ps
T1061 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3182761239 Jul 22 05:41:20 PM PDT 24 Jul 22 05:41:23 PM PDT 24 29463090 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3309211711 Jul 22 05:41:03 PM PDT 24 Jul 22 05:41:05 PM PDT 24 39887487 ps
T1063 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.297073638 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:20 PM PDT 24 245136107 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2763946141 Jul 22 05:41:03 PM PDT 24 Jul 22 05:41:39 PM PDT 24 20111237825 ps
T1065 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3243811918 Jul 22 05:41:21 PM PDT 24 Jul 22 05:41:25 PM PDT 24 1671059621 ps
T1066 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1456826470 Jul 22 05:41:42 PM PDT 24 Jul 22 05:41:43 PM PDT 24 105217997 ps
T1067 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2661554038 Jul 22 05:41:52 PM PDT 24 Jul 22 05:41:54 PM PDT 24 11076511 ps
T1068 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.841428686 Jul 22 05:41:12 PM PDT 24 Jul 22 05:41:15 PM PDT 24 29322202 ps
T1069 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3576753527 Jul 22 05:41:01 PM PDT 24 Jul 22 05:41:07 PM PDT 24 211407882 ps
T1070 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3032718146 Jul 22 05:41:15 PM PDT 24 Jul 22 05:41:22 PM PDT 24 180767662 ps
T1071 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4013774426 Jul 22 05:41:32 PM PDT 24 Jul 22 05:41:34 PM PDT 24 15311118 ps
T1072 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1411426176 Jul 22 05:42:32 PM PDT 24 Jul 22 05:42:34 PM PDT 24 53760960 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1458066480 Jul 22 05:41:03 PM PDT 24 Jul 22 05:41:20 PM PDT 24 214547812 ps
T112 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.339862080 Jul 22 05:41:13 PM PDT 24 Jul 22 05:41:20 PM PDT 24 876946542 ps
T1074 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1841273727 Jul 22 05:41:23 PM PDT 24 Jul 22 05:41:25 PM PDT 24 14032479 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1266378346 Jul 22 05:41:04 PM PDT 24 Jul 22 05:41:06 PM PDT 24 42891153 ps
T1076 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4251231724 Jul 22 05:41:20 PM PDT 24 Jul 22 05:41:24 PM PDT 24 70745300 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1401851161 Jul 22 05:41:05 PM PDT 24 Jul 22 05:41:06 PM PDT 24 16483271 ps
T1078 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.626353760 Jul 22 05:43:02 PM PDT 24 Jul 22 05:43:04 PM PDT 24 23516297 ps
T1079 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3950926604 Jul 22 05:41:15 PM PDT 24 Jul 22 05:41:20 PM PDT 24 178474193 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.896582006 Jul 22 05:41:16 PM PDT 24 Jul 22 05:41:20 PM PDT 24 90436307 ps
T1081 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1604500057 Jul 22 05:41:04 PM PDT 24 Jul 22 05:41:07 PM PDT 24 47763283 ps
T1082 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2443870908 Jul 22 05:41:33 PM PDT 24 Jul 22 05:41:36 PM PDT 24 153430419 ps
T1083 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3264624852 Jul 22 05:41:43 PM PDT 24 Jul 22 05:41:44 PM PDT 24 11364794 ps
T169 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.159809608 Jul 22 05:41:15 PM PDT 24 Jul 22 05:41:37 PM PDT 24 301687847 ps
T1084 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3765112764 Jul 22 05:41:29 PM PDT 24 Jul 22 05:41:35 PM PDT 24 764203128 ps
T1085 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4198358660 Jul 22 05:41:11 PM PDT 24 Jul 22 05:41:14 PM PDT 24 186221280 ps
T1086 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2769922656 Jul 22 05:41:41 PM PDT 24 Jul 22 05:41:42 PM PDT 24 24058940 ps
T1087 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.276139794 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:39 PM PDT 24 1179345431 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4252975366 Jul 22 05:41:33 PM PDT 24 Jul 22 05:41:38 PM PDT 24 310805430 ps
T1089 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3456429137 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:21 PM PDT 24 206419373 ps
T1090 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3107348586 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:32 PM PDT 24 15065239 ps
T1091 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3443625601 Jul 22 05:41:22 PM PDT 24 Jul 22 05:41:37 PM PDT 24 208273259 ps
T1092 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2192132864 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:33 PM PDT 24 383020247 ps
T1093 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1722899409 Jul 22 05:41:32 PM PDT 24 Jul 22 05:41:45 PM PDT 24 596669416 ps
T1094 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1038415050 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:18 PM PDT 24 15080830 ps
T120 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3222667665 Jul 22 05:41:12 PM PDT 24 Jul 22 05:41:16 PM PDT 24 33799005 ps
T172 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1039972310 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:51 PM PDT 24 299207469 ps
T1095 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2946535431 Jul 22 05:41:40 PM PDT 24 Jul 22 05:41:42 PM PDT 24 125641983 ps
T1096 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.288076772 Jul 22 05:41:23 PM PDT 24 Jul 22 05:41:29 PM PDT 24 157529200 ps
T1097 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4058467843 Jul 22 05:41:37 PM PDT 24 Jul 22 05:41:39 PM PDT 24 55492990 ps
T1098 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.935945166 Jul 22 05:41:22 PM PDT 24 Jul 22 05:41:23 PM PDT 24 156145746 ps
T170 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1137726335 Jul 22 05:41:11 PM PDT 24 Jul 22 05:41:34 PM PDT 24 4295589417 ps
T1099 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3777448579 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:35 PM PDT 24 91746323 ps
T1100 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.156990241 Jul 22 05:41:21 PM PDT 24 Jul 22 05:41:29 PM PDT 24 1351141017 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2044770595 Jul 22 05:41:18 PM PDT 24 Jul 22 05:41:24 PM PDT 24 1026935723 ps
T171 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1861607795 Jul 22 05:41:18 PM PDT 24 Jul 22 05:41:32 PM PDT 24 192628462 ps
T1102 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.807148718 Jul 22 05:41:44 PM PDT 24 Jul 22 05:41:45 PM PDT 24 13261384 ps
T1103 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2406206377 Jul 22 05:41:12 PM PDT 24 Jul 22 05:41:17 PM PDT 24 531045402 ps
T1104 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3347602029 Jul 22 05:41:12 PM PDT 24 Jul 22 05:41:16 PM PDT 24 28490954 ps
T1105 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4266882581 Jul 22 05:41:24 PM PDT 24 Jul 22 05:41:27 PM PDT 24 49321994 ps
T1106 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.760822294 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:35 PM PDT 24 337118651 ps
T1107 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4028635425 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:19 PM PDT 24 45518041 ps
T1108 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3157984516 Jul 22 05:41:13 PM PDT 24 Jul 22 05:41:30 PM PDT 24 939700754 ps
T1109 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3174966484 Jul 22 05:41:30 PM PDT 24 Jul 22 05:41:32 PM PDT 24 44781103 ps
T1110 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.218591946 Jul 22 05:41:05 PM PDT 24 Jul 22 05:41:08 PM PDT 24 105213210 ps
T1111 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1061727744 Jul 22 05:41:01 PM PDT 24 Jul 22 05:41:16 PM PDT 24 1884827433 ps
T1112 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3319901391 Jul 22 05:41:44 PM PDT 24 Jul 22 05:41:45 PM PDT 24 45072530 ps
T1113 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1813196206 Jul 22 05:41:32 PM PDT 24 Jul 22 05:41:37 PM PDT 24 176665118 ps
T1114 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.767663550 Jul 22 05:41:29 PM PDT 24 Jul 22 05:41:31 PM PDT 24 16306844 ps
T1115 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2508280360 Jul 22 05:41:15 PM PDT 24 Jul 22 05:41:21 PM PDT 24 209006617 ps
T1116 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4101258641 Jul 22 05:44:42 PM PDT 24 Jul 22 05:44:45 PM PDT 24 232764618 ps
T1117 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3349929627 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:35 PM PDT 24 72826911 ps
T1118 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3324889276 Jul 22 05:41:04 PM PDT 24 Jul 22 05:41:06 PM PDT 24 55008357 ps
T1119 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2102885987 Jul 22 05:41:24 PM PDT 24 Jul 22 05:41:29 PM PDT 24 2197066040 ps
T1120 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2591587038 Jul 22 05:41:40 PM PDT 24 Jul 22 05:41:42 PM PDT 24 109965380 ps
T1121 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3047197251 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:33 PM PDT 24 35958930 ps
T1122 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.809410134 Jul 22 05:41:31 PM PDT 24 Jul 22 05:41:34 PM PDT 24 63568501 ps
T1123 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1016381331 Jul 22 05:41:14 PM PDT 24 Jul 22 05:41:19 PM PDT 24 72230332 ps
T1124 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4120259359 Jul 22 05:41:18 PM PDT 24 Jul 22 05:41:41 PM PDT 24 4258044969 ps
T1125 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2874595733 Jul 22 05:41:23 PM PDT 24 Jul 22 05:41:32 PM PDT 24 418011318 ps
T1126 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3648678108 Jul 22 05:41:29 PM PDT 24 Jul 22 05:41:30 PM PDT 24 51294960 ps
T1127 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1349360023 Jul 22 05:41:10 PM PDT 24 Jul 22 05:41:14 PM PDT 24 321989010 ps
T1128 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.759808923 Jul 22 05:41:19 PM PDT 24 Jul 22 05:41:24 PM PDT 24 143168090 ps
T1129 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3454885669 Jul 22 05:41:20 PM PDT 24 Jul 22 05:41:23 PM PDT 24 94753358 ps
T1130 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4294181204 Jul 22 05:44:49 PM PDT 24 Jul 22 05:44:52 PM PDT 24 103332255 ps
T1131 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.762281793 Jul 22 05:44:47 PM PDT 24 Jul 22 05:44:49 PM PDT 24 34912122 ps

Test location /workspace/coverage/default/49.spi_device_flash_all.2443199713
Short name T5
Test name
Test status
Simulation time 106180358628 ps
CPU time 108.4 seconds
Started Jul 22 05:52:55 PM PDT 24
Finished Jul 22 05:54:43 PM PDT 24
Peak memory 249288 kb
Host smart-a4d513cd-1d86-4eb5-b809-74d64f681586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443199713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2443199713
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1528892250
Short name T12
Test name
Test status
Simulation time 16253192971 ps
CPU time 177.16 seconds
Started Jul 22 05:48:40 PM PDT 24
Finished Jul 22 05:51:37 PM PDT 24
Peak memory 273728 kb
Host smart-7924cae9-09c9-4aa9-8731-e122b2e964ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528892250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1528892250
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.40977485
Short name T17
Test name
Test status
Simulation time 3363089630 ps
CPU time 82.2 seconds
Started Jul 22 05:49:43 PM PDT 24
Finished Jul 22 05:51:06 PM PDT 24
Peak memory 252852 kb
Host smart-287b7591-aaad-4aae-8624-88daeb526253
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40977485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress
_all.40977485
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.913908264
Short name T67
Test name
Test status
Simulation time 110521912 ps
CPU time 2.93 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:35 PM PDT 24
Peak memory 217088 kb
Host smart-4440930d-7609-4e8f-a1c5-43c75150d059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913908264 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.913908264
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3452877663
Short name T49
Test name
Test status
Simulation time 4794227203 ps
CPU time 25.35 seconds
Started Jul 22 05:52:49 PM PDT 24
Finished Jul 22 05:53:15 PM PDT 24
Peak memory 216372 kb
Host smart-c7a97c69-8962-4b70-ac0a-00c460a73d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452877663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3452877663
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1013799687
Short name T184
Test name
Test status
Simulation time 769790458128 ps
CPU time 462.77 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:57:26 PM PDT 24
Peak memory 255072 kb
Host smart-7ef68a19-c41e-4a55-b7ac-f070969be528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013799687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1013799687
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3478095477
Short name T69
Test name
Test status
Simulation time 22070026 ps
CPU time 0.73 seconds
Started Jul 22 05:47:26 PM PDT 24
Finished Jul 22 05:47:27 PM PDT 24
Peak memory 216156 kb
Host smart-74d89708-9ab3-4612-88a6-101e010fce4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478095477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3478095477
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2944624015
Short name T14
Test name
Test status
Simulation time 4257979855 ps
CPU time 99.22 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:51:02 PM PDT 24
Peak memory 273924 kb
Host smart-5ee3327f-655f-46db-bff1-b7d8b1186d9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944624015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2944624015
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1360107825
Short name T137
Test name
Test status
Simulation time 273089556103 ps
CPU time 651.48 seconds
Started Jul 22 05:51:29 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 270772 kb
Host smart-d607416b-80f0-43dd-b8fd-32f236a1742b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360107825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1360107825
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2432109169
Short name T30
Test name
Test status
Simulation time 21564065424 ps
CPU time 201.96 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:52:47 PM PDT 24
Peak memory 255752 kb
Host smart-d0b26fca-21cb-4ad5-b9ab-3856b3cf3f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432109169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2432109169
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3118264439
Short name T22
Test name
Test status
Simulation time 986586688 ps
CPU time 1.05 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:00 PM PDT 24
Peak memory 236468 kb
Host smart-3d862b04-8498-4484-8445-84d9de949434
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118264439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3118264439
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1733322054
Short name T306
Test name
Test status
Simulation time 3482034843 ps
CPU time 27.28 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 05:52:24 PM PDT 24
Peak memory 220288 kb
Host smart-65d5b650-e5a3-433a-8ee9-03a63c8d83f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733322054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1733322054
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2387237249
Short name T191
Test name
Test status
Simulation time 18040744255 ps
CPU time 180.21 seconds
Started Jul 22 05:49:03 PM PDT 24
Finished Jul 22 05:52:03 PM PDT 24
Peak memory 261948 kb
Host smart-e2d29075-6f52-492a-a849-505963fc2805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387237249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2387237249
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.654235981
Short name T190
Test name
Test status
Simulation time 73453367363 ps
CPU time 194.96 seconds
Started Jul 22 05:52:43 PM PDT 24
Finished Jul 22 05:55:58 PM PDT 24
Peak memory 264404 kb
Host smart-8f76486c-7a92-4e0d-95ca-9b37b777cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654235981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.654235981
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1387089014
Short name T144
Test name
Test status
Simulation time 872577558 ps
CPU time 13.4 seconds
Started Jul 22 05:48:45 PM PDT 24
Finished Jul 22 05:48:59 PM PDT 24
Peak memory 233932 kb
Host smart-1c3bebe5-2606-4729-a5cc-030646171ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387089014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1387089014
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3079303102
Short name T213
Test name
Test status
Simulation time 14674879099 ps
CPU time 130.34 seconds
Started Jul 22 05:50:59 PM PDT 24
Finished Jul 22 05:53:10 PM PDT 24
Peak memory 241356 kb
Host smart-27da3ae3-cee4-4adc-bfa6-da72fea4ab72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079303102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3079303102
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1933589820
Short name T153
Test name
Test status
Simulation time 4393366104 ps
CPU time 14.58 seconds
Started Jul 22 05:41:02 PM PDT 24
Finished Jul 22 05:41:18 PM PDT 24
Peak memory 215608 kb
Host smart-7302d2b0-d352-4d34-8351-4f49c708d6fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933589820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1933589820
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.106091783
Short name T87
Test name
Test status
Simulation time 26749477 ps
CPU time 1.46 seconds
Started Jul 22 05:41:01 PM PDT 24
Finished Jul 22 05:41:03 PM PDT 24
Peak memory 207544 kb
Host smart-0cbe7e81-0e4a-4ce1-a95f-fa7c755a61cb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106091783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_hw_reset.106091783
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3888593815
Short name T175
Test name
Test status
Simulation time 29760809528 ps
CPU time 283.28 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:53:38 PM PDT 24
Peak memory 265756 kb
Host smart-90568f31-7e8f-4260-b6b9-2d1eccee9ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888593815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3888593815
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.907383672
Short name T31
Test name
Test status
Simulation time 27115338680 ps
CPU time 111.21 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:49:57 PM PDT 24
Peak memory 253168 kb
Host smart-49782131-f68d-4810-b194-39cbbfd385ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907383672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.907383672
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.384710702
Short name T110
Test name
Test status
Simulation time 128296779 ps
CPU time 3.06 seconds
Started Jul 22 05:41:24 PM PDT 24
Finished Jul 22 05:41:28 PM PDT 24
Peak memory 215644 kb
Host smart-2f2d6445-1984-4d10-90ee-36a9ab003770
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384710702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.384710702
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2346299884
Short name T39
Test name
Test status
Simulation time 139819721613 ps
CPU time 638.45 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 256620 kb
Host smart-91c87796-d032-4f6c-9ce2-8f765b4bb2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346299884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2346299884
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3284617365
Short name T212
Test name
Test status
Simulation time 6588346167 ps
CPU time 68.57 seconds
Started Jul 22 05:47:27 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 272500 kb
Host smart-f21a5d16-a6e4-418a-b292-d90ea159115d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284617365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3284617365
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3126928612
Short name T240
Test name
Test status
Simulation time 38539505063 ps
CPU time 401.07 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:56:30 PM PDT 24
Peak memory 265336 kb
Host smart-cd14010f-9fde-49dd-a9cc-e84ba3a5464d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126928612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3126928612
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.4291010323
Short name T8
Test name
Test status
Simulation time 22897877 ps
CPU time 0.72 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:23 PM PDT 24
Peak memory 205044 kb
Host smart-9a5b759b-d5ca-4004-9f6e-cf573c57bcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291010323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
4291010323
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3616103805
Short name T93
Test name
Test status
Simulation time 41296316 ps
CPU time 0.88 seconds
Started Jul 22 05:51:55 PM PDT 24
Finished Jul 22 05:51:56 PM PDT 24
Peak memory 207096 kb
Host smart-f6fcac3e-6ab1-48b4-88a3-cd2e693117a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616103805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3616103805
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.2410625187
Short name T188
Test name
Test status
Simulation time 4295952753 ps
CPU time 83.12 seconds
Started Jul 22 05:52:08 PM PDT 24
Finished Jul 22 05:53:32 PM PDT 24
Peak memory 269064 kb
Host smart-93fb2a81-032b-4a20-862d-2e14e929c3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410625187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.2410625187
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1937127351
Short name T706
Test name
Test status
Simulation time 15076610877 ps
CPU time 119.45 seconds
Started Jul 22 05:49:01 PM PDT 24
Finished Jul 22 05:51:01 PM PDT 24
Peak memory 251896 kb
Host smart-40cf5a54-7ba1-40f2-9cfb-3edc0ba8ba29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937127351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1937127351
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3118515817
Short name T156
Test name
Test status
Simulation time 10814348458 ps
CPU time 134.55 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:49:46 PM PDT 24
Peak memory 256744 kb
Host smart-42cd5210-0462-499e-8e9e-5e6af561a4e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118515817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3118515817
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.445536709
Short name T11
Test name
Test status
Simulation time 18699911266 ps
CPU time 82.39 seconds
Started Jul 22 05:48:23 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 252564 kb
Host smart-acacaef9-3fe8-4c6d-8ff8-e7e1ced0ca43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445536709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.445536709
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1104712046
Short name T51
Test name
Test status
Simulation time 31812672207 ps
CPU time 110.97 seconds
Started Jul 22 05:49:18 PM PDT 24
Finished Jul 22 05:51:09 PM PDT 24
Peak memory 266784 kb
Host smart-65ccef48-94d1-4c62-a72c-2f73e22db689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104712046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1104712046
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2291839676
Short name T224
Test name
Test status
Simulation time 259512404417 ps
CPU time 441.36 seconds
Started Jul 22 05:51:24 PM PDT 24
Finished Jul 22 05:58:45 PM PDT 24
Peak memory 254224 kb
Host smart-42d0df1d-1340-446e-8a23-2fc58eba739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291839676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2291839676
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1137726335
Short name T170
Test name
Test status
Simulation time 4295589417 ps
CPU time 21.82 seconds
Started Jul 22 05:41:11 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 216020 kb
Host smart-b4f9757a-a19a-471a-be80-c5e629d3e6d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137726335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1137726335
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1340664394
Short name T101
Test name
Test status
Simulation time 2073589527 ps
CPU time 53.12 seconds
Started Jul 22 05:49:41 PM PDT 24
Finished Jul 22 05:50:35 PM PDT 24
Peak memory 249276 kb
Host smart-48eb1247-181d-48df-b1ec-21ae3ff95aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340664394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1340664394
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.738691186
Short name T290
Test name
Test status
Simulation time 20370840335 ps
CPU time 220.8 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:53:50 PM PDT 24
Peak memory 266768 kb
Host smart-5eb8166b-5377-4ecb-86c2-8d5f3c157190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738691186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.738691186
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2787580981
Short name T310
Test name
Test status
Simulation time 13651322107 ps
CPU time 81.5 seconds
Started Jul 22 05:52:48 PM PDT 24
Finished Jul 22 05:54:10 PM PDT 24
Peak memory 249384 kb
Host smart-ae7e4657-f258-4e92-ad2a-7f0fdd02527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787580981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2787580981
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.601634856
Short name T300
Test name
Test status
Simulation time 1246513019 ps
CPU time 9.75 seconds
Started Jul 22 05:49:11 PM PDT 24
Finished Jul 22 05:49:21 PM PDT 24
Peak memory 224676 kb
Host smart-85e25058-8a8c-405f-86a6-9bc3b15adc65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601634856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.601634856
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3088829239
Short name T187
Test name
Test status
Simulation time 92282482893 ps
CPU time 154.69 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:52:12 PM PDT 24
Peak memory 250408 kb
Host smart-48a15e93-4222-4d97-b9e4-61278a3a7e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088829239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3088829239
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.803218919
Short name T115
Test name
Test status
Simulation time 271444766 ps
CPU time 3.44 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 215580 kb
Host smart-e3e8d1e4-e61c-4bdf-9c2c-76e8e0a84238
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803218919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.803218919
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.875867304
Short name T16
Test name
Test status
Simulation time 13434232898 ps
CPU time 138.97 seconds
Started Jul 22 05:47:56 PM PDT 24
Finished Jul 22 05:50:16 PM PDT 24
Peak memory 257556 kb
Host smart-93806df3-7d3a-4fe5-afc1-10cc62bc6234
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875867304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.875867304
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3472621583
Short name T194
Test name
Test status
Simulation time 239465213087 ps
CPU time 310.81 seconds
Started Jul 22 05:47:33 PM PDT 24
Finished Jul 22 05:52:44 PM PDT 24
Peak memory 255336 kb
Host smart-b4b423ea-c194-47a6-a72b-4ebc431da268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472621583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3472621583
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1082307682
Short name T607
Test name
Test status
Simulation time 3283741438 ps
CPU time 68.33 seconds
Started Jul 22 05:48:24 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 254152 kb
Host smart-60100c73-bbb8-4b2b-a789-2ff9f4dc72ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082307682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1082307682
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3350872346
Short name T75
Test name
Test status
Simulation time 16578229919 ps
CPU time 57.43 seconds
Started Jul 22 05:49:52 PM PDT 24
Finished Jul 22 05:50:49 PM PDT 24
Peak memory 224692 kb
Host smart-1ec76c6b-83f2-4154-9d3b-c2991a16900e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350872346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3350872346
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1116597042
Short name T280
Test name
Test status
Simulation time 3822999049 ps
CPU time 89.11 seconds
Started Jul 22 05:47:33 PM PDT 24
Finished Jul 22 05:49:02 PM PDT 24
Peak memory 273124 kb
Host smart-62a66c49-e383-408a-911f-4fad167da360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116597042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1116597042
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3945758526
Short name T136
Test name
Test status
Simulation time 14286350897 ps
CPU time 97.18 seconds
Started Jul 22 05:48:23 PM PDT 24
Finished Jul 22 05:50:01 PM PDT 24
Peak memory 273544 kb
Host smart-286b4990-0579-424c-9b3f-2e8f92cf4391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945758526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3945758526
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3864220669
Short name T293
Test name
Test status
Simulation time 34095164128 ps
CPU time 136.76 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:50:53 PM PDT 24
Peak memory 273392 kb
Host smart-ab3157a9-a235-4ae5-a97d-8f2b7851ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864220669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3864220669
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.826737967
Short name T219
Test name
Test status
Simulation time 5596864982 ps
CPU time 63.48 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:49:41 PM PDT 24
Peak memory 256800 kb
Host smart-48c00612-7d5b-4497-b132-d1dbbb436559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826737967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds
.826737967
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2082094072
Short name T100
Test name
Test status
Simulation time 75249254858 ps
CPU time 191.4 seconds
Started Jul 22 05:48:55 PM PDT 24
Finished Jul 22 05:52:07 PM PDT 24
Peak memory 249960 kb
Host smart-04166640-ff56-4a2c-a1f8-cfe7c64a4529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082094072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2082094072
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3749657299
Short name T163
Test name
Test status
Simulation time 1667595197 ps
CPU time 42.39 seconds
Started Jul 22 05:49:04 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 252972 kb
Host smart-3f574213-cbeb-4d8a-8929-93d7a214fb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749657299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3749657299
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3504988084
Short name T179
Test name
Test status
Simulation time 2757113000 ps
CPU time 12.73 seconds
Started Jul 22 05:49:23 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 251856 kb
Host smart-521c6dfe-eed3-4324-8225-386f63f48445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504988084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3504988084
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.772546947
Short name T68
Test name
Test status
Simulation time 29337684 ps
CPU time 1.92 seconds
Started Jul 22 05:41:36 PM PDT 24
Finished Jul 22 05:41:38 PM PDT 24
Peak memory 215580 kb
Host smart-eb2c338d-47f2-4b3b-8d1c-5791f649f0ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772546947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.772546947
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3929986760
Short name T108
Test name
Test status
Simulation time 727713847 ps
CPU time 7.43 seconds
Started Jul 22 05:41:03 PM PDT 24
Finished Jul 22 05:41:12 PM PDT 24
Peak memory 215876 kb
Host smart-0452f2c9-90a1-46e5-abb3-d89873467ef8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929986760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3929986760
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1458066480
Short name T1073
Test name
Test status
Simulation time 214547812 ps
CPU time 14.94 seconds
Started Jul 22 05:41:03 PM PDT 24
Finished Jul 22 05:41:20 PM PDT 24
Peak memory 207156 kb
Host smart-c08a0f6f-f499-4165-a195-5f940872ed59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458066480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1458066480
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2763946141
Short name T1064
Test name
Test status
Simulation time 20111237825 ps
CPU time 35.26 seconds
Started Jul 22 05:41:03 PM PDT 24
Finished Jul 22 05:41:39 PM PDT 24
Peak memory 215568 kb
Host smart-02f0c7fc-00dc-4438-bfe2-b2d731656488
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763946141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2763946141
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3649117688
Short name T1054
Test name
Test status
Simulation time 40820459 ps
CPU time 0.95 seconds
Started Jul 22 05:41:03 PM PDT 24
Finished Jul 22 05:41:05 PM PDT 24
Peak memory 207136 kb
Host smart-adb09746-c465-4246-bb0d-86c64e067eea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649117688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.3649117688
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2653548573
Short name T123
Test name
Test status
Simulation time 355202211 ps
CPU time 2.75 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:09 PM PDT 24
Peak memory 217440 kb
Host smart-2629f04f-778c-48f7-b927-f9da4ab751ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653548573 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2653548573
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1604500057
Short name T1081
Test name
Test status
Simulation time 47763283 ps
CPU time 1.37 seconds
Started Jul 22 05:41:04 PM PDT 24
Finished Jul 22 05:41:07 PM PDT 24
Peak memory 207288 kb
Host smart-0732f947-8749-42b3-a2c4-87eebb5db71e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604500057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
604500057
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.287724704
Short name T1014
Test name
Test status
Simulation time 32736731 ps
CPU time 0.73 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:07 PM PDT 24
Peak memory 204316 kb
Host smart-eda4e90b-b8b2-4ca8-9ba5-938aaa547e52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287724704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.287724704
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1030983441
Short name T128
Test name
Test status
Simulation time 356293737 ps
CPU time 1.89 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:08 PM PDT 24
Peak memory 215496 kb
Host smart-f2b7f23c-996b-4899-82f1-8273e314df15
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030983441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1030983441
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1401851161
Short name T1077
Test name
Test status
Simulation time 16483271 ps
CPU time 0.72 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:06 PM PDT 24
Peak memory 204256 kb
Host smart-6b96e693-f864-4c07-abbc-c1de62fbc8dc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401851161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1401851161
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3576753527
Short name T1069
Test name
Test status
Simulation time 211407882 ps
CPU time 4.55 seconds
Started Jul 22 05:41:01 PM PDT 24
Finished Jul 22 05:41:07 PM PDT 24
Peak memory 215736 kb
Host smart-4a0d2d5b-b676-4b0d-87a2-e6daeb14e9d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576753527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.3576753527
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.218591946
Short name T1110
Test name
Test status
Simulation time 105213210 ps
CPU time 1.93 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:08 PM PDT 24
Peak memory 216544 kb
Host smart-d964e84d-9073-4787-8c8d-03c0fc34ece1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218591946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.218591946
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1988260223
Short name T130
Test name
Test status
Simulation time 1601227808 ps
CPU time 14.19 seconds
Started Jul 22 05:41:01 PM PDT 24
Finished Jul 22 05:41:17 PM PDT 24
Peak memory 207224 kb
Host smart-65e07982-1757-4001-aa6c-c6b848f8cd85
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988260223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1988260223
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3141331078
Short name T131
Test name
Test status
Simulation time 590643842 ps
CPU time 24.28 seconds
Started Jul 22 05:41:04 PM PDT 24
Finished Jul 22 05:41:29 PM PDT 24
Peak memory 207212 kb
Host smart-4ecced26-8192-466a-92af-834fcb01399b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141331078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3141331078
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1688049858
Short name T88
Test name
Test status
Simulation time 44749886 ps
CPU time 1.43 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:40 PM PDT 24
Peak memory 215448 kb
Host smart-5c03d02d-f7eb-4ff6-aefe-a149c179b9a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688049858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1688049858
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2535385133
Short name T121
Test name
Test status
Simulation time 169568986 ps
CPU time 4.06 seconds
Started Jul 22 05:41:02 PM PDT 24
Finished Jul 22 05:41:07 PM PDT 24
Peak memory 218324 kb
Host smart-e1c4406d-1b0e-4ed0-9efd-e650ef3a2833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535385133 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2535385133
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1266378346
Short name T1075
Test name
Test status
Simulation time 42891153 ps
CPU time 1.27 seconds
Started Jul 22 05:41:04 PM PDT 24
Finished Jul 22 05:41:06 PM PDT 24
Peak memory 215496 kb
Host smart-ccdb74f5-2bed-4a35-b85f-b9ea255a49bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266378346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
266378346
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.415460372
Short name T1059
Test name
Test status
Simulation time 44033006 ps
CPU time 0.8 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:07 PM PDT 24
Peak memory 204196 kb
Host smart-0c1c06d6-eaf3-460f-ae7a-3db9ac22e0c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415460372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.415460372
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.4071056133
Short name T1045
Test name
Test status
Simulation time 224305652 ps
CPU time 2.31 seconds
Started Jul 22 05:41:02 PM PDT 24
Finished Jul 22 05:41:06 PM PDT 24
Peak memory 215400 kb
Host smart-8d784cbb-1e5d-4337-8db1-fb661124faf4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071056133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.4071056133
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3309211711
Short name T1062
Test name
Test status
Simulation time 39887487 ps
CPU time 0.71 seconds
Started Jul 22 05:41:03 PM PDT 24
Finished Jul 22 05:41:05 PM PDT 24
Peak memory 203864 kb
Host smart-1bef4286-1a53-42a0-8412-006573736ea6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309211711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3309211711
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1349360023
Short name T1127
Test name
Test status
Simulation time 321989010 ps
CPU time 4.01 seconds
Started Jul 22 05:41:10 PM PDT 24
Finished Jul 22 05:41:14 PM PDT 24
Peak memory 215460 kb
Host smart-3ed35cce-6a11-4552-a5af-c5c4dc8f7688
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349360023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1349360023
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3389066510
Short name T107
Test name
Test status
Simulation time 281019777 ps
CPU time 3.3 seconds
Started Jul 22 05:41:10 PM PDT 24
Finished Jul 22 05:41:13 PM PDT 24
Peak memory 216604 kb
Host smart-b7767b16-6fde-4789-8e87-1dd4325a4e33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389066510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
389066510
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1309766253
Short name T168
Test name
Test status
Simulation time 402866007 ps
CPU time 7.36 seconds
Started Jul 22 05:41:02 PM PDT 24
Finished Jul 22 05:41:11 PM PDT 24
Peak memory 215604 kb
Host smart-466322b1-6e66-4290-bee9-db31184d8231
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309766253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1309766253
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.4294181204
Short name T1130
Test name
Test status
Simulation time 103332255 ps
CPU time 1.75 seconds
Started Jul 22 05:44:49 PM PDT 24
Finished Jul 22 05:44:52 PM PDT 24
Peak memory 216652 kb
Host smart-17f4783a-4359-4a92-9c35-80e7d909e78a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294181204 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.4294181204
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1691947766
Short name T134
Test name
Test status
Simulation time 385805263 ps
CPU time 1.61 seconds
Started Jul 22 05:44:41 PM PDT 24
Finished Jul 22 05:44:43 PM PDT 24
Peak memory 207224 kb
Host smart-d107c13e-553b-4128-81e6-53b62adadb9e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691947766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1691947766
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.930433959
Short name T1035
Test name
Test status
Simulation time 54865844 ps
CPU time 0.78 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:33 PM PDT 24
Peak memory 203936 kb
Host smart-a2b2af23-259a-4ce5-91db-4a12f9681f6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930433959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.930433959
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4251231724
Short name T1076
Test name
Test status
Simulation time 70745300 ps
CPU time 1.84 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 207064 kb
Host smart-4a9ed8d3-491b-4150-89a9-22ce34237bfe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251231724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4251231724
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.288076772
Short name T1096
Test name
Test status
Simulation time 157529200 ps
CPU time 4.21 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:29 PM PDT 24
Peak memory 215640 kb
Host smart-1d16e883-e2e1-4bc2-8c94-c98c5db87c06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288076772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.288076772
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.156990241
Short name T1100
Test name
Test status
Simulation time 1351141017 ps
CPU time 7.02 seconds
Started Jul 22 05:41:21 PM PDT 24
Finished Jul 22 05:41:29 PM PDT 24
Peak memory 215580 kb
Host smart-0f2ddf2e-a08a-4575-a631-b3cdf21de7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156990241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.156990241
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1908281591
Short name T1050
Test name
Test status
Simulation time 57571195 ps
CPU time 1.71 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 216544 kb
Host smart-4e585191-d1cb-4a93-b903-c0b50ab76a07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908281591 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1908281591
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.762281793
Short name T1131
Test name
Test status
Simulation time 34912122 ps
CPU time 1.17 seconds
Started Jul 22 05:44:47 PM PDT 24
Finished Jul 22 05:44:49 PM PDT 24
Peak memory 215548 kb
Host smart-b9ae1277-094e-4168-9976-4f9eaf3d9d17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762281793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.762281793
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2424806994
Short name T1038
Test name
Test status
Simulation time 27910389 ps
CPU time 0.72 seconds
Started Jul 22 05:44:47 PM PDT 24
Finished Jul 22 05:44:48 PM PDT 24
Peak memory 204000 kb
Host smart-16f4610f-547c-4f3c-a45b-ebc865dc15ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424806994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2424806994
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3243811918
Short name T1065
Test name
Test status
Simulation time 1671059621 ps
CPU time 3.1 seconds
Started Jul 22 05:41:21 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 215448 kb
Host smart-2907db81-f546-4ffc-815c-1809a1c014e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243811918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3243811918
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3325468513
Short name T111
Test name
Test status
Simulation time 95032943 ps
CPU time 2.84 seconds
Started Jul 22 05:44:38 PM PDT 24
Finished Jul 22 05:44:41 PM PDT 24
Peak memory 215488 kb
Host smart-df4f6a64-94fa-4832-9aca-6d8e13510410
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325468513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3325468513
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3398001210
Short name T167
Test name
Test status
Simulation time 971618063 ps
CPU time 6.31 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:50 PM PDT 24
Peak memory 215544 kb
Host smart-0b6c95cd-c940-45c0-a475-c367e30e0560
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398001210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3398001210
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2824850958
Short name T119
Test name
Test status
Simulation time 127708133 ps
CPU time 1.8 seconds
Started Jul 22 05:41:22 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 215552 kb
Host smart-2c12424d-25c9-4d55-849b-cea4f91be549
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824850958 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2824850958
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2571924237
Short name T124
Test name
Test status
Simulation time 37006834 ps
CPU time 1.27 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 215476 kb
Host smart-dd09bf4e-0ece-4cc5-b6da-a7840ddf2355
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571924237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2571924237
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1841273727
Short name T1074
Test name
Test status
Simulation time 14032479 ps
CPU time 0.71 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 203884 kb
Host smart-d1d8c3a5-5e48-47ca-b6c8-3d077abd455f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841273727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1841273727
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4101258641
Short name T1116
Test name
Test status
Simulation time 232764618 ps
CPU time 1.6 seconds
Started Jul 22 05:44:42 PM PDT 24
Finished Jul 22 05:44:45 PM PDT 24
Peak memory 215560 kb
Host smart-c37910bf-b55a-4ee0-a1f1-f0381449246c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101258641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4101258641
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.4272188594
Short name T106
Test name
Test status
Simulation time 381914438 ps
CPU time 8.09 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:32 PM PDT 24
Peak memory 215460 kb
Host smart-2f8feb94-53d6-4fd8-9a1d-395f44db3df0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272188594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.4272188594
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3182761239
Short name T1061
Test name
Test status
Simulation time 29463090 ps
CPU time 1.88 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 216560 kb
Host smart-134ebe64-93cd-46d5-b41c-f2cb6dd66e91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182761239 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3182761239
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2375413579
Short name T1058
Test name
Test status
Simulation time 39866754 ps
CPU time 1.34 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:26 PM PDT 24
Peak memory 219880 kb
Host smart-b0cb56ba-59bb-4587-985b-bd9a0e80977e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375413579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2375413579
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.1521422663
Short name T1011
Test name
Test status
Simulation time 25844540 ps
CPU time 0.8 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 203976 kb
Host smart-3c53b04f-b24c-4b14-8937-e2e9e0dcf16b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521422663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
1521422663
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.759808923
Short name T1128
Test name
Test status
Simulation time 143168090 ps
CPU time 2.89 seconds
Started Jul 22 05:41:19 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 215452 kb
Host smart-35749a0f-44d3-4726-a124-94f3756e3298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759808923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.759808923
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3454885669
Short name T1129
Test name
Test status
Simulation time 94753358 ps
CPU time 1.83 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 215612 kb
Host smart-a956b8c8-4a1d-4768-a64f-5c762bc548df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454885669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3454885669
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1861607795
Short name T171
Test name
Test status
Simulation time 192628462 ps
CPU time 12.38 seconds
Started Jul 22 05:41:18 PM PDT 24
Finished Jul 22 05:41:32 PM PDT 24
Peak memory 216652 kb
Host smart-d9989286-d34a-40e7-be56-f6eba2162a65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861607795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1861607795
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2102885987
Short name T1119
Test name
Test status
Simulation time 2197066040 ps
CPU time 3.89 seconds
Started Jul 22 05:41:24 PM PDT 24
Finished Jul 22 05:41:29 PM PDT 24
Peak memory 218312 kb
Host smart-0a1d9fe7-ac3f-4956-89ec-edb61c171b9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102885987 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2102885987
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.2623566990
Short name T132
Test name
Test status
Simulation time 142714906 ps
CPU time 1.23 seconds
Started Jul 22 05:41:18 PM PDT 24
Finished Jul 22 05:41:21 PM PDT 24
Peak memory 207268 kb
Host smart-824f6c60-27ef-45d3-b017-890670622690
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623566990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
2623566990
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3506742216
Short name T1049
Test name
Test status
Simulation time 16362511 ps
CPU time 0.76 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 204292 kb
Host smart-83894ba7-6e0b-4070-9807-3773f4862166
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506742216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3506742216
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4266882581
Short name T1105
Test name
Test status
Simulation time 49321994 ps
CPU time 1.71 seconds
Started Jul 22 05:41:24 PM PDT 24
Finished Jul 22 05:41:27 PM PDT 24
Peak memory 215452 kb
Host smart-721d5734-c87f-42d9-b366-703158540996
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266882581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.4266882581
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2874595733
Short name T1125
Test name
Test status
Simulation time 418011318 ps
CPU time 6.69 seconds
Started Jul 22 05:41:23 PM PDT 24
Finished Jul 22 05:41:32 PM PDT 24
Peak memory 215512 kb
Host smart-94218abb-369f-41b1-9135-bef47c4f3abe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874595733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2874595733
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.421205683
Short name T66
Test name
Test status
Simulation time 154670475 ps
CPU time 2.84 seconds
Started Jul 22 05:41:38 PM PDT 24
Finished Jul 22 05:41:41 PM PDT 24
Peak memory 217340 kb
Host smart-b730f938-2aaf-4ef2-936f-3966cd245fbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421205683 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.421205683
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.3349929627
Short name T1117
Test name
Test status
Simulation time 72826911 ps
CPU time 2.53 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:35 PM PDT 24
Peak memory 207292 kb
Host smart-40ff964d-ab95-440e-8f78-b2763d33d08a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349929627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
3349929627
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.611799410
Short name T1008
Test name
Test status
Simulation time 19220017 ps
CPU time 0.77 seconds
Started Jul 22 05:41:37 PM PDT 24
Finished Jul 22 05:41:38 PM PDT 24
Peak memory 203952 kb
Host smart-40413422-8a8e-4003-8d35-249214d65d0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611799410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.611799410
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2192132864
Short name T1092
Test name
Test status
Simulation time 383020247 ps
CPU time 1.87 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:33 PM PDT 24
Peak memory 215452 kb
Host smart-88dc7f38-f897-43d0-8f97-a340aa997028
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192132864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2192132864
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.62184513
Short name T150
Test name
Test status
Simulation time 675254682 ps
CPU time 8.15 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:40 PM PDT 24
Peak memory 215604 kb
Host smart-c914bb77-9307-4f9c-8a3d-061732a9c97b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62184513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_
tl_intg_err.62184513
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2443870908
Short name T1082
Test name
Test status
Simulation time 153430419 ps
CPU time 2.5 seconds
Started Jul 22 05:41:33 PM PDT 24
Finished Jul 22 05:41:36 PM PDT 24
Peak memory 216600 kb
Host smart-a16c0d0a-278c-4c95-b424-46b8efb900c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443870908 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2443870908
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.445271848
Short name T133
Test name
Test status
Simulation time 301503380 ps
CPU time 2.06 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 207208 kb
Host smart-e92fcb3b-364b-4add-8e22-b887a593d77f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445271848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.445271848
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3648678108
Short name T1126
Test name
Test status
Simulation time 51294960 ps
CPU time 0.71 seconds
Started Jul 22 05:41:29 PM PDT 24
Finished Jul 22 05:41:30 PM PDT 24
Peak memory 203944 kb
Host smart-4d70f96c-77d4-40c6-89f4-d55e4f9718cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648678108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3648678108
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3506244519
Short name T154
Test name
Test status
Simulation time 125320847 ps
CPU time 2.86 seconds
Started Jul 22 05:41:38 PM PDT 24
Finished Jul 22 05:41:42 PM PDT 24
Peak memory 215452 kb
Host smart-95a8917b-a07d-4de1-b32d-7192373f6b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506244519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3506244519
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3125494398
Short name T117
Test name
Test status
Simulation time 145724472 ps
CPU time 2.15 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 215528 kb
Host smart-27beb564-baba-4a03-aaa5-70d608b920ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125494398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3125494398
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3659685036
Short name T165
Test name
Test status
Simulation time 1721602668 ps
CPU time 22.51 seconds
Started Jul 22 05:41:32 PM PDT 24
Finished Jul 22 05:41:56 PM PDT 24
Peak memory 215696 kb
Host smart-65ca8313-a292-419a-a5e4-e526a2c100fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659685036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3659685036
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3360568762
Short name T1056
Test name
Test status
Simulation time 117876819 ps
CPU time 4.3 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:37 PM PDT 24
Peak memory 218064 kb
Host smart-c771928f-c5c0-4c62-b6ed-5e926c71c6ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360568762 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3360568762
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3047197251
Short name T1121
Test name
Test status
Simulation time 35958930 ps
CPU time 1.37 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:33 PM PDT 24
Peak memory 215412 kb
Host smart-20c3ff28-8fc8-45fe-977b-68283c85866c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047197251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3047197251
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.934526430
Short name T1032
Test name
Test status
Simulation time 14987048 ps
CPU time 0.67 seconds
Started Jul 22 05:41:28 PM PDT 24
Finished Jul 22 05:41:29 PM PDT 24
Peak memory 203880 kb
Host smart-9e04845f-0d30-47a4-9d5c-83b12ecdb7cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934526430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.934526430
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3765112764
Short name T1084
Test name
Test status
Simulation time 764203128 ps
CPU time 4.59 seconds
Started Jul 22 05:41:29 PM PDT 24
Finished Jul 22 05:41:35 PM PDT 24
Peak memory 215456 kb
Host smart-34704ccc-c51f-4a3f-ba2a-02d96fd7b765
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765112764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3765112764
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.349843127
Short name T109
Test name
Test status
Simulation time 323251546 ps
CPU time 2.51 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:35 PM PDT 24
Peak memory 215796 kb
Host smart-9152d350-a906-4573-acc8-f74a3af9ca86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349843127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.349843127
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1039972310
Short name T172
Test name
Test status
Simulation time 299207469 ps
CPU time 19.18 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:51 PM PDT 24
Peak memory 215472 kb
Host smart-0ec854ab-0cd7-4a24-91b8-5cf3d28d7664
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039972310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1039972310
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.135159309
Short name T1019
Test name
Test status
Simulation time 37141353 ps
CPU time 1.3 seconds
Started Jul 22 05:41:29 PM PDT 24
Finished Jul 22 05:41:31 PM PDT 24
Peak memory 207228 kb
Host smart-ebc37c3c-8f5a-45b6-b9a5-0790e3900188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135159309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.135159309
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2026454186
Short name T1036
Test name
Test status
Simulation time 33148059 ps
CPU time 0.75 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:31 PM PDT 24
Peak memory 204016 kb
Host smart-a288a786-7f1f-462f-b4d8-eb742f3a1b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026454186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2026454186
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.809410134
Short name T1122
Test name
Test status
Simulation time 63568501 ps
CPU time 1.86 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 215496 kb
Host smart-3e042768-e3ad-487d-9fae-343066b601c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809410134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.809410134
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1813196206
Short name T1113
Test name
Test status
Simulation time 176665118 ps
CPU time 4.39 seconds
Started Jul 22 05:41:32 PM PDT 24
Finished Jul 22 05:41:37 PM PDT 24
Peak memory 215572 kb
Host smart-61fd40a6-b4f9-4ffe-8ac3-0384c3f96b17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813196206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1813196206
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.276139794
Short name T1087
Test name
Test status
Simulation time 1179345431 ps
CPU time 8.19 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:39 PM PDT 24
Peak memory 215540 kb
Host smart-07622aa5-82c3-4854-ac4d-dbf0efa396ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276139794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.276139794
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3777448579
Short name T1099
Test name
Test status
Simulation time 91746323 ps
CPU time 2.66 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:35 PM PDT 24
Peak memory 217480 kb
Host smart-2374b8da-5df6-495c-91df-23f635c4f7ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777448579 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3777448579
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4058467843
Short name T1097
Test name
Test status
Simulation time 55492990 ps
CPU time 1.74 seconds
Started Jul 22 05:41:37 PM PDT 24
Finished Jul 22 05:41:39 PM PDT 24
Peak memory 215444 kb
Host smart-89dc09f5-3bdb-4f76-ae62-cf59511651cf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058467843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4058467843
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.438196597
Short name T1037
Test name
Test status
Simulation time 24556460 ps
CPU time 0.73 seconds
Started Jul 22 05:41:37 PM PDT 24
Finished Jul 22 05:41:39 PM PDT 24
Peak memory 204268 kb
Host smart-c59b3e78-c945-4e46-b519-0cbffcba8b12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438196597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.438196597
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4252975366
Short name T1088
Test name
Test status
Simulation time 310805430 ps
CPU time 4.17 seconds
Started Jul 22 05:41:33 PM PDT 24
Finished Jul 22 05:41:38 PM PDT 24
Peak memory 215472 kb
Host smart-dcc7d11c-a5c7-4820-959c-050e53a23727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252975366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4252975366
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.760822294
Short name T1106
Test name
Test status
Simulation time 337118651 ps
CPU time 4.13 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:35 PM PDT 24
Peak memory 215612 kb
Host smart-19f9ee37-bb22-4bf1-ae8e-8cc179368b91
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760822294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.760822294
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1722899409
Short name T1093
Test name
Test status
Simulation time 596669416 ps
CPU time 12.08 seconds
Started Jul 22 05:41:32 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 215532 kb
Host smart-dd5a30cd-15b1-47a4-92d1-dfa6ea646d68
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722899409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1722899409
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2151389613
Short name T1048
Test name
Test status
Simulation time 1524342360 ps
CPU time 8.15 seconds
Started Jul 22 05:41:02 PM PDT 24
Finished Jul 22 05:41:11 PM PDT 24
Peak memory 207188 kb
Host smart-0dd220f2-5f7e-49c7-86a3-1d3381f9f8f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151389613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2151389613
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1061727744
Short name T1111
Test name
Test status
Simulation time 1884827433 ps
CPU time 15.01 seconds
Started Jul 22 05:41:01 PM PDT 24
Finished Jul 22 05:41:16 PM PDT 24
Peak memory 207212 kb
Host smart-e6b68759-9fa3-4745-9e68-11b5c9aac661
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061727744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1061727744
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3836827495
Short name T1047
Test name
Test status
Simulation time 264649284 ps
CPU time 1.63 seconds
Started Jul 22 05:42:21 PM PDT 24
Finished Jul 22 05:42:23 PM PDT 24
Peak memory 215740 kb
Host smart-07c82e24-1ca0-4362-8d3b-e663c92844b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836827495 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3836827495
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.646546245
Short name T1055
Test name
Test status
Simulation time 678106993 ps
CPU time 1.44 seconds
Started Jul 22 05:41:01 PM PDT 24
Finished Jul 22 05:41:04 PM PDT 24
Peak memory 207284 kb
Host smart-b4535491-5aa6-46db-bb5f-1a3ad5741d3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646546245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.646546245
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1368719615
Short name T1031
Test name
Test status
Simulation time 37711153 ps
CPU time 0.69 seconds
Started Jul 22 05:41:03 PM PDT 24
Finished Jul 22 05:41:05 PM PDT 24
Peak memory 203988 kb
Host smart-2376ea01-4778-45cc-a3e1-ada11f6022b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368719615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
368719615
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1467335062
Short name T127
Test name
Test status
Simulation time 20167250 ps
CPU time 1.3 seconds
Started Jul 22 05:41:05 PM PDT 24
Finished Jul 22 05:41:07 PM PDT 24
Peak memory 215432 kb
Host smart-7e2490a9-343f-4049-b6fb-7a40b660e5d1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467335062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1467335062
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3324889276
Short name T1118
Test name
Test status
Simulation time 55008357 ps
CPU time 0.64 seconds
Started Jul 22 05:41:04 PM PDT 24
Finished Jul 22 05:41:06 PM PDT 24
Peak memory 203804 kb
Host smart-18a95d98-ef98-403d-8d42-9c29a50b4f52
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324889276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3324889276
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.896582006
Short name T1080
Test name
Test status
Simulation time 90436307 ps
CPU time 1.76 seconds
Started Jul 22 05:41:16 PM PDT 24
Finished Jul 22 05:41:20 PM PDT 24
Peak memory 215564 kb
Host smart-14c078ff-35e4-4b62-867a-15d05e3c432c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896582006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.896582006
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.117302979
Short name T1051
Test name
Test status
Simulation time 67821581 ps
CPU time 2.11 seconds
Started Jul 22 05:41:02 PM PDT 24
Finished Jul 22 05:41:05 PM PDT 24
Peak memory 215552 kb
Host smart-33d8cf1f-9a17-417b-bcca-21b2f1e02892
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117302979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.117302979
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.2166619540
Short name T1009
Test name
Test status
Simulation time 38606525 ps
CPU time 0.74 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:31 PM PDT 24
Peak memory 203956 kb
Host smart-3ef8d3b8-500e-44ad-96e4-5e90f579b4be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166619540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
2166619540
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3174966484
Short name T1109
Test name
Test status
Simulation time 44781103 ps
CPU time 0.68 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:32 PM PDT 24
Peak memory 204288 kb
Host smart-69ebf672-923f-49b8-b346-340d691002a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174966484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3174966484
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3107348586
Short name T1090
Test name
Test status
Simulation time 15065239 ps
CPU time 0.71 seconds
Started Jul 22 05:41:30 PM PDT 24
Finished Jul 22 05:41:32 PM PDT 24
Peak memory 203984 kb
Host smart-f0a33dde-f58b-4f72-bb45-37f6b061ac74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107348586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3107348586
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2453287382
Short name T1040
Test name
Test status
Simulation time 69290289 ps
CPU time 0.71 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:33 PM PDT 24
Peak memory 203988 kb
Host smart-5a346d01-0b48-45c4-af56-e5dd5d950904
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453287382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2453287382
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.767663550
Short name T1114
Test name
Test status
Simulation time 16306844 ps
CPU time 0.76 seconds
Started Jul 22 05:41:29 PM PDT 24
Finished Jul 22 05:41:31 PM PDT 24
Peak memory 204200 kb
Host smart-0600d634-164c-4eb3-9f15-4c5d4b198dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767663550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.767663550
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4013774426
Short name T1071
Test name
Test status
Simulation time 15311118 ps
CPU time 0.76 seconds
Started Jul 22 05:41:32 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 204268 kb
Host smart-49b345ea-de90-4cfb-bc4a-9bbcefa763e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013774426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4013774426
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.854173868
Short name T1042
Test name
Test status
Simulation time 61276817 ps
CPU time 0.75 seconds
Started Jul 22 05:41:32 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 203968 kb
Host smart-b8333623-403c-48e6-8b52-e032793b01e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854173868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.854173868
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.252308161
Short name T1034
Test name
Test status
Simulation time 13850165 ps
CPU time 0.78 seconds
Started Jul 22 05:41:29 PM PDT 24
Finished Jul 22 05:41:30 PM PDT 24
Peak memory 203912 kb
Host smart-82233d79-6437-4beb-af32-d46b33ccc00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252308161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.252308161
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.3475157428
Short name T1026
Test name
Test status
Simulation time 14469001 ps
CPU time 0.74 seconds
Started Jul 22 05:41:31 PM PDT 24
Finished Jul 22 05:41:33 PM PDT 24
Peak memory 203924 kb
Host smart-6d25c6f9-4154-4c53-aa1b-d5b5929d37a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475157428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
3475157428
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1771456401
Short name T1018
Test name
Test status
Simulation time 15459391 ps
CPU time 0.74 seconds
Started Jul 22 05:41:29 PM PDT 24
Finished Jul 22 05:41:31 PM PDT 24
Peak memory 204300 kb
Host smart-4fa62cf6-7f35-43c9-a44b-dc9468e02269
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771456401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1771456401
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3509055234
Short name T129
Test name
Test status
Simulation time 1851923164 ps
CPU time 23.22 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:41 PM PDT 24
Peak memory 207072 kb
Host smart-a30ecb00-bd10-447b-860b-61a3a9b236ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509055234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3509055234
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3157984516
Short name T1108
Test name
Test status
Simulation time 939700754 ps
CPU time 13.96 seconds
Started Jul 22 05:41:13 PM PDT 24
Finished Jul 22 05:41:30 PM PDT 24
Peak memory 215388 kb
Host smart-e20cfa6a-f8a2-49a6-be8a-bcb5a71620d1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157984516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3157984516
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2525009861
Short name T89
Test name
Test status
Simulation time 138527624 ps
CPU time 1.2 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 207272 kb
Host smart-84a3bda0-8c00-4bde-9cb8-1660b8a21b07
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525009861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2525009861
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2565897340
Short name T152
Test name
Test status
Simulation time 153602753 ps
CPU time 3.54 seconds
Started Jul 22 05:41:17 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 217620 kb
Host smart-0ac67d3a-5ab7-43a4-bf6b-ec9273704cc2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565897340 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2565897340
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1387255746
Short name T126
Test name
Test status
Simulation time 213056313 ps
CPU time 1.8 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 215536 kb
Host smart-f8e9c979-1ab0-4675-bb4c-d60e26669866
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387255746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
387255746
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3532308720
Short name T1021
Test name
Test status
Simulation time 137698992 ps
CPU time 0.78 seconds
Started Jul 22 05:41:13 PM PDT 24
Finished Jul 22 05:41:17 PM PDT 24
Peak memory 203984 kb
Host smart-0d4a6d80-4f54-460c-8f95-3abe9b7915bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532308720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
532308720
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1943766903
Short name T1060
Test name
Test status
Simulation time 93295645 ps
CPU time 2.09 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 215464 kb
Host smart-ec2362e1-6bd3-4546-bc16-0123317cbc95
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943766903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1943766903
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3610228738
Short name T1043
Test name
Test status
Simulation time 12207859 ps
CPU time 0.68 seconds
Started Jul 22 05:41:13 PM PDT 24
Finished Jul 22 05:41:16 PM PDT 24
Peak memory 203908 kb
Host smart-87d0c691-6d3f-49f5-a113-f15d3ee40266
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610228738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3610228738
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3137070899
Short name T1013
Test name
Test status
Simulation time 479407643 ps
CPU time 1.81 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 207176 kb
Host smart-194f580e-8488-4a45-963a-c08960f4545e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137070899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.3137070899
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3647042487
Short name T116
Test name
Test status
Simulation time 239800279 ps
CPU time 3.06 seconds
Started Jul 22 05:41:11 PM PDT 24
Finished Jul 22 05:41:15 PM PDT 24
Peak memory 215676 kb
Host smart-434c46c1-4976-48d3-a6ef-b5c49a566523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647042487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
647042487
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.4120259359
Short name T1124
Test name
Test status
Simulation time 4258044969 ps
CPU time 21.72 seconds
Started Jul 22 05:41:18 PM PDT 24
Finished Jul 22 05:41:41 PM PDT 24
Peak memory 215768 kb
Host smart-ad4f4026-b097-4556-a46d-af723b90c613
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120259359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.4120259359
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.808954268
Short name T1027
Test name
Test status
Simulation time 40326648 ps
CPU time 0.76 seconds
Started Jul 22 05:41:32 PM PDT 24
Finished Jul 22 05:41:33 PM PDT 24
Peak memory 204316 kb
Host smart-65492ff4-af60-4920-9309-dafccc119341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808954268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.808954268
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.1411426176
Short name T1072
Test name
Test status
Simulation time 53760960 ps
CPU time 0.75 seconds
Started Jul 22 05:42:32 PM PDT 24
Finished Jul 22 05:42:34 PM PDT 24
Peak memory 204344 kb
Host smart-3b6e786b-7265-4522-97ff-f44322831feb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411426176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
1411426176
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.626353760
Short name T1078
Test name
Test status
Simulation time 23516297 ps
CPU time 0.69 seconds
Started Jul 22 05:43:02 PM PDT 24
Finished Jul 22 05:43:04 PM PDT 24
Peak memory 203884 kb
Host smart-46d29e89-696d-489d-a488-2f345c06570e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626353760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.626353760
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.296024808
Short name T1012
Test name
Test status
Simulation time 39306797 ps
CPU time 0.71 seconds
Started Jul 22 05:41:43 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 203976 kb
Host smart-5e4c4f14-45fb-4003-959c-d767a5882d83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296024808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.296024808
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3472501721
Short name T1033
Test name
Test status
Simulation time 15932005 ps
CPU time 0.77 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 203952 kb
Host smart-9c81d32c-ebf3-4145-9fe3-9d6fdf782dca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472501721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3472501721
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.2591587038
Short name T1120
Test name
Test status
Simulation time 109965380 ps
CPU time 0.72 seconds
Started Jul 22 05:41:40 PM PDT 24
Finished Jul 22 05:41:42 PM PDT 24
Peak memory 204300 kb
Host smart-223273b6-5c29-463b-9201-9244bb077ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591587038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
2591587038
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2946535431
Short name T1095
Test name
Test status
Simulation time 125641983 ps
CPU time 0.74 seconds
Started Jul 22 05:41:40 PM PDT 24
Finished Jul 22 05:41:42 PM PDT 24
Peak memory 204232 kb
Host smart-58f415c6-e53e-473d-89ae-e7c40e47354d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946535431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2946535431
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2661554038
Short name T1067
Test name
Test status
Simulation time 11076511 ps
CPU time 0.68 seconds
Started Jul 22 05:41:52 PM PDT 24
Finished Jul 22 05:41:54 PM PDT 24
Peak memory 203912 kb
Host smart-e9c264c0-3641-4168-9d58-9db8e6ce05d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661554038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2661554038
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3619707632
Short name T1020
Test name
Test status
Simulation time 14965386 ps
CPU time 0.76 seconds
Started Jul 22 05:41:46 PM PDT 24
Finished Jul 22 05:41:47 PM PDT 24
Peak memory 203992 kb
Host smart-08e25f52-2cb9-4e7c-a160-caadc67fa882
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619707632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3619707632
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3647877958
Short name T1057
Test name
Test status
Simulation time 24671071 ps
CPU time 0.75 seconds
Started Jul 22 05:41:46 PM PDT 24
Finished Jul 22 05:41:48 PM PDT 24
Peak memory 204288 kb
Host smart-4fc56518-2ca8-49e7-83c6-98292becc79f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647877958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3647877958
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.364448280
Short name T1052
Test name
Test status
Simulation time 1303674190 ps
CPU time 7.79 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:22 PM PDT 24
Peak memory 215504 kb
Host smart-b99936b6-ef17-477f-a608-50d75d1b5dea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364448280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.364448280
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2113701719
Short name T1016
Test name
Test status
Simulation time 1772096999 ps
CPU time 11.95 seconds
Started Jul 22 05:41:11 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 207312 kb
Host smart-907ce022-52d7-4f42-be49-c8e71cdd37b9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113701719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2113701719
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.508214900
Short name T1015
Test name
Test status
Simulation time 16591227 ps
CPU time 0.96 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:18 PM PDT 24
Peak memory 206996 kb
Host smart-9f8a2e81-7dc3-4472-a895-1d09aaf8b7ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508214900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.508214900
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.1511405412
Short name T122
Test name
Test status
Simulation time 52541282 ps
CPU time 1.85 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:15 PM PDT 24
Peak memory 216440 kb
Host smart-d95ae39b-9d0b-4b18-b9f3-e29c64f5205f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511405412 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.1511405412
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4028635425
Short name T1107
Test name
Test status
Simulation time 45518041 ps
CPU time 1.58 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 215484 kb
Host smart-57cc71dc-0c14-4adc-bbfe-a3fcb5e74985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028635425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
028635425
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.378744468
Short name T1044
Test name
Test status
Simulation time 106900770 ps
CPU time 0.75 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:15 PM PDT 24
Peak memory 203960 kb
Host smart-e26a960b-1322-4116-91d6-76b040cb8ba4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378744468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.378744468
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3717315595
Short name T125
Test name
Test status
Simulation time 70735710 ps
CPU time 2.31 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:15 PM PDT 24
Peak memory 215248 kb
Host smart-d0b39e8a-d407-421a-90c1-585a9be4f56b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717315595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3717315595
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3023817442
Short name T1007
Test name
Test status
Simulation time 10379506 ps
CPU time 0.66 seconds
Started Jul 22 05:41:11 PM PDT 24
Finished Jul 22 05:41:13 PM PDT 24
Peak memory 204244 kb
Host smart-1c8de736-524f-4c04-9fde-8beb7a5c6224
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023817442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3023817442
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3347602029
Short name T1104
Test name
Test status
Simulation time 28490954 ps
CPU time 1.9 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:16 PM PDT 24
Peak memory 215492 kb
Host smart-e1d9c911-1a17-4c33-9757-3d77b15594d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347602029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3347602029
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.339862080
Short name T112
Test name
Test status
Simulation time 876946542 ps
CPU time 4.68 seconds
Started Jul 22 05:41:13 PM PDT 24
Finished Jul 22 05:41:20 PM PDT 24
Peak memory 215748 kb
Host smart-25af66d5-18a8-427e-a9ed-eb46881dc03f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339862080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.339862080
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3523454958
Short name T164
Test name
Test status
Simulation time 275119032 ps
CPU time 7.29 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 215444 kb
Host smart-86443ef2-4322-4d88-8f91-a2cb733b94e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523454958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3523454958
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3769037548
Short name T1046
Test name
Test status
Simulation time 19953988 ps
CPU time 0.71 seconds
Started Jul 22 05:41:40 PM PDT 24
Finished Jul 22 05:41:41 PM PDT 24
Peak memory 204196 kb
Host smart-b593974f-c4cf-4940-944e-ed2b2dfda32e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769037548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3769037548
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.807148718
Short name T1102
Test name
Test status
Simulation time 13261384 ps
CPU time 0.73 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 203924 kb
Host smart-006c146d-058f-44e6-b891-b03c4e7da69d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807148718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.807148718
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3319901391
Short name T1112
Test name
Test status
Simulation time 45072530 ps
CPU time 0.74 seconds
Started Jul 22 05:41:44 PM PDT 24
Finished Jul 22 05:41:45 PM PDT 24
Peak memory 203988 kb
Host smart-5254ead4-e3b3-4183-8ba4-df13ee2d5596
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319901391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3319901391
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.3529579368
Short name T1022
Test name
Test status
Simulation time 128325145 ps
CPU time 0.72 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:43 PM PDT 24
Peak memory 204296 kb
Host smart-43295fe2-d923-4009-a53a-ce7963c7d43f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529579368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
3529579368
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2388264950
Short name T1030
Test name
Test status
Simulation time 49338665 ps
CPU time 0.72 seconds
Started Jul 22 05:41:40 PM PDT 24
Finished Jul 22 05:41:41 PM PDT 24
Peak memory 204180 kb
Host smart-c7fb4ff9-9ea8-4885-9d4c-9c341083cfe4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388264950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2388264950
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1968870049
Short name T1053
Test name
Test status
Simulation time 139583840 ps
CPU time 0.76 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 203988 kb
Host smart-8edce583-7a29-4742-b2b4-ef5e0b4b68e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968870049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1968870049
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3264624852
Short name T1083
Test name
Test status
Simulation time 11364794 ps
CPU time 0.75 seconds
Started Jul 22 05:41:43 PM PDT 24
Finished Jul 22 05:41:44 PM PDT 24
Peak memory 204252 kb
Host smart-b2f2c50d-efff-4aeb-8441-41ac19148696
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264624852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3264624852
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1210416389
Short name T1029
Test name
Test status
Simulation time 12480927 ps
CPU time 0.77 seconds
Started Jul 22 05:41:45 PM PDT 24
Finished Jul 22 05:41:46 PM PDT 24
Peak memory 204228 kb
Host smart-493e91c9-8610-4de8-8f80-eb210c7648a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210416389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1210416389
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.2769922656
Short name T1086
Test name
Test status
Simulation time 24058940 ps
CPU time 0.7 seconds
Started Jul 22 05:41:41 PM PDT 24
Finished Jul 22 05:41:42 PM PDT 24
Peak memory 204272 kb
Host smart-15a8c253-78db-48c0-b17c-cd277ea1535c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769922656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
2769922656
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1456826470
Short name T1066
Test name
Test status
Simulation time 105217997 ps
CPU time 0.73 seconds
Started Jul 22 05:41:42 PM PDT 24
Finished Jul 22 05:41:43 PM PDT 24
Peak memory 204000 kb
Host smart-f0c1a939-49ec-4ab2-942d-00be81aabb54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456826470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1456826470
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2044770595
Short name T1101
Test name
Test status
Simulation time 1026935723 ps
CPU time 3.79 seconds
Started Jul 22 05:41:18 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 217824 kb
Host smart-ce0c78d2-c387-4e7b-86ce-c38a767ea924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044770595 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2044770595
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.841428686
Short name T1068
Test name
Test status
Simulation time 29322202 ps
CPU time 1.88 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:15 PM PDT 24
Peak memory 215472 kb
Host smart-ba96caf8-8d98-49fb-aaf8-3e59fae1dd92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841428686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.841428686
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4017343116
Short name T1028
Test name
Test status
Simulation time 35452706 ps
CPU time 0.72 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:14 PM PDT 24
Peak memory 204260 kb
Host smart-86fcf444-978e-4e84-a347-c5d4c6e7efdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017343116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
017343116
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2508280360
Short name T1115
Test name
Test status
Simulation time 209006617 ps
CPU time 3.17 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:21 PM PDT 24
Peak memory 215532 kb
Host smart-19dd4a03-9a4d-46c4-8b92-41e3daccabd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508280360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2508280360
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.696471044
Short name T113
Test name
Test status
Simulation time 637178609 ps
CPU time 2.86 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:20 PM PDT 24
Peak memory 216480 kb
Host smart-e5cc895c-f956-45c4-aa62-42cc6bfebabc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696471044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.696471044
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.297073638
Short name T1063
Test name
Test status
Simulation time 245136107 ps
CPU time 2.66 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:20 PM PDT 24
Peak memory 216580 kb
Host smart-6edaf7f9-96e6-42f0-89fe-8467f9fc2305
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297073638 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.297073638
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4198358660
Short name T1085
Test name
Test status
Simulation time 186221280 ps
CPU time 1.53 seconds
Started Jul 22 05:41:11 PM PDT 24
Finished Jul 22 05:41:14 PM PDT 24
Peak memory 207492 kb
Host smart-fe4fd355-7229-4222-a4d1-70d513b2c3c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198358660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
198358660
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1038415050
Short name T1094
Test name
Test status
Simulation time 15080830 ps
CPU time 0.7 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:18 PM PDT 24
Peak memory 204308 kb
Host smart-c169d3e8-9084-43be-b98e-1a27f2c3ac12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038415050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
038415050
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.4027049819
Short name T1025
Test name
Test status
Simulation time 226058086 ps
CPU time 1.84 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 207260 kb
Host smart-5b3d5612-116a-4de5-953e-1a95883221d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027049819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.4027049819
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1016381331
Short name T1123
Test name
Test status
Simulation time 72230332 ps
CPU time 2.66 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:19 PM PDT 24
Peak memory 215684 kb
Host smart-e1030bd5-b144-4c9d-a361-e9bd76623200
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016381331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
016381331
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.159809608
Short name T169
Test name
Test status
Simulation time 301687847 ps
CPU time 19.32 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:37 PM PDT 24
Peak memory 215484 kb
Host smart-cf181b6c-fe0c-4963-85df-93b7642ce1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159809608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.159809608
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3456429137
Short name T1089
Test name
Test status
Simulation time 206419373 ps
CPU time 3.83 seconds
Started Jul 22 05:41:14 PM PDT 24
Finished Jul 22 05:41:21 PM PDT 24
Peak memory 218100 kb
Host smart-bac4e3b1-a0bf-4744-9f1d-2ae52328e0f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456429137 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3456429137
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3950926604
Short name T1079
Test name
Test status
Simulation time 178474193 ps
CPU time 2.61 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:20 PM PDT 24
Peak memory 215356 kb
Host smart-a3292418-6c88-4f52-967d-bd2fa47ade0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950926604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
950926604
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3644779210
Short name T1010
Test name
Test status
Simulation time 14524869 ps
CPU time 0.73 seconds
Started Jul 22 05:41:11 PM PDT 24
Finished Jul 22 05:41:13 PM PDT 24
Peak memory 203976 kb
Host smart-2ee2b96d-a3c1-485a-be79-cd15ce45f864
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644779210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
644779210
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3032718146
Short name T1070
Test name
Test status
Simulation time 180767662 ps
CPU time 4.15 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:22 PM PDT 24
Peak memory 215480 kb
Host smart-e1260d84-d738-4dea-b085-e0f0224ee72c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032718146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3032718146
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2406206377
Short name T1103
Test name
Test status
Simulation time 531045402 ps
CPU time 3.02 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:17 PM PDT 24
Peak memory 215804 kb
Host smart-43ee84eb-64d0-496f-b801-7288f9c3d4c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406206377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
406206377
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1171272573
Short name T105
Test name
Test status
Simulation time 1622957296 ps
CPU time 9.82 seconds
Started Jul 22 05:41:15 PM PDT 24
Finished Jul 22 05:41:27 PM PDT 24
Peak memory 215548 kb
Host smart-3ed919ae-fbc9-4ba5-af00-3decc4a1b09f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171272573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1171272573
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2464308731
Short name T118
Test name
Test status
Simulation time 130027088 ps
CPU time 3.55 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 217776 kb
Host smart-2311a428-734a-4169-9f94-d37e681407a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464308731 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2464308731
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2786521184
Short name T1017
Test name
Test status
Simulation time 143010188 ps
CPU time 2.26 seconds
Started Jul 22 05:41:18 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 207096 kb
Host smart-69a8d5a0-3715-494f-9525-ed00aa1b0c18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786521184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
786521184
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1418474468
Short name T1041
Test name
Test status
Simulation time 12217096 ps
CPU time 0.71 seconds
Started Jul 22 05:41:13 PM PDT 24
Finished Jul 22 05:41:16 PM PDT 24
Peak memory 203960 kb
Host smart-e479e1d7-eaa4-4913-8c74-7ab6acff1fd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418474468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
418474468
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3951449986
Short name T151
Test name
Test status
Simulation time 195003848 ps
CPU time 4.03 seconds
Started Jul 22 05:41:21 PM PDT 24
Finished Jul 22 05:41:26 PM PDT 24
Peak memory 215488 kb
Host smart-58bc5412-9ff8-42be-b7e8-503a3183f518
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951449986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3951449986
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3222667665
Short name T120
Test name
Test status
Simulation time 33799005 ps
CPU time 2.3 seconds
Started Jul 22 05:41:12 PM PDT 24
Finished Jul 22 05:41:16 PM PDT 24
Peak memory 215712 kb
Host smart-23f876a6-7dae-4920-889d-82133477d34e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222667665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
222667665
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2818357796
Short name T166
Test name
Test status
Simulation time 3640054288 ps
CPU time 13.83 seconds
Started Jul 22 05:41:18 PM PDT 24
Finished Jul 22 05:41:34 PM PDT 24
Peak memory 223888 kb
Host smart-fc33e4b4-e4d6-4585-8559-e14549f8dd6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818357796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2818357796
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1547919994
Short name T1039
Test name
Test status
Simulation time 29258969 ps
CPU time 1.99 seconds
Started Jul 22 05:41:22 PM PDT 24
Finished Jul 22 05:41:25 PM PDT 24
Peak memory 216564 kb
Host smart-d41d21c0-80e8-4013-a3a8-8d5c43a051a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547919994 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1547919994
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4293153293
Short name T1024
Test name
Test status
Simulation time 38050634 ps
CPU time 2.46 seconds
Started Jul 22 05:43:31 PM PDT 24
Finished Jul 22 05:43:34 PM PDT 24
Peak memory 215536 kb
Host smart-6e000a6e-5b9b-412d-ab3e-84b1b20f1c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293153293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
293153293
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.935945166
Short name T1098
Test name
Test status
Simulation time 156145746 ps
CPU time 0.77 seconds
Started Jul 22 05:41:22 PM PDT 24
Finished Jul 22 05:41:23 PM PDT 24
Peak memory 204284 kb
Host smart-fcfb7fd1-fa70-400d-acb1-e2645ced4f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935945166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.935945166
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2353325298
Short name T1023
Test name
Test status
Simulation time 44357553 ps
CPU time 2.62 seconds
Started Jul 22 05:41:20 PM PDT 24
Finished Jul 22 05:41:24 PM PDT 24
Peak memory 215480 kb
Host smart-de6075af-a832-4ff7-86a3-a964be5fa8ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353325298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2353325298
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2774798275
Short name T114
Test name
Test status
Simulation time 137847078 ps
CPU time 4.05 seconds
Started Jul 22 05:41:21 PM PDT 24
Finished Jul 22 05:41:26 PM PDT 24
Peak memory 215672 kb
Host smart-6da4af16-f474-4647-af9d-61b3c5b8d361
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774798275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
774798275
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3443625601
Short name T1091
Test name
Test status
Simulation time 208273259 ps
CPU time 13.61 seconds
Started Jul 22 05:41:22 PM PDT 24
Finished Jul 22 05:41:37 PM PDT 24
Peak memory 215720 kb
Host smart-58a77160-e07b-45ce-bc22-3ff8b4641806
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443625601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3443625601
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2077182411
Short name T906
Test name
Test status
Simulation time 48424721 ps
CPU time 0.77 seconds
Started Jul 22 05:47:21 PM PDT 24
Finished Jul 22 05:47:22 PM PDT 24
Peak memory 205908 kb
Host smart-3720bea9-07e7-49f4-a7e2-4e1c37d8c547
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077182411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
077182411
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1670274560
Short name T826
Test name
Test status
Simulation time 519466807 ps
CPU time 3.8 seconds
Started Jul 22 05:47:18 PM PDT 24
Finished Jul 22 05:47:22 PM PDT 24
Peak memory 232864 kb
Host smart-6d6a345c-de13-4ddf-a1e0-38abcfe8c098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670274560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1670274560
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3901126694
Short name T634
Test name
Test status
Simulation time 26107476 ps
CPU time 0.75 seconds
Started Jul 22 05:47:26 PM PDT 24
Finished Jul 22 05:47:28 PM PDT 24
Peak memory 207072 kb
Host smart-1da16f79-9ab1-4853-80ae-7602958e2ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901126694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3901126694
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3567953789
Short name T851
Test name
Test status
Simulation time 99523812255 ps
CPU time 213.52 seconds
Started Jul 22 05:47:27 PM PDT 24
Finished Jul 22 05:51:01 PM PDT 24
Peak memory 252528 kb
Host smart-83fff661-9a1f-48d1-98ba-14732e26513e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567953789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3567953789
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3474880613
Short name T435
Test name
Test status
Simulation time 53563369968 ps
CPU time 145.16 seconds
Started Jul 22 05:47:23 PM PDT 24
Finished Jul 22 05:49:49 PM PDT 24
Peak memory 265712 kb
Host smart-b92203c7-49c5-4d70-99cd-d4eaef6f49b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474880613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3474880613
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.2084077920
Short name T298
Test name
Test status
Simulation time 16050349576 ps
CPU time 51.86 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:48:12 PM PDT 24
Peak memory 232924 kb
Host smart-f6995457-66c2-4d31-a984-1e7e022a22e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084077920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.2084077920
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.1546814508
Short name T696
Test name
Test status
Simulation time 33288810 ps
CPU time 0.74 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:29 PM PDT 24
Peak memory 215868 kb
Host smart-7689440f-ac32-431c-9c3c-9af612f67bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546814508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.1546814508
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2984967208
Short name T682
Test name
Test status
Simulation time 11124508958 ps
CPU time 22.13 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:51 PM PDT 24
Peak memory 232916 kb
Host smart-7fc8b590-b48a-4748-8f31-4c406a359b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984967208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2984967208
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.721797360
Short name T556
Test name
Test status
Simulation time 4910445331 ps
CPU time 17.94 seconds
Started Jul 22 05:47:29 PM PDT 24
Finished Jul 22 05:47:47 PM PDT 24
Peak memory 232880 kb
Host smart-3513cb65-2b6b-4676-a649-2804e0f4279f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721797360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.721797360
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.487337714
Short name T527
Test name
Test status
Simulation time 30316135 ps
CPU time 2.56 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:47:23 PM PDT 24
Peak memory 232460 kb
Host smart-c3a3a42f-4801-4005-809c-5a16fcdedcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487337714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
487337714
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2069857833
Short name T842
Test name
Test status
Simulation time 64927371 ps
CPU time 2.53 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:47:23 PM PDT 24
Peak memory 224636 kb
Host smart-15a1d73c-9cef-4bf3-b42b-d4b277a34c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069857833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2069857833
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.4236564357
Short name T56
Test name
Test status
Simulation time 2549729240 ps
CPU time 13.06 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:47:33 PM PDT 24
Peak memory 222500 kb
Host smart-a072c30f-c8d1-422c-ac84-e960171108cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4236564357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.4236564357
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3998100383
Short name T73
Test name
Test status
Simulation time 329876517 ps
CPU time 1.11 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:47:21 PM PDT 24
Peak memory 236468 kb
Host smart-4be64e0e-b367-450d-aca2-af111318e79e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998100383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3998100383
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3638030304
Short name T811
Test name
Test status
Simulation time 31540124853 ps
CPU time 115.76 seconds
Started Jul 22 05:49:21 PM PDT 24
Finished Jul 22 05:51:19 PM PDT 24
Peak memory 257300 kb
Host smart-64b0ec1c-a73e-4bd3-ad92-291acfd93447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638030304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3638030304
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3925338425
Short name T415
Test name
Test status
Simulation time 1864723165 ps
CPU time 5.11 seconds
Started Jul 22 05:47:25 PM PDT 24
Finished Jul 22 05:47:31 PM PDT 24
Peak memory 216728 kb
Host smart-b0cc0b5f-baad-44a1-ab12-e6a52ddffa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925338425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3925338425
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3213234693
Short name T530
Test name
Test status
Simulation time 20297024187 ps
CPU time 15.35 seconds
Started Jul 22 05:47:29 PM PDT 24
Finished Jul 22 05:47:45 PM PDT 24
Peak memory 216384 kb
Host smart-bd8000ee-9bac-4dd4-bcdc-ffcbe101fc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213234693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3213234693
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2152495617
Short name T354
Test name
Test status
Simulation time 171761308 ps
CPU time 3.02 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:25 PM PDT 24
Peak memory 216296 kb
Host smart-aff0903c-d375-46ed-907c-c4dd58d3f7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152495617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2152495617
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1024097374
Short name T810
Test name
Test status
Simulation time 33541347 ps
CPU time 0.76 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:29 PM PDT 24
Peak memory 206068 kb
Host smart-e65f2bd8-038a-450c-8de6-79029c647091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024097374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1024097374
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3577747856
Short name T493
Test name
Test status
Simulation time 657529329 ps
CPU time 3.49 seconds
Started Jul 22 05:47:23 PM PDT 24
Finished Jul 22 05:47:26 PM PDT 24
Peak memory 232828 kb
Host smart-a50ee62a-a14d-4bda-bb81-1148900702e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577747856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3577747856
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.440127635
Short name T593
Test name
Test status
Simulation time 51205865 ps
CPU time 0.74 seconds
Started Jul 22 05:47:32 PM PDT 24
Finished Jul 22 05:47:33 PM PDT 24
Peak memory 205920 kb
Host smart-434f88a0-4c65-4c22-8a78-421dc4e07f17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440127635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.440127635
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.88901391
Short name T743
Test name
Test status
Simulation time 1244217232 ps
CPU time 5.21 seconds
Started Jul 22 05:47:32 PM PDT 24
Finished Jul 22 05:47:37 PM PDT 24
Peak memory 232792 kb
Host smart-3e7bca44-3182-4063-aa54-f3e83de6baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88901391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.88901391
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1303691103
Short name T462
Test name
Test status
Simulation time 17936213 ps
CPU time 0.79 seconds
Started Jul 22 05:47:22 PM PDT 24
Finished Jul 22 05:47:23 PM PDT 24
Peak memory 206756 kb
Host smart-e858386c-5223-424a-999e-f18901582623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303691103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1303691103
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.3608460195
Short name T475
Test name
Test status
Simulation time 18727894224 ps
CPU time 14.82 seconds
Started Jul 22 05:47:30 PM PDT 24
Finished Jul 22 05:47:45 PM PDT 24
Peak memory 224616 kb
Host smart-36360321-fc04-488c-ab97-13eede4862b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608460195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.3608460195
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3853478640
Short name T147
Test name
Test status
Simulation time 13485875834 ps
CPU time 38.14 seconds
Started Jul 22 05:47:30 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 249300 kb
Host smart-849d1ead-e28e-4664-b8b9-38909f9294dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853478640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3853478640
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1219208869
Short name T656
Test name
Test status
Simulation time 1494287000 ps
CPU time 15.7 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:47:47 PM PDT 24
Peak memory 224744 kb
Host smart-484ef3c9-d565-4fae-9c48-4d4f3f23310f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219208869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1219208869
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.753730726
Short name T249
Test name
Test status
Simulation time 557838257 ps
CPU time 3.47 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:47:35 PM PDT 24
Peak memory 232856 kb
Host smart-a2152fb9-07f6-4a2e-910d-d63afc58d23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753730726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.753730726
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2510432458
Short name T258
Test name
Test status
Simulation time 11687484147 ps
CPU time 34.57 seconds
Started Jul 22 05:47:25 PM PDT 24
Finished Jul 22 05:48:00 PM PDT 24
Peak memory 232904 kb
Host smart-b60fd5cf-71f9-414a-bb3f-d9693f119739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510432458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2510432458
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4178729732
Short name T869
Test name
Test status
Simulation time 5303361721 ps
CPU time 9.96 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:39 PM PDT 24
Peak memory 232844 kb
Host smart-ab689b55-5e28-4f73-b443-965f5e680f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178729732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4178729732
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.157005861
Short name T97
Test name
Test status
Simulation time 268035499 ps
CPU time 3.34 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:47:35 PM PDT 24
Peak memory 223724 kb
Host smart-e28d80da-f86c-4a11-b134-83ec7e04562e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=157005861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.157005861
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2483375580
Short name T72
Test name
Test status
Simulation time 104147547 ps
CPU time 1.01 seconds
Started Jul 22 05:47:30 PM PDT 24
Finished Jul 22 05:47:31 PM PDT 24
Peak memory 236404 kb
Host smart-c7269b31-8b4d-4911-93f0-0732fb3ee7c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483375580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2483375580
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2671157426
Short name T317
Test name
Test status
Simulation time 10171747453 ps
CPU time 23.06 seconds
Started Jul 22 05:47:21 PM PDT 24
Finished Jul 22 05:47:44 PM PDT 24
Peak memory 217772 kb
Host smart-6aa92a9b-d557-4229-9cbd-d011324a7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671157426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2671157426
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1816415782
Short name T717
Test name
Test status
Simulation time 2743220925 ps
CPU time 8.4 seconds
Started Jul 22 05:47:29 PM PDT 24
Finished Jul 22 05:47:38 PM PDT 24
Peak memory 216492 kb
Host smart-bec93d3b-96ad-45dd-8893-fdf9cd27ae37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816415782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1816415782
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.131462965
Short name T843
Test name
Test status
Simulation time 120368127 ps
CPU time 1.93 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:47:22 PM PDT 24
Peak memory 216356 kb
Host smart-e87512df-65dd-40af-bea5-98e914dc411d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131462965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.131462965
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.747873075
Short name T838
Test name
Test status
Simulation time 138897477 ps
CPU time 0.84 seconds
Started Jul 22 05:47:20 PM PDT 24
Finished Jul 22 05:47:22 PM PDT 24
Peak memory 206132 kb
Host smart-eaea9cd3-00e7-4389-8dc8-ec501cbeb08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747873075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.747873075
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1840281957
Short name T411
Test name
Test status
Simulation time 21355674840 ps
CPU time 15.2 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:43 PM PDT 24
Peak memory 224760 kb
Host smart-f3f718e0-dd0d-4780-83ff-9298e64ea7e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840281957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1840281957
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.836206355
Short name T858
Test name
Test status
Simulation time 22604718 ps
CPU time 0.71 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:48:54 PM PDT 24
Peak memory 205540 kb
Host smart-e754a212-f1fb-4c16-bd6a-f23a0ca720a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836206355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.836206355
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3894029433
Short name T273
Test name
Test status
Simulation time 6557879683 ps
CPU time 11.15 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:25 PM PDT 24
Peak memory 232864 kb
Host smart-7c74412f-7603-4975-8b81-a02b3b840156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894029433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3894029433
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.832762234
Short name T508
Test name
Test status
Simulation time 75867671 ps
CPU time 0.79 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 207016 kb
Host smart-167ac880-503e-4d24-98c7-b57ffdf4e858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832762234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.832762234
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.4139790291
Short name T976
Test name
Test status
Simulation time 163061789324 ps
CPU time 278.99 seconds
Started Jul 22 05:48:23 PM PDT 24
Finished Jul 22 05:53:03 PM PDT 24
Peak memory 251388 kb
Host smart-d94ac007-9b18-4dbb-b316-791973b5d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139790291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.4139790291
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.147625065
Short name T83
Test name
Test status
Simulation time 10255364344 ps
CPU time 83.33 seconds
Started Jul 22 05:48:19 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 249452 kb
Host smart-f3c438d9-b4f1-4d52-94a8-3441fe8f8298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147625065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.147625065
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3407605794
Short name T902
Test name
Test status
Simulation time 1524912138 ps
CPU time 9.79 seconds
Started Jul 22 05:48:16 PM PDT 24
Finished Jul 22 05:48:26 PM PDT 24
Peak memory 249096 kb
Host smart-9d639c5a-fb58-479e-baeb-beaba930f269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407605794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3407605794
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.1426729894
Short name T541
Test name
Test status
Simulation time 60355911960 ps
CPU time 74.2 seconds
Started Jul 22 05:48:22 PM PDT 24
Finished Jul 22 05:49:37 PM PDT 24
Peak memory 256608 kb
Host smart-2bb504a4-20ff-4ca4-8ea9-7f2c64ad9ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426729894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.1426729894
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1797943750
Short name T960
Test name
Test status
Simulation time 10968307287 ps
CPU time 17.75 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:32 PM PDT 24
Peak memory 232968 kb
Host smart-48cf12f8-edd7-49e5-816b-f31fb5a23178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797943750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1797943750
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.3819416714
Short name T883
Test name
Test status
Simulation time 1342143569 ps
CPU time 7.8 seconds
Started Jul 22 05:48:11 PM PDT 24
Finished Jul 22 05:48:20 PM PDT 24
Peak memory 232920 kb
Host smart-17c80833-2183-4046-a202-62509f9af221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819416714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.3819416714
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1783262001
Short name T612
Test name
Test status
Simulation time 7291086395 ps
CPU time 5.99 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:19 PM PDT 24
Peak memory 232948 kb
Host smart-e8b33dcc-f3f6-4783-a410-da305b6c6f5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783262001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1783262001
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1383938325
Short name T529
Test name
Test status
Simulation time 2983612731 ps
CPU time 8.67 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:48:27 PM PDT 24
Peak memory 224648 kb
Host smart-41ffec57-70a8-4e35-acdb-a4ca2cd7f5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383938325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1383938325
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1567390393
Short name T458
Test name
Test status
Simulation time 1428639094 ps
CPU time 12.42 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:35 PM PDT 24
Peak memory 220644 kb
Host smart-ba04206c-56a2-4024-a01f-a41b22a83bd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1567390393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1567390393
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1084877327
Short name T714
Test name
Test status
Simulation time 55721702427 ps
CPU time 29.98 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 220364 kb
Host smart-1b6835fc-e460-4bc1-84a9-ee696e8e608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084877327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1084877327
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2365385973
Short name T544
Test name
Test status
Simulation time 8948460216 ps
CPU time 26.1 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:40 PM PDT 24
Peak memory 216356 kb
Host smart-09d7b6dd-1362-448a-b812-555c9aa5982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365385973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2365385973
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2903311613
Short name T546
Test name
Test status
Simulation time 50335934 ps
CPU time 1.35 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:48:20 PM PDT 24
Peak memory 216436 kb
Host smart-8569ccec-fabd-41df-ad7c-a2ea2754ec7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903311613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2903311613
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.4270191897
Short name T955
Test name
Test status
Simulation time 140524962 ps
CPU time 0.83 seconds
Started Jul 22 05:48:16 PM PDT 24
Finished Jul 22 05:48:17 PM PDT 24
Peak memory 206096 kb
Host smart-46825757-c181-4b6d-bc1c-15570a7be170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270191897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.4270191897
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3589776227
Short name T644
Test name
Test status
Simulation time 20408957641 ps
CPU time 7 seconds
Started Jul 22 05:48:15 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 224684 kb
Host smart-99944728-503b-414b-87c9-177d7a86a51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589776227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3589776227
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3621439889
Short name T978
Test name
Test status
Simulation time 21846905 ps
CPU time 0.71 seconds
Started Jul 22 05:48:25 PM PDT 24
Finished Jul 22 05:48:26 PM PDT 24
Peak memory 205016 kb
Host smart-045bd116-9c68-4369-b868-68fc9e1e104a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621439889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3621439889
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3884308245
Short name T370
Test name
Test status
Simulation time 726224063 ps
CPU time 5.98 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:28 PM PDT 24
Peak memory 232868 kb
Host smart-44ab592c-db4c-42d9-bced-97eb603e2bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884308245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3884308245
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.459861586
Short name T416
Test name
Test status
Simulation time 110514932 ps
CPU time 0.75 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 207060 kb
Host smart-fc32a2f3-947f-4234-bbc7-48e38af22ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459861586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.459861586
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3506859641
Short name T823
Test name
Test status
Simulation time 16072395406 ps
CPU time 109.65 seconds
Started Jul 22 05:48:24 PM PDT 24
Finished Jul 22 05:50:15 PM PDT 24
Peak memory 256436 kb
Host smart-67c681ca-4a77-453c-bc3a-9ce91c234f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506859641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3506859641
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2480899885
Short name T395
Test name
Test status
Simulation time 384618989 ps
CPU time 5 seconds
Started Jul 22 05:48:23 PM PDT 24
Finished Jul 22 05:48:29 PM PDT 24
Peak memory 224692 kb
Host smart-b41c0b6c-5c50-4a59-8504-e27e75bd430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480899885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2480899885
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3173280178
Short name T173
Test name
Test status
Simulation time 349575229357 ps
CPU time 210.71 seconds
Started Jul 22 05:48:23 PM PDT 24
Finished Jul 22 05:51:55 PM PDT 24
Peak memory 253560 kb
Host smart-43b08160-acbb-4011-b02b-d535ca3025cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173280178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3173280178
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1807315366
Short name T444
Test name
Test status
Simulation time 2691788247 ps
CPU time 6.67 seconds
Started Jul 22 05:48:24 PM PDT 24
Finished Jul 22 05:48:31 PM PDT 24
Peak memory 232960 kb
Host smart-2404e1ee-f8bb-48ca-8482-2bde1aa71314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807315366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1807315366
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1123742561
Short name T987
Test name
Test status
Simulation time 4363937595 ps
CPU time 44.25 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:49:06 PM PDT 24
Peak memory 239640 kb
Host smart-c7dd3dbd-152a-4cf8-b95d-4e4f3b5fddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123742561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1123742561
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2560561488
Short name T226
Test name
Test status
Simulation time 898012729 ps
CPU time 5.08 seconds
Started Jul 22 05:48:20 PM PDT 24
Finished Jul 22 05:48:26 PM PDT 24
Peak memory 224644 kb
Host smart-ffd35aa1-dca4-4cb8-8fd0-eb5c718f6f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560561488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2560561488
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.690077387
Short name T613
Test name
Test status
Simulation time 3498881254 ps
CPU time 10.03 seconds
Started Jul 22 05:48:42 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 239976 kb
Host smart-26fca07f-3637-4af7-8f9e-ed86e5256c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690077387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.690077387
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3932880659
Short name T422
Test name
Test status
Simulation time 92848743 ps
CPU time 3.8 seconds
Started Jul 22 05:48:26 PM PDT 24
Finished Jul 22 05:48:30 PM PDT 24
Peak memory 218972 kb
Host smart-929a97ae-fd79-4109-9119-3ffa100ac68d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3932880659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3932880659
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.724275174
Short name T519
Test name
Test status
Simulation time 68261490030 ps
CPU time 46.2 seconds
Started Jul 22 05:48:24 PM PDT 24
Finished Jul 22 05:49:11 PM PDT 24
Peak memory 251732 kb
Host smart-28921b1e-51b7-4a62-a82c-fffe215ec359
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724275174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.724275174
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1356572964
Short name T524
Test name
Test status
Simulation time 6428796934 ps
CPU time 16.31 seconds
Started Jul 22 05:48:24 PM PDT 24
Finished Jul 22 05:48:41 PM PDT 24
Peak memory 216452 kb
Host smart-2677ce40-86d6-477e-8de3-e223cc4a984d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356572964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1356572964
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2357993066
Short name T679
Test name
Test status
Simulation time 17070065837 ps
CPU time 5.59 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:28 PM PDT 24
Peak memory 217612 kb
Host smart-d37c1cf3-5b74-4f24-8d62-cdfb3fa3eff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357993066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2357993066
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.1917676139
Short name T34
Test name
Test status
Simulation time 47514269 ps
CPU time 2.48 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:24 PM PDT 24
Peak memory 216420 kb
Host smart-278b46e1-e8d1-4f43-b2c4-8c5b7fe83342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917676139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1917676139
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3849230679
Short name T600
Test name
Test status
Simulation time 169698986 ps
CPU time 0.98 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 206500 kb
Host smart-0213a6d0-088b-4d41-9a05-a96ef8ea8427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849230679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3849230679
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1670024673
Short name T540
Test name
Test status
Simulation time 7595298746 ps
CPU time 14.69 seconds
Started Jul 22 05:48:25 PM PDT 24
Finished Jul 22 05:48:40 PM PDT 24
Peak memory 240732 kb
Host smart-9f8d8a82-e046-45ed-85cb-708a283b67b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670024673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1670024673
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2994294731
Short name T951
Test name
Test status
Simulation time 12390131 ps
CPU time 0.72 seconds
Started Jul 22 05:48:40 PM PDT 24
Finished Jul 22 05:48:41 PM PDT 24
Peak memory 205032 kb
Host smart-2b91e08c-8d62-413e-b509-d46866d5e52f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994294731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2994294731
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1073566695
Short name T479
Test name
Test status
Simulation time 221101274 ps
CPU time 3.32 seconds
Started Jul 22 05:48:37 PM PDT 24
Finished Jul 22 05:48:41 PM PDT 24
Peak memory 224664 kb
Host smart-540e20f4-8d09-454a-892d-6bbd2fa4cd3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073566695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1073566695
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3961523903
Short name T326
Test name
Test status
Simulation time 186092575 ps
CPU time 0.78 seconds
Started Jul 22 05:48:22 PM PDT 24
Finished Jul 22 05:48:24 PM PDT 24
Peak memory 206764 kb
Host smart-77b2177c-43e8-4937-8898-e78c6497ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961523903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3961523903
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1316734644
Short name T959
Test name
Test status
Simulation time 5859151718 ps
CPU time 78.38 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:49:52 PM PDT 24
Peak memory 251976 kb
Host smart-fe584cd9-e4c4-4453-8003-8be26c3e5666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316734644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1316734644
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2883468270
Short name T511
Test name
Test status
Simulation time 3308238304 ps
CPU time 80.41 seconds
Started Jul 22 05:48:32 PM PDT 24
Finished Jul 22 05:49:53 PM PDT 24
Peak memory 263396 kb
Host smart-b1357573-e199-48db-96b5-f397c2472e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883468270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2883468270
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.92527434
Short name T343
Test name
Test status
Simulation time 215917447 ps
CPU time 3.62 seconds
Started Jul 22 05:48:35 PM PDT 24
Finished Jul 22 05:48:39 PM PDT 24
Peak memory 232784 kb
Host smart-b0d00485-b797-4ce9-9941-43c3255f562a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92527434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.92527434
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.4289751321
Short name T217
Test name
Test status
Simulation time 1916264648 ps
CPU time 43.53 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:49:17 PM PDT 24
Peak memory 255056 kb
Host smart-8724913d-4a5b-4843-a88c-f6619a3f9b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289751321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.4289751321
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.409073157
Short name T782
Test name
Test status
Simulation time 79323004 ps
CPU time 3.16 seconds
Started Jul 22 05:48:39 PM PDT 24
Finished Jul 22 05:48:42 PM PDT 24
Peak memory 232776 kb
Host smart-39c10cfa-0073-4f38-8c0b-f90c06e6fea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409073157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.409073157
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.110932591
Short name T372
Test name
Test status
Simulation time 1278643622 ps
CPU time 5.41 seconds
Started Jul 22 05:48:32 PM PDT 24
Finished Jul 22 05:48:38 PM PDT 24
Peak memory 232868 kb
Host smart-aff6453c-a61d-40d2-bf99-38fd01795856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110932591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.110932591
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.1269910841
Short name T328
Test name
Test status
Simulation time 245647245 ps
CPU time 2.53 seconds
Started Jul 22 05:48:32 PM PDT 24
Finished Jul 22 05:48:35 PM PDT 24
Peak memory 232844 kb
Host smart-3e5adae7-0e86-47c5-b5a2-3d72c3f1860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269910841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.1269910841
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1905722643
Short name T798
Test name
Test status
Simulation time 78394775 ps
CPU time 2.69 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:48:40 PM PDT 24
Peak memory 224588 kb
Host smart-ba15e928-3c16-4857-b7da-2929f7dc2ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905722643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1905722643
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.1959959423
Short name T487
Test name
Test status
Simulation time 1753501613 ps
CPU time 8.84 seconds
Started Jul 22 05:48:34 PM PDT 24
Finished Jul 22 05:48:43 PM PDT 24
Peak memory 220764 kb
Host smart-9387ee0b-d40f-4da6-bfe8-81128ac31ee3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1959959423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.1959959423
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2062280597
Short name T992
Test name
Test status
Simulation time 37216339303 ps
CPU time 93.82 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:50:08 PM PDT 24
Peak memory 254940 kb
Host smart-a8f36e93-bc4c-4a0f-a153-641879457168
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062280597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2062280597
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2452888820
Short name T304
Test name
Test status
Simulation time 1846929290 ps
CPU time 22.25 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:48:58 PM PDT 24
Peak memory 219636 kb
Host smart-fa2b7031-0c0e-40ec-8694-a6a705256101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452888820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2452888820
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.4266637426
Short name T818
Test name
Test status
Simulation time 544212982 ps
CPU time 4.1 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:48:37 PM PDT 24
Peak memory 216460 kb
Host smart-23ec5efe-0f7f-436c-a2dd-29895a00421e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266637426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.4266637426
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3339679442
Short name T752
Test name
Test status
Simulation time 10334987 ps
CPU time 0.71 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:48:38 PM PDT 24
Peak memory 205700 kb
Host smart-05b28430-86e5-4397-a373-6d8155a7b6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339679442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3339679442
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.266305261
Short name T816
Test name
Test status
Simulation time 52583096 ps
CPU time 0.75 seconds
Started Jul 22 05:48:34 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 206116 kb
Host smart-907877a4-5a79-4fc9-91df-03a5bea3be3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266305261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.266305261
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3334777000
Short name T729
Test name
Test status
Simulation time 2175483093 ps
CPU time 10.26 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 232904 kb
Host smart-e1dc3ed4-e817-4483-abf8-de573826db94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334777000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3334777000
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2679405754
Short name T619
Test name
Test status
Simulation time 19383745 ps
CPU time 0.7 seconds
Started Jul 22 05:49:14 PM PDT 24
Finished Jul 22 05:49:15 PM PDT 24
Peak memory 205900 kb
Host smart-5fe885cc-2670-4b32-9417-cda8a72d9ce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679405754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2679405754
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2406704565
Short name T269
Test name
Test status
Simulation time 2503258572 ps
CPU time 8.9 seconds
Started Jul 22 05:48:35 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 224708 kb
Host smart-63d90f83-3663-4baa-9671-d1a0bf8a59cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406704565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2406704565
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2552134659
Short name T582
Test name
Test status
Simulation time 140880422 ps
CPU time 0.8 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:48:38 PM PDT 24
Peak memory 206700 kb
Host smart-f1c57ae3-66a4-4ef9-8120-6f93cab75b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552134659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2552134659
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2955848536
Short name T764
Test name
Test status
Simulation time 42959016 ps
CPU time 0.78 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:49:50 PM PDT 24
Peak memory 215852 kb
Host smart-036fc866-69ef-47c5-affa-475bf336ecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955848536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2955848536
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.723608942
Short name T522
Test name
Test status
Simulation time 99290963 ps
CPU time 3.48 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:48:37 PM PDT 24
Peak memory 224648 kb
Host smart-c097463e-079e-4168-9e18-95061847c58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723608942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.723608942
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2832710070
Short name T547
Test name
Test status
Simulation time 4640641739 ps
CPU time 11.7 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:48:49 PM PDT 24
Peak memory 224636 kb
Host smart-589f2dec-74e5-4a68-a2db-48ac85f157c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832710070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2832710070
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2162864154
Short name T456
Test name
Test status
Simulation time 101839788 ps
CPU time 2.61 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 232508 kb
Host smart-636f5e26-462b-4a0e-a7dd-889e3d00bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162864154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2162864154
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2954649227
Short name T279
Test name
Test status
Simulation time 144514453 ps
CPU time 2.54 seconds
Started Jul 22 05:48:33 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 224604 kb
Host smart-77b3c05e-8b5a-4e35-a880-1f07a894dc43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954649227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2954649227
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.43803694
Short name T725
Test name
Test status
Simulation time 444133337 ps
CPU time 3.17 seconds
Started Jul 22 05:48:36 PM PDT 24
Finished Jul 22 05:48:40 PM PDT 24
Peak memory 233040 kb
Host smart-8e768b73-7299-41a2-84fd-bc4b69804a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43803694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.43803694
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3355021129
Short name T432
Test name
Test status
Simulation time 6239426125 ps
CPU time 15.18 seconds
Started Jul 22 05:48:35 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 220044 kb
Host smart-63b7f6a0-a669-491b-be9e-98bef643f05d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3355021129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3355021129
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2754206509
Short name T822
Test name
Test status
Simulation time 20723907125 ps
CPU time 184.78 seconds
Started Jul 22 05:48:34 PM PDT 24
Finished Jul 22 05:51:39 PM PDT 24
Peak memory 250612 kb
Host smart-4f5d8ae7-1655-446b-872f-e8163ca038c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754206509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2754206509
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1475095718
Short name T535
Test name
Test status
Simulation time 20752279037 ps
CPU time 14.37 seconds
Started Jul 22 05:48:35 PM PDT 24
Finished Jul 22 05:48:50 PM PDT 24
Peak memory 216412 kb
Host smart-ced3b308-1737-420e-aefe-74f4c7067fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475095718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1475095718
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2595932209
Short name T497
Test name
Test status
Simulation time 18181318776 ps
CPU time 14.55 seconds
Started Jul 22 05:48:37 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 216484 kb
Host smart-4b826618-004d-404c-b5b0-d92db82c3430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595932209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2595932209
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2036491532
Short name T583
Test name
Test status
Simulation time 488546504 ps
CPU time 6.26 seconds
Started Jul 22 05:49:48 PM PDT 24
Finished Jul 22 05:49:55 PM PDT 24
Peak memory 216436 kb
Host smart-ba44a879-3a98-4179-b10b-2184d502e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036491532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2036491532
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.341072008
Short name T455
Test name
Test status
Simulation time 348385687 ps
CPU time 0.99 seconds
Started Jul 22 05:49:48 PM PDT 24
Finished Jul 22 05:49:50 PM PDT 24
Peak memory 207104 kb
Host smart-975b9911-c92c-4538-be75-77a3eeb651e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341072008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.341072008
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1418682082
Short name T470
Test name
Test status
Simulation time 13389827075 ps
CPU time 17.14 seconds
Started Jul 22 05:48:34 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 232908 kb
Host smart-82acad4a-5b3b-4185-a7cb-dabec21b9aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418682082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1418682082
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.209277892
Short name T794
Test name
Test status
Simulation time 25902874 ps
CPU time 0.74 seconds
Started Jul 22 05:48:42 PM PDT 24
Finished Jul 22 05:48:43 PM PDT 24
Peak memory 205524 kb
Host smart-8ee7126b-dfa2-4d7b-b45d-0436780ceb89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209277892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.209277892
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3669348939
Short name T551
Test name
Test status
Simulation time 341930141 ps
CPU time 4.77 seconds
Started Jul 22 05:48:51 PM PDT 24
Finished Jul 22 05:48:56 PM PDT 24
Peak memory 232844 kb
Host smart-23b32b10-fbd1-49a2-aec8-3ac44bbd5d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669348939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3669348939
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.119932137
Short name T936
Test name
Test status
Simulation time 48675183 ps
CPU time 0.84 seconds
Started Jul 22 05:48:35 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 205752 kb
Host smart-9d0d6592-68cc-4aa4-a5c1-cc3dcb0fd806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119932137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.119932137
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3100261104
Short name T736
Test name
Test status
Simulation time 1754351693 ps
CPU time 5.3 seconds
Started Jul 22 05:48:45 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 235612 kb
Host smart-054e9867-f436-41f0-a647-6bdc4e76d606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100261104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3100261104
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2908969741
Short name T32
Test name
Test status
Simulation time 24330350966 ps
CPU time 123.49 seconds
Started Jul 22 05:48:46 PM PDT 24
Finished Jul 22 05:50:50 PM PDT 24
Peak memory 249620 kb
Host smart-e97787c5-e2e9-4141-866b-f7d9025a257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908969741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2908969741
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.3190557538
Short name T274
Test name
Test status
Simulation time 8411807919 ps
CPU time 84.54 seconds
Started Jul 22 05:48:42 PM PDT 24
Finished Jul 22 05:50:07 PM PDT 24
Peak memory 255636 kb
Host smart-8dca4eb5-7831-4688-b975-0a042b0ffbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190557538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.3190557538
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2218517025
Short name T464
Test name
Test status
Simulation time 758553912 ps
CPU time 6.99 seconds
Started Jul 22 05:48:49 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 224760 kb
Host smart-bdb0660b-2483-4411-938e-43c17c63b0ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218517025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2218517025
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2568749952
Short name T337
Test name
Test status
Simulation time 2707498116 ps
CPU time 8.08 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 224724 kb
Host smart-c0535485-8817-4362-ac71-d1e110b1eff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568749952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2568749952
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1494308347
Short name T549
Test name
Test status
Simulation time 5255940443 ps
CPU time 8.16 seconds
Started Jul 22 05:48:42 PM PDT 24
Finished Jul 22 05:48:50 PM PDT 24
Peak memory 224660 kb
Host smart-2e71d4b1-a012-42d4-b0cc-272c96b70f49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494308347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1494308347
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.252101792
Short name T847
Test name
Test status
Simulation time 17385055176 ps
CPU time 31.9 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:49:21 PM PDT 24
Peak memory 253628 kb
Host smart-5e758346-92eb-43ba-87c0-ec6d7264b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252101792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.252101792
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2397327677
Short name T677
Test name
Test status
Simulation time 822746708 ps
CPU time 8.61 seconds
Started Jul 22 05:48:42 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 219904 kb
Host smart-3531f820-6b25-41dd-82c4-faeeab2f40d5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2397327677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2397327677
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.3951307897
Short name T748
Test name
Test status
Simulation time 1151843562967 ps
CPU time 600.55 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 272132 kb
Host smart-2b9cc7f6-2e0e-4b60-b9f7-8ac052c8ea5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951307897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.3951307897
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2457220889
Short name T476
Test name
Test status
Simulation time 1227844652 ps
CPU time 11.87 seconds
Started Jul 22 05:48:31 PM PDT 24
Finished Jul 22 05:48:43 PM PDT 24
Peak memory 219900 kb
Host smart-1cae8c92-6498-48e7-9e8a-d3c050e56cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457220889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2457220889
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.942930547
Short name T441
Test name
Test status
Simulation time 14421154714 ps
CPU time 9.5 seconds
Started Jul 22 05:48:34 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 216440 kb
Host smart-e852c4db-c75e-4382-9e19-ddaef6ee1796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942930547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.942930547
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3546168402
Short name T473
Test name
Test status
Simulation time 317850529 ps
CPU time 2.79 seconds
Started Jul 22 05:48:39 PM PDT 24
Finished Jul 22 05:48:42 PM PDT 24
Peak memory 216664 kb
Host smart-c504066b-1fe0-4bab-99a5-fbfe6497c8a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546168402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3546168402
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.933568048
Short name T834
Test name
Test status
Simulation time 88685111 ps
CPU time 0.85 seconds
Started Jul 22 05:48:37 PM PDT 24
Finished Jul 22 05:48:38 PM PDT 24
Peak memory 206112 kb
Host smart-81706be2-e90b-4328-816d-c996a740ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933568048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.933568048
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3988424819
Short name T506
Test name
Test status
Simulation time 1313178190 ps
CPU time 3.42 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 224720 kb
Host smart-ff3eb4fe-7d27-47ee-942e-4117cad961a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988424819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3988424819
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3747453851
Short name T678
Test name
Test status
Simulation time 13658696 ps
CPU time 0.72 seconds
Started Jul 22 05:48:43 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 204976 kb
Host smart-7b268333-0b42-4c0b-b149-5c36ce9e422d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747453851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3747453851
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1347796860
Short name T859
Test name
Test status
Simulation time 109032999 ps
CPU time 4.21 seconds
Started Jul 22 05:48:45 PM PDT 24
Finished Jul 22 05:48:50 PM PDT 24
Peak memory 232808 kb
Host smart-a9a1f58c-35c7-434a-99bc-9183fc3d7da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347796860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1347796860
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1070087912
Short name T568
Test name
Test status
Simulation time 38404767 ps
CPU time 0.75 seconds
Started Jul 22 05:48:47 PM PDT 24
Finished Jul 22 05:48:48 PM PDT 24
Peak memory 206000 kb
Host smart-0c6925f7-152d-4f35-823b-c318e29e4abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070087912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1070087912
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.735826983
Short name T833
Test name
Test status
Simulation time 4232746754 ps
CPU time 18.57 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:49:07 PM PDT 24
Peak memory 234764 kb
Host smart-d6c59a21-28b5-4449-9d34-54aa448826eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735826983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.735826983
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.60266817
Short name T140
Test name
Test status
Simulation time 5014578401 ps
CPU time 115.15 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:50:46 PM PDT 24
Peak memory 265032 kb
Host smart-0d800247-489f-454c-b27d-270261aa69be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60266817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.60266817
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1242138917
Short name T608
Test name
Test status
Simulation time 2163946636 ps
CPU time 18.16 seconds
Started Jul 22 05:48:45 PM PDT 24
Finished Jul 22 05:49:04 PM PDT 24
Peak memory 249244 kb
Host smart-87167c2f-d9d8-4262-be63-295ae890c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242138917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1242138917
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4086810099
Short name T183
Test name
Test status
Simulation time 37585189697 ps
CPU time 285.3 seconds
Started Jul 22 05:48:47 PM PDT 24
Finished Jul 22 05:53:33 PM PDT 24
Peak memory 249328 kb
Host smart-f2234ca4-c1bf-48cf-bac5-c116af099a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086810099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4086810099
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3738199842
Short name T225
Test name
Test status
Simulation time 313581775 ps
CPU time 5.62 seconds
Started Jul 22 05:48:43 PM PDT 24
Finished Jul 22 05:48:50 PM PDT 24
Peak memory 224640 kb
Host smart-6e0b019b-69c5-4ed1-afae-cbb1369d3182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738199842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3738199842
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2991025843
Short name T685
Test name
Test status
Simulation time 629761007 ps
CPU time 3.64 seconds
Started Jul 22 05:48:45 PM PDT 24
Finished Jul 22 05:48:49 PM PDT 24
Peak memory 232788 kb
Host smart-f6a372d3-dcab-452f-960f-e71575f6a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991025843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2991025843
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1478209536
Short name T228
Test name
Test status
Simulation time 2792494970 ps
CPU time 13.51 seconds
Started Jul 22 05:48:44 PM PDT 24
Finished Jul 22 05:48:58 PM PDT 24
Peak memory 232856 kb
Host smart-9859eaff-4f80-4282-99c7-847bd2899f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478209536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1478209536
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1559298549
Short name T691
Test name
Test status
Simulation time 460653170 ps
CPU time 4.19 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:48:53 PM PDT 24
Peak memory 232784 kb
Host smart-721820f8-294e-469c-b84a-d07e0b512fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559298549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1559298549
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1061199551
Short name T812
Test name
Test status
Simulation time 254872427 ps
CPU time 5.39 seconds
Started Jul 22 05:48:47 PM PDT 24
Finished Jul 22 05:48:53 PM PDT 24
Peak memory 219028 kb
Host smart-4ce304b8-f3c7-437a-a268-78e890f09d0f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1061199551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1061199551
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2808066382
Short name T23
Test name
Test status
Simulation time 4121706804 ps
CPU time 49.28 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:49:38 PM PDT 24
Peak memory 255420 kb
Host smart-b9a31b69-d055-43b8-8f9a-a1098f8ddbf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808066382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2808066382
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1633648759
Short name T313
Test name
Test status
Simulation time 1292079802 ps
CPU time 12.55 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:49:03 PM PDT 24
Peak memory 216912 kb
Host smart-8c919c40-1f44-4aa1-9d36-1dab86435e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633648759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1633648759
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.126218522
Short name T939
Test name
Test status
Simulation time 1412495329 ps
CPU time 3.46 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 216400 kb
Host smart-76263dc9-27ed-4bd6-b056-b3e4f9bfb468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126218522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.126218522
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.18168556
Short name T894
Test name
Test status
Simulation time 393660678 ps
CPU time 2.58 seconds
Started Jul 22 05:48:41 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 216296 kb
Host smart-481894a1-2abc-4614-8691-352ab41ea48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18168556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.18168556
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2311713793
Short name T888
Test name
Test status
Simulation time 30279087 ps
CPU time 0.77 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 206128 kb
Host smart-d35830c8-e854-4ba2-b757-d46036498265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311713793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2311713793
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.887939856
Short name T788
Test name
Test status
Simulation time 5750533145 ps
CPU time 10.26 seconds
Started Jul 22 05:48:46 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 232816 kb
Host smart-ab3acf7c-81e3-42e8-86e7-daddf98eac7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887939856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.887939856
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.4061052007
Short name T344
Test name
Test status
Simulation time 33066646 ps
CPU time 0.75 seconds
Started Jul 22 05:48:56 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 205608 kb
Host smart-d1c07cb5-111d-414e-bd51-dc76b4a7d4d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061052007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
4061052007
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2553804058
Short name T848
Test name
Test status
Simulation time 400565808 ps
CPU time 2.42 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 224660 kb
Host smart-6a6e9844-9ef9-4af1-bf1c-dfa240064716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553804058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2553804058
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3875559688
Short name T701
Test name
Test status
Simulation time 19450977 ps
CPU time 0.79 seconds
Started Jul 22 05:48:42 PM PDT 24
Finished Jul 22 05:48:44 PM PDT 24
Peak memory 206668 kb
Host smart-1e4f0547-1a47-4ce4-a886-6692f8163443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875559688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3875559688
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1276599186
Short name T923
Test name
Test status
Simulation time 122862683 ps
CPU time 0.74 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:54 PM PDT 24
Peak memory 215892 kb
Host smart-b3a61739-0b09-468b-98fb-37e68456af11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276599186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1276599186
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.3955490168
Short name T627
Test name
Test status
Simulation time 38928952125 ps
CPU time 107.47 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:50:40 PM PDT 24
Peak memory 257208 kb
Host smart-3f61bc48-4e2f-4ee2-94a0-1f7833aedfd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955490168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.3955490168
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2520194571
Short name T670
Test name
Test status
Simulation time 11356573775 ps
CPU time 48.94 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 224836 kb
Host smart-226034c2-2ded-42f0-adc8-a44234ae486b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520194571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2520194571
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2956605559
Short name T569
Test name
Test status
Simulation time 425170618 ps
CPU time 4.62 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 224588 kb
Host smart-d0703136-0de2-42a5-92b1-a0517a094804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956605559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2956605559
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3736520231
Short name T673
Test name
Test status
Simulation time 17238355125 ps
CPU time 111.53 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:50:46 PM PDT 24
Peak memory 249276 kb
Host smart-1b4a056c-6d17-48bd-b0c9-98d5e9289bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736520231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3736520231
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3284862932
Short name T268
Test name
Test status
Simulation time 32405452679 ps
CPU time 41.23 seconds
Started Jul 22 05:48:47 PM PDT 24
Finished Jul 22 05:49:29 PM PDT 24
Peak memory 233176 kb
Host smart-ed9fa852-016f-4fd3-9853-8440f5a702bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284862932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3284862932
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.898769225
Short name T994
Test name
Test status
Simulation time 30059983073 ps
CPU time 76.61 seconds
Started Jul 22 05:48:41 PM PDT 24
Finished Jul 22 05:49:58 PM PDT 24
Peak memory 251972 kb
Host smart-23bf1ee4-f549-4c2e-9d17-ee214b00715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898769225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.898769225
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3202422157
Short name T376
Test name
Test status
Simulation time 135594465 ps
CPU time 2.51 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 232820 kb
Host smart-86976ec0-5d92-4272-a3bc-a96c05085b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202422157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3202422157
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2656656243
Short name T687
Test name
Test status
Simulation time 1146842747 ps
CPU time 6.35 seconds
Started Jul 22 05:48:46 PM PDT 24
Finished Jul 22 05:48:53 PM PDT 24
Peak memory 232940 kb
Host smart-492a9033-643d-48b0-b7db-b254c0b3bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656656243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2656656243
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.4190481449
Short name T914
Test name
Test status
Simulation time 2795714237 ps
CPU time 10.59 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:49:04 PM PDT 24
Peak memory 219592 kb
Host smart-3c3b23d4-b91e-4b3d-a25d-1fa0f5098fde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4190481449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.4190481449
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2892967884
Short name T896
Test name
Test status
Simulation time 53250156847 ps
CPU time 147.17 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:51:18 PM PDT 24
Peak memory 273604 kb
Host smart-002efda4-7fa5-46d8-8d22-9fbac760c534
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892967884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2892967884
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.4115299864
Short name T689
Test name
Test status
Simulation time 3991114571 ps
CPU time 24.9 seconds
Started Jul 22 05:49:15 PM PDT 24
Finished Jul 22 05:49:41 PM PDT 24
Peak memory 216468 kb
Host smart-40f50d4e-8102-43a2-8f52-05dba414fe21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115299864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.4115299864
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1001807393
Short name T759
Test name
Test status
Simulation time 752685971 ps
CPU time 2.87 seconds
Started Jul 22 05:48:48 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 216236 kb
Host smart-e98a7633-a393-4319-9010-cfac909f57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001807393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1001807393
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.141907960
Short name T737
Test name
Test status
Simulation time 108932921 ps
CPU time 4.55 seconds
Started Jul 22 05:49:18 PM PDT 24
Finished Jul 22 05:49:23 PM PDT 24
Peak memory 216372 kb
Host smart-d93d6e51-3c0f-47cd-a6ec-2d927ec9bbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141907960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.141907960
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.502307725
Short name T809
Test name
Test status
Simulation time 411660969 ps
CPU time 1.01 seconds
Started Jul 22 05:49:15 PM PDT 24
Finished Jul 22 05:49:17 PM PDT 24
Peak memory 206580 kb
Host smart-95b315da-8216-4a02-bdbb-ee9ba16eda57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502307725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.502307725
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.3272548521
Short name T857
Test name
Test status
Simulation time 738556602 ps
CPU time 4.13 seconds
Started Jul 22 05:48:43 PM PDT 24
Finished Jul 22 05:48:48 PM PDT 24
Peak memory 224644 kb
Host smart-af65f2f1-4e03-444e-a85e-ffb0d8ae6177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272548521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.3272548521
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.914641510
Short name T709
Test name
Test status
Simulation time 26114122 ps
CPU time 0.7 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:55 PM PDT 24
Peak memory 205596 kb
Host smart-de29c26e-4a77-4dc6-afa8-bae955050704
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914641510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.914641510
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3440306908
Short name T246
Test name
Test status
Simulation time 403320413 ps
CPU time 6.54 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:48:59 PM PDT 24
Peak memory 232948 kb
Host smart-8de23f43-39f6-4c2b-bae1-c2e21a44b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440306908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3440306908
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.273782573
Short name T545
Test name
Test status
Simulation time 24387787 ps
CPU time 0.8 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 206744 kb
Host smart-bb80ecf5-76a4-4c77-865d-290940c0095c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273782573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.273782573
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1881066299
Short name T431
Test name
Test status
Simulation time 75361591928 ps
CPU time 164.81 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:51:40 PM PDT 24
Peak memory 250492 kb
Host smart-0ac8fb10-e4de-45d8-95b3-7a73c034313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881066299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1881066299
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2295853310
Short name T614
Test name
Test status
Simulation time 151743541699 ps
CPU time 278.3 seconds
Started Jul 22 05:48:56 PM PDT 24
Finished Jul 22 05:53:35 PM PDT 24
Peak memory 253784 kb
Host smart-02952cfa-6073-475f-8d49-b8ad95d35270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295853310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2295853310
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.3383374405
Short name T604
Test name
Test status
Simulation time 1487999073 ps
CPU time 26.18 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:49:20 PM PDT 24
Peak memory 248704 kb
Host smart-bdfc5354-7ac3-43dc-a330-4fc479a60889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383374405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.3383374405
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.715649347
Short name T598
Test name
Test status
Simulation time 10995220706 ps
CPU time 40.35 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 249240 kb
Host smart-f55b266a-fe7f-4144-8b45-d839390ef289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715649347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.715649347
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.912192034
Short name T948
Test name
Test status
Simulation time 226426147716 ps
CPU time 187.47 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:51:58 PM PDT 24
Peak memory 255616 kb
Host smart-15dabee9-7f33-420b-a9fa-9350f85d1192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912192034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.912192034
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.378200117
Short name T495
Test name
Test status
Simulation time 421311827 ps
CPU time 6.3 seconds
Started Jul 22 05:48:58 PM PDT 24
Finished Jul 22 05:49:04 PM PDT 24
Peak memory 224652 kb
Host smart-e0be2455-dac5-4100-a815-bc950c0cd2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378200117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.378200117
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.986959559
Short name T543
Test name
Test status
Simulation time 882215006 ps
CPU time 8.75 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:49:04 PM PDT 24
Peak memory 224664 kb
Host smart-27739be1-065f-4c1a-99a7-4f3ee6c0b622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986959559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.986959559
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.4014456157
Short name T915
Test name
Test status
Simulation time 654869994 ps
CPU time 4.88 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:59 PM PDT 24
Peak memory 224664 kb
Host smart-97c0dc5b-09eb-4c5d-a85d-ecdf5c6d823c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014456157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.4014456157
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1081665640
Short name T243
Test name
Test status
Simulation time 33105480413 ps
CPU time 12.19 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:49:06 PM PDT 24
Peak memory 232916 kb
Host smart-86c83bda-1d9a-4326-813c-d817371b81e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081665640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1081665640
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.677747056
Short name T640
Test name
Test status
Simulation time 440060407 ps
CPU time 3.97 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 219384 kb
Host smart-681672b1-c639-4477-a77f-cf3d1a71751d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=677747056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dire
ct.677747056
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2279296429
Short name T21
Test name
Test status
Simulation time 10881790913 ps
CPU time 72.41 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:50:08 PM PDT 24
Peak memory 254980 kb
Host smart-a147f785-c49a-4b08-8ea6-78f286b410b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279296429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2279296429
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1138292257
Short name T911
Test name
Test status
Simulation time 14394399495 ps
CPU time 43.24 seconds
Started Jul 22 05:48:55 PM PDT 24
Finished Jul 22 05:49:39 PM PDT 24
Peak memory 216456 kb
Host smart-bf59568b-0ffa-4b3e-9912-7226edc00a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138292257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1138292257
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.4233473373
Short name T938
Test name
Test status
Simulation time 1686673720 ps
CPU time 6.1 seconds
Started Jul 22 05:48:51 PM PDT 24
Finished Jul 22 05:48:58 PM PDT 24
Peak memory 216380 kb
Host smart-52d7d503-88c0-47a3-ba7e-ab6e801422d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233473373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.4233473373
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.794717705
Short name T320
Test name
Test status
Simulation time 15931248 ps
CPU time 0.85 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:48:53 PM PDT 24
Peak memory 206164 kb
Host smart-e8690698-aaf8-4606-a323-98e367981ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794717705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.794717705
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.992392906
Short name T790
Test name
Test status
Simulation time 88390486 ps
CPU time 0.77 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:54 PM PDT 24
Peak memory 206108 kb
Host smart-733d6a65-2775-4b15-bb1e-ae286ab6aa0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992392906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.992392906
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.3427829613
Short name T373
Test name
Test status
Simulation time 1592705458 ps
CPU time 5.91 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 224688 kb
Host smart-429b191e-a900-4496-8777-42e014992874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427829613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.3427829613
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3873346813
Short name T874
Test name
Test status
Simulation time 14947758 ps
CPU time 0.73 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:07 PM PDT 24
Peak memory 205028 kb
Host smart-8df077df-8c8e-48c3-984a-67c215089083
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873346813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3873346813
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.4123744295
Short name T390
Test name
Test status
Simulation time 32126933 ps
CPU time 2.48 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 232804 kb
Host smart-286dafa6-7e88-4ff3-b269-6c383f08b33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123744295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.4123744295
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3636380786
Short name T585
Test name
Test status
Simulation time 73805305 ps
CPU time 0.76 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:48:56 PM PDT 24
Peak memory 206708 kb
Host smart-c934b172-f00d-4099-a02e-edd9bbbafbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636380786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3636380786
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2788584097
Short name T291
Test name
Test status
Simulation time 10179684413 ps
CPU time 46.54 seconds
Started Jul 22 05:48:49 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 255800 kb
Host smart-60223faf-e7cc-4111-bef1-a5dd5b734e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788584097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2788584097
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1879785861
Short name T201
Test name
Test status
Simulation time 3260802468 ps
CPU time 83.35 seconds
Started Jul 22 05:48:55 PM PDT 24
Finished Jul 22 05:50:19 PM PDT 24
Peak memory 255752 kb
Host smart-475e6306-b78a-49e1-8877-fc1f35107d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879785861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1879785861
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3771607171
Short name T872
Test name
Test status
Simulation time 679228367 ps
CPU time 7.91 seconds
Started Jul 22 05:48:58 PM PDT 24
Finished Jul 22 05:49:06 PM PDT 24
Peak memory 232760 kb
Host smart-f2315c54-8423-46d2-8fa4-b63e35251c0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771607171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3771607171
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.826338829
Short name T282
Test name
Test status
Simulation time 1757301872 ps
CPU time 23.52 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:49:16 PM PDT 24
Peak memory 252380 kb
Host smart-30948cba-e2b3-4cdf-a6fc-e6f1732c3599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826338829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.826338829
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3485840446
Short name T596
Test name
Test status
Simulation time 8921398872 ps
CPU time 23.47 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:49:17 PM PDT 24
Peak memory 224660 kb
Host smart-c09b2c2e-4baa-42b9-ba23-76ab585a1658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485840446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3485840446
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.281231776
Short name T969
Test name
Test status
Simulation time 162503565 ps
CPU time 5.43 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 224696 kb
Host smart-a7641a55-84a2-4d59-a141-ce1e69008691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281231776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.281231776
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4279005822
Short name T220
Test name
Test status
Simulation time 6127119423 ps
CPU time 10.99 seconds
Started Jul 22 05:48:50 PM PDT 24
Finished Jul 22 05:49:01 PM PDT 24
Peak memory 248952 kb
Host smart-777a2254-1d0e-4e5a-a346-2ac76670c899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279005822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4279005822
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1092783580
Short name T760
Test name
Test status
Simulation time 131929644 ps
CPU time 2.08 seconds
Started Jul 22 05:48:55 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 224564 kb
Host smart-3698c908-b3a9-4037-8971-5930909386f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092783580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1092783580
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1397390783
Short name T363
Test name
Test status
Simulation time 6130768579 ps
CPU time 13.14 seconds
Started Jul 22 05:48:52 PM PDT 24
Finished Jul 22 05:49:06 PM PDT 24
Peak memory 220216 kb
Host smart-95f0370e-2582-4fb4-8422-a5e8ef47bd35
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1397390783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1397390783
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3659249532
Short name T222
Test name
Test status
Simulation time 166779410620 ps
CPU time 311.06 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:54:17 PM PDT 24
Peak memory 255280 kb
Host smart-99bff2a2-7e29-4b5e-83b2-01e495e14aba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659249532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3659249532
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3664629187
Short name T380
Test name
Test status
Simulation time 1793176311 ps
CPU time 3.19 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:57 PM PDT 24
Peak memory 216400 kb
Host smart-768fc748-f337-48f5-9b06-b1803be42f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664629187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3664629187
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1902150531
Short name T837
Test name
Test status
Simulation time 4940151363 ps
CPU time 4.69 seconds
Started Jul 22 05:48:55 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 217520 kb
Host smart-e1c84f8c-b7e3-4e91-907b-8fed0caf661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902150531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1902150531
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2920589107
Short name T367
Test name
Test status
Simulation time 1314318204 ps
CPU time 1.93 seconds
Started Jul 22 05:48:53 PM PDT 24
Finished Jul 22 05:48:56 PM PDT 24
Peak memory 216456 kb
Host smart-1cc11267-a116-4708-80dc-a2269781eced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920589107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2920589107
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2792714647
Short name T898
Test name
Test status
Simulation time 18356704 ps
CPU time 0.74 seconds
Started Jul 22 05:48:54 PM PDT 24
Finished Jul 22 05:48:56 PM PDT 24
Peak memory 206096 kb
Host smart-c012bede-9e47-493a-92d0-fbeccf3b6d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792714647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2792714647
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.635771531
Short name T330
Test name
Test status
Simulation time 114180764177 ps
CPU time 21.63 seconds
Started Jul 22 05:48:51 PM PDT 24
Finished Jul 22 05:49:13 PM PDT 24
Peak memory 237496 kb
Host smart-a8e1738a-dafc-49c2-af9d-7ef1d3dd143a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635771531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.635771531
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.137641664
Short name T808
Test name
Test status
Simulation time 17746145 ps
CPU time 0.74 seconds
Started Jul 22 05:49:07 PM PDT 24
Finished Jul 22 05:49:08 PM PDT 24
Peak memory 205868 kb
Host smart-de3efc61-9ee2-4822-ad41-cc30a4e5dad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137641664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.137641664
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.885837588
Short name T690
Test name
Test status
Simulation time 296183255 ps
CPU time 2.87 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:49:10 PM PDT 24
Peak memory 232892 kb
Host smart-36398ea0-ebee-40b5-a9af-e0178d030cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885837588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.885837588
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.663994058
Short name T946
Test name
Test status
Simulation time 54086831 ps
CPU time 0.83 seconds
Started Jul 22 05:49:03 PM PDT 24
Finished Jul 22 05:49:04 PM PDT 24
Peak memory 206740 kb
Host smart-bb0690cd-1b32-418c-af5e-6e76aa0aeb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663994058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.663994058
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3407723883
Short name T552
Test name
Test status
Simulation time 13495967194 ps
CPU time 138.38 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:51:24 PM PDT 24
Peak memory 257728 kb
Host smart-310ea7e6-5730-4e41-9eb1-e12211105e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407723883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3407723883
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1455056011
Short name T494
Test name
Test status
Simulation time 21766827463 ps
CPU time 114.94 seconds
Started Jul 22 05:49:00 PM PDT 24
Finished Jul 22 05:50:55 PM PDT 24
Peak memory 267740 kb
Host smart-a479c30d-d2b7-4e69-896d-29849a0d6b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455056011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1455056011
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1395039392
Short name T927
Test name
Test status
Simulation time 6267505021 ps
CPU time 29.05 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 240972 kb
Host smart-acc34bd2-f152-4f99-85f3-4ec2310da26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395039392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1395039392
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1527471544
Short name T275
Test name
Test status
Simulation time 91657818528 ps
CPU time 252.98 seconds
Started Jul 22 05:49:08 PM PDT 24
Finished Jul 22 05:53:21 PM PDT 24
Peak memory 264520 kb
Host smart-759c7b91-9e8f-48a8-8923-78d184d8ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527471544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1527471544
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1162611707
Short name T563
Test name
Test status
Simulation time 2370390365 ps
CPU time 27.54 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 224724 kb
Host smart-e5c7a8f1-7ac7-4c3f-8ae3-a86d21dcafa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162611707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1162611707
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.203681580
Short name T58
Test name
Test status
Simulation time 135205270 ps
CPU time 5.43 seconds
Started Jul 22 05:49:01 PM PDT 24
Finished Jul 22 05:49:07 PM PDT 24
Peak memory 232868 kb
Host smart-38574d38-fc3f-486a-8960-4c4b6b2c6240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203681580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.203681580
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2087772681
Short name T735
Test name
Test status
Simulation time 2367782210 ps
CPU time 7.76 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:14 PM PDT 24
Peak memory 232904 kb
Host smart-4a98b4e4-b414-4c2d-a4c5-f96dc1630668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087772681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2087772681
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.20107009
Short name T648
Test name
Test status
Simulation time 489526428 ps
CPU time 4.64 seconds
Started Jul 22 05:49:03 PM PDT 24
Finished Jul 22 05:49:08 PM PDT 24
Peak memory 224708 kb
Host smart-e73dae03-8515-4994-8fbe-e13493cb85ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20107009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.20107009
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3504140858
Short name T484
Test name
Test status
Simulation time 186955854 ps
CPU time 3.98 seconds
Started Jul 22 05:49:07 PM PDT 24
Finished Jul 22 05:49:12 PM PDT 24
Peak memory 219064 kb
Host smart-c07f0031-9db4-4377-830f-3aa6b14d2376
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3504140858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3504140858
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2381274648
Short name T158
Test name
Test status
Simulation time 71465733 ps
CPU time 1.1 seconds
Started Jul 22 05:49:04 PM PDT 24
Finished Jul 22 05:49:06 PM PDT 24
Peak memory 207848 kb
Host smart-41a66594-754a-46ad-80ec-31eb0651b731
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381274648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2381274648
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.974384730
Short name T308
Test name
Test status
Simulation time 11360429500 ps
CPU time 21.33 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:27 PM PDT 24
Peak memory 220212 kb
Host smart-97db9ea4-de1f-4cc6-9bbc-5ba284c28fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974384730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.974384730
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1819084442
Short name T880
Test name
Test status
Simulation time 1256748573 ps
CPU time 4.55 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:10 PM PDT 24
Peak memory 216360 kb
Host smart-cddcef76-552f-4e30-9443-f0c6cd22524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819084442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1819084442
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.468685888
Short name T357
Test name
Test status
Simulation time 15060312 ps
CPU time 0.79 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:49:08 PM PDT 24
Peak memory 206132 kb
Host smart-0526ba82-ea42-41ab-9e97-5aa455128fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468685888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.468685888
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.56484132
Short name T4
Test name
Test status
Simulation time 817832105 ps
CPU time 1.01 seconds
Started Jul 22 05:49:01 PM PDT 24
Finished Jul 22 05:49:02 PM PDT 24
Peak memory 207336 kb
Host smart-842cb843-c456-4bf8-923c-dfb5f033fbae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56484132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.56484132
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1281000250
Short name T253
Test name
Test status
Simulation time 236797839 ps
CPU time 6.7 seconds
Started Jul 22 05:49:04 PM PDT 24
Finished Jul 22 05:49:12 PM PDT 24
Peak memory 232844 kb
Host smart-be3e75eb-37d4-4262-a482-eb2457ae4238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281000250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1281000250
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.200891585
Short name T926
Test name
Test status
Simulation time 23609969 ps
CPU time 0.74 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:47:49 PM PDT 24
Peak memory 205040 kb
Host smart-4fd1b667-0ca7-409f-8068-5ab976961ace
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200891585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.200891585
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.4210189611
Short name T466
Test name
Test status
Simulation time 2801532049 ps
CPU time 11.66 seconds
Started Jul 22 05:47:32 PM PDT 24
Finished Jul 22 05:47:44 PM PDT 24
Peak memory 232940 kb
Host smart-774bb0e9-1be5-409a-b762-467942b6ad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210189611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.4210189611
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1351848481
Short name T420
Test name
Test status
Simulation time 40932656 ps
CPU time 0.78 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:29 PM PDT 24
Peak memory 206772 kb
Host smart-d9199619-42fa-455b-a2bd-4c4c4bdf0216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351848481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1351848481
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.667039748
Short name T501
Test name
Test status
Simulation time 4148273042 ps
CPU time 42.61 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:48:14 PM PDT 24
Peak memory 249392 kb
Host smart-711264c3-5b22-421c-8246-f4cdd866d4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667039748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.667039748
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2505883599
Short name T580
Test name
Test status
Simulation time 21396814114 ps
CPU time 152.96 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:50:20 PM PDT 24
Peak memory 257596 kb
Host smart-0b40e620-b8b3-45ff-a3e3-849e1063900f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505883599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2505883599
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1547211076
Short name T178
Test name
Test status
Simulation time 11219283608 ps
CPU time 113.8 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 256096 kb
Host smart-507a5174-5f18-46cc-b1bd-a9cdee9bcb78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547211076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1547211076
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.494580355
Short name T500
Test name
Test status
Simulation time 3249270060 ps
CPU time 20.96 seconds
Started Jul 22 05:47:32 PM PDT 24
Finished Jul 22 05:47:53 PM PDT 24
Peak memory 232972 kb
Host smart-b3918836-bd0b-4054-acbb-096a304d37ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494580355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.494580355
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2213720077
Short name T283
Test name
Test status
Simulation time 14486400424 ps
CPU time 102.42 seconds
Started Jul 22 05:47:29 PM PDT 24
Finished Jul 22 05:49:12 PM PDT 24
Peak memory 249332 kb
Host smart-2abc200e-56b6-4a2b-a288-b05cde69df45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213720077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2213720077
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3871206832
Short name T365
Test name
Test status
Simulation time 48129622 ps
CPU time 2.74 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:47:34 PM PDT 24
Peak memory 232852 kb
Host smart-e18778b3-1f1d-470d-8795-b98a996d587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871206832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3871206832
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3629165321
Short name T657
Test name
Test status
Simulation time 38501329720 ps
CPU time 85.34 seconds
Started Jul 22 05:47:30 PM PDT 24
Finished Jul 22 05:48:56 PM PDT 24
Peak memory 234984 kb
Host smart-28a07c13-2a9f-40ad-9a85-c5a687ce72b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629165321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3629165321
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.763950149
Short name T6
Test name
Test status
Simulation time 850972436 ps
CPU time 7.08 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:36 PM PDT 24
Peak memory 232816 kb
Host smart-e4adc093-6330-4a8b-9ceb-cc36c942ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763950149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
763950149
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4206665110
Short name T611
Test name
Test status
Simulation time 397831328 ps
CPU time 4.71 seconds
Started Jul 22 05:47:29 PM PDT 24
Finished Jul 22 05:47:34 PM PDT 24
Peak memory 232824 kb
Host smart-c308fc05-8af7-415e-91ea-bc780e5e153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206665110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4206665110
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2380762367
Short name T756
Test name
Test status
Simulation time 1066263436 ps
CPU time 11.55 seconds
Started Jul 22 05:47:28 PM PDT 24
Finished Jul 22 05:47:40 PM PDT 24
Peak memory 222232 kb
Host smart-27ffddef-36e1-43ff-961b-a8df4dc99220
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380762367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2380762367
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3539665012
Short name T71
Test name
Test status
Simulation time 129622538 ps
CPU time 1.05 seconds
Started Jul 22 05:47:46 PM PDT 24
Finished Jul 22 05:47:48 PM PDT 24
Peak memory 235820 kb
Host smart-e15eff84-d01d-47c3-b6e2-0457c9bbbf7c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539665012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3539665012
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1443002480
Short name T86
Test name
Test status
Simulation time 109722716152 ps
CPU time 256.92 seconds
Started Jul 22 05:47:41 PM PDT 24
Finished Jul 22 05:51:58 PM PDT 24
Peak memory 256500 kb
Host smart-281ad78a-b540-46e6-b93b-5203ec9c606f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443002480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1443002480
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3535300312
Short name T668
Test name
Test status
Simulation time 5072641914 ps
CPU time 32.24 seconds
Started Jul 22 05:47:30 PM PDT 24
Finished Jul 22 05:48:03 PM PDT 24
Peak memory 216476 kb
Host smart-2b28e0a8-d132-4c3e-aa14-f83aeea4300f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535300312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3535300312
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.3836257464
Short name T91
Test name
Test status
Simulation time 761162560 ps
CPU time 3.89 seconds
Started Jul 22 05:47:31 PM PDT 24
Finished Jul 22 05:47:35 PM PDT 24
Peak memory 216408 kb
Host smart-ea9dc38e-ebfc-4823-b509-e10afe299eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836257464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.3836257464
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3236726459
Short name T335
Test name
Test status
Simulation time 13890467 ps
CPU time 0.81 seconds
Started Jul 22 05:47:29 PM PDT 24
Finished Jul 22 05:47:31 PM PDT 24
Peak memory 206680 kb
Host smart-909ef7c7-0dd6-433f-8f02-762dcf80de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236726459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3236726459
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4214549809
Short name T740
Test name
Test status
Simulation time 47603623 ps
CPU time 0.81 seconds
Started Jul 22 05:47:30 PM PDT 24
Finished Jul 22 05:47:31 PM PDT 24
Peak memory 206080 kb
Host smart-a51aefbb-d515-4d71-916b-715ceb8fa07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214549809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4214549809
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3920653649
Short name T423
Test name
Test status
Simulation time 1299523610 ps
CPU time 6.75 seconds
Started Jul 22 05:47:34 PM PDT 24
Finished Jul 22 05:47:41 PM PDT 24
Peak memory 239420 kb
Host smart-befb02de-cb8b-4434-997c-89541a17f8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920653649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3920653649
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2871945751
Short name T732
Test name
Test status
Simulation time 15547167 ps
CPU time 0.78 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:49:50 PM PDT 24
Peak memory 205596 kb
Host smart-4fa45c06-fa9f-460b-a29c-d6ca16fa09af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871945751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2871945751
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.731327261
Short name T537
Test name
Test status
Simulation time 4338681708 ps
CPU time 41.7 seconds
Started Jul 22 05:49:02 PM PDT 24
Finished Jul 22 05:49:44 PM PDT 24
Peak memory 224708 kb
Host smart-1fec9546-4bb3-487c-be16-25d7c4a8ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731327261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.731327261
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2753581066
Short name T412
Test name
Test status
Simulation time 79922895 ps
CPU time 0.81 seconds
Started Jul 22 05:49:04 PM PDT 24
Finished Jul 22 05:49:05 PM PDT 24
Peak memory 206700 kb
Host smart-bb0b6f3b-eccd-4fcb-99a6-3de48f67ccaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753581066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2753581066
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3384574733
Short name T468
Test name
Test status
Simulation time 30165931196 ps
CPU time 130.4 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:51:17 PM PDT 24
Peak memory 249288 kb
Host smart-fa3f8354-27d8-4721-af55-0eaf3352bc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384574733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3384574733
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.2338308725
Short name T745
Test name
Test status
Simulation time 2830869258 ps
CPU time 16.46 seconds
Started Jul 22 05:49:16 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 235744 kb
Host smart-e49a5dfb-e111-4ff8-b95c-55b6a1d485e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338308725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.2338308725
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3821873748
Short name T301
Test name
Test status
Simulation time 4305619674 ps
CPU time 9.17 seconds
Started Jul 22 05:49:03 PM PDT 24
Finished Jul 22 05:49:13 PM PDT 24
Peak memory 232948 kb
Host smart-2408e118-e738-4e9d-904f-90cd6c1647dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821873748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3821873748
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.3196781873
Short name T162
Test name
Test status
Simulation time 9882891869 ps
CPU time 68.9 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:50:16 PM PDT 24
Peak memory 241024 kb
Host smart-64c955ea-051b-498c-a1cd-091b9ab91f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196781873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.3196781873
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.17102115
Short name T638
Test name
Test status
Simulation time 3783450495 ps
CPU time 17.95 seconds
Started Jul 22 05:49:08 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 232888 kb
Host smart-0c91d7cd-8c80-4940-9ad5-edebc391cb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17102115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.17102115
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1138613620
Short name T442
Test name
Test status
Simulation time 27158704691 ps
CPU time 50.81 seconds
Started Jul 22 05:49:03 PM PDT 24
Finished Jul 22 05:49:55 PM PDT 24
Peak memory 224756 kb
Host smart-05879c63-d4fb-4a15-bfba-7ee0e1e58fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138613620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1138613620
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2011294752
Short name T964
Test name
Test status
Simulation time 388791834 ps
CPU time 5.7 seconds
Started Jul 22 05:49:25 PM PDT 24
Finished Jul 22 05:49:31 PM PDT 24
Peak memory 224688 kb
Host smart-78940f05-1389-40b1-99b6-d1ed9e0a99a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011294752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2011294752
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.430691896
Short name T606
Test name
Test status
Simulation time 9002852130 ps
CPU time 9.45 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:49:16 PM PDT 24
Peak memory 241008 kb
Host smart-4b5f13b2-2b1a-4947-947a-2cb4306b8cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430691896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.430691896
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3730204071
Short name T148
Test name
Test status
Simulation time 1217540363 ps
CPU time 7.64 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:14 PM PDT 24
Peak memory 220808 kb
Host smart-d5ae7925-e925-4062-a183-b6fc26fd16ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3730204071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3730204071
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1088365076
Short name T57
Test name
Test status
Simulation time 12697893087 ps
CPU time 155.6 seconds
Started Jul 22 05:49:12 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 254976 kb
Host smart-40670eaa-5bc1-42ec-aee3-0b5bf5dc1de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088365076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1088365076
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3344253897
Short name T465
Test name
Test status
Simulation time 3039299325 ps
CPU time 4.92 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:49:12 PM PDT 24
Peak memory 216576 kb
Host smart-ad0b2de2-ae35-43a5-b831-f9dc818b9528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344253897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3344253897
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.674393206
Short name T449
Test name
Test status
Simulation time 942445084 ps
CPU time 5.89 seconds
Started Jul 22 05:49:06 PM PDT 24
Finished Jul 22 05:49:13 PM PDT 24
Peak memory 216428 kb
Host smart-07d0542b-f05f-43ec-a675-06020d554bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674393206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.674393206
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1117158792
Short name T331
Test name
Test status
Simulation time 35495220 ps
CPU time 1.59 seconds
Started Jul 22 05:49:03 PM PDT 24
Finished Jul 22 05:49:05 PM PDT 24
Peak memory 217396 kb
Host smart-e2afe30a-93a9-47ae-9de6-e9e7672c0611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117158792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1117158792
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1576960330
Short name T712
Test name
Test status
Simulation time 64407235 ps
CPU time 0.82 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:06 PM PDT 24
Peak memory 206116 kb
Host smart-6e88a165-a675-4a56-9465-02f1dfb4623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576960330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1576960330
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.1899772156
Short name T25
Test name
Test status
Simulation time 9539157519 ps
CPU time 32.45 seconds
Started Jul 22 05:49:05 PM PDT 24
Finished Jul 22 05:49:38 PM PDT 24
Peak memory 251092 kb
Host smart-b2144a7e-4250-434a-97ac-8f2a67284280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899772156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.1899772156
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2891330063
Short name T771
Test name
Test status
Simulation time 43180192 ps
CPU time 0.72 seconds
Started Jul 22 05:49:11 PM PDT 24
Finished Jul 22 05:49:12 PM PDT 24
Peak memory 205532 kb
Host smart-01ca5295-f986-44a2-9719-8e4c20650c6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891330063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2891330063
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2782112925
Short name T947
Test name
Test status
Simulation time 115353965 ps
CPU time 3.83 seconds
Started Jul 22 05:49:44 PM PDT 24
Finished Jul 22 05:49:49 PM PDT 24
Peak memory 224616 kb
Host smart-68fe1c0e-d3d1-4979-9dde-5b11ace1f0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782112925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2782112925
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.982932290
Short name T643
Test name
Test status
Simulation time 21714866 ps
CPU time 0.76 seconds
Started Jul 22 05:49:12 PM PDT 24
Finished Jul 22 05:49:13 PM PDT 24
Peak memory 207060 kb
Host smart-61367520-8c08-4ec1-a2c0-bf46566434ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982932290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.982932290
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.154098077
Short name T844
Test name
Test status
Simulation time 3198243206 ps
CPU time 26.81 seconds
Started Jul 22 05:49:20 PM PDT 24
Finished Jul 22 05:49:48 PM PDT 24
Peak memory 238280 kb
Host smart-00561473-bb7a-49a8-9528-7acb04545bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154098077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.154098077
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2448409283
Short name T460
Test name
Test status
Simulation time 3343290048 ps
CPU time 19.52 seconds
Started Jul 22 05:49:19 PM PDT 24
Finished Jul 22 05:49:39 PM PDT 24
Peak memory 238696 kb
Host smart-753fcc57-9e94-486f-bf58-5b0cedc10196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448409283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2448409283
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1763121401
Short name T40
Test name
Test status
Simulation time 59210681277 ps
CPU time 195.27 seconds
Started Jul 22 05:49:09 PM PDT 24
Finished Jul 22 05:52:25 PM PDT 24
Peak memory 256000 kb
Host smart-384237bb-d1f4-4595-915d-e869b3cb60d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763121401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1763121401
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.2167408311
Short name T605
Test name
Test status
Simulation time 3326040446 ps
CPU time 14.38 seconds
Started Jul 22 05:49:13 PM PDT 24
Finished Jul 22 05:49:28 PM PDT 24
Peak memory 232892 kb
Host smart-1bec1024-91af-4abe-a352-67e3eb0eaf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167408311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.2167408311
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.36212281
Short name T482
Test name
Test status
Simulation time 3518343399 ps
CPU time 31.66 seconds
Started Jul 22 05:49:17 PM PDT 24
Finished Jul 22 05:49:49 PM PDT 24
Peak memory 234504 kb
Host smart-25a27d1b-2bd2-4cf9-b5b1-2ff46cec6003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36212281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.36212281
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3695064759
Short name T182
Test name
Test status
Simulation time 177923246 ps
CPU time 3.43 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:49:53 PM PDT 24
Peak memory 224716 kb
Host smart-2cd2c007-461c-4358-88c9-d9e40e90f062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695064759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3695064759
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3355688943
Short name T1000
Test name
Test status
Simulation time 26935122012 ps
CPU time 40.61 seconds
Started Jul 22 05:49:16 PM PDT 24
Finished Jul 22 05:49:57 PM PDT 24
Peak memory 239436 kb
Host smart-969c3ba7-3247-4d32-a560-88b0ddf362d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355688943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3355688943
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.398402219
Short name T82
Test name
Test status
Simulation time 15111926479 ps
CPU time 36.26 seconds
Started Jul 22 05:49:10 PM PDT 24
Finished Jul 22 05:49:46 PM PDT 24
Peak memory 232836 kb
Host smart-14968035-1df2-4ba6-89a4-7302ca53fbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398402219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.398402219
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2289340020
Short name T683
Test name
Test status
Simulation time 883794075 ps
CPU time 10 seconds
Started Jul 22 05:49:44 PM PDT 24
Finished Jul 22 05:49:55 PM PDT 24
Peak memory 241072 kb
Host smart-3da7339b-77c6-4636-bb14-f3d75f9cb580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289340020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2289340020
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2023615602
Short name T360
Test name
Test status
Simulation time 9282010375 ps
CPU time 10.41 seconds
Started Jul 22 05:49:18 PM PDT 24
Finished Jul 22 05:49:29 PM PDT 24
Peak memory 222288 kb
Host smart-a063a7f5-02e7-4e62-91ee-d4bb5d712389
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2023615602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2023615602
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2710888594
Short name T157
Test name
Test status
Simulation time 55095036568 ps
CPU time 468.89 seconds
Started Jul 22 05:49:14 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 266296 kb
Host smart-11fe4827-e183-4249-993d-47ffaa206f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710888594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2710888594
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.3985191657
Short name T628
Test name
Test status
Simulation time 5051807890 ps
CPU time 27.94 seconds
Started Jul 22 05:49:20 PM PDT 24
Finished Jul 22 05:49:49 PM PDT 24
Peak memory 216464 kb
Host smart-020ac544-9248-48f7-b537-4bdf23e8b424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985191657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.3985191657
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3219276243
Short name T307
Test name
Test status
Simulation time 549141404 ps
CPU time 2.46 seconds
Started Jul 22 05:49:19 PM PDT 24
Finished Jul 22 05:49:22 PM PDT 24
Peak memory 216452 kb
Host smart-58be2583-559c-4a8c-910c-1df87850487d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219276243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3219276243
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3787552734
Short name T700
Test name
Test status
Simulation time 588460320 ps
CPU time 2.17 seconds
Started Jul 22 05:49:16 PM PDT 24
Finished Jul 22 05:49:18 PM PDT 24
Peak memory 216476 kb
Host smart-d6bbaf71-0440-4e4b-b79f-682248c6bc30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787552734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3787552734
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.4143051551
Short name T932
Test name
Test status
Simulation time 107947000 ps
CPU time 1.01 seconds
Started Jul 22 05:49:43 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 206076 kb
Host smart-d9d037d7-561c-4583-8450-8b3699258192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143051551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.4143051551
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.72023942
Short name T871
Test name
Test status
Simulation time 41153052259 ps
CPU time 35.58 seconds
Started Jul 22 05:49:44 PM PDT 24
Finished Jul 22 05:50:21 PM PDT 24
Peak memory 232896 kb
Host smart-1674acb8-0c06-4ef8-af78-f5966eb227aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72023942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.72023942
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2574714410
Short name T341
Test name
Test status
Simulation time 51497314 ps
CPU time 0.73 seconds
Started Jul 22 05:49:19 PM PDT 24
Finished Jul 22 05:49:20 PM PDT 24
Peak memory 205600 kb
Host smart-02dd8cfe-a1a1-4424-940d-fba4210337f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574714410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2574714410
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.142339768
Short name T633
Test name
Test status
Simulation time 54697303 ps
CPU time 2.54 seconds
Started Jul 22 05:49:17 PM PDT 24
Finished Jul 22 05:49:20 PM PDT 24
Peak memory 232140 kb
Host smart-e1ad78fe-f238-48b0-8657-d2285a8aa872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142339768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.142339768
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1197922959
Short name T962
Test name
Test status
Simulation time 242645218 ps
CPU time 0.84 seconds
Started Jul 22 05:49:20 PM PDT 24
Finished Jul 22 05:49:22 PM PDT 24
Peak memory 206748 kb
Host smart-e6795327-9647-4a26-bcb3-3602947e482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197922959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1197922959
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.543453439
Short name T284
Test name
Test status
Simulation time 151333654658 ps
CPU time 529.74 seconds
Started Jul 22 05:49:17 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 272984 kb
Host smart-01ca34bc-6cfb-448f-8b08-1040a3eeb809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543453439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.543453439
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2763203624
Short name T723
Test name
Test status
Simulation time 48338321236 ps
CPU time 205.07 seconds
Started Jul 22 05:49:14 PM PDT 24
Finished Jul 22 05:52:40 PM PDT 24
Peak memory 257604 kb
Host smart-bb8c97a1-8599-4ca3-ba35-5be38c50e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763203624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2763203624
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4050472145
Short name T893
Test name
Test status
Simulation time 24352199201 ps
CPU time 97.49 seconds
Started Jul 22 05:49:14 PM PDT 24
Finished Jul 22 05:50:52 PM PDT 24
Peak memory 240236 kb
Host smart-2a9eceb8-0fe7-43ec-934e-c512a8e4303b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050472145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4050472145
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.4119083171
Short name T981
Test name
Test status
Simulation time 8420538580 ps
CPU time 63.99 seconds
Started Jul 22 05:49:19 PM PDT 24
Finished Jul 22 05:50:24 PM PDT 24
Peak memory 249352 kb
Host smart-67676720-28fe-4769-b00b-d2fd35a70458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119083171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.4119083171
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.4259956072
Short name T665
Test name
Test status
Simulation time 131385638 ps
CPU time 4.7 seconds
Started Jul 22 05:49:16 PM PDT 24
Finished Jul 22 05:49:21 PM PDT 24
Peak memory 224712 kb
Host smart-be1ac6ea-6f49-42a9-a4a0-aa7d356ead2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259956072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.4259956072
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3870307804
Short name T232
Test name
Test status
Simulation time 10241969833 ps
CPU time 14.8 seconds
Started Jul 22 05:49:44 PM PDT 24
Finished Jul 22 05:50:00 PM PDT 24
Peak memory 233904 kb
Host smart-e337ffec-4e7a-41d2-b89e-dd05df47db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870307804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3870307804
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1692454041
Short name T974
Test name
Test status
Simulation time 7512115729 ps
CPU time 12.96 seconds
Started Jul 22 05:49:13 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 224636 kb
Host smart-c1aa23dc-8726-4ead-99d6-a28287ff2182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692454041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1692454041
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.21894363
Short name T200
Test name
Test status
Simulation time 1221493839 ps
CPU time 4.35 seconds
Started Jul 22 05:49:12 PM PDT 24
Finished Jul 22 05:49:17 PM PDT 24
Peak memory 218988 kb
Host smart-5e66851b-f884-4de0-836f-0c3f70a31c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21894363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.21894363
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1925245181
Short name T426
Test name
Test status
Simulation time 192564295 ps
CPU time 4.36 seconds
Started Jul 22 05:49:12 PM PDT 24
Finished Jul 22 05:49:17 PM PDT 24
Peak memory 223256 kb
Host smart-1110b947-78e1-4e08-bffa-5d09b6d3eb6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1925245181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1925245181
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2863845437
Short name T972
Test name
Test status
Simulation time 153658650 ps
CPU time 0.9 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:49:50 PM PDT 24
Peak memory 205876 kb
Host smart-b0c13cc3-6269-4abd-807e-f378b52b2ae0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863845437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2863845437
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.282857758
Short name T854
Test name
Test status
Simulation time 34172044193 ps
CPU time 41.95 seconds
Started Jul 22 05:49:13 PM PDT 24
Finished Jul 22 05:49:55 PM PDT 24
Peak memory 216396 kb
Host smart-8be6b606-b235-413e-bf91-a607329dd70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282857758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.282857758
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3699869773
Short name T746
Test name
Test status
Simulation time 434005205 ps
CPU time 3.6 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:49:53 PM PDT 24
Peak memory 216436 kb
Host smart-c9776ee9-4636-4ab5-bea9-0bc58064d8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699869773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3699869773
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2608701497
Short name T913
Test name
Test status
Simulation time 17770699 ps
CPU time 1.11 seconds
Started Jul 22 05:49:17 PM PDT 24
Finished Jul 22 05:49:18 PM PDT 24
Peak memory 208000 kb
Host smart-ade00990-61d7-4df5-9dab-d0956d35c7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608701497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2608701497
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2876583913
Short name T436
Test name
Test status
Simulation time 460732187 ps
CPU time 0.99 seconds
Started Jul 22 05:49:13 PM PDT 24
Finished Jul 22 05:49:15 PM PDT 24
Peak memory 207116 kb
Host smart-3af90bb0-7113-49cc-95dc-75e69e245c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876583913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2876583913
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.2323266421
Short name T761
Test name
Test status
Simulation time 2369123008 ps
CPU time 5.87 seconds
Started Jul 22 05:49:13 PM PDT 24
Finished Jul 22 05:49:19 PM PDT 24
Peak memory 224632 kb
Host smart-1c7192c7-f072-4437-9316-04e30267e8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323266421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.2323266421
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2842710243
Short name T29
Test name
Test status
Simulation time 12564670 ps
CPU time 0.76 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:25 PM PDT 24
Peak memory 205820 kb
Host smart-c2658f14-b59f-48ca-8672-aa98ee972f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842710243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2842710243
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1195607711
Short name T887
Test name
Test status
Simulation time 83184163 ps
CPU time 2.93 seconds
Started Jul 22 05:49:23 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 233092 kb
Host smart-7be1367d-0037-4fcd-b25a-911a060f94b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195607711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1195607711
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.864937054
Short name T397
Test name
Test status
Simulation time 51053833 ps
CPU time 0.84 seconds
Started Jul 22 05:49:43 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 206684 kb
Host smart-af4e7a84-6371-4a4e-af01-45d168c61cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864937054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.864937054
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1857732420
Short name T43
Test name
Test status
Simulation time 123568344799 ps
CPU time 205.29 seconds
Started Jul 22 05:49:28 PM PDT 24
Finished Jul 22 05:52:54 PM PDT 24
Peak memory 253564 kb
Host smart-2d4ab07a-4d99-412f-b513-683a0fab4a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857732420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1857732420
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3113962762
Short name T921
Test name
Test status
Simulation time 2725323781 ps
CPU time 48.42 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:50:13 PM PDT 24
Peak memory 250560 kb
Host smart-b79bd03e-c4ae-49ea-9afb-c7dc4b6b0fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113962762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3113962762
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.3428049106
Short name T79
Test name
Test status
Simulation time 157897241918 ps
CPU time 362.54 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:55:27 PM PDT 24
Peak memory 257564 kb
Host smart-bcbd61b5-16fa-43f6-8c0c-5f13aca94939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428049106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.3428049106
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.1941489660
Short name T655
Test name
Test status
Simulation time 10915456 ps
CPU time 0.74 seconds
Started Jul 22 05:49:21 PM PDT 24
Finished Jul 22 05:49:23 PM PDT 24
Peak memory 215960 kb
Host smart-f80adcd6-cc22-42df-9971-a5237d88649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941489660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.1941489660
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4095484148
Short name T758
Test name
Test status
Simulation time 1620115022 ps
CPU time 7.49 seconds
Started Jul 22 05:49:21 PM PDT 24
Finished Jul 22 05:49:30 PM PDT 24
Peak memory 232688 kb
Host smart-ecefc791-a621-4662-b62c-24a3eecdbb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095484148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4095484148
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.235172977
Short name T1
Test name
Test status
Simulation time 61896690528 ps
CPU time 175.46 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:52:18 PM PDT 24
Peak memory 241112 kb
Host smart-c338a285-1d25-4086-a83f-4f0591b35838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235172977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.235172977
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2948239740
Short name T694
Test name
Test status
Simulation time 14599154196 ps
CPU time 11.6 seconds
Started Jul 22 05:49:25 PM PDT 24
Finished Jul 22 05:49:38 PM PDT 24
Peak memory 224640 kb
Host smart-ed905c32-f574-4aff-96b4-c454a1f3b12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948239740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2948239740
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.4136775048
Short name T559
Test name
Test status
Simulation time 5458542608 ps
CPU time 8.12 seconds
Started Jul 22 05:49:26 PM PDT 24
Finished Jul 22 05:49:34 PM PDT 24
Peak memory 224716 kb
Host smart-4b11aeef-83c6-4fed-98d3-d8abfd8f3a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136775048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4136775048
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4255837451
Short name T407
Test name
Test status
Simulation time 647868264 ps
CPU time 3.59 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 223304 kb
Host smart-94375fa7-02b0-418d-80dc-47855ef0c553
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4255837451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4255837451
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.970208273
Short name T309
Test name
Test status
Simulation time 6048722960 ps
CPU time 25.24 seconds
Started Jul 22 05:49:19 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 217964 kb
Host smart-137d0b65-f40f-4533-815f-7ae426a212c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970208273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.970208273
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3067738675
Short name T351
Test name
Test status
Simulation time 8377510991 ps
CPU time 23.61 seconds
Started Jul 22 05:49:12 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 216492 kb
Host smart-d524347e-1090-49ed-ae4a-a9ba1fdcf9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067738675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3067738675
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.2997422005
Short name T565
Test name
Test status
Simulation time 11780388 ps
CPU time 0.69 seconds
Started Jul 22 05:49:29 PM PDT 24
Finished Jul 22 05:49:31 PM PDT 24
Peak memory 205776 kb
Host smart-83bbf8a8-293d-4f85-adbd-268461bf928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997422005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2997422005
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3208459290
Short name T419
Test name
Test status
Simulation time 133189812 ps
CPU time 0.92 seconds
Started Jul 22 05:49:20 PM PDT 24
Finished Jul 22 05:49:22 PM PDT 24
Peak memory 206116 kb
Host smart-433a39a6-172b-4571-b012-eb13ff5cd9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208459290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3208459290
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.144626274
Short name T388
Test name
Test status
Simulation time 550420400 ps
CPU time 5.66 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:28 PM PDT 24
Peak memory 232868 kb
Host smart-09595215-7fb4-4267-85e3-e91b221fe9aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144626274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.144626274
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.495249399
Short name T98
Test name
Test status
Simulation time 85320774 ps
CPU time 2.26 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:27 PM PDT 24
Peak memory 224640 kb
Host smart-42393e5f-80f5-4ba3-879b-f71c99d7d4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495249399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.495249399
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3198458348
Short name T369
Test name
Test status
Simulation time 36486349 ps
CPU time 0.76 seconds
Started Jul 22 05:49:46 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 205652 kb
Host smart-1faabf8a-5505-41e1-b69a-84dd3ddf9000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198458348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3198458348
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1724966856
Short name T647
Test name
Test status
Simulation time 58429918091 ps
CPU time 111.89 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:51:14 PM PDT 24
Peak memory 249356 kb
Host smart-bc519245-c116-40a4-9c89-49f843fac3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724966856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1724966856
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.496594417
Short name T316
Test name
Test status
Simulation time 5005731348 ps
CPU time 43.42 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:50:08 PM PDT 24
Peak memory 239788 kb
Host smart-0fefe48e-e372-4bb4-b146-3e168c4eba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496594417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.496594417
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3922501637
Short name T146
Test name
Test status
Simulation time 384753504 ps
CPU time 7.35 seconds
Started Jul 22 05:49:21 PM PDT 24
Finished Jul 22 05:49:30 PM PDT 24
Peak memory 224708 kb
Host smart-870990e9-f54c-4121-9583-f80a1240c3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922501637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3922501637
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1121566309
Short name T763
Test name
Test status
Simulation time 56633619423 ps
CPU time 277.51 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:54:03 PM PDT 24
Peak memory 257116 kb
Host smart-ba1b12b6-dc5e-49e1-922b-c0a1df8b88af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121566309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1121566309
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3156166495
Short name T561
Test name
Test status
Simulation time 7237953967 ps
CPU time 10.91 seconds
Started Jul 22 05:49:18 PM PDT 24
Finished Jul 22 05:49:30 PM PDT 24
Peak memory 232932 kb
Host smart-ce5cf082-50cb-4549-8430-a480f7326a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156166495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3156166495
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1470967891
Short name T525
Test name
Test status
Simulation time 2240199219 ps
CPU time 17.53 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 232960 kb
Host smart-9cb61827-59ce-47f5-8489-ecccfbd9b96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470967891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1470967891
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2510676449
Short name T806
Test name
Test status
Simulation time 882162251 ps
CPU time 3.91 seconds
Started Jul 22 05:49:23 PM PDT 24
Finished Jul 22 05:49:27 PM PDT 24
Peak memory 233116 kb
Host smart-6630fc31-5d08-4ad6-8450-8326ee0c674b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510676449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2510676449
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2652038815
Short name T599
Test name
Test status
Simulation time 4227607157 ps
CPU time 10.73 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 220640 kb
Host smart-4c914230-e1c7-4970-932e-d2bdafba40fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652038815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2652038815
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.783238561
Short name T610
Test name
Test status
Simulation time 113726081 ps
CPU time 0.9 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 205772 kb
Host smart-9e2ccf6c-3d62-42af-963d-e43e384c3199
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783238561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.783238561
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.902693170
Short name T314
Test name
Test status
Simulation time 1452355132 ps
CPU time 14.64 seconds
Started Jul 22 05:49:26 PM PDT 24
Finished Jul 22 05:49:41 PM PDT 24
Peak memory 216592 kb
Host smart-6059d812-c3a4-4b57-a934-cdcec799f342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902693170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.902693170
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.388945632
Short name T457
Test name
Test status
Simulation time 19202553443 ps
CPU time 14.9 seconds
Started Jul 22 05:49:26 PM PDT 24
Finished Jul 22 05:49:41 PM PDT 24
Peak memory 216468 kb
Host smart-5bb131fb-810e-4bc2-9877-ce1190591ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388945632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.388945632
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.4190451325
Short name T801
Test name
Test status
Simulation time 311048100 ps
CPU time 1.28 seconds
Started Jul 22 05:49:25 PM PDT 24
Finished Jul 22 05:49:27 PM PDT 24
Peak memory 216400 kb
Host smart-536e6c63-fd75-405f-b584-b55405ee471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190451325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.4190451325
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.839679212
Short name T61
Test name
Test status
Simulation time 25471331 ps
CPU time 0.8 seconds
Started Jul 22 05:49:52 PM PDT 24
Finished Jul 22 05:49:53 PM PDT 24
Peak memory 206076 kb
Host smart-e3c7ab2a-1e51-4b43-846e-ad0e3a8900ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839679212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.839679212
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1119883126
Short name T877
Test name
Test status
Simulation time 102425549236 ps
CPU time 19.15 seconds
Started Jul 22 05:49:25 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 224728 kb
Host smart-f705c789-1406-408c-98e7-7875568f89c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119883126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1119883126
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2055956325
Short name T749
Test name
Test status
Simulation time 110130631 ps
CPU time 0.74 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 205928 kb
Host smart-b3860cad-357b-46fd-95e3-d4eb123389a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055956325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2055956325
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3514224680
Short name T897
Test name
Test status
Simulation time 32485034 ps
CPU time 2.07 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:50:12 PM PDT 24
Peak memory 224320 kb
Host smart-0377dc96-e36e-4ba5-a767-44bd25134e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514224680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3514224680
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4174190037
Short name T979
Test name
Test status
Simulation time 19444237 ps
CPU time 0.78 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:24 PM PDT 24
Peak memory 207064 kb
Host smart-89c26987-2875-4e45-84db-a71384cae504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174190037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4174190037
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3546030468
Short name T651
Test name
Test status
Simulation time 27656725059 ps
CPU time 207.45 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:52:59 PM PDT 24
Peak memory 253908 kb
Host smart-0ab2ebb6-2d0d-4b70-a449-3c4f2380388b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546030468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3546030468
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2656645415
Short name T434
Test name
Test status
Simulation time 4125877101 ps
CPU time 107.19 seconds
Started Jul 22 05:50:03 PM PDT 24
Finished Jul 22 05:51:51 PM PDT 24
Peak memory 261880 kb
Host smart-f538b74e-e7e9-4122-ac2a-4cd37143231f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656645415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2656645415
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2457389049
Short name T787
Test name
Test status
Simulation time 18607067354 ps
CPU time 121.64 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:51:33 PM PDT 24
Peak memory 241196 kb
Host smart-49423f3c-d84d-4665-a722-3d1ad2e5f527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457389049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2457389049
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1297411893
Short name T813
Test name
Test status
Simulation time 5264743103 ps
CPU time 58.77 seconds
Started Jul 22 05:49:33 PM PDT 24
Finished Jul 22 05:50:32 PM PDT 24
Peak memory 250108 kb
Host smart-805759c9-9883-4d10-a85e-12a77530cf84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297411893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1297411893
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2786624211
Short name T394
Test name
Test status
Simulation time 29265863005 ps
CPU time 55.04 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:50:27 PM PDT 24
Peak memory 255468 kb
Host smart-e99b0474-73fc-443f-ad9d-3e6528b15096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786624211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2786624211
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.2049324398
Short name T215
Test name
Test status
Simulation time 2499641869 ps
CPU time 13.21 seconds
Started Jul 22 05:49:21 PM PDT 24
Finished Jul 22 05:49:34 PM PDT 24
Peak memory 232884 kb
Host smart-aabb2fb4-4a06-4639-83e1-8e951480a237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049324398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2049324398
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1170731738
Short name T805
Test name
Test status
Simulation time 508783156 ps
CPU time 13.25 seconds
Started Jul 22 05:49:23 PM PDT 24
Finished Jul 22 05:49:37 PM PDT 24
Peak memory 241060 kb
Host smart-3b279dbb-47e5-415c-a23d-c6dff507ed24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170731738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1170731738
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.436022541
Short name T751
Test name
Test status
Simulation time 13643373526 ps
CPU time 10.43 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 224728 kb
Host smart-ffd14ba9-74eb-4b81-b94a-58e0138bcd80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436022541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.436022541
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1667968348
Short name T766
Test name
Test status
Simulation time 3319923815 ps
CPU time 11.68 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 233904 kb
Host smart-13780a71-10a4-492a-9d36-65869e835421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667968348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1667968348
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.554948113
Short name T2
Test name
Test status
Simulation time 297062317 ps
CPU time 3.62 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 222884 kb
Host smart-0b39cdd5-0f7e-4db1-82b5-bee4c3d534cd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=554948113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.554948113
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1724821800
Short name T891
Test name
Test status
Simulation time 10731615860 ps
CPU time 111.56 seconds
Started Jul 22 05:50:04 PM PDT 24
Finished Jul 22 05:51:56 PM PDT 24
Peak memory 255424 kb
Host smart-9b89cc04-7eda-4f2a-8ea2-04da95e3e32e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724821800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1724821800
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3180127353
Short name T949
Test name
Test status
Simulation time 10150078192 ps
CPU time 7.4 seconds
Started Jul 22 05:49:25 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 216444 kb
Host smart-9d26f9c4-3756-46a9-a65a-f9305179c258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180127353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3180127353
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.217125417
Short name T975
Test name
Test status
Simulation time 3649691505 ps
CPU time 11.51 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 216400 kb
Host smart-bb5c846f-53a1-4f94-a7ab-7ae821bc560a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217125417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.217125417
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.2140840361
Short name T548
Test name
Test status
Simulation time 65605737 ps
CPU time 1.11 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 207856 kb
Host smart-ccd84da9-a0d2-48bd-b161-8b063e4079f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140840361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2140840361
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3277789905
Short name T94
Test name
Test status
Simulation time 48186988 ps
CPU time 0.83 seconds
Started Jul 22 05:49:24 PM PDT 24
Finished Jul 22 05:49:26 PM PDT 24
Peak memory 206080 kb
Host smart-cebd60b1-0268-4045-ad52-02438e634cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277789905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3277789905
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.460609073
Short name T597
Test name
Test status
Simulation time 7674140997 ps
CPU time 14.9 seconds
Started Jul 22 05:49:55 PM PDT 24
Finished Jul 22 05:50:10 PM PDT 24
Peak memory 236296 kb
Host smart-2145d500-5c31-41b1-9983-5174bf1375c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460609073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.460609073
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.3203649567
Short name T574
Test name
Test status
Simulation time 34875225 ps
CPU time 0.79 seconds
Started Jul 22 05:49:46 PM PDT 24
Finished Jul 22 05:49:48 PM PDT 24
Peak memory 205516 kb
Host smart-5e0bd383-c842-4539-9f4d-d6662a993305
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203649567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
3203649567
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1099056141
Short name T514
Test name
Test status
Simulation time 211738464 ps
CPU time 4.19 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:49:37 PM PDT 24
Peak memory 232820 kb
Host smart-8a9df4ef-5d38-4e54-ad0c-be00f882a2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099056141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1099056141
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1924418627
Short name T903
Test name
Test status
Simulation time 45469509 ps
CPU time 0.79 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:49:39 PM PDT 24
Peak memory 206732 kb
Host smart-8f6cea00-b01c-486e-9509-f69747ad7dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924418627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1924418627
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1596279153
Short name T216
Test name
Test status
Simulation time 3388022495 ps
CPU time 41.02 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:50:11 PM PDT 24
Peak memory 250036 kb
Host smart-6bea9a23-5d6c-4807-98f7-8708d8dcb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596279153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1596279153
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2869836157
Short name T884
Test name
Test status
Simulation time 1365148439 ps
CPU time 38.13 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:50:10 PM PDT 24
Peak memory 250408 kb
Host smart-3676edd8-52bd-4a6f-9306-15d4652ad8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869836157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2869836157
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.1090868151
Short name T728
Test name
Test status
Simulation time 181658228 ps
CPU time 5.07 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 232916 kb
Host smart-d7a86b81-73bb-4316-b312-cfea8b7a5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090868151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.1090868151
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.525231620
Short name T557
Test name
Test status
Simulation time 3573364107 ps
CPU time 12.8 seconds
Started Jul 22 05:49:33 PM PDT 24
Finished Jul 22 05:49:46 PM PDT 24
Peak memory 232932 kb
Host smart-38ec5e1d-655f-4d76-9196-41bde4097e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525231620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.525231620
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.419943089
Short name T239
Test name
Test status
Simulation time 527419002 ps
CPU time 4.48 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:49:41 PM PDT 24
Peak memory 224720 kb
Host smart-cb30db2e-6208-4680-9729-7e6d13f175f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419943089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.419943089
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.4213778766
Short name T202
Test name
Test status
Simulation time 2004108900 ps
CPU time 15.37 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 232868 kb
Host smart-33ddf4e4-f35f-438e-8189-b34da3efea29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213778766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.4213778766
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3868536812
Short name T264
Test name
Test status
Simulation time 17664865679 ps
CPU time 28.28 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:50:00 PM PDT 24
Peak memory 232888 kb
Host smart-7a78ad76-f3c7-4a69-84fc-4c0624d1020d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868536812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3868536812
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.1793304009
Short name T793
Test name
Test status
Simulation time 7740685727 ps
CPU time 8.58 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:49:39 PM PDT 24
Peak memory 224680 kb
Host smart-280df86e-bd0c-449e-8c44-0e43d015ef63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793304009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1793304009
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1423900484
Short name T379
Test name
Test status
Simulation time 3903073823 ps
CPU time 9.05 seconds
Started Jul 22 05:49:33 PM PDT 24
Finished Jul 22 05:49:43 PM PDT 24
Peak memory 222268 kb
Host smart-8f021f91-efd4-4b13-b6ab-04f0ebbd6d05
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1423900484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1423900484
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3266830375
Short name T54
Test name
Test status
Simulation time 107791957208 ps
CPU time 438.04 seconds
Started Jul 22 05:50:07 PM PDT 24
Finished Jul 22 05:57:25 PM PDT 24
Peak memory 269996 kb
Host smart-448fc994-fbd4-41ac-af85-5cd37eb3c4f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266830375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3266830375
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.602827613
Short name T396
Test name
Test status
Simulation time 8901914875 ps
CPU time 29.51 seconds
Started Jul 22 05:49:27 PM PDT 24
Finished Jul 22 05:49:57 PM PDT 24
Peak memory 217888 kb
Host smart-aae38f96-ffa8-4493-b646-8550d6053e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602827613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.602827613
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2068210719
Short name T516
Test name
Test status
Simulation time 3077707202 ps
CPU time 5.94 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:49:37 PM PDT 24
Peak memory 216492 kb
Host smart-536c9cc3-646a-4c61-b038-1d5a0a96dbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068210719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2068210719
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3549976213
Short name T321
Test name
Test status
Simulation time 323724104 ps
CPU time 2.77 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:49:36 PM PDT 24
Peak memory 216388 kb
Host smart-9e2dc391-9f4f-415f-bc80-8aaac664d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549976213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3549976213
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1845340750
Short name T589
Test name
Test status
Simulation time 39149585 ps
CPU time 0.77 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 206160 kb
Host smart-cdfdc910-1526-4b33-99ec-9143a683c7e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845340750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1845340750
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1997858283
Short name T864
Test name
Test status
Simulation time 57471793727 ps
CPU time 42.66 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:50:14 PM PDT 24
Peak memory 236180 kb
Host smart-316f226d-7bfc-49c8-b39c-5e1929121447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997858283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1997858283
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4053655702
Short name T922
Test name
Test status
Simulation time 12742850 ps
CPU time 0.69 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 205996 kb
Host smart-088116e5-6944-4103-bf79-aad44ca1fbc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053655702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4053655702
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.148214831
Short name T850
Test name
Test status
Simulation time 2732234326 ps
CPU time 7.45 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 232944 kb
Host smart-583f0af1-c5b2-4bc6-9eef-6edd675a3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148214831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.148214831
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2997150325
Short name T699
Test name
Test status
Simulation time 17721372 ps
CPU time 0.75 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:49:39 PM PDT 24
Peak memory 206032 kb
Host smart-b2a510a4-95bd-4f98-a7a3-8216e5c0eae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997150325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2997150325
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3444618128
Short name T185
Test name
Test status
Simulation time 7074777523 ps
CPU time 41.13 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:50:13 PM PDT 24
Peak memory 249408 kb
Host smart-7320d56c-6ceb-4c4f-8e0f-cc1736ceddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444618128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3444618128
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2989652157
Short name T773
Test name
Test status
Simulation time 68091965717 ps
CPU time 299.17 seconds
Started Jul 22 05:50:07 PM PDT 24
Finished Jul 22 05:55:06 PM PDT 24
Peak memory 257576 kb
Host smart-12ccab39-0bf9-4501-8542-7fd9ba6eeba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989652157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2989652157
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1111134136
Short name T50
Test name
Test status
Simulation time 7206378943 ps
CPU time 61.24 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:50:32 PM PDT 24
Peak memory 232032 kb
Host smart-dcc098db-cf68-421c-8b62-a32f615a059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111134136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1111134136
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.175073785
Short name T324
Test name
Test status
Simulation time 226209981 ps
CPU time 5.35 seconds
Started Jul 22 05:49:46 PM PDT 24
Finished Jul 22 05:49:52 PM PDT 24
Peak memory 232856 kb
Host smart-727405c4-9409-416b-913f-589c5c17a156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175073785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.175073785
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2940846261
Short name T247
Test name
Test status
Simulation time 1246378805 ps
CPU time 8.95 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:49:40 PM PDT 24
Peak memory 232852 kb
Host smart-579e06db-444b-4c1c-a553-935f5e820cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940846261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2940846261
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.3209239138
Short name T59
Test name
Test status
Simulation time 18862946106 ps
CPU time 128.25 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:51:39 PM PDT 24
Peak memory 232976 kb
Host smart-ccac3ab0-74db-43b8-886e-9ca9abb691ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209239138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.3209239138
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3494520086
Short name T784
Test name
Test status
Simulation time 1869028846 ps
CPU time 9.73 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:50:19 PM PDT 24
Peak memory 232784 kb
Host smart-0d37e4f6-a9f6-4523-870b-07cdf162844f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494520086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3494520086
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2027410399
Short name T189
Test name
Test status
Simulation time 432593143 ps
CPU time 3.33 seconds
Started Jul 22 05:50:07 PM PDT 24
Finished Jul 22 05:50:10 PM PDT 24
Peak memory 224688 kb
Host smart-a6aeadbc-b4be-44e3-85c8-f1d2c5f36b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027410399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2027410399
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1541136119
Short name T642
Test name
Test status
Simulation time 1328305068 ps
CPU time 8.73 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:49:39 PM PDT 24
Peak memory 222904 kb
Host smart-97139b46-8c30-47f9-af1d-3f0308ef4908
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1541136119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1541136119
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3657763441
Short name T629
Test name
Test status
Simulation time 201530901 ps
CPU time 1.07 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:50:11 PM PDT 24
Peak memory 207180 kb
Host smart-e1f6c797-0760-4ca1-9fbc-2709c2bb5a67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657763441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3657763441
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1825912933
Short name T741
Test name
Test status
Simulation time 10821708323 ps
CPU time 28.68 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:50:07 PM PDT 24
Peak memory 220300 kb
Host smart-f878d471-db19-4310-9b19-2913f6ae121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825912933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1825912933
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3445695724
Short name T576
Test name
Test status
Simulation time 10461449905 ps
CPU time 7.03 seconds
Started Jul 22 05:50:03 PM PDT 24
Finished Jul 22 05:50:11 PM PDT 24
Peak memory 216492 kb
Host smart-a352efc6-4475-4aee-8836-afed456d8117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445695724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3445695724
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3388548648
Short name T667
Test name
Test status
Simulation time 60884667 ps
CPU time 1.69 seconds
Started Jul 22 05:49:46 PM PDT 24
Finished Jul 22 05:49:49 PM PDT 24
Peak memory 216120 kb
Host smart-742de123-f718-4aad-8391-0adf4557e5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388548648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3388548648
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.432387332
Short name T505
Test name
Test status
Simulation time 84776712 ps
CPU time 0.81 seconds
Started Jul 22 05:49:30 PM PDT 24
Finished Jul 22 05:49:31 PM PDT 24
Peak memory 206104 kb
Host smart-173c52f4-cb8d-4ae1-aec0-e03b4ebb52d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432387332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.432387332
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.4169710155
Short name T584
Test name
Test status
Simulation time 100734745 ps
CPU time 3.15 seconds
Started Jul 22 05:49:35 PM PDT 24
Finished Jul 22 05:49:38 PM PDT 24
Peak memory 232908 kb
Host smart-e6ddb840-17fa-47f3-8aab-1c78fe8540a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169710155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4169710155
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1248534061
Short name T339
Test name
Test status
Simulation time 25060194 ps
CPU time 0.73 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:44 PM PDT 24
Peak memory 205544 kb
Host smart-61130416-d102-4f43-bbb0-e7f7e109b685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248534061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1248534061
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.964906949
Short name T450
Test name
Test status
Simulation time 467431323 ps
CPU time 6.12 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:49 PM PDT 24
Peak memory 232864 kb
Host smart-de699ddd-cb2a-4d8f-855e-cd79d4f0cea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964906949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.964906949
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.2212278069
Short name T323
Test name
Test status
Simulation time 13906111 ps
CPU time 0.75 seconds
Started Jul 22 05:49:31 PM PDT 24
Finished Jul 22 05:49:32 PM PDT 24
Peak memory 206756 kb
Host smart-a0405339-82e5-4662-b5e2-31038e9626bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212278069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2212278069
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1249695306
Short name T496
Test name
Test status
Simulation time 11729942 ps
CPU time 0.78 seconds
Started Jul 22 05:49:38 PM PDT 24
Finished Jul 22 05:49:40 PM PDT 24
Peak memory 207712 kb
Host smart-5e0c58f3-1b1d-44d7-beb4-0180b294f1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249695306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1249695306
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2360236924
Short name T223
Test name
Test status
Simulation time 2631782548 ps
CPU time 16.84 seconds
Started Jul 22 05:49:41 PM PDT 24
Finished Jul 22 05:49:58 PM PDT 24
Peak memory 234556 kb
Host smart-9e36c9db-e902-4dc8-b077-9f853376b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360236924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2360236924
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2830032598
Short name T299
Test name
Test status
Simulation time 15610485800 ps
CPU time 42.36 seconds
Started Jul 22 05:49:43 PM PDT 24
Finished Jul 22 05:50:26 PM PDT 24
Peak memory 236384 kb
Host smart-06f1ebaa-28c7-4a58-94cb-09600d1d075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830032598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2830032598
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2038963110
Short name T281
Test name
Test status
Simulation time 14658278250 ps
CPU time 117.31 seconds
Started Jul 22 05:49:43 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 249908 kb
Host smart-38b5c188-9f9e-4204-9123-ccb0bdf985fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038963110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2038963110
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3874533650
Short name T502
Test name
Test status
Simulation time 207684575 ps
CPU time 4.46 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:46 PM PDT 24
Peak memory 224680 kb
Host smart-54f51883-52bd-4713-9e33-1e32e74a44e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874533650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3874533650
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.116925327
Short name T205
Test name
Test status
Simulation time 6136267190 ps
CPU time 18.64 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:50:02 PM PDT 24
Peak memory 232820 kb
Host smart-64d5477e-e2cb-416b-a703-bbe3c3ec0eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116925327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.116925327
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3194392747
Short name T214
Test name
Test status
Simulation time 1614717880 ps
CPU time 5.21 seconds
Started Jul 22 05:50:04 PM PDT 24
Finished Jul 22 05:50:09 PM PDT 24
Peak memory 232828 kb
Host smart-bfb0748e-cd98-4a3f-90ab-55cb7a13e8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194392747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3194392747
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2922648752
Short name T990
Test name
Test status
Simulation time 1152849328 ps
CPU time 6.05 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 224692 kb
Host smart-778b06ef-7f1c-45e9-8ecc-a97d7c8dded9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922648752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2922648752
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3817054865
Short name T659
Test name
Test status
Simulation time 84486627 ps
CPU time 3.49 seconds
Started Jul 22 05:49:39 PM PDT 24
Finished Jul 22 05:49:43 PM PDT 24
Peak memory 223580 kb
Host smart-45b1e881-996b-46d0-9684-161e0937c470
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3817054865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3817054865
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.4032040767
Short name T730
Test name
Test status
Simulation time 3706214211 ps
CPU time 20.29 seconds
Started Jul 22 05:49:33 PM PDT 24
Finished Jul 22 05:49:54 PM PDT 24
Peak memory 216448 kb
Host smart-9c3a0082-7466-4351-a194-d472ea27a678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032040767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.4032040767
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1154366170
Short name T943
Test name
Test status
Simulation time 9290054810 ps
CPU time 8.35 seconds
Started Jul 22 05:49:37 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 216516 kb
Host smart-a240a4da-18ad-442d-8928-7b18fc9defbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154366170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1154366170
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2620815846
Short name T579
Test name
Test status
Simulation time 75556869 ps
CPU time 1.71 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 216452 kb
Host smart-3d5ff435-e2c7-45c5-81b2-65255cf7d387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620815846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2620815846
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.2208716670
Short name T715
Test name
Test status
Simulation time 70273069 ps
CPU time 0.79 seconds
Started Jul 22 05:49:32 PM PDT 24
Finished Jul 22 05:49:33 PM PDT 24
Peak memory 206092 kb
Host smart-eab8a876-dc3b-4ecc-93fa-0957eaf4104e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208716670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.2208716670
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2181871558
Short name T983
Test name
Test status
Simulation time 4360427247 ps
CPU time 7.17 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:49:48 PM PDT 24
Peak memory 224756 kb
Host smart-2b9b2a5f-eb7a-4ed9-a14f-945b699d3a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181871558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2181871558
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2909479165
Short name T581
Test name
Test status
Simulation time 12566828 ps
CPU time 0.72 seconds
Started Jul 22 05:49:41 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 205048 kb
Host smart-0d806708-6057-41eb-8af0-2de9c85449f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909479165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2909479165
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3227208004
Short name T727
Test name
Test status
Simulation time 396448971 ps
CPU time 7.07 seconds
Started Jul 22 05:49:39 PM PDT 24
Finished Jul 22 05:49:47 PM PDT 24
Peak memory 232800 kb
Host smart-64fce156-c726-4008-814d-85504d531d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227208004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3227208004
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.162419301
Short name T421
Test name
Test status
Simulation time 28971984 ps
CPU time 0.81 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:44 PM PDT 24
Peak memory 206724 kb
Host smart-ecbbbfe1-45f8-464e-b1dd-602585b493df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162419301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.162419301
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1209218209
Short name T861
Test name
Test status
Simulation time 2404573252 ps
CPU time 41.47 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:50:24 PM PDT 24
Peak memory 252228 kb
Host smart-cc6b9e9d-3de8-46c3-924d-b0da606fce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209218209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1209218209
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4109080148
Short name T471
Test name
Test status
Simulation time 19590681247 ps
CPU time 62.7 seconds
Started Jul 22 05:49:43 PM PDT 24
Finished Jul 22 05:50:46 PM PDT 24
Peak memory 234028 kb
Host smart-97ab5167-9226-4077-8eb8-c9e57a9a2d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109080148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4109080148
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3063565276
Short name T218
Test name
Test status
Simulation time 7483537712 ps
CPU time 58.59 seconds
Started Jul 22 05:49:56 PM PDT 24
Finished Jul 22 05:50:55 PM PDT 24
Peak memory 238448 kb
Host smart-f42570e6-b04b-4a08-b6af-2de97a7200bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063565276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3063565276
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3872125379
Short name T302
Test name
Test status
Simulation time 1390479330 ps
CPU time 13.08 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:49:53 PM PDT 24
Peak memory 224648 kb
Host smart-ae38f6cd-e4a0-4a01-9676-f0fe55861a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872125379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3872125379
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3643745314
Short name T197
Test name
Test status
Simulation time 99782087344 ps
CPU time 160.04 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:52:21 PM PDT 24
Peak memory 224644 kb
Host smart-e03c7117-cfd0-4414-a94b-12688443f7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643745314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3643745314
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.437097041
Short name T177
Test name
Test status
Simulation time 1077604185 ps
CPU time 7.04 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:50 PM PDT 24
Peak memory 224652 kb
Host smart-c90035ab-48ab-4f0f-8ad3-085386c9acb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437097041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.437097041
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1619923544
Short name T904
Test name
Test status
Simulation time 26767350295 ps
CPU time 23.14 seconds
Started Jul 22 05:49:39 PM PDT 24
Finished Jul 22 05:50:03 PM PDT 24
Peak memory 235408 kb
Host smart-f7b92c10-96f5-4adb-bd5c-4c4b65b7519f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619923544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1619923544
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1941632857
Short name T289
Test name
Test status
Simulation time 7130624274 ps
CPU time 9.46 seconds
Started Jul 22 05:49:54 PM PDT 24
Finished Jul 22 05:50:04 PM PDT 24
Peak memory 232880 kb
Host smart-7417e971-cb72-4f17-a6cb-280a606d45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941632857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1941632857
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.4014431798
Short name T242
Test name
Test status
Simulation time 124097725 ps
CPU time 3.49 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:49:44 PM PDT 24
Peak memory 232760 kb
Host smart-6ed59817-32fc-42de-b527-b7c08d99fb89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014431798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.4014431798
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3768107598
Short name T836
Test name
Test status
Simulation time 275968957 ps
CPU time 5.71 seconds
Started Jul 22 05:49:39 PM PDT 24
Finished Jul 22 05:49:46 PM PDT 24
Peak memory 223476 kb
Host smart-f6c9b3f4-4bda-48a1-89d0-a042a9a20dd9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3768107598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3768107598
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.477245798
Short name T925
Test name
Test status
Simulation time 3914945886 ps
CPU time 103.26 seconds
Started Jul 22 05:49:41 PM PDT 24
Finished Jul 22 05:51:25 PM PDT 24
Peak memory 256116 kb
Host smart-b0cb8ae0-fa07-4537-9f1d-5c0ce7973712
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477245798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.477245798
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2914114837
Short name T695
Test name
Test status
Simulation time 6126897859 ps
CPU time 37.25 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:50:19 PM PDT 24
Peak memory 216412 kb
Host smart-6cf9221c-c691-4770-b9d9-8dfab8ae62cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914114837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2914114837
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.2159909318
Short name T375
Test name
Test status
Simulation time 1942911290 ps
CPU time 7.3 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:49:48 PM PDT 24
Peak memory 216392 kb
Host smart-b76d2ee5-2d7d-461a-b6bd-21d203fcae41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159909318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2159909318
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.567181622
Short name T446
Test name
Test status
Simulation time 686501965 ps
CPU time 1.43 seconds
Started Jul 22 05:49:42 PM PDT 24
Finished Jul 22 05:49:45 PM PDT 24
Peak memory 216396 kb
Host smart-08df3c79-f275-4687-b403-4d9d520837f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567181622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.567181622
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3499582393
Short name T477
Test name
Test status
Simulation time 100369425 ps
CPU time 0.81 seconds
Started Jul 22 05:49:41 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 206072 kb
Host smart-713177b0-fde9-4fca-b4eb-f85178d43822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499582393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3499582393
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.3035291960
Short name T986
Test name
Test status
Simulation time 44110988 ps
CPU time 2.05 seconds
Started Jul 22 05:49:40 PM PDT 24
Finished Jul 22 05:49:43 PM PDT 24
Peak memory 223896 kb
Host smart-b92abb27-700e-4e0e-bf23-29c03e4135dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035291960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.3035291960
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.769881386
Short name T507
Test name
Test status
Simulation time 19852251 ps
CPU time 0.69 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:47:52 PM PDT 24
Peak memory 205600 kb
Host smart-71087827-43a9-4368-87c9-b498853785d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769881386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.769881386
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3231066484
Short name T578
Test name
Test status
Simulation time 327435733 ps
CPU time 3 seconds
Started Jul 22 05:47:39 PM PDT 24
Finished Jul 22 05:47:43 PM PDT 24
Peak memory 232868 kb
Host smart-621c7fa1-9672-4a2e-8614-45f111d9f82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231066484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3231066484
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3519762840
Short name T350
Test name
Test status
Simulation time 56936588 ps
CPU time 0.8 seconds
Started Jul 22 05:47:38 PM PDT 24
Finished Jul 22 05:47:39 PM PDT 24
Peak memory 207052 kb
Host smart-64e8c02b-6a8b-482e-8598-40588da4e7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519762840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3519762840
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3267567
Short name T439
Test name
Test status
Simulation time 6830465034 ps
CPU time 8.33 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:48:00 PM PDT 24
Peak memory 233940 kb
Host smart-6f88cbeb-1bd8-4d51-8a61-411815702b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3267567
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2341741028
Short name T776
Test name
Test status
Simulation time 6830375910 ps
CPU time 96.25 seconds
Started Jul 22 05:47:45 PM PDT 24
Finished Jul 22 05:49:22 PM PDT 24
Peak memory 257592 kb
Host smart-b6a480d1-02a4-47b2-9d50-cf2320f74221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341741028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2341741028
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4143289310
Short name T312
Test name
Test status
Simulation time 4421263246 ps
CPU time 35.26 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:48:24 PM PDT 24
Peak memory 249416 kb
Host smart-d01af0ec-532a-4194-b927-b213bff7494c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143289310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4143289310
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.2168839573
Short name T631
Test name
Test status
Simulation time 130588918 ps
CPU time 7.09 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:47:57 PM PDT 24
Peak memory 224704 kb
Host smart-ed2a4e82-55fa-44f0-aa0a-41809fd12fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168839573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2168839573
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.3646444751
Short name T963
Test name
Test status
Simulation time 18356018378 ps
CPU time 34.31 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:48:26 PM PDT 24
Peak memory 240100 kb
Host smart-a2cad542-5114-420b-a3cc-bab1af966edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646444751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.3646444751
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1356060515
Short name T233
Test name
Test status
Simulation time 885254372 ps
CPU time 4.78 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:47:52 PM PDT 24
Peak memory 224644 kb
Host smart-d74dde32-353e-4d38-99d9-1ec0e1d54f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356060515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1356060515
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1583162777
Short name T199
Test name
Test status
Simulation time 42220886349 ps
CPU time 25.07 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:48:13 PM PDT 24
Peak memory 232960 kb
Host smart-cb102b6c-adda-498c-bc57-dc5df626d4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583162777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1583162777
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2686846497
Short name T44
Test name
Test status
Simulation time 2661755074 ps
CPU time 12.1 seconds
Started Jul 22 05:47:37 PM PDT 24
Finished Jul 22 05:47:50 PM PDT 24
Peak memory 240760 kb
Host smart-f73c7d05-6337-4b24-a86d-bc3eabc76a11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686846497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2686846497
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.531104190
Short name T60
Test name
Test status
Simulation time 664969542 ps
CPU time 5.96 seconds
Started Jul 22 05:47:40 PM PDT 24
Finished Jul 22 05:47:47 PM PDT 24
Peak memory 232760 kb
Host smart-3df33b2a-bb35-4b7e-aaa6-fee4aa1490f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531104190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.531104190
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3979842963
Short name T928
Test name
Test status
Simulation time 693675752 ps
CPU time 8.93 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:47:58 PM PDT 24
Peak memory 221752 kb
Host smart-6b90f216-f606-4f53-bc0b-faa95fa5e36b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3979842963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3979842963
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4281869585
Short name T70
Test name
Test status
Simulation time 138166934 ps
CPU time 0.97 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:47:50 PM PDT 24
Peak memory 235852 kb
Host smart-8e0cf7eb-b42a-450c-8eab-2c93b6498d1c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4281869585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4281869585
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2965053438
Short name T192
Test name
Test status
Simulation time 25584988735 ps
CPU time 161.85 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:50:29 PM PDT 24
Peak memory 268532 kb
Host smart-3e2da78b-49c7-4d05-87df-49997f96510b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965053438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2965053438
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.573449289
Short name T780
Test name
Test status
Simulation time 4998591066 ps
CPU time 34.56 seconds
Started Jul 22 05:47:37 PM PDT 24
Finished Jul 22 05:48:12 PM PDT 24
Peak memory 216468 kb
Host smart-bbc8a5b5-2385-4799-a1ca-ac70564a0934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573449289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.573449289
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.165805696
Short name T636
Test name
Test status
Simulation time 7297697779 ps
CPU time 18.71 seconds
Started Jul 22 05:47:38 PM PDT 24
Finished Jul 22 05:47:57 PM PDT 24
Peak memory 216472 kb
Host smart-09830d65-248b-4d5c-b19c-548b2ea895b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165805696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.165805696
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.2370156716
Short name T653
Test name
Test status
Simulation time 219098875 ps
CPU time 2.19 seconds
Started Jul 22 05:47:43 PM PDT 24
Finished Jul 22 05:47:46 PM PDT 24
Peak memory 216332 kb
Host smart-5d22dcff-085a-4b0a-8830-fb06e97cd745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370156716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.2370156716
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1790332518
Short name T622
Test name
Test status
Simulation time 36898374 ps
CPU time 0.85 seconds
Started Jul 22 05:47:38 PM PDT 24
Finished Jul 22 05:47:39 PM PDT 24
Peak memory 206088 kb
Host smart-25c8b9c5-f115-4d6b-9afd-46a3b4e529b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790332518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1790332518
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.3294277633
Short name T945
Test name
Test status
Simulation time 365480229 ps
CPU time 2.72 seconds
Started Jul 22 05:47:38 PM PDT 24
Finished Jul 22 05:47:41 PM PDT 24
Peak memory 232892 kb
Host smart-10e8eb4c-362c-4401-a50a-e0c16bbafd6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294277633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3294277633
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3121614334
Short name T348
Test name
Test status
Simulation time 14420777 ps
CPU time 0.77 seconds
Started Jul 22 05:49:59 PM PDT 24
Finished Jul 22 05:50:00 PM PDT 24
Peak memory 205580 kb
Host smart-a4bc2368-27a7-4163-a971-01196d96a1bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121614334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3121614334
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2847591489
Short name T961
Test name
Test status
Simulation time 295404639 ps
CPU time 3.21 seconds
Started Jul 22 05:50:02 PM PDT 24
Finished Jul 22 05:50:05 PM PDT 24
Peak memory 232864 kb
Host smart-a1067f83-1a6e-4570-bfcc-33a69c44eb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847591489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2847591489
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1293454213
Short name T509
Test name
Test status
Simulation time 52596554 ps
CPU time 0.76 seconds
Started Jul 22 05:49:55 PM PDT 24
Finished Jul 22 05:49:56 PM PDT 24
Peak memory 206700 kb
Host smart-bbcac5af-c213-4064-aef1-f32bf9706f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293454213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1293454213
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3655187630
Short name T42
Test name
Test status
Simulation time 10240712919 ps
CPU time 56.12 seconds
Started Jul 22 05:50:06 PM PDT 24
Finished Jul 22 05:51:02 PM PDT 24
Peak memory 249288 kb
Host smart-3bc483b4-b15c-4336-8457-71a7b2671ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655187630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3655187630
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.371382769
Short name T661
Test name
Test status
Simulation time 52994816908 ps
CPU time 494.49 seconds
Started Jul 22 05:49:59 PM PDT 24
Finished Jul 22 05:58:14 PM PDT 24
Peak memory 249668 kb
Host smart-f8931499-e079-48dc-b850-5c4d0c3662e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371382769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.371382769
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3593385021
Short name T532
Test name
Test status
Simulation time 30504199962 ps
CPU time 271.75 seconds
Started Jul 22 05:50:00 PM PDT 24
Finished Jul 22 05:54:32 PM PDT 24
Peak memory 249352 kb
Host smart-a1415578-ddea-46eb-9277-2fd667d9b399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593385021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3593385021
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2077161205
Short name T882
Test name
Test status
Simulation time 14162900888 ps
CPU time 51.14 seconds
Started Jul 22 05:49:48 PM PDT 24
Finished Jul 22 05:50:40 PM PDT 24
Peak memory 250216 kb
Host smart-df16a1cc-8b42-4297-ae04-f56b1613afff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077161205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2077161205
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.3569548096
Short name T820
Test name
Test status
Simulation time 113098177413 ps
CPU time 185.1 seconds
Started Jul 22 05:49:51 PM PDT 24
Finished Jul 22 05:52:56 PM PDT 24
Peak memory 256924 kb
Host smart-f2ce8129-5401-4e0f-8a73-9db7111b2e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569548096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.3569548096
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3091166799
Short name T384
Test name
Test status
Simulation time 311361100 ps
CPU time 3.2 seconds
Started Jul 22 05:49:50 PM PDT 24
Finished Jul 22 05:49:53 PM PDT 24
Peak memory 219052 kb
Host smart-58c8e9bf-a2ed-43c9-969a-f6bbd2c9f6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091166799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3091166799
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1946206868
Short name T832
Test name
Test status
Simulation time 690012512 ps
CPU time 9.98 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:50:00 PM PDT 24
Peak memory 237312 kb
Host smart-25fed0d5-d5bb-4c91-88ae-6631abac8a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946206868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1946206868
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.265722914
Short name T257
Test name
Test status
Simulation time 7442438841 ps
CPU time 4.85 seconds
Started Jul 22 05:49:50 PM PDT 24
Finished Jul 22 05:49:55 PM PDT 24
Peak memory 224764 kb
Host smart-7a0f9974-543d-42b4-8f81-bc4f49647083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265722914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.265722914
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2757470999
Short name T829
Test name
Test status
Simulation time 33378856 ps
CPU time 2.73 seconds
Started Jul 22 05:50:01 PM PDT 24
Finished Jul 22 05:50:04 PM PDT 24
Peak memory 232840 kb
Host smart-e0b090e2-60e1-42b6-8d9e-35b426a63bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757470999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2757470999
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1208764134
Short name T428
Test name
Test status
Simulation time 737065829 ps
CPU time 9.2 seconds
Started Jul 22 05:49:56 PM PDT 24
Finished Jul 22 05:50:06 PM PDT 24
Peak memory 222164 kb
Host smart-4772906f-a97a-4b42-97f2-8bf28f5f7946
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1208764134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1208764134
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.677703582
Short name T970
Test name
Test status
Simulation time 3615413859 ps
CPU time 90.8 seconds
Started Jul 22 05:50:00 PM PDT 24
Finished Jul 22 05:51:31 PM PDT 24
Peak memory 255760 kb
Host smart-4e3c509d-e121-4f57-8afa-d71a59d84326
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677703582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.677703582
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1528841802
Short name T448
Test name
Test status
Simulation time 24072643527 ps
CPU time 6.76 seconds
Started Jul 22 05:49:50 PM PDT 24
Finished Jul 22 05:49:57 PM PDT 24
Peak memory 216756 kb
Host smart-1e8fddd8-da6a-4a88-a08c-924ac66e7815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528841802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1528841802
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2216646883
Short name T686
Test name
Test status
Simulation time 4365500330 ps
CPU time 11.85 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:50:02 PM PDT 24
Peak memory 216388 kb
Host smart-683afe09-21ba-4405-ab26-2fe4abf72b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216646883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2216646883
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2300345847
Short name T953
Test name
Test status
Simulation time 40471218 ps
CPU time 1.24 seconds
Started Jul 22 05:49:51 PM PDT 24
Finished Jul 22 05:49:52 PM PDT 24
Peak memory 207912 kb
Host smart-8907e5b0-d4f7-4b35-8f45-6207a75d0606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300345847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2300345847
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.912109967
Short name T383
Test name
Test status
Simulation time 122042531 ps
CPU time 0.78 seconds
Started Jul 22 05:50:06 PM PDT 24
Finished Jul 22 05:50:07 PM PDT 24
Peak memory 206060 kb
Host smart-fa292812-d7c0-4de6-a067-4c48521ea22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912109967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.912109967
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.3228969160
Short name T203
Test name
Test status
Simulation time 103070352054 ps
CPU time 27.25 seconds
Started Jul 22 05:49:49 PM PDT 24
Finished Jul 22 05:50:17 PM PDT 24
Peak memory 230876 kb
Host smart-03dcde52-43d4-4b83-b752-518419bbe0f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228969160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.3228969160
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1291173510
Short name T474
Test name
Test status
Simulation time 12161308 ps
CPU time 0.74 seconds
Started Jul 22 05:50:11 PM PDT 24
Finished Jul 22 05:50:12 PM PDT 24
Peak memory 205040 kb
Host smart-73e026ff-9440-43d7-abfb-5795ee478b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291173510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1291173510
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1684027993
Short name T533
Test name
Test status
Simulation time 409775002 ps
CPU time 7.19 seconds
Started Jul 22 05:50:00 PM PDT 24
Finished Jul 22 05:50:08 PM PDT 24
Peak memory 224576 kb
Host smart-4384f47f-b77c-4525-8bf3-8ef247c970cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684027993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1684027993
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2859555805
Short name T680
Test name
Test status
Simulation time 32355515 ps
CPU time 0.77 seconds
Started Jul 22 05:50:12 PM PDT 24
Finished Jul 22 05:50:13 PM PDT 24
Peak memory 206036 kb
Host smart-7321158d-efd3-4544-8a7f-4c937af7e824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859555805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2859555805
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1551101127
Short name T646
Test name
Test status
Simulation time 102566433437 ps
CPU time 229.82 seconds
Started Jul 22 05:50:10 PM PDT 24
Finished Jul 22 05:54:01 PM PDT 24
Peak memory 249812 kb
Host smart-ee5198fe-a47d-4783-a132-13024ca7dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551101127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1551101127
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1192762570
Short name T295
Test name
Test status
Simulation time 4372652426 ps
CPU time 92.69 seconds
Started Jul 22 05:50:22 PM PDT 24
Finished Jul 22 05:51:56 PM PDT 24
Peak memory 272060 kb
Host smart-efb85690-166b-4a20-b998-1d049c0e9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192762570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1192762570
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1852403271
Short name T814
Test name
Test status
Simulation time 2899295907 ps
CPU time 11.39 seconds
Started Jul 22 05:50:18 PM PDT 24
Finished Jul 22 05:50:30 PM PDT 24
Peak memory 234940 kb
Host smart-ade41795-3d65-4f39-b7ba-74960b20940d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852403271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1852403271
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1580689213
Short name T856
Test name
Test status
Simulation time 1347737585 ps
CPU time 15.13 seconds
Started Jul 22 05:50:08 PM PDT 24
Finished Jul 22 05:50:23 PM PDT 24
Peak memory 238400 kb
Host smart-76425594-38ac-448e-9e69-3f19ca87fd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580689213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1580689213
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.2993020659
Short name T3
Test name
Test status
Simulation time 341244591 ps
CPU time 2.85 seconds
Started Jul 22 05:49:58 PM PDT 24
Finished Jul 22 05:50:01 PM PDT 24
Peak memory 232908 kb
Host smart-8f17fd51-6330-487a-a671-804cb33c2892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993020659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.2993020659
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3797023660
Short name T835
Test name
Test status
Simulation time 37500685300 ps
CPU time 75.82 seconds
Started Jul 22 05:50:00 PM PDT 24
Finished Jul 22 05:51:17 PM PDT 24
Peak memory 249352 kb
Host smart-83d74695-8b00-4bc6-92fc-d18b6087d988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797023660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3797023660
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.3199658582
Short name T285
Test name
Test status
Simulation time 1043335109 ps
CPU time 6.14 seconds
Started Jul 22 05:49:59 PM PDT 24
Finished Jul 22 05:50:05 PM PDT 24
Peak memory 224724 kb
Host smart-812b3396-eded-4226-bd05-feb566522c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199658582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.3199658582
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.4223320090
Short name T230
Test name
Test status
Simulation time 756570588 ps
CPU time 7.96 seconds
Started Jul 22 05:50:01 PM PDT 24
Finished Jul 22 05:50:09 PM PDT 24
Peak memory 232884 kb
Host smart-6824b67e-a1b1-41cb-bb1a-1ea091b63955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223320090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4223320090
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3381205919
Short name T425
Test name
Test status
Simulation time 14394759856 ps
CPU time 12.05 seconds
Started Jul 22 05:50:10 PM PDT 24
Finished Jul 22 05:50:23 PM PDT 24
Peak memory 219460 kb
Host smart-ce02c25e-69b1-4876-84d9-7a2c22aa061d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3381205919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3381205919
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.796976042
Short name T15
Test name
Test status
Simulation time 10171696816 ps
CPU time 38.04 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:50:59 PM PDT 24
Peak memory 249424 kb
Host smart-82a06043-ce31-4e82-bd14-1ca601157de6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796976042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.796976042
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.4037698210
Short name T480
Test name
Test status
Simulation time 4894671602 ps
CPU time 8.92 seconds
Started Jul 22 05:49:59 PM PDT 24
Finished Jul 22 05:50:08 PM PDT 24
Peak memory 216832 kb
Host smart-12ecc187-0b07-4fe2-a917-1c6791cfa38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037698210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.4037698210
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2367072043
Short name T609
Test name
Test status
Simulation time 2092039528 ps
CPU time 7.05 seconds
Started Jul 22 05:50:08 PM PDT 24
Finished Jul 22 05:50:15 PM PDT 24
Peak memory 216408 kb
Host smart-52687330-55f9-4d2a-82e6-071eb722ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367072043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2367072043
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3028743920
Short name T385
Test name
Test status
Simulation time 458496461 ps
CPU time 4.45 seconds
Started Jul 22 05:50:00 PM PDT 24
Finished Jul 22 05:50:05 PM PDT 24
Peak memory 216380 kb
Host smart-949587dd-b496-41ba-969f-a882262d4215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028743920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3028743920
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1741653029
Short name T703
Test name
Test status
Simulation time 69406109 ps
CPU time 0.7 seconds
Started Jul 22 05:50:01 PM PDT 24
Finished Jul 22 05:50:02 PM PDT 24
Peak memory 206076 kb
Host smart-b3b44b2b-baec-4be7-afa0-4782bcc22887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741653029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1741653029
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1820880322
Short name T472
Test name
Test status
Simulation time 126976551 ps
CPU time 3.66 seconds
Started Jul 22 05:50:00 PM PDT 24
Finished Jul 22 05:50:04 PM PDT 24
Peak memory 236048 kb
Host smart-0491b7c8-ed37-4b5c-8b8f-107c3c2c7007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820880322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1820880322
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2497992440
Short name T755
Test name
Test status
Simulation time 31895717 ps
CPU time 0.69 seconds
Started Jul 22 05:50:21 PM PDT 24
Finished Jul 22 05:50:22 PM PDT 24
Peak memory 205036 kb
Host smart-210653c7-b2e9-456e-b3c4-3ae2060ee1a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497992440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2497992440
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3092767346
Short name T720
Test name
Test status
Simulation time 5057775618 ps
CPU time 27.99 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:50:38 PM PDT 24
Peak memory 232876 kb
Host smart-1cb33ce9-daff-42cf-bd80-e1159281d1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092767346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3092767346
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.34197502
Short name T930
Test name
Test status
Simulation time 128181611 ps
CPU time 0.79 seconds
Started Jul 22 05:50:08 PM PDT 24
Finished Jul 22 05:50:09 PM PDT 24
Peak memory 206596 kb
Host smart-c449cbad-8844-466c-b665-b51254c2da1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34197502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.34197502
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1623671476
Short name T550
Test name
Test status
Simulation time 4160395052 ps
CPU time 16.09 seconds
Started Jul 22 05:50:10 PM PDT 24
Finished Jul 22 05:50:27 PM PDT 24
Peak memory 232872 kb
Host smart-31beb2ce-2385-42aa-b3a8-4816081bac1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623671476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1623671476
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2935427429
Short name T698
Test name
Test status
Simulation time 8731786992 ps
CPU time 110.36 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:52:00 PM PDT 24
Peak memory 255752 kb
Host smart-0c5f92f6-a2f7-4d57-b5ba-a0abe21644ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935427429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2935427429
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3692322537
Short name T440
Test name
Test status
Simulation time 12678283797 ps
CPU time 83.37 seconds
Started Jul 22 05:50:18 PM PDT 24
Finished Jul 22 05:51:42 PM PDT 24
Peak memory 265716 kb
Host smart-b521946a-3521-4253-9677-79ebe31551b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692322537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3692322537
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3341502530
Short name T515
Test name
Test status
Simulation time 1128762400 ps
CPU time 16.82 seconds
Started Jul 22 05:50:25 PM PDT 24
Finished Jul 22 05:50:43 PM PDT 24
Peak memory 240628 kb
Host smart-102d1135-33c8-4479-92cf-4eaba9ca03b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341502530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3341502530
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2668386261
Short name T489
Test name
Test status
Simulation time 27527066316 ps
CPU time 52.12 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:51:02 PM PDT 24
Peak memory 253980 kb
Host smart-31a8dc4c-6701-4343-87bc-1e0af8d6caa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668386261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2668386261
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1438781106
Short name T567
Test name
Test status
Simulation time 730759218 ps
CPU time 8.23 seconds
Started Jul 22 05:50:18 PM PDT 24
Finished Jul 22 05:50:27 PM PDT 24
Peak memory 224684 kb
Host smart-98c50ae8-7eb1-4536-b837-37993e79f67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438781106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1438781106
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2000846416
Short name T562
Test name
Test status
Simulation time 823386136 ps
CPU time 11.28 seconds
Started Jul 22 05:50:11 PM PDT 24
Finished Jul 22 05:50:23 PM PDT 24
Peak memory 237916 kb
Host smart-08fff5e1-609d-452a-877d-c631478c4729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000846416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2000846416
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2468994565
Short name T873
Test name
Test status
Simulation time 1172757545 ps
CPU time 10.84 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:50:20 PM PDT 24
Peak memory 249156 kb
Host smart-26d704d7-d8fd-4409-8b81-f7c08b84d2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468994565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2468994565
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2999044772
Short name T250
Test name
Test status
Simulation time 16358060506 ps
CPU time 15.49 seconds
Started Jul 22 05:50:19 PM PDT 24
Finished Jul 22 05:50:35 PM PDT 24
Peak memory 224776 kb
Host smart-f8900630-d7dc-4ba8-9d57-5685f4d01ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999044772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2999044772
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2864421418
Short name T445
Test name
Test status
Simulation time 400696577 ps
CPU time 5.22 seconds
Started Jul 22 05:50:22 PM PDT 24
Finished Jul 22 05:50:28 PM PDT 24
Peak memory 222780 kb
Host smart-ad931b76-848f-4d07-b49b-946cf54c1178
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2864421418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2864421418
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.122064920
Short name T781
Test name
Test status
Simulation time 18204058670 ps
CPU time 59.97 seconds
Started Jul 22 05:50:19 PM PDT 24
Finished Jul 22 05:51:19 PM PDT 24
Peak memory 240224 kb
Host smart-ce3f04ab-5b6a-4643-acbf-3320e9b16635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122064920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stres
s_all.122064920
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3227669464
Short name T750
Test name
Test status
Simulation time 2042955071 ps
CPU time 3.66 seconds
Started Jul 22 05:50:08 PM PDT 24
Finished Jul 22 05:50:13 PM PDT 24
Peak memory 216404 kb
Host smart-ea3793ef-8823-4b36-85c0-f124acdcab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227669464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3227669464
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1569861792
Short name T957
Test name
Test status
Simulation time 1491468770 ps
CPU time 4.83 seconds
Started Jul 22 05:50:12 PM PDT 24
Finished Jul 22 05:50:17 PM PDT 24
Peak memory 216380 kb
Host smart-2ce52dbf-51e4-4fae-9beb-817e9b98a0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569861792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1569861792
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1048715002
Short name T984
Test name
Test status
Simulation time 245330923 ps
CPU time 1.92 seconds
Started Jul 22 05:50:09 PM PDT 24
Finished Jul 22 05:50:12 PM PDT 24
Peak memory 216556 kb
Host smart-813effff-c974-43e3-b7f6-e46607bf0e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048715002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1048715002
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1798504140
Short name T95
Test name
Test status
Simulation time 94832905 ps
CPU time 0.88 seconds
Started Jul 22 05:50:11 PM PDT 24
Finished Jul 22 05:50:12 PM PDT 24
Peak memory 206188 kb
Host smart-058559f4-832e-4e20-b881-b64c6b83165c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798504140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1798504140
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3601598800
Short name T244
Test name
Test status
Simulation time 299645071 ps
CPU time 2.65 seconds
Started Jul 22 05:50:11 PM PDT 24
Finished Jul 22 05:50:14 PM PDT 24
Peak memory 232884 kb
Host smart-8be8c6f7-570a-4a97-ba21-cc6b3791555a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601598800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3601598800
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.3745795081
Short name T352
Test name
Test status
Simulation time 80120662 ps
CPU time 0.72 seconds
Started Jul 22 05:50:31 PM PDT 24
Finished Jul 22 05:50:32 PM PDT 24
Peak memory 205040 kb
Host smart-ed973ac7-e73f-4c0c-a85a-89727fef82ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745795081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
3745795081
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2615253619
Short name T971
Test name
Test status
Simulation time 462995012 ps
CPU time 3.9 seconds
Started Jul 22 05:50:21 PM PDT 24
Finished Jul 22 05:50:25 PM PDT 24
Peak memory 232828 kb
Host smart-b2414583-41e8-447c-bb6d-c2f59c3e545d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615253619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2615253619
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.2374511888
Short name T573
Test name
Test status
Simulation time 52279021 ps
CPU time 0.76 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:50:22 PM PDT 24
Peak memory 206672 kb
Host smart-94b6a83c-3907-407e-8078-49fe5c15ae90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374511888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.2374511888
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1232621170
Short name T768
Test name
Test status
Simulation time 2951980084 ps
CPU time 25.56 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:50:46 PM PDT 24
Peak memory 241148 kb
Host smart-0934b746-36bb-4057-8522-50dd02c09b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232621170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1232621170
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.906418269
Short name T296
Test name
Test status
Simulation time 55878871323 ps
CPU time 114.95 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:52:15 PM PDT 24
Peak memory 255192 kb
Host smart-4a75dd64-716f-44ea-b4a3-4f55066bc68b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906418269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.906418269
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.4019361877
Short name T231
Test name
Test status
Simulation time 116304948611 ps
CPU time 357.23 seconds
Started Jul 22 05:50:30 PM PDT 24
Finished Jul 22 05:56:27 PM PDT 24
Peak memory 255556 kb
Host smart-f4a6439e-77fb-4b40-ba28-84dc29e5db11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019361877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.4019361877
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1197319204
Short name T831
Test name
Test status
Simulation time 1136060418 ps
CPU time 13.87 seconds
Started Jul 22 05:50:19 PM PDT 24
Finished Jul 22 05:50:34 PM PDT 24
Peak memory 241016 kb
Host smart-1132d2a6-1529-44cf-ae83-ef656acb2209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197319204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1197319204
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1299879957
Short name T985
Test name
Test status
Simulation time 155263568257 ps
CPU time 257.61 seconds
Started Jul 22 05:50:19 PM PDT 24
Finished Jul 22 05:54:37 PM PDT 24
Peak memory 252960 kb
Host smart-8a521a7b-5b50-426e-898b-a21c7c56d01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299879957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1299879957
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.918120078
Short name T248
Test name
Test status
Simulation time 183505063 ps
CPU time 5.84 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:50:26 PM PDT 24
Peak memory 232840 kb
Host smart-74645a3e-5139-4979-888c-f4950fa9398f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918120078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.918120078
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3482438516
Short name T868
Test name
Test status
Simulation time 6386883309 ps
CPU time 88.17 seconds
Started Jul 22 05:50:18 PM PDT 24
Finished Jul 22 05:51:47 PM PDT 24
Peak memory 232964 kb
Host smart-20be7497-cbfd-49c0-b4ba-11de1cc1b5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482438516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3482438516
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1739771091
Short name T271
Test name
Test status
Simulation time 13245877431 ps
CPU time 20.18 seconds
Started Jul 22 05:50:21 PM PDT 24
Finished Jul 22 05:50:41 PM PDT 24
Peak memory 240944 kb
Host smart-ce729340-1961-4227-8712-96d7a886a384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739771091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1739771091
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2180815577
Short name T967
Test name
Test status
Simulation time 1147134284 ps
CPU time 4.02 seconds
Started Jul 22 05:50:19 PM PDT 24
Finished Jul 22 05:50:23 PM PDT 24
Peak memory 232936 kb
Host smart-aad54127-8e90-4ef1-b27a-dc9677a5ac77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180815577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2180815577
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3459642141
Short name T570
Test name
Test status
Simulation time 207752038 ps
CPU time 4.49 seconds
Started Jul 22 05:50:19 PM PDT 24
Finished Jul 22 05:50:24 PM PDT 24
Peak memory 223800 kb
Host smart-e716d646-54ed-40a0-8951-73c7d854bbe0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3459642141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3459642141
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1518048405
Short name T860
Test name
Test status
Simulation time 23959391607 ps
CPU time 102.82 seconds
Started Jul 22 05:50:26 PM PDT 24
Finished Jul 22 05:52:10 PM PDT 24
Peak memory 250900 kb
Host smart-0920128a-8c0a-4da5-bda5-64f90f0bcb7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518048405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1518048405
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4009839309
Short name T461
Test name
Test status
Simulation time 2246932325 ps
CPU time 20.53 seconds
Started Jul 22 05:50:17 PM PDT 24
Finished Jul 22 05:50:38 PM PDT 24
Peak memory 216500 kb
Host smart-128d6e74-7aa5-4cf3-9b68-564b80378a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009839309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4009839309
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3866490259
Short name T451
Test name
Test status
Simulation time 3352461313 ps
CPU time 4.77 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:50:25 PM PDT 24
Peak memory 216404 kb
Host smart-b62fd2a4-f84a-4f2c-9ad0-fb8bb856e6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866490259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3866490259
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2522805026
Short name T346
Test name
Test status
Simulation time 219971503 ps
CPU time 3.32 seconds
Started Jul 22 05:50:20 PM PDT 24
Finished Jul 22 05:50:24 PM PDT 24
Peak memory 216416 kb
Host smart-ae56103a-2351-4a3e-885c-a8578df9ec6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522805026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2522805026
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3695378849
Short name T616
Test name
Test status
Simulation time 48446030 ps
CPU time 0.8 seconds
Started Jul 22 05:50:18 PM PDT 24
Finished Jul 22 05:50:20 PM PDT 24
Peak memory 206044 kb
Host smart-2411333c-5aa9-485a-abdc-2fb9aaa8fd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695378849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3695378849
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3369026412
Short name T256
Test name
Test status
Simulation time 769168036 ps
CPU time 4.69 seconds
Started Jul 22 05:50:29 PM PDT 24
Finished Jul 22 05:50:34 PM PDT 24
Peak memory 224704 kb
Host smart-81167023-11f1-4689-8827-5e0ba9901bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369026412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3369026412
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1183027351
Short name T840
Test name
Test status
Simulation time 14710933 ps
CPU time 0.78 seconds
Started Jul 22 05:50:32 PM PDT 24
Finished Jul 22 05:50:33 PM PDT 24
Peak memory 205036 kb
Host smart-07e7c9a1-33cf-483e-8bbe-f38817f92487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183027351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1183027351
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.404012023
Short name T361
Test name
Test status
Simulation time 142572980 ps
CPU time 2.9 seconds
Started Jul 22 05:50:27 PM PDT 24
Finished Jul 22 05:50:31 PM PDT 24
Peak memory 224712 kb
Host smart-fd343488-7075-4a1f-80fd-d24950c7f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404012023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.404012023
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4277308378
Short name T378
Test name
Test status
Simulation time 68698019 ps
CPU time 0.79 seconds
Started Jul 22 05:50:27 PM PDT 24
Finished Jul 22 05:50:28 PM PDT 24
Peak memory 206728 kb
Host smart-06b7b57a-8bab-4670-b233-70b48c2aaf4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277308378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4277308378
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1040326257
Short name T24
Test name
Test status
Simulation time 10305196251 ps
CPU time 144.57 seconds
Started Jul 22 05:50:29 PM PDT 24
Finished Jul 22 05:52:54 PM PDT 24
Peak memory 251212 kb
Host smart-164e7109-fdab-49aa-a967-99809b32e2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040326257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1040326257
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1739673340
Short name T196
Test name
Test status
Simulation time 25153994676 ps
CPU time 71.89 seconds
Started Jul 22 05:50:29 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 241168 kb
Host smart-a004cae8-d636-429c-8f54-39552df5de33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739673340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1739673340
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2640487925
Short name T796
Test name
Test status
Simulation time 13755836750 ps
CPU time 188.56 seconds
Started Jul 22 05:50:32 PM PDT 24
Finished Jul 22 05:53:40 PM PDT 24
Peak memory 267364 kb
Host smart-048b10c8-13cc-450a-bd12-477db801051a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640487925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2640487925
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2835105818
Short name T940
Test name
Test status
Simulation time 114146276 ps
CPU time 5.46 seconds
Started Jul 22 05:50:52 PM PDT 24
Finished Jul 22 05:50:58 PM PDT 24
Peak memory 232772 kb
Host smart-e5758853-011f-4e86-8d26-5e93da172d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835105818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2835105818
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2551666598
Short name T99
Test name
Test status
Simulation time 16924104930 ps
CPU time 133.21 seconds
Started Jul 22 05:50:35 PM PDT 24
Finished Jul 22 05:52:49 PM PDT 24
Peak memory 249356 kb
Host smart-88a67ecf-5a5b-4117-9e68-8d82da69f9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551666598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2551666598
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.452175337
Short name T663
Test name
Test status
Simulation time 4912329340 ps
CPU time 11.36 seconds
Started Jul 22 05:50:31 PM PDT 24
Finished Jul 22 05:50:43 PM PDT 24
Peak memory 224724 kb
Host smart-6204c982-eccf-43af-8371-a68eb689ac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452175337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.452175337
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3853264404
Short name T825
Test name
Test status
Simulation time 3162308177 ps
CPU time 25.01 seconds
Started Jul 22 05:50:30 PM PDT 24
Finished Jul 22 05:50:55 PM PDT 24
Peak memory 237552 kb
Host smart-98b35369-aa41-4dfe-8701-0f70aac2f012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853264404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3853264404
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4294719897
Short name T266
Test name
Test status
Simulation time 6036063609 ps
CPU time 23.04 seconds
Started Jul 22 05:50:30 PM PDT 24
Finished Jul 22 05:50:54 PM PDT 24
Peak memory 238712 kb
Host smart-182126b4-9e59-4ff3-a1b5-170a0f25a03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294719897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4294719897
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1737444654
Short name T255
Test name
Test status
Simulation time 359032404 ps
CPU time 4.39 seconds
Started Jul 22 05:50:26 PM PDT 24
Finished Jul 22 05:50:31 PM PDT 24
Peak memory 232836 kb
Host smart-49b46180-2dff-4cad-92b4-b1f87d7af1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737444654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1737444654
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3636133282
Short name T362
Test name
Test status
Simulation time 436275623 ps
CPU time 6.07 seconds
Started Jul 22 05:50:49 PM PDT 24
Finished Jul 22 05:50:56 PM PDT 24
Peak memory 223124 kb
Host smart-e33360e6-8785-4adf-a9f0-0f5f756bb1a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3636133282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3636133282
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2365476764
Short name T718
Test name
Test status
Simulation time 600050065 ps
CPU time 1.06 seconds
Started Jul 22 05:50:27 PM PDT 24
Finished Jul 22 05:50:29 PM PDT 24
Peak memory 207796 kb
Host smart-e3010b44-0110-4099-9fed-b21bc4731d7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365476764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2365476764
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.548753165
Short name T35
Test name
Test status
Simulation time 26737174040 ps
CPU time 36.27 seconds
Started Jul 22 05:50:51 PM PDT 24
Finished Jul 22 05:51:28 PM PDT 24
Peak memory 216528 kb
Host smart-b91b3263-f8aa-46ba-af21-02b1aa919da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548753165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.548753165
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2297375772
Short name T443
Test name
Test status
Simulation time 2948678645 ps
CPU time 3.11 seconds
Started Jul 22 05:50:27 PM PDT 24
Finished Jul 22 05:50:30 PM PDT 24
Peak memory 216280 kb
Host smart-59cb1fb1-5559-48aa-a50a-269909e7145b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297375772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2297375772
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2252985961
Short name T669
Test name
Test status
Simulation time 65110645 ps
CPU time 2.55 seconds
Started Jul 22 05:50:28 PM PDT 24
Finished Jul 22 05:50:31 PM PDT 24
Peak memory 216412 kb
Host smart-1ac786a6-fa1c-46b9-b2b0-33c42ec90c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252985961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2252985961
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2376802513
Short name T33
Test name
Test status
Simulation time 55428492 ps
CPU time 0.85 seconds
Started Jul 22 05:50:36 PM PDT 24
Finished Jul 22 05:50:37 PM PDT 24
Peak memory 206040 kb
Host smart-0742b6a2-16b8-4df8-80b4-2f01429fc9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376802513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2376802513
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1131888535
Short name T889
Test name
Test status
Simulation time 137716839 ps
CPU time 2.56 seconds
Started Jul 22 05:50:29 PM PDT 24
Finished Jul 22 05:50:32 PM PDT 24
Peak memory 224364 kb
Host smart-4a377508-38e1-46b1-a67a-b2578a306ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131888535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1131888535
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.2672759870
Short name T28
Test name
Test status
Simulation time 40128939 ps
CPU time 0.69 seconds
Started Jul 22 05:50:38 PM PDT 24
Finished Jul 22 05:50:39 PM PDT 24
Peak memory 205264 kb
Host smart-993f37e4-a97f-4819-98da-a6b138347ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672759870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
2672759870
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.45433949
Short name T733
Test name
Test status
Simulation time 2199827744 ps
CPU time 19.47 seconds
Started Jul 22 05:50:37 PM PDT 24
Finished Jul 22 05:50:58 PM PDT 24
Peak memory 224700 kb
Host smart-f9e97ae2-8a94-4c0a-9bb8-18039c814138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45433949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.45433949
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2187873222
Short name T777
Test name
Test status
Simulation time 19940724 ps
CPU time 0.76 seconds
Started Jul 22 05:50:30 PM PDT 24
Finished Jul 22 05:50:31 PM PDT 24
Peak memory 207028 kb
Host smart-b62a3883-cba8-46df-8290-8a19fc6e49ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187873222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2187873222
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3341820383
Short name T286
Test name
Test status
Simulation time 15353709780 ps
CPU time 88.91 seconds
Started Jul 22 05:50:38 PM PDT 24
Finished Jul 22 05:52:08 PM PDT 24
Peak memory 267208 kb
Host smart-203c5493-10ef-4b5f-ac72-eada0d795462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341820383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3341820383
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.355411441
Short name T207
Test name
Test status
Simulation time 60034870988 ps
CPU time 97.27 seconds
Started Jul 22 05:52:12 PM PDT 24
Finished Jul 22 05:53:50 PM PDT 24
Peak memory 273904 kb
Host smart-e97557d3-76ea-4a52-bec7-4979133770ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355411441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.355411441
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4209162731
Short name T770
Test name
Test status
Simulation time 6637724855 ps
CPU time 94.91 seconds
Started Jul 22 05:52:12 PM PDT 24
Finished Jul 22 05:53:47 PM PDT 24
Peak memory 254244 kb
Host smart-b9365897-aee2-4d9e-ba14-23d926eab97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209162731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4209162731
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.771728569
Short name T303
Test name
Test status
Simulation time 4134798625 ps
CPU time 27.85 seconds
Started Jul 22 05:50:38 PM PDT 24
Finished Jul 22 05:51:07 PM PDT 24
Peak memory 232984 kb
Host smart-f52e5509-27d4-44bf-8ac7-ad5186243618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771728569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.771728569
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1023068367
Short name T965
Test name
Test status
Simulation time 6381953593 ps
CPU time 26.25 seconds
Started Jul 22 05:50:36 PM PDT 24
Finished Jul 22 05:51:03 PM PDT 24
Peak memory 250140 kb
Host smart-e898f537-1168-4a8e-b9a4-6ef7ecb4f08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023068367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1023068367
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2809702555
Short name T47
Test name
Test status
Simulation time 653072780 ps
CPU time 11.13 seconds
Started Jul 22 05:52:12 PM PDT 24
Finished Jul 22 05:52:23 PM PDT 24
Peak memory 224668 kb
Host smart-3f7bc697-309c-4d8b-8bf7-b22d8caac999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809702555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2809702555
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3679086595
Short name T210
Test name
Test status
Simulation time 14894411583 ps
CPU time 30.55 seconds
Started Jul 22 05:51:02 PM PDT 24
Finished Jul 22 05:51:33 PM PDT 24
Peak memory 240916 kb
Host smart-f4415c21-85d6-4b99-b6c3-0cb69902f4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679086595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3679086595
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.4037212527
Short name T336
Test name
Test status
Simulation time 705132140 ps
CPU time 4.83 seconds
Started Jul 22 05:50:41 PM PDT 24
Finished Jul 22 05:50:46 PM PDT 24
Peak memory 224648 kb
Host smart-0283f58c-a853-471e-b6c5-357f675939a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037212527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.4037212527
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3408477888
Short name T254
Test name
Test status
Simulation time 36572178704 ps
CPU time 28.94 seconds
Started Jul 22 05:50:37 PM PDT 24
Finished Jul 22 05:51:07 PM PDT 24
Peak memory 232952 kb
Host smart-e54b4dfd-e8ef-47ea-aaa9-733486c64757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408477888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3408477888
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2946816587
Short name T403
Test name
Test status
Simulation time 143937439 ps
CPU time 3.98 seconds
Started Jul 22 05:50:38 PM PDT 24
Finished Jul 22 05:50:42 PM PDT 24
Peak memory 222940 kb
Host smart-52087919-82a1-462c-98f6-d09366bd4096
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2946816587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2946816587
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.1892159358
Short name T697
Test name
Test status
Simulation time 231540013 ps
CPU time 1.01 seconds
Started Jul 22 05:50:37 PM PDT 24
Finished Jul 22 05:50:38 PM PDT 24
Peak memory 215096 kb
Host smart-d369d504-e005-4832-82b7-6cd617ba4a0b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892159358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.1892159358
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.713151581
Short name T305
Test name
Test status
Simulation time 14256757708 ps
CPU time 31 seconds
Started Jul 22 05:50:32 PM PDT 24
Finished Jul 22 05:51:03 PM PDT 24
Peak memory 216416 kb
Host smart-22455970-8faf-4764-b792-5c6f3aade76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713151581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.713151581
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.23122886
Short name T726
Test name
Test status
Simulation time 2044034966 ps
CPU time 4.99 seconds
Started Jul 22 05:50:36 PM PDT 24
Finished Jul 22 05:50:41 PM PDT 24
Peak memory 216352 kb
Host smart-c3aa02cd-a18d-48a0-864b-471f200876d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23122886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.23122886
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.967471372
Short name T676
Test name
Test status
Simulation time 179173362 ps
CPU time 1.22 seconds
Started Jul 22 05:50:56 PM PDT 24
Finished Jul 22 05:50:58 PM PDT 24
Peak memory 216440 kb
Host smart-184b48bd-fdcd-4f59-b532-da25fd142d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967471372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.967471372
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3148759189
Short name T539
Test name
Test status
Simulation time 80269378 ps
CPU time 0.75 seconds
Started Jul 22 05:50:26 PM PDT 24
Finished Jul 22 05:50:28 PM PDT 24
Peak memory 206116 kb
Host smart-ab55d9f7-c71f-4802-b846-47cc5f7dc0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148759189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3148759189
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3078380799
Short name T48
Test name
Test status
Simulation time 543468806 ps
CPU time 2.99 seconds
Started Jul 22 05:50:40 PM PDT 24
Finished Jul 22 05:50:43 PM PDT 24
Peak memory 224668 kb
Host smart-71da6d8d-6378-4d31-ad27-bb52787626da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078380799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3078380799
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.409969341
Short name T996
Test name
Test status
Simulation time 20877223 ps
CPU time 0.7 seconds
Started Jul 22 05:50:49 PM PDT 24
Finished Jul 22 05:50:51 PM PDT 24
Peak memory 204992 kb
Host smart-238a4c52-5bd3-4452-9160-43a2fadf5dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409969341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.409969341
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2679685509
Short name T783
Test name
Test status
Simulation time 164582673 ps
CPU time 3.99 seconds
Started Jul 22 05:50:48 PM PDT 24
Finished Jul 22 05:50:53 PM PDT 24
Peak memory 224588 kb
Host smart-eccb0535-ca99-43bc-a491-a224b864618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679685509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2679685509
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3980721324
Short name T866
Test name
Test status
Simulation time 15657109 ps
CPU time 0.77 seconds
Started Jul 22 05:50:38 PM PDT 24
Finished Jul 22 05:50:39 PM PDT 24
Peak memory 206700 kb
Host smart-078d14ec-13c5-4d0e-acd3-a07135573667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980721324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3980721324
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2449112495
Short name T160
Test name
Test status
Simulation time 1303553741 ps
CPU time 9.96 seconds
Started Jul 22 05:50:46 PM PDT 24
Finished Jul 22 05:50:56 PM PDT 24
Peak memory 241088 kb
Host smart-01245d9a-7b7d-415b-bda0-9d9db1794ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449112495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2449112495
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.138364513
Short name T55
Test name
Test status
Simulation time 27910009537 ps
CPU time 198.8 seconds
Started Jul 22 05:50:45 PM PDT 24
Finished Jul 22 05:54:05 PM PDT 24
Peak memory 249544 kb
Host smart-f93aff4f-dc79-44be-8ce8-228f849209ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138364513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.138364513
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.216867170
Short name T90
Test name
Test status
Simulation time 25869626318 ps
CPU time 43.25 seconds
Started Jul 22 05:52:12 PM PDT 24
Finished Jul 22 05:52:56 PM PDT 24
Peak memory 233980 kb
Host smart-ad4503e0-2ba0-4c5f-ad95-edb1a4fa5bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216867170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.216867170
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.712921607
Short name T349
Test name
Test status
Simulation time 3679310908 ps
CPU time 19.23 seconds
Started Jul 22 05:50:47 PM PDT 24
Finished Jul 22 05:51:06 PM PDT 24
Peak memory 224620 kb
Host smart-8ba697a3-0a1d-4823-9822-a92da0026f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712921607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.712921607
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.3849700711
Short name T41
Test name
Test status
Simulation time 18060849770 ps
CPU time 90.98 seconds
Started Jul 22 05:50:48 PM PDT 24
Finished Jul 22 05:52:19 PM PDT 24
Peak memory 257184 kb
Host smart-cf22ebba-d802-44d8-8478-4ee1c802d772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849700711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.3849700711
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.878663448
Short name T824
Test name
Test status
Simulation time 1660443770 ps
CPU time 6.77 seconds
Started Jul 22 05:50:51 PM PDT 24
Finished Jul 22 05:50:58 PM PDT 24
Peak memory 232808 kb
Host smart-65886930-0bdd-42ae-80d1-746571d423a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878663448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.878663448
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3618207129
Short name T937
Test name
Test status
Simulation time 2317737909 ps
CPU time 10.91 seconds
Started Jul 22 05:52:11 PM PDT 24
Finished Jul 22 05:52:22 PM PDT 24
Peak memory 232924 kb
Host smart-9a8ee321-cc19-4f26-834b-460c3d06e2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618207129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3618207129
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3112652980
Short name T198
Test name
Test status
Simulation time 169594538 ps
CPU time 4.28 seconds
Started Jul 22 05:50:47 PM PDT 24
Finished Jul 22 05:50:52 PM PDT 24
Peak memory 224596 kb
Host smart-e8e82b5d-ffb2-4c3e-9e9a-66bc16c1dde7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112652980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3112652980
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1989942583
Short name T797
Test name
Test status
Simulation time 1446624751 ps
CPU time 5.77 seconds
Started Jul 22 05:50:49 PM PDT 24
Finished Jul 22 05:50:55 PM PDT 24
Peak memory 224676 kb
Host smart-8f06c401-58cf-48f4-8b88-cbe82c1a3c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989942583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1989942583
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2830043583
Short name T988
Test name
Test status
Simulation time 1657611386 ps
CPU time 6.04 seconds
Started Jul 22 05:50:47 PM PDT 24
Finished Jul 22 05:50:53 PM PDT 24
Peak memory 219088 kb
Host smart-215c966a-5b81-45b4-948d-06166327812b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2830043583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2830043583
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4093179709
Short name T211
Test name
Test status
Simulation time 24272701505 ps
CPU time 192.92 seconds
Started Jul 22 05:50:48 PM PDT 24
Finished Jul 22 05:54:01 PM PDT 24
Peak memory 237972 kb
Host smart-0c9c16a8-9d37-467c-9b2f-8f7c57737aa4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093179709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4093179709
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.3062503967
Short name T791
Test name
Test status
Simulation time 828389660 ps
CPU time 3.62 seconds
Started Jul 22 05:50:46 PM PDT 24
Finished Jul 22 05:50:50 PM PDT 24
Peak memory 216756 kb
Host smart-07b2baf2-b37e-40d0-96be-2786794d311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062503967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3062503967
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2583752212
Short name T358
Test name
Test status
Simulation time 1545665252 ps
CPU time 4.23 seconds
Started Jul 22 05:50:46 PM PDT 24
Finished Jul 22 05:50:51 PM PDT 24
Peak memory 216276 kb
Host smart-69697b8a-0626-44da-9045-b1fd2f6a5a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583752212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2583752212
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.549572816
Short name T577
Test name
Test status
Simulation time 207244674 ps
CPU time 1.24 seconds
Started Jul 22 05:53:03 PM PDT 24
Finished Jul 22 05:53:04 PM PDT 24
Peak memory 216244 kb
Host smart-158531c7-1b55-4969-b294-c6c5ee8b02ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549572816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.549572816
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.176977564
Short name T338
Test name
Test status
Simulation time 32520712 ps
CPU time 0.81 seconds
Started Jul 22 05:50:49 PM PDT 24
Finished Jul 22 05:50:50 PM PDT 24
Peak memory 206036 kb
Host smart-5f0ff494-dd59-4f79-a365-5e60f955dfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176977564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.176977564
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1050617549
Short name T863
Test name
Test status
Simulation time 263504114 ps
CPU time 2.3 seconds
Started Jul 22 05:50:46 PM PDT 24
Finished Jul 22 05:50:49 PM PDT 24
Peak memory 224320 kb
Host smart-9c0b79f4-970e-4f90-9d63-73d0b5de6841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050617549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1050617549
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2743316002
Short name T62
Test name
Test status
Simulation time 115572370 ps
CPU time 0.74 seconds
Started Jul 22 05:50:56 PM PDT 24
Finished Jul 22 05:50:57 PM PDT 24
Peak memory 205608 kb
Host smart-070d5f42-f3b6-41bb-a7c5-bb88a9185616
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743316002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2743316002
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2714602705
Short name T875
Test name
Test status
Simulation time 609926734 ps
CPU time 2.82 seconds
Started Jul 22 05:51:15 PM PDT 24
Finished Jul 22 05:51:19 PM PDT 24
Peak memory 224636 kb
Host smart-38ba634b-deb8-41ca-a40d-ca32c397503d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714602705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2714602705
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.2923999209
Short name T779
Test name
Test status
Simulation time 16921758 ps
CPU time 0.75 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:51:21 PM PDT 24
Peak memory 206028 kb
Host smart-dc2a1de9-d7a6-41a0-aa7f-b15f70c0374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923999209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.2923999209
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2318800197
Short name T10
Test name
Test status
Simulation time 9388468580 ps
CPU time 75.5 seconds
Started Jul 22 05:50:55 PM PDT 24
Finished Jul 22 05:52:11 PM PDT 24
Peak memory 255640 kb
Host smart-52a39281-27c5-4e6e-a1b4-306792dfece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318800197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2318800197
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1459089357
Short name T311
Test name
Test status
Simulation time 2423810017 ps
CPU time 6.83 seconds
Started Jul 22 05:51:04 PM PDT 24
Finished Jul 22 05:51:13 PM PDT 24
Peak memory 217644 kb
Host smart-6a6c378b-d55e-4785-8aae-eea5ef7960fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459089357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1459089357
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.1378130675
Short name T410
Test name
Test status
Simulation time 250169584 ps
CPU time 2.86 seconds
Started Jul 22 05:50:56 PM PDT 24
Finished Jul 22 05:50:59 PM PDT 24
Peak memory 224716 kb
Host smart-b44039e4-18d7-4851-be0c-7438fc4a5ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378130675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.1378130675
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.2478100804
Short name T235
Test name
Test status
Simulation time 8173953802 ps
CPU time 90.05 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:52:51 PM PDT 24
Peak memory 267776 kb
Host smart-f4081f85-39c9-42b5-9062-1bf907932894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478100804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.2478100804
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4026501198
Short name T739
Test name
Test status
Simulation time 178756056 ps
CPU time 4.68 seconds
Started Jul 22 05:53:02 PM PDT 24
Finished Jul 22 05:53:08 PM PDT 24
Peak memory 232912 kb
Host smart-25806839-38ed-4aba-84d6-cfb19b2c36a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026501198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4026501198
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.4170051395
Short name T862
Test name
Test status
Simulation time 491706681 ps
CPU time 9.97 seconds
Started Jul 22 05:50:57 PM PDT 24
Finished Jul 22 05:51:07 PM PDT 24
Peak memory 224648 kb
Host smart-7338e72d-6b72-443f-af35-c6440024380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170051395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.4170051395
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1290069763
Short name T876
Test name
Test status
Simulation time 135376598 ps
CPU time 3.89 seconds
Started Jul 22 05:50:55 PM PDT 24
Finished Jul 22 05:51:00 PM PDT 24
Peak memory 232784 kb
Host smart-4aaef45e-7a45-474d-88d0-3e4faef780ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290069763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1290069763
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3176743881
Short name T803
Test name
Test status
Simulation time 4855151361 ps
CPU time 10.47 seconds
Started Jul 22 05:50:55 PM PDT 24
Finished Jul 22 05:51:06 PM PDT 24
Peak memory 240192 kb
Host smart-8c9bc801-cbc9-45f9-b89f-bb8ff8b569a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176743881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3176743881
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1460401605
Short name T392
Test name
Test status
Simulation time 567273749 ps
CPU time 4.57 seconds
Started Jul 22 05:50:54 PM PDT 24
Finished Jul 22 05:50:59 PM PDT 24
Peak memory 220672 kb
Host smart-c21427be-7fd9-4b59-9d70-73c1f4159037
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1460401605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1460401605
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1008405859
Short name T688
Test name
Test status
Simulation time 31411695638 ps
CPU time 154.78 seconds
Started Jul 22 05:50:57 PM PDT 24
Finished Jul 22 05:53:32 PM PDT 24
Peak memory 249424 kb
Host smart-d369f982-464f-4092-9288-f8eaccec1d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008405859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1008405859
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.188493174
Short name T917
Test name
Test status
Simulation time 58855901 ps
CPU time 0.76 seconds
Started Jul 22 05:50:48 PM PDT 24
Finished Jul 22 05:50:50 PM PDT 24
Peak memory 205800 kb
Host smart-c7846145-9178-43c7-8dc1-59742ea00919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188493174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.188493174
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.1948447475
Short name T630
Test name
Test status
Simulation time 2291166933 ps
CPU time 3.92 seconds
Started Jul 22 05:50:47 PM PDT 24
Finished Jul 22 05:50:51 PM PDT 24
Peak memory 216496 kb
Host smart-7d58192d-831c-4c04-b1c0-06f0a4060c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948447475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.1948447475
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2500575567
Short name T968
Test name
Test status
Simulation time 625458757 ps
CPU time 1 seconds
Started Jul 22 05:51:07 PM PDT 24
Finished Jul 22 05:51:09 PM PDT 24
Peak memory 208016 kb
Host smart-d281fa38-fa12-4cb1-bdd1-f711133c7790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500575567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2500575567
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.960665967
Short name T389
Test name
Test status
Simulation time 87951885 ps
CPU time 0.89 seconds
Started Jul 22 05:50:52 PM PDT 24
Finished Jul 22 05:50:53 PM PDT 24
Peak memory 207084 kb
Host smart-261e884b-2e9b-4ba1-a4eb-56b5605b7909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960665967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.960665967
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.420515681
Short name T204
Test name
Test status
Simulation time 180128438 ps
CPU time 2.33 seconds
Started Jul 22 05:50:57 PM PDT 24
Finished Jul 22 05:51:00 PM PDT 24
Peak memory 224720 kb
Host smart-7673e3b5-0fc2-4e03-98c9-ba22078032b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420515681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.420515681
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3554276579
Short name T601
Test name
Test status
Simulation time 28018195 ps
CPU time 0.79 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:51:12 PM PDT 24
Peak memory 205908 kb
Host smart-5883e904-0294-46f2-9948-685414399f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554276579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3554276579
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.3924494606
Short name T454
Test name
Test status
Simulation time 1562817149 ps
CPU time 9.85 seconds
Started Jul 22 05:51:09 PM PDT 24
Finished Jul 22 05:51:20 PM PDT 24
Peak memory 232948 kb
Host smart-f41fc3f3-8a1e-4c79-97b6-0b6ddcc4a90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924494606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.3924494606
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2103084150
Short name T64
Test name
Test status
Simulation time 18699091 ps
CPU time 0.79 seconds
Started Jul 22 05:51:04 PM PDT 24
Finished Jul 22 05:51:06 PM PDT 24
Peak memory 207060 kb
Host smart-1d70f27f-c25c-4952-a935-c05a81c1f841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103084150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2103084150
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3458239195
Short name T885
Test name
Test status
Simulation time 25412685569 ps
CPU time 42.42 seconds
Started Jul 22 05:51:10 PM PDT 24
Finished Jul 22 05:51:53 PM PDT 24
Peak memory 237072 kb
Host smart-ca28077d-9930-4582-8018-ee8f054cb61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458239195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3458239195
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.762365891
Short name T865
Test name
Test status
Simulation time 41838798448 ps
CPU time 86.34 seconds
Started Jul 22 05:51:10 PM PDT 24
Finished Jul 22 05:52:37 PM PDT 24
Peak memory 225032 kb
Host smart-4f85c7ae-b6aa-47c3-8b54-6138c6725e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762365891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.762365891
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2496428755
Short name T221
Test name
Test status
Simulation time 46615919578 ps
CPU time 372.07 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 252448 kb
Host smart-0304a95d-5c48-49ec-bc60-92f88912e139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496428755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2496428755
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.64697738
Short name T503
Test name
Test status
Simulation time 3492110506 ps
CPU time 14.41 seconds
Started Jul 22 05:52:19 PM PDT 24
Finished Jul 22 05:52:34 PM PDT 24
Peak memory 232960 kb
Host smart-f42f9697-37f4-477a-8551-83680c522067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64697738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.64697738
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3788535410
Short name T941
Test name
Test status
Simulation time 2218814941 ps
CPU time 28.24 seconds
Started Jul 22 05:51:10 PM PDT 24
Finished Jul 22 05:51:39 PM PDT 24
Peak memory 250600 kb
Host smart-cfc83472-2a8e-4b74-a715-1afb97cd57ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788535410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3788535410
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.4101816928
Short name T681
Test name
Test status
Simulation time 417034691 ps
CPU time 2.69 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:51:14 PM PDT 24
Peak memory 224672 kb
Host smart-78f812c8-70e0-4633-8715-063531517858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101816928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.4101816928
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3751677925
Short name T386
Test name
Test status
Simulation time 48557361944 ps
CPU time 94.62 seconds
Started Jul 22 05:51:10 PM PDT 24
Finished Jul 22 05:52:46 PM PDT 24
Peak memory 224716 kb
Host smart-8b34055c-b6ef-4357-bf0c-febad589a04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751677925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3751677925
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2580180697
Short name T918
Test name
Test status
Simulation time 1596223024 ps
CPU time 9.82 seconds
Started Jul 22 05:52:59 PM PDT 24
Finished Jul 22 05:53:10 PM PDT 24
Peak memory 232808 kb
Host smart-7af38a79-02e6-45bf-9a89-7483e4e268ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580180697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2580180697
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.1166683161
Short name T241
Test name
Test status
Simulation time 1036669287 ps
CPU time 5.41 seconds
Started Jul 22 05:51:12 PM PDT 24
Finished Jul 22 05:51:18 PM PDT 24
Peak memory 224708 kb
Host smart-c0168443-befc-44e3-b8fc-72d77259ed1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166683161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.1166683161
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2130606569
Short name T499
Test name
Test status
Simulation time 423632454 ps
CPU time 8.3 seconds
Started Jul 22 05:51:10 PM PDT 24
Finished Jul 22 05:51:19 PM PDT 24
Peak memory 220924 kb
Host smart-1d7cbdcf-9470-44df-8e27-af1d7f5393ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2130606569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2130606569
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1642696215
Short name T186
Test name
Test status
Simulation time 97189746252 ps
CPU time 421.52 seconds
Started Jul 22 05:51:12 PM PDT 24
Finished Jul 22 05:58:14 PM PDT 24
Peak memory 271320 kb
Host smart-e66db5bb-6ffb-48b3-97eb-a4794aed8417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642696215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1642696215
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.787966051
Short name T675
Test name
Test status
Simulation time 632200315 ps
CPU time 5.12 seconds
Started Jul 22 05:50:59 PM PDT 24
Finished Jul 22 05:51:05 PM PDT 24
Peak memory 216336 kb
Host smart-db6d7a94-4ce2-4484-b34f-9501d28c23df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787966051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.787966051
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.24993422
Short name T901
Test name
Test status
Simulation time 7597312357 ps
CPU time 8.92 seconds
Started Jul 22 05:50:59 PM PDT 24
Finished Jul 22 05:51:09 PM PDT 24
Peak memory 216612 kb
Host smart-d3df7211-4736-4c67-80b4-51646a693699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24993422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.24993422
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2045633070
Short name T74
Test name
Test status
Simulation time 90344755 ps
CPU time 0.99 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:51:13 PM PDT 24
Peak memory 207172 kb
Host smart-465ecd96-f3f7-4561-8cfc-71c747f4941e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045633070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2045633070
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.1672028474
Short name T334
Test name
Test status
Simulation time 60942304 ps
CPU time 0.87 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:21 PM PDT 24
Peak memory 206120 kb
Host smart-68798009-23e8-4a63-8db5-436bb8c8fcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672028474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1672028474
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3142273071
Short name T399
Test name
Test status
Simulation time 266873559 ps
CPU time 2.94 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:51:15 PM PDT 24
Peak memory 232900 kb
Host smart-5c971fad-4fb8-4d12-af8a-a67eacefcb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142273071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3142273071
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3144984454
Short name T408
Test name
Test status
Simulation time 41957341 ps
CPU time 0.71 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:20 PM PDT 24
Peak memory 205616 kb
Host smart-a9afc1cc-7700-43c5-97ee-de26975a0d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144984454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3144984454
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2685914430
Short name T521
Test name
Test status
Simulation time 750343331 ps
CPU time 3.49 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:51:24 PM PDT 24
Peak memory 233040 kb
Host smart-38a4612f-7415-43d3-9e4f-b9a78853fb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685914430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2685914430
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.2065918475
Short name T327
Test name
Test status
Simulation time 73166315 ps
CPU time 0.8 seconds
Started Jul 22 05:51:10 PM PDT 24
Finished Jul 22 05:51:11 PM PDT 24
Peak memory 206732 kb
Host smart-39ce083b-67a9-4cbf-917d-1a75905053aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065918475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.2065918475
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2772912341
Short name T528
Test name
Test status
Simulation time 63137349073 ps
CPU time 84.05 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:52:44 PM PDT 24
Peak memory 250808 kb
Host smart-57b006ae-081e-4e65-a2a2-bbc9225400bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772912341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2772912341
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2423515960
Short name T272
Test name
Test status
Simulation time 161589144013 ps
CPU time 423.11 seconds
Started Jul 22 05:51:21 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 266676 kb
Host smart-04d12df6-40ec-46be-92b2-4eeff68f94bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423515960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2423515960
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.434190707
Short name T342
Test name
Test status
Simulation time 256498124 ps
CPU time 8.56 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:51:29 PM PDT 24
Peak memory 232804 kb
Host smart-df6be840-6b69-46f7-a455-c00e22d36659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434190707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.434190707
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.4032113365
Short name T641
Test name
Test status
Simulation time 1448492856 ps
CPU time 2.14 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:22 PM PDT 24
Peak memory 223200 kb
Host smart-3ac4a749-7580-47a2-bcc7-65baca161be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032113365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.4032113365
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1081918959
Short name T632
Test name
Test status
Simulation time 6274432942 ps
CPU time 21.57 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 241000 kb
Host smart-68b516d7-4887-47b5-bfaa-06686827d797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081918959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1081918959
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3685253516
Short name T491
Test name
Test status
Simulation time 544134287 ps
CPU time 4.41 seconds
Started Jul 22 05:51:09 PM PDT 24
Finished Jul 22 05:51:14 PM PDT 24
Peak memory 232912 kb
Host smart-3224aea3-3e44-4f71-8954-e8ee1c733458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685253516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3685253516
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1545523127
Short name T804
Test name
Test status
Simulation time 6383295765 ps
CPU time 10.07 seconds
Started Jul 22 05:51:09 PM PDT 24
Finished Jul 22 05:51:20 PM PDT 24
Peak memory 232848 kb
Host smart-1cf9cd9d-b5dc-422b-a2cd-a1d1c536ad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545523127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1545523127
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1267799762
Short name T400
Test name
Test status
Simulation time 340398066 ps
CPU time 4.45 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:24 PM PDT 24
Peak memory 223304 kb
Host smart-be1dadbf-001e-4720-bfeb-223a50d1b444
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1267799762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1267799762
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1645799369
Short name T899
Test name
Test status
Simulation time 37469492427 ps
CPU time 123.07 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:53:23 PM PDT 24
Peak memory 250928 kb
Host smart-9579e193-e3c7-48b1-b575-d48f76f83e2f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645799369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1645799369
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2512686238
Short name T704
Test name
Test status
Simulation time 80717631569 ps
CPU time 31.98 seconds
Started Jul 22 05:51:09 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 216708 kb
Host smart-4181e2e7-d441-4839-b24e-5fa5e92111c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512686238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2512686238
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1953464515
Short name T371
Test name
Test status
Simulation time 1559375441 ps
CPU time 5.11 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:51:16 PM PDT 24
Peak memory 216464 kb
Host smart-43118488-4816-4d66-b796-5c6e634852ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953464515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1953464515
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2400859444
Short name T1006
Test name
Test status
Simulation time 155707930 ps
CPU time 3.17 seconds
Started Jul 22 05:51:11 PM PDT 24
Finished Jul 22 05:51:15 PM PDT 24
Peak memory 216476 kb
Host smart-dbf99966-ffb8-4f7d-913b-bf8b9990886d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400859444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2400859444
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3005485961
Short name T353
Test name
Test status
Simulation time 49345436 ps
CPU time 0.81 seconds
Started Jul 22 05:51:09 PM PDT 24
Finished Jul 22 05:51:11 PM PDT 24
Peak memory 206040 kb
Host smart-fc41956b-a62f-4cf9-9976-8aab11ab600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005485961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3005485961
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.685688305
Short name T393
Test name
Test status
Simulation time 1035165766 ps
CPU time 5.68 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:51:26 PM PDT 24
Peak memory 232924 kb
Host smart-62f6c682-a378-4f28-ba53-eaa3b9c53df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685688305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.685688305
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2206829219
Short name T603
Test name
Test status
Simulation time 37805449 ps
CPU time 0.69 seconds
Started Jul 22 05:47:55 PM PDT 24
Finished Jul 22 05:47:56 PM PDT 24
Peak memory 205548 kb
Host smart-66e8ce2a-8372-440a-a054-d8ef8fa130ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206829219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
206829219
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2112688614
Short name T558
Test name
Test status
Simulation time 1303806211 ps
CPU time 3.71 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:47:54 PM PDT 24
Peak memory 224668 kb
Host smart-2c198bed-311a-461f-87b2-235d22784cc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112688614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2112688614
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3683481149
Short name T340
Test name
Test status
Simulation time 54497597 ps
CPU time 0.74 seconds
Started Jul 22 05:49:12 PM PDT 24
Finished Jul 22 05:49:13 PM PDT 24
Peak memory 207064 kb
Host smart-2b071140-218f-4f06-933a-bc6f6553fde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683481149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3683481149
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2480790524
Short name T624
Test name
Test status
Simulation time 932177124 ps
CPU time 5.82 seconds
Started Jul 22 05:47:51 PM PDT 24
Finished Jul 22 05:47:58 PM PDT 24
Peak memory 224648 kb
Host smart-6df36d09-51fa-42be-aadd-741a13ba9963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480790524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2480790524
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.41006629
Short name T139
Test name
Test status
Simulation time 56931521178 ps
CPU time 110.76 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:49:42 PM PDT 24
Peak memory 249388 kb
Host smart-2546a77b-b4ec-48b8-85a7-48e47d880375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41006629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.41006629
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.202454812
Short name T141
Test name
Test status
Simulation time 69810622953 ps
CPU time 83.51 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:49:22 PM PDT 24
Peak memory 250364 kb
Host smart-391ee7e8-d32a-4f2c-a0a7-e673da7eaa4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202454812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
202454812
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.633311666
Short name T359
Test name
Test status
Simulation time 3405451679 ps
CPU time 17.27 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:48:07 PM PDT 24
Peak memory 238800 kb
Host smart-fb84150f-c040-4aec-8388-5e61743ab6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633311666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.633311666
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3015602510
Short name T786
Test name
Test status
Simulation time 42438881006 ps
CPU time 76.92 seconds
Started Jul 22 05:47:48 PM PDT 24
Finished Jul 22 05:49:05 PM PDT 24
Peak memory 238940 kb
Host smart-d9ecede9-281b-4096-90fb-8ae8577df139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015602510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3015602510
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1018355192
Short name T1001
Test name
Test status
Simulation time 3124981537 ps
CPU time 13.73 seconds
Started Jul 22 05:47:53 PM PDT 24
Finished Jul 22 05:48:07 PM PDT 24
Peak memory 232968 kb
Host smart-036330de-d359-4967-bf7c-7e5f2e47babd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018355192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1018355192
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4156361024
Short name T332
Test name
Test status
Simulation time 5659401249 ps
CPU time 13.44 seconds
Started Jul 22 05:47:51 PM PDT 24
Finished Jul 22 05:48:05 PM PDT 24
Peak memory 232916 kb
Host smart-068a0eee-1288-4ab5-9f58-e543c0a534a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156361024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4156361024
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.4280229725
Short name T536
Test name
Test status
Simulation time 432593089 ps
CPU time 4.83 seconds
Started Jul 22 05:49:22 PM PDT 24
Finished Jul 22 05:49:28 PM PDT 24
Peak memory 239248 kb
Host smart-6eef3a96-8c0f-4d7f-8389-1225667c15a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280229725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.4280229725
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.2668424703
Short name T193
Test name
Test status
Simulation time 38279409016 ps
CPU time 21.39 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:48:08 PM PDT 24
Peak memory 232916 kb
Host smart-85006094-2576-4ec1-92db-f465be253399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668424703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.2668424703
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1002271036
Short name T467
Test name
Test status
Simulation time 2697391012 ps
CPU time 6.63 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:47:57 PM PDT 24
Peak memory 220376 kb
Host smart-d101aad6-efcb-4e8e-8812-fa97e97cf704
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1002271036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1002271036
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.3872504103
Short name T674
Test name
Test status
Simulation time 69852963618 ps
CPU time 340.58 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:53:39 PM PDT 24
Peak memory 256668 kb
Host smart-137718cf-5438-4e6e-ae94-a6339bcb1bf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872504103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.3872504103
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.873729930
Short name T827
Test name
Test status
Simulation time 872436284 ps
CPU time 3.28 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:47:54 PM PDT 24
Peak memory 217648 kb
Host smart-ab13abfa-aaf9-47f0-80b6-650b65a707c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873729930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.873729930
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.19965841
Short name T76
Test name
Test status
Simulation time 3981819120 ps
CPU time 6.91 seconds
Started Jul 22 05:47:51 PM PDT 24
Finished Jul 22 05:47:59 PM PDT 24
Peak memory 216400 kb
Host smart-9e78bf83-cb36-4092-8d5a-3b14ebda934c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19965841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.19965841
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3992362891
Short name T933
Test name
Test status
Simulation time 37667587 ps
CPU time 0.71 seconds
Started Jul 22 05:47:49 PM PDT 24
Finished Jul 22 05:47:51 PM PDT 24
Peak memory 205792 kb
Host smart-af54275d-05f0-471b-bca3-578dfa275e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992362891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3992362891
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.607646395
Short name T886
Test name
Test status
Simulation time 66827167 ps
CPU time 0.76 seconds
Started Jul 22 05:47:50 PM PDT 24
Finished Jul 22 05:47:52 PM PDT 24
Peak memory 206408 kb
Host smart-c5c15d03-88fd-4319-a7ef-7a9384ad96b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607646395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.607646395
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.4058963096
Short name T571
Test name
Test status
Simulation time 7379749813 ps
CPU time 15 seconds
Started Jul 22 05:47:47 PM PDT 24
Finished Jul 22 05:48:03 PM PDT 24
Peak memory 241100 kb
Host smart-a2ce9ede-3349-443f-a5dc-00e0eaa08b1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058963096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.4058963096
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.1976972034
Short name T792
Test name
Test status
Simulation time 30426494 ps
CPU time 0.72 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:20 PM PDT 24
Peak memory 205872 kb
Host smart-c06e21a1-0230-420e-8f77-00f941acbb0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976972034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
1976972034
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3406183350
Short name T586
Test name
Test status
Simulation time 616900381 ps
CPU time 4.36 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:51:25 PM PDT 24
Peak memory 232896 kb
Host smart-1e0ee3e9-a1dc-403f-bf12-c85c515a1a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406183350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3406183350
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3050029924
Short name T621
Test name
Test status
Simulation time 18496966 ps
CPU time 0.78 seconds
Started Jul 22 05:51:25 PM PDT 24
Finished Jul 22 05:51:26 PM PDT 24
Peak memory 205720 kb
Host smart-53e8d5d4-1519-4f6a-9edd-bcf64a7dd957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050029924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3050029924
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3443185357
Short name T488
Test name
Test status
Simulation time 11994527488 ps
CPU time 42.36 seconds
Started Jul 22 05:52:35 PM PDT 24
Finished Jul 22 05:53:18 PM PDT 24
Peak memory 238296 kb
Host smart-4f393f60-1f58-4dc4-949b-ecfb4d2cb652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443185357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3443185357
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2510504815
Short name T993
Test name
Test status
Simulation time 9126311260 ps
CPU time 112.42 seconds
Started Jul 22 05:51:18 PM PDT 24
Finished Jul 22 05:53:10 PM PDT 24
Peak memory 252500 kb
Host smart-7d5db1ad-37a0-440f-8076-c167ce4a180c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510504815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2510504815
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.758115982
Short name T135
Test name
Test status
Simulation time 78716553849 ps
CPU time 223.96 seconds
Started Jul 22 05:51:24 PM PDT 24
Finished Jul 22 05:55:09 PM PDT 24
Peak memory 265608 kb
Host smart-f0c0a42b-1094-4e5c-a116-4fd2aa63da4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758115982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle
.758115982
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.650459303
Short name T846
Test name
Test status
Simulation time 5703982677 ps
CPU time 9.1 seconds
Started Jul 22 05:51:23 PM PDT 24
Finished Jul 22 05:51:32 PM PDT 24
Peak memory 224756 kb
Host smart-b0a733e7-dfdc-4bfc-9c7a-c44d4b41e700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650459303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.650459303
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.1173568965
Short name T531
Test name
Test status
Simulation time 17795274 ps
CPU time 0.73 seconds
Started Jul 22 05:51:23 PM PDT 24
Finished Jul 22 05:51:24 PM PDT 24
Peak memory 215916 kb
Host smart-89c6493f-d6fe-4c5a-840d-99edab91c573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173568965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmd
s.1173568965
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2118932670
Short name T929
Test name
Test status
Simulation time 2710733789 ps
CPU time 24.67 seconds
Started Jul 22 05:51:24 PM PDT 24
Finished Jul 22 05:51:49 PM PDT 24
Peak memory 232844 kb
Host smart-3cbe0e99-7833-4381-a281-e50d6435135d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118932670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2118932670
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3145110323
Short name T430
Test name
Test status
Simulation time 131178154 ps
CPU time 2.65 seconds
Started Jul 22 05:51:24 PM PDT 24
Finished Jul 22 05:51:27 PM PDT 24
Peak memory 224664 kb
Host smart-1b30833e-2fb0-4d91-9fc0-4548528d9863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145110323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3145110323
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.503207837
Short name T355
Test name
Test status
Simulation time 3486623537 ps
CPU time 10.15 seconds
Started Jul 22 05:51:18 PM PDT 24
Finished Jul 22 05:51:28 PM PDT 24
Peak memory 232928 kb
Host smart-9dbeb062-df51-4b84-a1e6-b4ca6dceb907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503207837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.503207837
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3948080088
Short name T236
Test name
Test status
Simulation time 2631917883 ps
CPU time 8.72 seconds
Started Jul 22 05:51:24 PM PDT 24
Finished Jul 22 05:51:33 PM PDT 24
Peak memory 232924 kb
Host smart-18022369-e837-4a53-9e7c-90c507c362ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948080088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3948080088
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2929758922
Short name T142
Test name
Test status
Simulation time 77901023 ps
CPU time 4.27 seconds
Started Jul 22 05:51:20 PM PDT 24
Finished Jul 22 05:51:25 PM PDT 24
Peak memory 222760 kb
Host smart-79f746b0-7830-4881-8423-d90c6b254a56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2929758922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2929758922
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2489549028
Short name T572
Test name
Test status
Simulation time 4405420984 ps
CPU time 65.99 seconds
Started Jul 22 05:52:35 PM PDT 24
Finished Jul 22 05:53:42 PM PDT 24
Peak memory 251340 kb
Host smart-e7ebe202-932d-4ae3-9f47-d59ecea636f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489549028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2489549028
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2114041531
Short name T319
Test name
Test status
Simulation time 7737875601 ps
CPU time 9.93 seconds
Started Jul 22 05:51:21 PM PDT 24
Finished Jul 22 05:51:31 PM PDT 24
Peak memory 216472 kb
Host smart-2741f08b-3355-413b-a9bb-a2e0792e8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114041531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2114041531
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1687668038
Short name T402
Test name
Test status
Simulation time 576409693 ps
CPU time 4.03 seconds
Started Jul 22 05:51:18 PM PDT 24
Finished Jul 22 05:51:22 PM PDT 24
Peak memory 216460 kb
Host smart-6c12172a-4d50-4662-9631-00b9edbb9adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687668038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1687668038
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.957754945
Short name T427
Test name
Test status
Simulation time 21167040 ps
CPU time 0.93 seconds
Started Jul 22 05:51:25 PM PDT 24
Finished Jul 22 05:51:26 PM PDT 24
Peak memory 207348 kb
Host smart-763ef38e-cf4f-4894-bf42-f51621f223d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957754945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.957754945
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.927292096
Short name T518
Test name
Test status
Simulation time 197907576 ps
CPU time 0.84 seconds
Started Jul 22 05:51:19 PM PDT 24
Finished Jul 22 05:51:20 PM PDT 24
Peak memory 206144 kb
Host smart-6ffe2e2d-f44b-483a-ab97-5195da1c9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927292096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.927292096
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3111650288
Short name T802
Test name
Test status
Simulation time 813354548 ps
CPU time 4.91 seconds
Started Jul 22 05:51:25 PM PDT 24
Finished Jul 22 05:51:30 PM PDT 24
Peak memory 236260 kb
Host smart-4a1454fd-cc93-4537-9e47-105955c53f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111650288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3111650288
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1705360349
Short name T635
Test name
Test status
Simulation time 17964523 ps
CPU time 0.76 seconds
Started Jul 22 05:51:41 PM PDT 24
Finished Jul 22 05:51:42 PM PDT 24
Peak memory 205624 kb
Host smart-c8e9422a-9a27-4c3f-a70c-b9296e13cb64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705360349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1705360349
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4274317616
Short name T1002
Test name
Test status
Simulation time 84771756 ps
CPU time 2.35 seconds
Started Jul 22 05:51:31 PM PDT 24
Finished Jul 22 05:51:33 PM PDT 24
Peak memory 224640 kb
Host smart-475dab19-120e-4a38-a092-c2d40a520f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274317616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4274317616
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3792956293
Short name T405
Test name
Test status
Simulation time 61498704 ps
CPU time 0.77 seconds
Started Jul 22 05:51:24 PM PDT 24
Finished Jul 22 05:51:25 PM PDT 24
Peak memory 205688 kb
Host smart-82290a8f-a9a3-41ce-b98e-30df5dd72a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792956293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3792956293
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.259101117
Short name T84
Test name
Test status
Simulation time 2287581167 ps
CPU time 45.04 seconds
Started Jul 22 05:51:31 PM PDT 24
Finished Jul 22 05:52:16 PM PDT 24
Peak memory 250900 kb
Host smart-d2640ee6-4410-4fa1-ade0-519db1bea545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259101117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.259101117
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1927872394
Short name T52
Test name
Test status
Simulation time 69693839595 ps
CPU time 192.96 seconds
Started Jul 22 05:51:27 PM PDT 24
Finished Jul 22 05:54:40 PM PDT 24
Peak memory 253864 kb
Host smart-f480dade-bc3e-4649-b824-73c6ab9d854a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927872394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1927872394
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2708768133
Short name T952
Test name
Test status
Simulation time 15828961657 ps
CPU time 38.93 seconds
Started Jul 22 05:51:38 PM PDT 24
Finished Jul 22 05:52:17 PM PDT 24
Peak memory 236276 kb
Host smart-c4c43ca8-b0b3-4466-b305-8bc8ec3bae6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708768133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2708768133
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.139196394
Short name T591
Test name
Test status
Simulation time 4321887927 ps
CPU time 9.52 seconds
Started Jul 22 05:51:31 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 232892 kb
Host smart-1ae88fef-a324-44ec-a13c-14340d6aec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139196394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.139196394
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.1375565579
Short name T731
Test name
Test status
Simulation time 126749341 ps
CPU time 0.73 seconds
Started Jul 22 05:51:28 PM PDT 24
Finished Jul 22 05:51:29 PM PDT 24
Peak memory 215836 kb
Host smart-d04122d9-51c3-45c0-9da7-db03b11ab8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375565579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.1375565579
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1785373189
Short name T867
Test name
Test status
Simulation time 178196634 ps
CPU time 4.73 seconds
Started Jul 22 05:51:30 PM PDT 24
Finished Jul 22 05:51:35 PM PDT 24
Peak memory 232792 kb
Host smart-77922b9c-e6fa-4255-8be8-d3959864bbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785373189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1785373189
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.363691402
Short name T45
Test name
Test status
Simulation time 1138044901 ps
CPU time 15.53 seconds
Started Jul 22 05:51:28 PM PDT 24
Finished Jul 22 05:51:44 PM PDT 24
Peak memory 224728 kb
Host smart-291c7884-a6f7-4b1f-85bd-76e8e89014f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363691402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.363691402
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2448707785
Short name T778
Test name
Test status
Simulation time 2026843534 ps
CPU time 8.26 seconds
Started Jul 22 05:51:29 PM PDT 24
Finished Jul 22 05:51:37 PM PDT 24
Peak memory 248696 kb
Host smart-6c5cc913-2c20-40d3-a417-a15bb02018a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448707785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2448707785
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.1112009155
Short name T81
Test name
Test status
Simulation time 855403734 ps
CPU time 4.1 seconds
Started Jul 22 05:52:31 PM PDT 24
Finished Jul 22 05:52:36 PM PDT 24
Peak memory 224668 kb
Host smart-07b8bd09-a924-4f21-9891-b93efbb1272e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112009155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.1112009155
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.728453806
Short name T881
Test name
Test status
Simulation time 5567456659 ps
CPU time 17.33 seconds
Started Jul 22 05:51:29 PM PDT 24
Finished Jul 22 05:51:46 PM PDT 24
Peak memory 223304 kb
Host smart-ca1824bf-39f6-4e88-be75-2985e75f6bd3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=728453806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.728453806
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1508327476
Short name T155
Test name
Test status
Simulation time 2216597271 ps
CPU time 45.81 seconds
Started Jul 22 05:51:40 PM PDT 24
Finished Jul 22 05:52:27 PM PDT 24
Peak memory 249368 kb
Host smart-1afe0276-ed84-43e2-bde3-e857132911bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508327476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1508327476
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1431486794
Short name T950
Test name
Test status
Simulation time 6474597183 ps
CPU time 44.95 seconds
Started Jul 22 05:51:40 PM PDT 24
Finished Jul 22 05:52:25 PM PDT 24
Peak memory 216552 kb
Host smart-e386f1a6-f71f-4013-97fb-83fbc2234423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431486794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1431486794
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2285769703
Short name T80
Test name
Test status
Simulation time 9527898442 ps
CPU time 15.08 seconds
Started Jul 22 05:51:29 PM PDT 24
Finished Jul 22 05:51:44 PM PDT 24
Peak memory 216456 kb
Host smart-470efc51-fa6f-419a-b38d-01b3c0306b16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285769703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2285769703
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.4135214098
Short name T333
Test name
Test status
Simulation time 25841211 ps
CPU time 1.16 seconds
Started Jul 22 05:51:39 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 216408 kb
Host smart-f99ee5f0-6f49-4eac-8cb0-a9cf060797d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135214098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.4135214098
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.233742416
Short name T96
Test name
Test status
Simulation time 41420296 ps
CPU time 0.77 seconds
Started Jul 22 05:52:49 PM PDT 24
Finished Jul 22 05:52:50 PM PDT 24
Peak memory 206100 kb
Host smart-5c7c2eb9-5015-43ce-9206-0b7d30c534e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233742416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.233742416
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1390728611
Short name T46
Test name
Test status
Simulation time 6313776664 ps
CPU time 19.61 seconds
Started Jul 22 05:51:28 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 232856 kb
Host smart-498d9367-9dc2-41bc-aded-afe52b16b9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390728611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1390728611
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2368616508
Short name T368
Test name
Test status
Simulation time 31029556 ps
CPU time 0.69 seconds
Started Jul 22 05:51:40 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 205664 kb
Host smart-c588bf5b-f6b9-4129-a399-4641f3d09553
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368616508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2368616508
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.4169025121
Short name T566
Test name
Test status
Simulation time 10244212804 ps
CPU time 20.69 seconds
Started Jul 22 05:51:50 PM PDT 24
Finished Jul 22 05:52:11 PM PDT 24
Peak memory 224680 kb
Host smart-c24ad676-3feb-4e0f-8905-11797fb06975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169025121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.4169025121
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2458832260
Short name T374
Test name
Test status
Simulation time 65493624 ps
CPU time 0.8 seconds
Started Jul 22 05:51:40 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 206696 kb
Host smart-228395b7-6220-4e1a-aab3-9cdf444328a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458832260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2458832260
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.4089809960
Short name T292
Test name
Test status
Simulation time 12182568228 ps
CPU time 37.7 seconds
Started Jul 22 05:53:44 PM PDT 24
Finished Jul 22 05:54:22 PM PDT 24
Peak memory 235940 kb
Host smart-75adfffc-b1d0-4262-9141-f9ccc4774d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089809960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.4089809960
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.536319293
Short name T315
Test name
Test status
Simulation time 21775955347 ps
CPU time 155.69 seconds
Started Jul 22 05:51:39 PM PDT 24
Finished Jul 22 05:54:16 PM PDT 24
Peak memory 249964 kb
Host smart-a0e1f2d4-fc19-4a38-9c24-59f5eded07ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536319293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.536319293
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2565324765
Short name T564
Test name
Test status
Simulation time 5699538988 ps
CPU time 33.82 seconds
Started Jul 22 05:51:36 PM PDT 24
Finished Jul 22 05:52:11 PM PDT 24
Peak memory 217772 kb
Host smart-1d918afd-da97-4584-8f85-385a837b1d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565324765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2565324765
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.4198635576
Short name T753
Test name
Test status
Simulation time 850996753 ps
CPU time 6.11 seconds
Started Jul 22 05:51:41 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 232936 kb
Host smart-9b2ea3ea-c813-4c47-9ff3-a8a6b08cd177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198635576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.4198635576
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.760802188
Short name T702
Test name
Test status
Simulation time 22116898435 ps
CPU time 47.97 seconds
Started Jul 22 05:51:52 PM PDT 24
Finished Jul 22 05:52:40 PM PDT 24
Peak memory 253804 kb
Host smart-a3848315-f5a6-4c46-b7bf-efa8fafc7ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760802188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.760802188
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2783527893
Short name T1003
Test name
Test status
Simulation time 381269726 ps
CPU time 5.06 seconds
Started Jul 22 05:51:38 PM PDT 24
Finished Jul 22 05:51:44 PM PDT 24
Peak memory 232832 kb
Host smart-8ab01e5f-43fd-4935-a569-1816b2db4fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783527893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2783527893
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.536724311
Short name T664
Test name
Test status
Simulation time 4710597644 ps
CPU time 19.57 seconds
Started Jul 22 05:51:38 PM PDT 24
Finished Jul 22 05:51:58 PM PDT 24
Peak memory 251356 kb
Host smart-a545fa49-0d50-4e7c-8e95-8067cbe233ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536724311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.536724311
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2685266537
Short name T849
Test name
Test status
Simulation time 7844545895 ps
CPU time 18.56 seconds
Started Jul 22 05:51:39 PM PDT 24
Finished Jul 22 05:51:58 PM PDT 24
Peak memory 240776 kb
Host smart-7a517982-a8e2-49e2-bdeb-f0f167d471e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685266537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2685266537
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.480829638
Short name T684
Test name
Test status
Simulation time 123173195 ps
CPU time 2.85 seconds
Started Jul 22 05:51:41 PM PDT 24
Finished Jul 22 05:51:44 PM PDT 24
Peak memory 224628 kb
Host smart-3977b921-adad-42e1-8fcf-946e79d708af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480829638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.480829638
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2573324857
Short name T639
Test name
Test status
Simulation time 156490716 ps
CPU time 4.19 seconds
Started Jul 22 05:51:52 PM PDT 24
Finished Jul 22 05:51:56 PM PDT 24
Peak memory 223276 kb
Host smart-fe7b56be-cfd3-47ad-a6a6-6bd508c792d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2573324857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2573324857
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.473049710
Short name T447
Test name
Test status
Simulation time 53244969228 ps
CPU time 132.21 seconds
Started Jul 22 05:51:40 PM PDT 24
Finished Jul 22 05:53:53 PM PDT 24
Peak memory 257104 kb
Host smart-e594ab0c-3d81-44d2-874c-1a7cedc9747a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473049710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.473049710
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.280743225
Short name T995
Test name
Test status
Simulation time 28206605466 ps
CPU time 27.21 seconds
Started Jul 22 05:51:38 PM PDT 24
Finished Jul 22 05:52:06 PM PDT 24
Peak memory 216460 kb
Host smart-efa9a8ad-e842-4ced-a8db-16fe9c866045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280743225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.280743225
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.838461545
Short name T775
Test name
Test status
Simulation time 2226754644 ps
CPU time 4.26 seconds
Started Jul 22 05:51:37 PM PDT 24
Finished Jul 22 05:51:41 PM PDT 24
Peak memory 216488 kb
Host smart-568feb7b-a6c4-4eb8-956c-91f41b1831f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838461545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.838461545
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.796795546
Short name T956
Test name
Test status
Simulation time 335954442 ps
CPU time 1.64 seconds
Started Jul 22 05:51:38 PM PDT 24
Finished Jul 22 05:51:40 PM PDT 24
Peak memory 216416 kb
Host smart-14fe5929-5e29-4f5c-a6fd-ac00fc17c7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796795546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.796795546
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2008317827
Short name T734
Test name
Test status
Simulation time 86455901 ps
CPU time 0.84 seconds
Started Jul 22 05:51:44 PM PDT 24
Finished Jul 22 05:51:45 PM PDT 24
Peak memory 207084 kb
Host smart-bdc2428c-f445-4c12-be03-782a3b6cb59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008317827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2008317827
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2896473832
Short name T789
Test name
Test status
Simulation time 596345163 ps
CPU time 6.97 seconds
Started Jul 22 05:51:40 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 239672 kb
Host smart-2281dc7e-6a8e-4dcd-baca-77c07e5a4742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896473832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2896473832
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.234061753
Short name T658
Test name
Test status
Simulation time 206192589 ps
CPU time 0.76 seconds
Started Jul 22 05:51:57 PM PDT 24
Finished Jul 22 05:51:58 PM PDT 24
Peak memory 205540 kb
Host smart-b96d6b8b-fec7-4266-992e-bd0efa2fa639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234061753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.234061753
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1808752026
Short name T555
Test name
Test status
Simulation time 2057204978 ps
CPU time 3.14 seconds
Started Jul 22 05:51:55 PM PDT 24
Finished Jul 22 05:51:59 PM PDT 24
Peak memory 224552 kb
Host smart-cfdb51e1-f544-4bf4-b897-dcba0276344f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808752026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1808752026
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1899929414
Short name T523
Test name
Test status
Simulation time 106053005 ps
CPU time 0.81 seconds
Started Jul 22 05:51:39 PM PDT 24
Finished Jul 22 05:51:40 PM PDT 24
Peak memory 206752 kb
Host smart-0e04c4e1-5f37-4b67-b1eb-c387113389be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899929414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1899929414
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2914940591
Short name T931
Test name
Test status
Simulation time 43871116853 ps
CPU time 95.58 seconds
Started Jul 22 05:51:58 PM PDT 24
Finished Jul 22 05:53:34 PM PDT 24
Peak memory 249292 kb
Host smart-e8ee71dc-4d62-460f-bdd9-38c89613f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914940591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2914940591
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3157523598
Short name T278
Test name
Test status
Simulation time 19690513238 ps
CPU time 121.07 seconds
Started Jul 22 05:51:55 PM PDT 24
Finished Jul 22 05:53:57 PM PDT 24
Peak memory 264544 kb
Host smart-f04278c4-b800-4458-96ff-942f456a7027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157523598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3157523598
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.114042734
Short name T260
Test name
Test status
Simulation time 62266531421 ps
CPU time 626.95 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 273620 kb
Host smart-fa63c1fe-f2ae-4a28-8556-28a042725d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114042734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.114042734
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3306278606
Short name T478
Test name
Test status
Simulation time 1955763003 ps
CPU time 8.67 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 05:52:05 PM PDT 24
Peak memory 224568 kb
Host smart-12b6004e-922b-4a69-a1a7-ba4268431f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306278606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3306278606
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.2889785446
Short name T828
Test name
Test status
Simulation time 17901924625 ps
CPU time 121.76 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 05:53:59 PM PDT 24
Peak memory 255460 kb
Host smart-1623e5b0-f94c-41ff-82ea-9833479cc168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889785446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.2889785446
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1900751097
Short name T409
Test name
Test status
Simulation time 1587799762 ps
CPU time 6.79 seconds
Started Jul 22 05:51:47 PM PDT 24
Finished Jul 22 05:51:54 PM PDT 24
Peak memory 224704 kb
Host smart-ab76b878-89f7-47bb-ac2f-5791cd043848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900751097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1900751097
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.4150827312
Short name T977
Test name
Test status
Simulation time 10257454450 ps
CPU time 31.17 seconds
Started Jul 22 05:51:49 PM PDT 24
Finished Jul 22 05:52:21 PM PDT 24
Peak memory 232896 kb
Host smart-7c7335d8-6c94-472a-a675-07ca5ace665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150827312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.4150827312
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.4214149408
Short name T104
Test name
Test status
Simulation time 41795735011 ps
CPU time 17.63 seconds
Started Jul 22 05:51:47 PM PDT 24
Finished Jul 22 05:52:05 PM PDT 24
Peak memory 232940 kb
Host smart-ccb4730a-df79-40c4-97bc-b96cf72b0edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214149408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.4214149408
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2363429502
Short name T181
Test name
Test status
Simulation time 13887911973 ps
CPU time 13.36 seconds
Started Jul 22 05:51:47 PM PDT 24
Finished Jul 22 05:52:00 PM PDT 24
Peak memory 238744 kb
Host smart-4889b959-d326-4e9f-96d4-e784e34396cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363429502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2363429502
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.81631431
Short name T9
Test name
Test status
Simulation time 965571961 ps
CPU time 5.08 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 05:52:01 PM PDT 24
Peak memory 219684 kb
Host smart-e642081f-13c8-47c4-b5d6-127d6737d47a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=81631431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direc
t.81631431
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1801229704
Short name T991
Test name
Test status
Simulation time 30377569633 ps
CPU time 153.47 seconds
Started Jul 22 05:51:59 PM PDT 24
Finished Jul 22 05:54:33 PM PDT 24
Peak memory 262328 kb
Host smart-e70622c5-fd47-40d5-b24a-aa5b76d8c03a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801229704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1801229704
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.4242011380
Short name T318
Test name
Test status
Simulation time 19497676287 ps
CPU time 54.09 seconds
Started Jul 22 05:51:46 PM PDT 24
Finished Jul 22 05:52:41 PM PDT 24
Peak memory 216500 kb
Host smart-74e7fba3-3617-45d6-868a-9951c5aa0ba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242011380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.4242011380
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.3259606089
Short name T989
Test name
Test status
Simulation time 508628681 ps
CPU time 2.69 seconds
Started Jul 22 05:51:45 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 216184 kb
Host smart-2b8598a7-61fe-49e7-8178-8e212fa3688b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259606089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.3259606089
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.144208045
Short name T414
Test name
Test status
Simulation time 93612877 ps
CPU time 1.88 seconds
Started Jul 22 05:51:47 PM PDT 24
Finished Jul 22 05:51:49 PM PDT 24
Peak memory 216404 kb
Host smart-f17ff6db-7fd2-4cd2-9a3a-c3a0f305944d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144208045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.144208045
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2470009063
Short name T322
Test name
Test status
Simulation time 13306499 ps
CPU time 0.7 seconds
Started Jul 22 05:51:47 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 205756 kb
Host smart-6045f4f3-de7a-47f0-b95c-49b7b151e62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470009063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2470009063
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.472189941
Short name T406
Test name
Test status
Simulation time 506118691 ps
CPU time 6.71 seconds
Started Jul 22 05:51:55 PM PDT 24
Finished Jul 22 05:52:03 PM PDT 24
Peak memory 224628 kb
Host smart-84295469-d7d4-4be3-9040-6fe05783120e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472189941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.472189941
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.513119290
Short name T492
Test name
Test status
Simulation time 22867042 ps
CPU time 0.76 seconds
Started Jul 22 05:52:06 PM PDT 24
Finished Jul 22 05:52:07 PM PDT 24
Peak memory 205576 kb
Host smart-a7ed7da9-4403-423b-94ac-4974eb62bf2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513119290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.513119290
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4004651297
Short name T510
Test name
Test status
Simulation time 922175616 ps
CPU time 3.99 seconds
Started Jul 22 05:52:08 PM PDT 24
Finished Jul 22 05:52:12 PM PDT 24
Peak memory 224652 kb
Host smart-10569b0f-aa8c-4c9c-a4d0-12bf1dd11d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004651297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4004651297
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.912872611
Short name T481
Test name
Test status
Simulation time 26637716 ps
CPU time 0.77 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 05:51:57 PM PDT 24
Peak memory 206796 kb
Host smart-4eb94ebf-26c1-4e7f-92ba-f0c6a9c5609a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912872611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.912872611
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1649616819
Short name T821
Test name
Test status
Simulation time 28847424393 ps
CPU time 112.63 seconds
Started Jul 22 05:53:16 PM PDT 24
Finished Jul 22 05:55:09 PM PDT 24
Peak memory 253904 kb
Host smart-e894b40e-470b-4550-9d36-b590d0b4ac03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649616819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1649616819
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1181088488
Short name T53
Test name
Test status
Simulation time 51791536633 ps
CPU time 520 seconds
Started Jul 22 05:52:07 PM PDT 24
Finished Jul 22 06:00:47 PM PDT 24
Peak memory 265776 kb
Host smart-d2b4f2b1-3a8f-494c-abf8-c3d7eccece7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181088488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1181088488
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4068414384
Short name T982
Test name
Test status
Simulation time 3696549492 ps
CPU time 15.57 seconds
Started Jul 22 05:52:08 PM PDT 24
Finished Jul 22 05:52:24 PM PDT 24
Peak memory 241140 kb
Host smart-f431851b-5949-40c0-b934-2852c83cf47c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068414384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4068414384
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.2737255455
Short name T102
Test name
Test status
Simulation time 16182782332 ps
CPU time 113.48 seconds
Started Jul 22 05:52:08 PM PDT 24
Finished Jul 22 05:54:02 PM PDT 24
Peak memory 249364 kb
Host smart-612bef8b-1a23-4d76-aaab-9ee5c4da174c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737255455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.2737255455
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2273951957
Short name T666
Test name
Test status
Simulation time 28535433 ps
CPU time 2.27 seconds
Started Jul 22 05:52:08 PM PDT 24
Finished Jul 22 05:52:11 PM PDT 24
Peak memory 232524 kb
Host smart-3c8b57f2-5802-4ef3-b4b9-ff849db12bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273951957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2273951957
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.189034113
Short name T229
Test name
Test status
Simulation time 4645317660 ps
CPU time 9.95 seconds
Started Jul 22 05:52:09 PM PDT 24
Finished Jul 22 05:52:20 PM PDT 24
Peak memory 232912 kb
Host smart-f01fd5ff-1194-46b7-8951-d18b6cf9f3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189034113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.189034113
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3698485747
Short name T13
Test name
Test status
Simulation time 5301926138 ps
CPU time 19.69 seconds
Started Jul 22 05:52:07 PM PDT 24
Finished Jul 22 05:52:27 PM PDT 24
Peak memory 232884 kb
Host smart-021725ec-1ed3-44f3-ae9c-89357f5fbfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698485747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3698485747
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1571182092
Short name T424
Test name
Test status
Simulation time 7499403599 ps
CPU time 10.13 seconds
Started Jul 22 05:51:56 PM PDT 24
Finished Jul 22 05:52:06 PM PDT 24
Peak memory 232956 kb
Host smart-1cbad83a-ae38-43b7-9e16-baf82c5a15c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571182092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1571182092
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.4067239378
Short name T839
Test name
Test status
Simulation time 1871247930 ps
CPU time 12.15 seconds
Started Jul 22 05:52:11 PM PDT 24
Finished Jul 22 05:52:23 PM PDT 24
Peak memory 220664 kb
Host smart-e9872c0a-05b6-4902-bed3-5b3e212c617c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4067239378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.4067239378
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1733660419
Short name T954
Test name
Test status
Simulation time 159402185 ps
CPU time 0.95 seconds
Started Jul 22 05:52:07 PM PDT 24
Finished Jul 22 05:52:09 PM PDT 24
Peak memory 206908 kb
Host smart-a21e652e-6743-468a-8199-950c7f6e5a17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733660419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1733660419
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2928933000
Short name T722
Test name
Test status
Simulation time 541896919 ps
CPU time 2.15 seconds
Started Jul 22 05:51:58 PM PDT 24
Finished Jul 22 05:52:00 PM PDT 24
Peak memory 216340 kb
Host smart-e72a702b-db58-4abf-a344-b9be7a323d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928933000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2928933000
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2535547939
Short name T944
Test name
Test status
Simulation time 126009410 ps
CPU time 1.64 seconds
Started Jul 22 05:53:08 PM PDT 24
Finished Jul 22 05:53:10 PM PDT 24
Peak memory 216376 kb
Host smart-a740d289-92c4-4f73-aefe-ff2d40a5a753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535547939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2535547939
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_upload.2730261125
Short name T693
Test name
Test status
Simulation time 161312346 ps
CPU time 2.5 seconds
Started Jul 22 05:52:07 PM PDT 24
Finished Jul 22 05:52:10 PM PDT 24
Peak memory 232596 kb
Host smart-4ee57653-5347-45b9-bc53-e2fca7de6350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730261125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.2730261125
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.2096830943
Short name T417
Test name
Test status
Simulation time 22506797 ps
CPU time 0.72 seconds
Started Jul 22 05:52:20 PM PDT 24
Finished Jul 22 05:52:21 PM PDT 24
Peak memory 205596 kb
Host smart-6c2a399c-1370-495f-a3bf-2e1814553c39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096830943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
2096830943
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.624531699
Short name T38
Test name
Test status
Simulation time 131185108 ps
CPU time 2.84 seconds
Started Jul 22 05:52:17 PM PDT 24
Finished Jul 22 05:52:20 PM PDT 24
Peak memory 232856 kb
Host smart-29de0a70-8e35-490f-af02-923469ada294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624531699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.624531699
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1664356119
Short name T1004
Test name
Test status
Simulation time 62464152 ps
CPU time 0.76 seconds
Started Jul 22 05:52:09 PM PDT 24
Finished Jul 22 05:52:11 PM PDT 24
Peak memory 207060 kb
Host smart-13a01b5d-cf30-44ea-ba6a-c3559b31ff91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664356119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1664356119
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2110542422
Short name T234
Test name
Test status
Simulation time 36443460164 ps
CPU time 134.69 seconds
Started Jul 22 05:52:15 PM PDT 24
Finished Jul 22 05:54:30 PM PDT 24
Peak memory 241180 kb
Host smart-ef15111f-46e2-4719-8e0b-c4eea0f2361c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110542422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2110542422
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.4187121489
Short name T623
Test name
Test status
Simulation time 2661179057 ps
CPU time 32.31 seconds
Started Jul 22 05:52:29 PM PDT 24
Finished Jul 22 05:53:02 PM PDT 24
Peak memory 217692 kb
Host smart-bf9df81d-9fe2-40eb-8f46-354c30419777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187121489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.4187121489
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3657004340
Short name T852
Test name
Test status
Simulation time 5486590540 ps
CPU time 148.37 seconds
Started Jul 22 05:52:20 PM PDT 24
Finished Jul 22 05:54:49 PM PDT 24
Peak memory 259544 kb
Host smart-218b6042-a6be-4644-86f8-841bb3b42484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657004340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3657004340
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.172545822
Short name T387
Test name
Test status
Simulation time 1336107220 ps
CPU time 4.7 seconds
Started Jul 22 05:52:19 PM PDT 24
Finished Jul 22 05:52:25 PM PDT 24
Peak memory 232860 kb
Host smart-e3490ecf-0e1a-4d3e-8933-e38f2ade1e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172545822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.172545822
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2244834592
Short name T485
Test name
Test status
Simulation time 41948108427 ps
CPU time 149.05 seconds
Started Jul 22 05:52:16 PM PDT 24
Finished Jul 22 05:54:45 PM PDT 24
Peak memory 257528 kb
Host smart-a61c70ff-8763-461e-adf9-6da090fc7572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244834592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2244834592
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.2276899701
Short name T878
Test name
Test status
Simulation time 1682986715 ps
CPU time 14.96 seconds
Started Jul 22 05:52:17 PM PDT 24
Finished Jul 22 05:52:32 PM PDT 24
Peak memory 224660 kb
Host smart-e0071e63-6135-4e9f-83b4-3a23efd3d355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276899701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2276899701
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2169432616
Short name T742
Test name
Test status
Simulation time 6790628460 ps
CPU time 23.13 seconds
Started Jul 22 05:52:20 PM PDT 24
Finished Jul 22 05:52:44 PM PDT 24
Peak memory 233992 kb
Host smart-27315754-76fc-4e85-9f1a-58af81dc6398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169432616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2169432616
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1566179184
Short name T855
Test name
Test status
Simulation time 5108764546 ps
CPU time 9.15 seconds
Started Jul 22 05:52:11 PM PDT 24
Finished Jul 22 05:52:20 PM PDT 24
Peak memory 224728 kb
Host smart-849bb774-9619-4793-adcd-d24fc8658b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566179184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1566179184
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2451173730
Short name T252
Test name
Test status
Simulation time 17604912605 ps
CPU time 28.82 seconds
Started Jul 22 05:52:09 PM PDT 24
Finished Jul 22 05:52:38 PM PDT 24
Peak memory 232920 kb
Host smart-e0421045-0a81-470b-9ab0-7e96aa2c92a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451173730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2451173730
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1114141137
Short name T553
Test name
Test status
Simulation time 7190370478 ps
CPU time 12.5 seconds
Started Jul 22 05:52:20 PM PDT 24
Finished Jul 22 05:52:33 PM PDT 24
Peak memory 219676 kb
Host smart-a2200e01-fd63-4fc1-ae99-aedebcd384de
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1114141137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1114141137
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3710557453
Short name T19
Test name
Test status
Simulation time 37259215427 ps
CPU time 323.64 seconds
Started Jul 22 05:52:19 PM PDT 24
Finished Jul 22 05:57:43 PM PDT 24
Peak memory 256320 kb
Host smart-f5d27838-00b4-4bf1-a82a-3536fa7b1424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710557453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3710557453
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3486776815
Short name T398
Test name
Test status
Simulation time 588280464 ps
CPU time 6.37 seconds
Started Jul 22 05:52:07 PM PDT 24
Finished Jul 22 05:52:14 PM PDT 24
Peak memory 216520 kb
Host smart-8e82a826-37b0-42c2-b3f0-ef763d0fcdae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486776815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3486776815
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2194682942
Short name T1005
Test name
Test status
Simulation time 4971122511 ps
CPU time 6.54 seconds
Started Jul 22 05:52:06 PM PDT 24
Finished Jul 22 05:52:13 PM PDT 24
Peak memory 216480 kb
Host smart-49e84ffe-2b3f-4ade-895d-278e84a8280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194682942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2194682942
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.110614267
Short name T345
Test name
Test status
Simulation time 32395537 ps
CPU time 0.69 seconds
Started Jul 22 05:52:12 PM PDT 24
Finished Jul 22 05:52:13 PM PDT 24
Peak memory 205748 kb
Host smart-dcaac65a-9676-4ebf-94e7-421c8cf571f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110614267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.110614267
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2228069826
Short name T347
Test name
Test status
Simulation time 137027048 ps
CPU time 0.89 seconds
Started Jul 22 05:52:11 PM PDT 24
Finished Jul 22 05:52:12 PM PDT 24
Peak memory 206084 kb
Host smart-4728edc1-c906-4b32-90c8-52b569e7c1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228069826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2228069826
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3201588396
Short name T916
Test name
Test status
Simulation time 246756292 ps
CPU time 2.38 seconds
Started Jul 22 05:52:15 PM PDT 24
Finished Jul 22 05:52:18 PM PDT 24
Peak memory 232832 kb
Host smart-a5378673-38fb-46ff-ad1a-2bbf2d686a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201588396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3201588396
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3876883651
Short name T895
Test name
Test status
Simulation time 37914587 ps
CPU time 0.72 seconds
Started Jul 22 05:52:25 PM PDT 24
Finished Jul 22 05:52:26 PM PDT 24
Peak memory 204976 kb
Host smart-d7e76c9c-9e8d-4eb1-afee-59549fa85b20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876883651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3876883651
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2942487304
Short name T504
Test name
Test status
Simulation time 4337079347 ps
CPU time 10.49 seconds
Started Jul 22 05:52:28 PM PDT 24
Finished Jul 22 05:52:39 PM PDT 24
Peak memory 224720 kb
Host smart-f5a099aa-b972-4c93-839e-a92782cf2347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942487304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2942487304
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1615980916
Short name T453
Test name
Test status
Simulation time 19758357 ps
CPU time 0.88 seconds
Started Jul 22 05:52:18 PM PDT 24
Finished Jul 22 05:52:19 PM PDT 24
Peak memory 207056 kb
Host smart-8f4b894a-510b-4d7b-b9ec-c50758ed097f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615980916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1615980916
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.3189409076
Short name T907
Test name
Test status
Simulation time 8999393151 ps
CPU time 56.55 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:53:21 PM PDT 24
Peak memory 241104 kb
Host smart-fd1b1eec-a443-413c-b63c-b9bc2f72cc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189409076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3189409076
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.2368979739
Short name T208
Test name
Test status
Simulation time 3325340345 ps
CPU time 25.36 seconds
Started Jul 22 05:52:28 PM PDT 24
Finished Jul 22 05:52:54 PM PDT 24
Peak memory 233964 kb
Host smart-24cddf16-ddd2-44f2-af12-20a11a1db1e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368979739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2368979739
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4279709610
Short name T85
Test name
Test status
Simulation time 6032888850 ps
CPU time 78.62 seconds
Started Jul 22 05:52:25 PM PDT 24
Finished Jul 22 05:53:44 PM PDT 24
Peak memory 256652 kb
Host smart-92c4d1b3-bfcb-4228-be71-9b3ae7b9e2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279709610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4279709610
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1097785218
Short name T767
Test name
Test status
Simulation time 442069813 ps
CPU time 9.83 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:52:34 PM PDT 24
Peak memory 224672 kb
Host smart-62563cba-c99b-425a-9c67-52374b4fcc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097785218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1097785218
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4109420490
Short name T294
Test name
Test status
Simulation time 11430244501 ps
CPU time 152.84 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:54:58 PM PDT 24
Peak memory 270776 kb
Host smart-939b214c-8e73-4076-8df5-7473880e88bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109420490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4109420490
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1968080213
Short name T26
Test name
Test status
Simulation time 39527210726 ps
CPU time 22.11 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:52:46 PM PDT 24
Peak memory 224704 kb
Host smart-11d1eea1-1903-44b1-85d8-119a17841d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968080213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1968080213
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.4141360180
Short name T671
Test name
Test status
Simulation time 2512600091 ps
CPU time 34.2 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:52:59 PM PDT 24
Peak memory 239368 kb
Host smart-9b7b5359-7715-45ae-8072-1c08d25fc2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141360180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.4141360180
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1878744797
Short name T721
Test name
Test status
Simulation time 99382088 ps
CPU time 2.14 seconds
Started Jul 22 05:52:29 PM PDT 24
Finished Jul 22 05:52:31 PM PDT 24
Peak memory 223928 kb
Host smart-abdb32f5-3364-4f27-a425-355086e34493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878744797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1878744797
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3341908453
Short name T649
Test name
Test status
Simulation time 2866703135 ps
CPU time 9.87 seconds
Started Jul 22 05:52:20 PM PDT 24
Finished Jul 22 05:52:30 PM PDT 24
Peak memory 232944 kb
Host smart-456c6712-90ac-44fc-818e-5ca29baa4d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341908453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3341908453
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.881066964
Short name T37
Test name
Test status
Simulation time 162695344 ps
CPU time 4.36 seconds
Started Jul 22 05:52:29 PM PDT 24
Finished Jul 22 05:52:34 PM PDT 24
Peak memory 223360 kb
Host smart-528f607f-d8b7-4c5b-bb2f-5005d62573e3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=881066964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.881066964
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.3899711349
Short name T716
Test name
Test status
Simulation time 32735391042 ps
CPU time 210.52 seconds
Started Jul 22 05:52:26 PM PDT 24
Finished Jul 22 05:55:56 PM PDT 24
Peak memory 267360 kb
Host smart-26a2e752-0f52-45ab-a561-ac67d4ca4f1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899711349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.3899711349
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3000161741
Short name T538
Test name
Test status
Simulation time 3333892776 ps
CPU time 18.8 seconds
Started Jul 22 05:52:20 PM PDT 24
Finished Jul 22 05:52:39 PM PDT 24
Peak memory 216676 kb
Host smart-dae9f9df-4aec-4aa3-abe1-069484183658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000161741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3000161741
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.4245411902
Short name T705
Test name
Test status
Simulation time 40446814726 ps
CPU time 25.82 seconds
Started Jul 22 05:52:15 PM PDT 24
Finished Jul 22 05:52:42 PM PDT 24
Peak memory 216712 kb
Host smart-a0548b86-7b96-42de-9e9e-95f03e596308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245411902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.4245411902
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2165920286
Short name T78
Test name
Test status
Simulation time 20810993 ps
CPU time 1.05 seconds
Started Jul 22 05:52:17 PM PDT 24
Finished Jul 22 05:52:18 PM PDT 24
Peak memory 207380 kb
Host smart-afc11d53-25e6-4b94-b428-ae686884db49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165920286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2165920286
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1190066232
Short name T912
Test name
Test status
Simulation time 122633842 ps
CPU time 0.85 seconds
Started Jul 22 05:52:18 PM PDT 24
Finished Jul 22 05:52:20 PM PDT 24
Peak memory 206052 kb
Host smart-727e08df-2446-4a2b-87ba-d61e16363b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190066232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1190066232
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.154505125
Short name T575
Test name
Test status
Simulation time 316524666 ps
CPU time 5.96 seconds
Started Jul 22 05:52:27 PM PDT 24
Finished Jul 22 05:52:33 PM PDT 24
Peak memory 232752 kb
Host smart-f920ef8c-74ea-44e2-afca-258592fb6646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154505125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.154505125
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.4161180795
Short name T65
Test name
Test status
Simulation time 49019485 ps
CPU time 0.71 seconds
Started Jul 22 05:52:48 PM PDT 24
Finished Jul 22 05:52:49 PM PDT 24
Peak memory 205060 kb
Host smart-3dfe0b98-4f72-4897-8c0d-4ff2e3483b79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161180795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
4161180795
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2899413317
Short name T382
Test name
Test status
Simulation time 106194781 ps
CPU time 2.44 seconds
Started Jul 22 05:52:36 PM PDT 24
Finished Jul 22 05:52:38 PM PDT 24
Peak memory 224620 kb
Host smart-1c893b96-2d01-4464-9b0b-db3df228adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899413317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2899413317
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.432319532
Short name T879
Test name
Test status
Simulation time 59492052 ps
CPU time 0.75 seconds
Started Jul 22 05:52:22 PM PDT 24
Finished Jul 22 05:52:23 PM PDT 24
Peak memory 205876 kb
Host smart-599a7e64-554a-48a7-b04a-6dd268904928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432319532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.432319532
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.263769617
Short name T870
Test name
Test status
Simulation time 204437279880 ps
CPU time 143.85 seconds
Started Jul 22 05:52:35 PM PDT 24
Finished Jul 22 05:54:59 PM PDT 24
Peak memory 260356 kb
Host smart-3e4eb129-bebd-4b8b-a8aa-d97badffdf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263769617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.263769617
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2592981186
Short name T245
Test name
Test status
Simulation time 293268419664 ps
CPU time 159.95 seconds
Started Jul 22 05:52:37 PM PDT 24
Finished Jul 22 05:55:18 PM PDT 24
Peak memory 224168 kb
Host smart-cbffdcd4-ba4d-4ca0-a934-ff66b07c36aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592981186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2592981186
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1525022899
Short name T592
Test name
Test status
Simulation time 2256843756 ps
CPU time 10.1 seconds
Started Jul 22 05:52:36 PM PDT 24
Finished Jul 22 05:52:47 PM PDT 24
Peak memory 241204 kb
Host smart-e09474e4-d5d5-43e8-bc31-2392fa2fe222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525022899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1525022899
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.3633028703
Short name T708
Test name
Test status
Simulation time 929603579 ps
CPU time 24.7 seconds
Started Jul 22 05:52:34 PM PDT 24
Finished Jul 22 05:52:59 PM PDT 24
Peak memory 250572 kb
Host smart-da8caf75-45db-4888-b3bf-e3239d1f600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633028703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.3633028703
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4085360908
Short name T595
Test name
Test status
Simulation time 2714648979 ps
CPU time 15.52 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:52:40 PM PDT 24
Peak memory 232956 kb
Host smart-e80b19d6-2428-4968-871d-efefe7771cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085360908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4085360908
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3871290541
Short name T747
Test name
Test status
Simulation time 646286455 ps
CPU time 8.7 seconds
Started Jul 22 05:52:36 PM PDT 24
Finished Jul 22 05:52:46 PM PDT 24
Peak memory 229576 kb
Host smart-b2ce3e57-dac5-4418-978a-6c931bb35a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871290541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3871290541
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3076532583
Short name T259
Test name
Test status
Simulation time 412489869 ps
CPU time 3.55 seconds
Started Jul 22 05:52:21 PM PDT 24
Finished Jul 22 05:52:25 PM PDT 24
Peak memory 224644 kb
Host smart-c51e7585-bbee-4688-b1e9-aba5f0a9c98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076532583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3076532583
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.30300698
Short name T238
Test name
Test status
Simulation time 1180216507 ps
CPU time 4.54 seconds
Started Jul 22 05:52:27 PM PDT 24
Finished Jul 22 05:52:32 PM PDT 24
Peak memory 224612 kb
Host smart-088706c9-cb21-4b86-9e88-a61c2513a42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30300698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.30300698
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1024100994
Short name T377
Test name
Test status
Simulation time 517673947 ps
CPU time 4.32 seconds
Started Jul 22 05:52:35 PM PDT 24
Finished Jul 22 05:52:40 PM PDT 24
Peak memory 223304 kb
Host smart-27a2d703-fd0b-448f-9a02-f4676500e59c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1024100994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1024100994
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3958120653
Short name T710
Test name
Test status
Simulation time 80135941364 ps
CPU time 159.26 seconds
Started Jul 22 05:52:49 PM PDT 24
Finished Jul 22 05:55:28 PM PDT 24
Peak memory 270580 kb
Host smart-46ee5bd3-019b-42a3-8d61-5e161699161c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958120653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3958120653
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2642355436
Short name T799
Test name
Test status
Simulation time 1005076688 ps
CPU time 4.96 seconds
Started Jul 22 05:52:27 PM PDT 24
Finished Jul 22 05:52:33 PM PDT 24
Peak memory 216688 kb
Host smart-47a62f74-fcb9-40aa-a655-f2878bd00f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642355436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2642355436
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1982410532
Short name T364
Test name
Test status
Simulation time 148998255 ps
CPU time 0.72 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:52:25 PM PDT 24
Peak memory 205824 kb
Host smart-4bd337d4-23f7-445d-bc10-6b27411ffbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982410532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1982410532
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1968008908
Short name T892
Test name
Test status
Simulation time 186524248 ps
CPU time 2.22 seconds
Started Jul 22 05:52:24 PM PDT 24
Finished Jul 22 05:52:27 PM PDT 24
Peak memory 216408 kb
Host smart-73905a79-bdca-43b6-8a9f-ea9c8c11c07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968008908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1968008908
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.2734527476
Short name T520
Test name
Test status
Simulation time 86385287 ps
CPU time 1 seconds
Started Jul 22 05:52:29 PM PDT 24
Finished Jul 22 05:52:30 PM PDT 24
Peak memory 207196 kb
Host smart-9c6c3397-4a6c-4e1d-8ed2-0fa0aea727db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734527476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.2734527476
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2569968811
Short name T174
Test name
Test status
Simulation time 251153727 ps
CPU time 2.81 seconds
Started Jul 22 05:52:33 PM PDT 24
Finished Jul 22 05:52:36 PM PDT 24
Peak memory 232916 kb
Host smart-bd9d078a-8b67-44ea-aae3-6efd7bd6889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569968811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2569968811
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1108423511
Short name T590
Test name
Test status
Simulation time 12886000 ps
CPU time 0.69 seconds
Started Jul 22 05:52:46 PM PDT 24
Finished Jul 22 05:52:47 PM PDT 24
Peak memory 205920 kb
Host smart-2a38d2ef-774d-4f98-8c5c-486ac2ad7834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108423511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1108423511
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3890468997
Short name T841
Test name
Test status
Simulation time 85197163 ps
CPU time 2.48 seconds
Started Jul 22 05:52:45 PM PDT 24
Finished Jul 22 05:52:48 PM PDT 24
Peak memory 224608 kb
Host smart-ceaf8638-39cd-486e-95ab-1c362029a79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890468997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3890468997
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.317374465
Short name T654
Test name
Test status
Simulation time 40961891 ps
CPU time 0.77 seconds
Started Jul 22 05:52:33 PM PDT 24
Finished Jul 22 05:52:34 PM PDT 24
Peak memory 206680 kb
Host smart-f27aa711-4b48-4295-a6a1-14cfefe6c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317374465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.317374465
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4180626041
Short name T267
Test name
Test status
Simulation time 350256836701 ps
CPU time 462.74 seconds
Started Jul 22 05:52:45 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 265876 kb
Host smart-bb9ef0d9-85bf-4ee3-8924-2e593142ea7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180626041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4180626041
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.2232795187
Short name T934
Test name
Test status
Simulation time 93239251039 ps
CPU time 268.18 seconds
Started Jul 22 05:52:46 PM PDT 24
Finished Jul 22 05:57:15 PM PDT 24
Peak memory 265752 kb
Host smart-31a9a185-c1cf-415d-95f3-9183a746fb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232795187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.2232795187
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1638023891
Short name T618
Test name
Test status
Simulation time 28142400866 ps
CPU time 260.77 seconds
Started Jul 22 05:52:44 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 252912 kb
Host smart-7afe54bf-6387-48de-ab24-ffcae64a7554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638023891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1638023891
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2260371554
Short name T145
Test name
Test status
Simulation time 7263325949 ps
CPU time 19.37 seconds
Started Jul 22 05:52:46 PM PDT 24
Finished Jul 22 05:53:06 PM PDT 24
Peak memory 237656 kb
Host smart-7e7544dd-4a53-4a46-9e46-7a327a4a3ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260371554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2260371554
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2232970215
Short name T744
Test name
Test status
Simulation time 3273511126 ps
CPU time 6.27 seconds
Started Jul 22 05:52:48 PM PDT 24
Finished Jul 22 05:52:55 PM PDT 24
Peak memory 232900 kb
Host smart-163a1856-a7a4-41b2-850d-0e67e06ba110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232970215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2232970215
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2569744797
Short name T615
Test name
Test status
Simulation time 3247087467 ps
CPU time 34.75 seconds
Started Jul 22 05:52:43 PM PDT 24
Finished Jul 22 05:53:18 PM PDT 24
Peak memory 232964 kb
Host smart-9147f43c-1b97-4a5e-ab0d-28433a911062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569744797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2569744797
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.612974644
Short name T287
Test name
Test status
Simulation time 2615943898 ps
CPU time 12.54 seconds
Started Jul 22 05:52:48 PM PDT 24
Finished Jul 22 05:53:01 PM PDT 24
Peak memory 249160 kb
Host smart-478a326c-9ba5-4cd7-acec-9d314e60e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612974644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.612974644
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.13638562
Short name T227
Test name
Test status
Simulation time 6195097388 ps
CPU time 14.74 seconds
Started Jul 22 05:52:43 PM PDT 24
Finished Jul 22 05:52:58 PM PDT 24
Peak memory 224540 kb
Host smart-c82e5a8f-bbbe-4d5d-9ea4-b8eec7190371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13638562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.13638562
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2259592806
Short name T418
Test name
Test status
Simulation time 137102064 ps
CPU time 3.87 seconds
Started Jul 22 05:52:48 PM PDT 24
Finished Jul 22 05:52:52 PM PDT 24
Peak memory 223304 kb
Host smart-4787f63d-0e3c-4a04-8f3a-b46f9a36c402
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2259592806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2259592806
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1967584196
Short name T18
Test name
Test status
Simulation time 459229492 ps
CPU time 0.92 seconds
Started Jul 22 05:52:49 PM PDT 24
Finished Jul 22 05:52:50 PM PDT 24
Peak memory 206752 kb
Host smart-b247009f-0947-4b4a-91c6-9ea92df28ec2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967584196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1967584196
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3011056405
Short name T526
Test name
Test status
Simulation time 1048027815 ps
CPU time 13.37 seconds
Started Jul 22 05:52:33 PM PDT 24
Finished Jul 22 05:52:47 PM PDT 24
Peak memory 220224 kb
Host smart-47111a61-f4e3-487a-931b-240f32a728a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011056405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3011056405
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1856462838
Short name T366
Test name
Test status
Simulation time 17467123803 ps
CPU time 12.75 seconds
Started Jul 22 05:52:34 PM PDT 24
Finished Jul 22 05:52:47 PM PDT 24
Peak memory 216500 kb
Host smart-610e91a8-40e3-4b12-a20d-09042a05518c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856462838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1856462838
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.2383578093
Short name T391
Test name
Test status
Simulation time 1173651446 ps
CPU time 3.87 seconds
Started Jul 22 05:52:36 PM PDT 24
Finished Jul 22 05:52:40 PM PDT 24
Peak memory 216328 kb
Host smart-eaf45ae2-e06e-4060-aad6-cd0d3f5a2dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383578093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2383578093
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3185791984
Short name T772
Test name
Test status
Simulation time 58696616 ps
CPU time 0.83 seconds
Started Jul 22 05:52:38 PM PDT 24
Finished Jul 22 05:52:40 PM PDT 24
Peak memory 206068 kb
Host smart-c4b2a815-8de0-4fb5-b082-d360a2ed3221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185791984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3185791984
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2932901191
Short name T845
Test name
Test status
Simulation time 373697885 ps
CPU time 7.24 seconds
Started Jul 22 05:52:43 PM PDT 24
Finished Jul 22 05:52:51 PM PDT 24
Peak memory 232912 kb
Host smart-5c7d8c63-077d-4645-9582-a99eac584923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932901191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2932901191
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1013548748
Short name T910
Test name
Test status
Simulation time 14292098 ps
CPU time 0.7 seconds
Started Jul 22 05:52:57 PM PDT 24
Finished Jul 22 05:52:58 PM PDT 24
Peak memory 205044 kb
Host smart-02c7e09f-cc1e-4c82-bee8-ab3795a9042c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013548748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1013548748
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4050280315
Short name T724
Test name
Test status
Simulation time 2306245780 ps
CPU time 6.55 seconds
Started Jul 22 05:52:53 PM PDT 24
Finished Jul 22 05:53:00 PM PDT 24
Peak memory 232888 kb
Host smart-a4f0645e-6f65-4f0e-b70b-5aa4b1949923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050280315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4050280315
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1396083218
Short name T27
Test name
Test status
Simulation time 14001003 ps
CPU time 0.77 seconds
Started Jul 22 05:52:43 PM PDT 24
Finished Jul 22 05:52:45 PM PDT 24
Peak memory 207068 kb
Host smart-958ed43e-c17b-4170-accc-511368129cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396083218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1396083218
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.531892265
Short name T769
Test name
Test status
Simulation time 3073035636 ps
CPU time 38.3 seconds
Started Jul 22 05:52:57 PM PDT 24
Finished Jul 22 05:53:35 PM PDT 24
Peak memory 249004 kb
Host smart-bb589b77-eea3-4973-8515-dec5c125d131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531892265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.531892265
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3200120355
Short name T483
Test name
Test status
Simulation time 2577391796 ps
CPU time 14.85 seconds
Started Jul 22 05:53:47 PM PDT 24
Finished Jul 22 05:54:02 PM PDT 24
Peak memory 217856 kb
Host smart-1a6719d8-3a1e-4315-ba04-7d575778026e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200120355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3200120355
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.4089352696
Short name T587
Test name
Test status
Simulation time 118050651 ps
CPU time 3.19 seconds
Started Jul 22 05:52:59 PM PDT 24
Finished Jul 22 05:53:02 PM PDT 24
Peak memory 224684 kb
Host smart-11c8db74-ceab-41ee-aa3e-c873f6391ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089352696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.4089352696
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3307603610
Short name T999
Test name
Test status
Simulation time 30496704619 ps
CPU time 155.58 seconds
Started Jul 22 05:52:56 PM PDT 24
Finished Jul 22 05:55:32 PM PDT 24
Peak memory 241184 kb
Host smart-30d08579-c6f2-4f62-aa53-e6736214a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307603610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3307603610
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.209775343
Short name T413
Test name
Test status
Simulation time 191232113 ps
CPU time 3.05 seconds
Started Jul 22 05:52:57 PM PDT 24
Finished Jul 22 05:53:00 PM PDT 24
Peak memory 232788 kb
Host smart-72ccc018-12aa-405c-a240-326cef14bad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209775343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.209775343
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.182742313
Short name T853
Test name
Test status
Simulation time 49045560201 ps
CPU time 94.78 seconds
Started Jul 22 05:52:54 PM PDT 24
Finished Jul 22 05:54:30 PM PDT 24
Peak memory 232932 kb
Host smart-a8ef0ae2-f68b-4630-8406-a5b05e0caea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182742313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.182742313
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.4061900659
Short name T645
Test name
Test status
Simulation time 1181653478 ps
CPU time 3.86 seconds
Started Jul 22 05:52:54 PM PDT 24
Finished Jul 22 05:52:59 PM PDT 24
Peak memory 224580 kb
Host smart-37d65503-f124-43c1-94f1-0824388b1930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061900659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.4061900659
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.4140497623
Short name T512
Test name
Test status
Simulation time 42264786237 ps
CPU time 22.88 seconds
Started Jul 22 05:52:54 PM PDT 24
Finished Jul 22 05:53:17 PM PDT 24
Peak memory 232920 kb
Host smart-75d975b9-d6a0-4ba3-ba38-ff40491303b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140497623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.4140497623
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3818691248
Short name T452
Test name
Test status
Simulation time 1111453724 ps
CPU time 6.59 seconds
Started Jul 22 05:52:54 PM PDT 24
Finished Jul 22 05:53:01 PM PDT 24
Peak memory 219484 kb
Host smart-eeb90cbf-0731-4c35-948c-18b918e4308d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3818691248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3818691248
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.4180623708
Short name T138
Test name
Test status
Simulation time 263579854809 ps
CPU time 233.48 seconds
Started Jul 22 05:52:58 PM PDT 24
Finished Jul 22 05:56:52 PM PDT 24
Peak memory 263228 kb
Host smart-12567d19-7702-4593-9659-288ce0180377
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180623708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.4180623708
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1632960679
Short name T433
Test name
Test status
Simulation time 1457561884 ps
CPU time 4.75 seconds
Started Jul 22 05:52:41 PM PDT 24
Finished Jul 22 05:52:46 PM PDT 24
Peak memory 216440 kb
Host smart-4e148f9c-5b0c-4de4-b5cd-eefc0e0cbfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632960679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1632960679
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2769668577
Short name T958
Test name
Test status
Simulation time 83232630 ps
CPU time 1.3 seconds
Started Jul 22 05:52:54 PM PDT 24
Finished Jul 22 05:52:56 PM PDT 24
Peak memory 216336 kb
Host smart-11209921-f686-48f9-853f-8882702d2a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769668577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2769668577
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.77910447
Short name T625
Test name
Test status
Simulation time 84141837 ps
CPU time 0.74 seconds
Started Jul 22 05:52:49 PM PDT 24
Finished Jul 22 05:52:50 PM PDT 24
Peak memory 206144 kb
Host smart-2363be86-b272-4b41-9a02-217c22de4c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77910447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.77910447
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.558489635
Short name T774
Test name
Test status
Simulation time 262560752 ps
CPU time 6.45 seconds
Started Jul 22 05:52:59 PM PDT 24
Finished Jul 22 05:53:06 PM PDT 24
Peak memory 232916 kb
Host smart-da756b53-e2a4-46a0-a64e-d9bde85373bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558489635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.558489635
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2442233563
Short name T719
Test name
Test status
Simulation time 32198441 ps
CPU time 0.72 seconds
Started Jul 22 05:48:00 PM PDT 24
Finished Jul 22 05:48:02 PM PDT 24
Peak memory 205868 kb
Host smart-3bb4f633-8923-432e-a790-b2da54983a5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442233563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
442233563
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.189370448
Short name T620
Test name
Test status
Simulation time 222406517 ps
CPU time 2.63 seconds
Started Jul 22 05:48:17 PM PDT 24
Finished Jul 22 05:48:20 PM PDT 24
Peak memory 232332 kb
Host smart-16840cf8-8b46-46eb-8812-f20a5d79ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189370448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.189370448
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.940359011
Short name T713
Test name
Test status
Simulation time 17865233 ps
CPU time 0.78 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:48:01 PM PDT 24
Peak memory 206048 kb
Host smart-0de2594f-7bb6-440d-a959-f77af6ad9339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940359011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.940359011
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3179000657
Short name T195
Test name
Test status
Simulation time 10868546875 ps
CPU time 42.89 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:42 PM PDT 24
Peak memory 249348 kb
Host smart-8e59d762-91a2-4742-9321-41d8a8148676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179000657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3179000657
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.753561859
Short name T263
Test name
Test status
Simulation time 7414189507 ps
CPU time 37.85 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:49:00 PM PDT 24
Peak memory 249368 kb
Host smart-3086b8f9-2c21-4a75-98b0-21fd482f4a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753561859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.753561859
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.4042381684
Short name T754
Test name
Test status
Simulation time 1196361975 ps
CPU time 19.6 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:48:17 PM PDT 24
Peak memory 217644 kb
Host smart-2248df3d-d95d-476a-a50d-5d6576d20c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042381684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.4042381684
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.320846235
Short name T672
Test name
Test status
Simulation time 769178630 ps
CPU time 4.41 seconds
Started Jul 22 05:48:00 PM PDT 24
Finished Jul 22 05:48:05 PM PDT 24
Peak memory 224660 kb
Host smart-a8b85d8f-430b-4983-9a83-cf825cbdf5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320846235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.320846235
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.2503009573
Short name T905
Test name
Test status
Simulation time 37767855612 ps
CPU time 230.34 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:51:48 PM PDT 24
Peak memory 249328 kb
Host smart-52f89227-2248-4867-aafa-2c11e604a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503009573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.2503009573
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.4162438075
Short name T438
Test name
Test status
Simulation time 1222913835 ps
CPU time 4.61 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:48:03 PM PDT 24
Peak memory 224716 kb
Host smart-01287a4e-36d6-40d0-b705-fc48f986611f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162438075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4162438075
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3725354406
Short name T909
Test name
Test status
Simulation time 1145592271 ps
CPU time 8.98 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:07 PM PDT 24
Peak memory 224684 kb
Host smart-82b2fed8-885e-44c8-ae1f-89397ca5b3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725354406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3725354406
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1778297227
Short name T265
Test name
Test status
Simulation time 2315575105 ps
CPU time 5.64 seconds
Started Jul 22 05:48:04 PM PDT 24
Finished Jul 22 05:48:10 PM PDT 24
Peak memory 224624 kb
Host smart-80651a8e-7636-4b69-9c15-7533489cb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778297227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1778297227
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2816093757
Short name T807
Test name
Test status
Simulation time 46314599040 ps
CPU time 34.24 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:33 PM PDT 24
Peak memory 240404 kb
Host smart-ed59df78-3b81-4ea5-84b1-c9021b653fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816093757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2816093757
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.972533321
Short name T149
Test name
Test status
Simulation time 451084587 ps
CPU time 5.21 seconds
Started Jul 22 05:48:35 PM PDT 24
Finished Jul 22 05:48:41 PM PDT 24
Peak memory 223264 kb
Host smart-b23a6388-947a-4a62-940a-6c242772e6c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=972533321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.972533321
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3323412213
Short name T660
Test name
Test status
Simulation time 25449105457 ps
CPU time 27.79 seconds
Started Jul 22 05:48:04 PM PDT 24
Finished Jul 22 05:48:32 PM PDT 24
Peak memory 220184 kb
Host smart-39db92b3-c81a-412e-b812-a71d1b96b5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323412213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3323412213
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3449385370
Short name T92
Test name
Test status
Simulation time 6483492913 ps
CPU time 13.95 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:13 PM PDT 24
Peak memory 216452 kb
Host smart-1566e9ba-7d7b-4a7e-92ad-5f8df1082718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449385370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3449385370
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3994598064
Short name T935
Test name
Test status
Simulation time 51970333 ps
CPU time 0.7 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 206104 kb
Host smart-e390ddfc-9fd1-4ed7-b98c-41bc55543c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994598064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3994598064
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1172762438
Short name T401
Test name
Test status
Simulation time 25362862 ps
CPU time 0.82 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:47:59 PM PDT 24
Peak memory 206096 kb
Host smart-63bcb7d2-ea33-492c-904a-cf7eccc536c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172762438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1172762438
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.852090182
Short name T517
Test name
Test status
Simulation time 14210172399 ps
CPU time 10.35 seconds
Started Jul 22 05:47:56 PM PDT 24
Finished Jul 22 05:48:07 PM PDT 24
Peak memory 224832 kb
Host smart-008c70c7-45ca-4718-9ea9-c521bf412f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852090182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.852090182
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1622437431
Short name T650
Test name
Test status
Simulation time 33918002 ps
CPU time 0.73 seconds
Started Jul 22 05:48:07 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 204992 kb
Host smart-6fe66fb9-d19f-4789-aa96-6da0d5080d42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622437431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
622437431
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3878179930
Short name T738
Test name
Test status
Simulation time 2250326329 ps
CPU time 6.12 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:48:04 PM PDT 24
Peak memory 233128 kb
Host smart-4ff3c266-797c-49e5-96e1-a4ab88d21523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878179930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3878179930
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.569983460
Short name T707
Test name
Test status
Simulation time 13537498 ps
CPU time 0.77 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:00 PM PDT 24
Peak memory 205708 kb
Host smart-89c47526-a023-4a75-af21-302bc7766d44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569983460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.569983460
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.970074771
Short name T815
Test name
Test status
Simulation time 13440492507 ps
CPU time 53.54 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:52 PM PDT 24
Peak memory 250308 kb
Host smart-a44008a6-544c-4e9f-afbf-9e969747eee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970074771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.970074771
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1530143379
Short name T288
Test name
Test status
Simulation time 102584520844 ps
CPU time 252.25 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:52:12 PM PDT 24
Peak memory 257016 kb
Host smart-157ed7c2-f6cd-4d26-83aa-9f10f71a2c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530143379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1530143379
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3831561720
Short name T161
Test name
Test status
Simulation time 7794895458 ps
CPU time 35.11 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:48:35 PM PDT 24
Peak memory 248888 kb
Host smart-86cf1952-8cd1-4348-ae26-861cc94fc887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831561720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3831561720
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2987410596
Short name T143
Test name
Test status
Simulation time 2688504270 ps
CPU time 44.09 seconds
Started Jul 22 05:48:04 PM PDT 24
Finished Jul 22 05:48:48 PM PDT 24
Peak memory 249892 kb
Host smart-b281568d-20d7-4e35-8c9f-d3f79f4ed802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987410596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2987410596
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.3842637609
Short name T463
Test name
Test status
Simulation time 5611982971 ps
CPU time 45.17 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:48:45 PM PDT 24
Peak memory 236228 kb
Host smart-1ef97ec4-4a31-44df-ba4c-18192e88d346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842637609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.3842637609
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1697697642
Short name T437
Test name
Test status
Simulation time 221912566 ps
CPU time 3.18 seconds
Started Jul 22 05:47:57 PM PDT 24
Finished Jul 22 05:48:00 PM PDT 24
Peak memory 233060 kb
Host smart-3c817740-60ad-45d1-963b-6579491e1241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697697642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1697697642
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1366801682
Short name T819
Test name
Test status
Simulation time 292908293 ps
CPU time 8.33 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:48:08 PM PDT 24
Peak memory 241020 kb
Host smart-44a6ca15-88e0-44eb-a3aa-a3a4ab3ff95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366801682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1366801682
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2956959391
Short name T270
Test name
Test status
Simulation time 6436842687 ps
CPU time 8.01 seconds
Started Jul 22 05:48:04 PM PDT 24
Finished Jul 22 05:48:13 PM PDT 24
Peak memory 236220 kb
Host smart-0fdfebe9-ae60-418a-8f99-d5a14c746f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956959391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2956959391
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.2624838430
Short name T652
Test name
Test status
Simulation time 5581536756 ps
CPU time 14 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:13 PM PDT 24
Peak memory 240896 kb
Host smart-5507fb58-9fa0-4128-9ef7-85c46d0b7723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624838430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2624838430
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2937973658
Short name T900
Test name
Test status
Simulation time 2795175349 ps
CPU time 13.83 seconds
Started Jul 22 05:48:21 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 222432 kb
Host smart-8f0df67b-951b-45da-8427-1373e2bf8536
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2937973658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2937973658
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1925289646
Short name T277
Test name
Test status
Simulation time 517543527739 ps
CPU time 626.39 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:58:37 PM PDT 24
Peak memory 285072 kb
Host smart-0e63281c-56b1-4445-bee5-2f0e0c6f99da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925289646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1925289646
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3282602696
Short name T36
Test name
Test status
Simulation time 1443243129 ps
CPU time 20.77 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 216456 kb
Host smart-1a80d522-fe97-4c9b-9d55-e5f3ff92500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282602696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3282602696
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1930242145
Short name T662
Test name
Test status
Simulation time 35023569 ps
CPU time 0.7 seconds
Started Jul 22 05:47:58 PM PDT 24
Finished Jul 22 05:48:00 PM PDT 24
Peak memory 205824 kb
Host smart-f260eacc-dec3-410d-bafa-edea377be401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930242145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1930242145
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1992590840
Short name T817
Test name
Test status
Simulation time 86902660 ps
CPU time 2.3 seconds
Started Jul 22 05:47:59 PM PDT 24
Finished Jul 22 05:48:02 PM PDT 24
Peak memory 216408 kb
Host smart-f75efee5-84c4-4f82-8771-c5e55f1b6c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992590840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1992590840
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2908492062
Short name T711
Test name
Test status
Simulation time 70612011 ps
CPU time 0.9 seconds
Started Jul 22 05:48:17 PM PDT 24
Finished Jul 22 05:48:18 PM PDT 24
Peak memory 205516 kb
Host smart-41c922a8-d468-4930-a32e-0b77cca45ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908492062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2908492062
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1969702809
Short name T534
Test name
Test status
Simulation time 4913729138 ps
CPU time 12.81 seconds
Started Jul 22 05:47:55 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 219160 kb
Host smart-8d701553-81c3-47dc-801c-e4ef14a67a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969702809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1969702809
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3284674697
Short name T942
Test name
Test status
Simulation time 16208968 ps
CPU time 0.82 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:11 PM PDT 24
Peak memory 204996 kb
Host smart-6d3a84b1-c7d2-42b2-95bc-08e8fc7bad66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284674697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
284674697
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2194948296
Short name T757
Test name
Test status
Simulation time 225038098 ps
CPU time 2.66 seconds
Started Jul 22 05:48:07 PM PDT 24
Finished Jul 22 05:48:10 PM PDT 24
Peak memory 232872 kb
Host smart-2aab740b-ae8e-4149-89be-f1cdbb8381c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194948296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2194948296
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.1747572390
Short name T594
Test name
Test status
Simulation time 45097654 ps
CPU time 0.78 seconds
Started Jul 22 05:48:08 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 205696 kb
Host smart-9170ee47-8faa-45ab-8149-764d1af2a46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747572390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1747572390
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.937548261
Short name T356
Test name
Test status
Simulation time 15033075153 ps
CPU time 27.8 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:34 PM PDT 24
Peak memory 236912 kb
Host smart-ff10481a-29eb-43f9-b6b5-4fe522925f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937548261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.937548261
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1726549956
Short name T637
Test name
Test status
Simulation time 8903408890 ps
CPU time 53.47 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:49:03 PM PDT 24
Peak memory 219484 kb
Host smart-2e0209f1-894c-439e-bd59-13016bd237d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726549956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1726549956
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2372053281
Short name T602
Test name
Test status
Simulation time 8754656274 ps
CPU time 51.22 seconds
Started Jul 22 05:48:10 PM PDT 24
Finished Jul 22 05:49:02 PM PDT 24
Peak memory 240160 kb
Host smart-98094a96-47cf-4ae5-9ab5-7ed81c57f1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372053281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2372053281
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.408649272
Short name T980
Test name
Test status
Simulation time 63727751 ps
CPU time 2.66 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 224732 kb
Host smart-80ed0a10-de60-484f-8439-a9262fa5e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408649272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.408649272
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3008791840
Short name T919
Test name
Test status
Simulation time 23420961273 ps
CPU time 120.74 seconds
Started Jul 22 05:48:08 PM PDT 24
Finished Jul 22 05:50:10 PM PDT 24
Peak memory 252712 kb
Host smart-6a8f71fd-dd85-42b8-afbb-5456957627d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008791840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3008791840
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1435246369
Short name T924
Test name
Test status
Simulation time 180472817 ps
CPU time 3.47 seconds
Started Jul 22 05:48:08 PM PDT 24
Finished Jul 22 05:48:12 PM PDT 24
Peak memory 224648 kb
Host smart-c524a20e-3216-42fc-befb-ca352649ea02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435246369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1435246369
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.2829824237
Short name T513
Test name
Test status
Simulation time 7302276125 ps
CPU time 76.13 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:49:23 PM PDT 24
Peak memory 224704 kb
Host smart-edc3d2db-2351-4cec-9437-cd73d0be9c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829824237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2829824237
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.344542122
Short name T103
Test name
Test status
Simulation time 3689824685 ps
CPU time 8.4 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 232900 kb
Host smart-daaa4925-1c4f-42cc-9183-165064644394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344542122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.
344542122
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3342836566
Short name T329
Test name
Test status
Simulation time 100842926 ps
CPU time 2.35 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:12 PM PDT 24
Peak memory 232580 kb
Host smart-66c8f30a-dbbb-42b7-83c9-124c40bbc469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342836566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3342836566
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.853403255
Short name T381
Test name
Test status
Simulation time 753699451 ps
CPU time 10.19 seconds
Started Jul 22 05:48:05 PM PDT 24
Finished Jul 22 05:48:16 PM PDT 24
Peak memory 221796 kb
Host smart-9bf1ae4b-d3c5-4609-9be7-61a3286992f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=853403255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.853403255
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.958792268
Short name T276
Test name
Test status
Simulation time 133122650801 ps
CPU time 480.42 seconds
Started Jul 22 05:48:10 PM PDT 24
Finished Jul 22 05:56:12 PM PDT 24
Peak memory 252212 kb
Host smart-4e14c01f-5c1e-40dd-93a5-c397ad463d0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958792268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.958792268
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3947482043
Short name T7
Test name
Test status
Simulation time 43794502 ps
CPU time 0.75 seconds
Started Jul 22 05:48:04 PM PDT 24
Finished Jul 22 05:48:05 PM PDT 24
Peak memory 205848 kb
Host smart-672ee524-58da-4a86-a6be-65c4a0204e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947482043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3947482043
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3480488197
Short name T63
Test name
Test status
Simulation time 11538475 ps
CPU time 0.69 seconds
Started Jul 22 05:48:10 PM PDT 24
Finished Jul 22 05:48:12 PM PDT 24
Peak memory 205808 kb
Host smart-fbe1a987-e13f-4c1c-ac73-354f6c6477f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480488197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3480488197
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3495096616
Short name T469
Test name
Test status
Simulation time 150853987 ps
CPU time 6.46 seconds
Started Jul 22 05:48:05 PM PDT 24
Finished Jul 22 05:48:13 PM PDT 24
Peak memory 216396 kb
Host smart-fecd6967-9b9a-44b1-b556-1f506330754c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495096616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3495096616
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1427628470
Short name T692
Test name
Test status
Simulation time 78178949 ps
CPU time 0.96 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:10 PM PDT 24
Peak memory 206128 kb
Host smart-89f75058-11af-4c6a-8396-8eec96e204fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427628470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1427628470
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.404156999
Short name T251
Test name
Test status
Simulation time 152810109065 ps
CPU time 27.13 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:37 PM PDT 24
Peak memory 232864 kb
Host smart-32ada8b4-84ff-4740-9632-2c018238e673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404156999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.404156999
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.891791998
Short name T588
Test name
Test status
Simulation time 77510310 ps
CPU time 0.73 seconds
Started Jul 22 05:48:14 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 205972 kb
Host smart-f81e06e9-2cb2-4be4-b960-742387dbd3bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891791998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.891791998
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.239973197
Short name T795
Test name
Test status
Simulation time 169918748 ps
CPU time 2.66 seconds
Started Jul 22 05:48:07 PM PDT 24
Finished Jul 22 05:48:10 PM PDT 24
Peak memory 232876 kb
Host smart-0db62bb9-0856-4730-8fbb-87e320a6ea70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239973197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.239973197
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3407535247
Short name T908
Test name
Test status
Simulation time 28289117 ps
CPU time 0.81 seconds
Started Jul 22 05:48:08 PM PDT 24
Finished Jul 22 05:48:09 PM PDT 24
Peak memory 206732 kb
Host smart-ec215e0a-7c2a-47c2-91eb-3dbf51aa3ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407535247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3407535247
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1929745797
Short name T176
Test name
Test status
Simulation time 1375721896 ps
CPU time 29.34 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:36 PM PDT 24
Peak memory 250616 kb
Host smart-ffa3c256-0bf8-43c0-8e31-e9600c9438c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929745797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1929745797
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2817268631
Short name T261
Test name
Test status
Simulation time 26075519393 ps
CPU time 171.22 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:51:01 PM PDT 24
Peak memory 250428 kb
Host smart-bce1822e-d47e-4f84-80c6-801c368609e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817268631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2817268631
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.432804457
Short name T297
Test name
Test status
Simulation time 339274256 ps
CPU time 10.83 seconds
Started Jul 22 05:48:08 PM PDT 24
Finished Jul 22 05:48:19 PM PDT 24
Peak memory 224644 kb
Host smart-2c3fb40f-24f0-43d7-b6f5-d6a5de4cfc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432804457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.432804457
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.691695921
Short name T486
Test name
Test status
Simulation time 12754798657 ps
CPU time 47.95 seconds
Started Jul 22 05:48:07 PM PDT 24
Finished Jul 22 05:48:55 PM PDT 24
Peak memory 250320 kb
Host smart-88fad93e-eb4f-4838-a209-b40ba09c50ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691695921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.
691695921
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.2350442549
Short name T920
Test name
Test status
Simulation time 1741575571 ps
CPU time 10.68 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:20 PM PDT 24
Peak memory 220288 kb
Host smart-bcc775a4-11ad-46c7-8315-c1d873391be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350442549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2350442549
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1053378903
Short name T77
Test name
Test status
Simulation time 132322616 ps
CPU time 3.06 seconds
Started Jul 22 05:48:24 PM PDT 24
Finished Jul 22 05:48:28 PM PDT 24
Peak memory 232892 kb
Host smart-299813b0-6d5f-4065-b236-ed2f6fc0c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053378903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1053378903
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2642130181
Short name T262
Test name
Test status
Simulation time 1527892138 ps
CPU time 6.61 seconds
Started Jul 22 05:48:10 PM PDT 24
Finished Jul 22 05:48:17 PM PDT 24
Peak memory 224644 kb
Host smart-b17c6ba9-9625-4489-bc36-f9a33569dc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642130181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2642130181
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.3086851667
Short name T800
Test name
Test status
Simulation time 3213257207 ps
CPU time 5.14 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:12 PM PDT 24
Peak memory 224652 kb
Host smart-b1797e20-b825-4e8a-a8a2-17b966f35514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086851667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3086851667
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1573860989
Short name T973
Test name
Test status
Simulation time 1097781283 ps
CPU time 10.76 seconds
Started Jul 22 05:48:10 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 221776 kb
Host smart-46bbe5c4-9e7a-47d7-9117-86ddea54372c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1573860989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1573860989
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.3807964092
Short name T20
Test name
Test status
Simulation time 53008843 ps
CPU time 1.07 seconds
Started Jul 22 05:48:16 PM PDT 24
Finished Jul 22 05:48:17 PM PDT 24
Peak memory 207104 kb
Host smart-dd59c782-e0de-42d1-b520-13d9380326aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807964092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.3807964092
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.926541848
Short name T997
Test name
Test status
Simulation time 153836494 ps
CPU time 0.76 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:11 PM PDT 24
Peak memory 206168 kb
Host smart-199f68e5-4bd4-40c2-9a0b-1b2f01683593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926541848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.926541848
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.32601797
Short name T498
Test name
Test status
Simulation time 18327992910 ps
CPU time 15.94 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:22 PM PDT 24
Peak memory 216476 kb
Host smart-b17c4d85-19c9-4036-a3b4-84b9142d9b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32601797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.32601797
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2075173711
Short name T890
Test name
Test status
Simulation time 107204771 ps
CPU time 1.8 seconds
Started Jul 22 05:48:07 PM PDT 24
Finished Jul 22 05:48:10 PM PDT 24
Peak memory 216452 kb
Host smart-2f649fe6-dae6-40f2-83d7-0bbd00424f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075173711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2075173711
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1013842669
Short name T560
Test name
Test status
Simulation time 276832043 ps
CPU time 1.08 seconds
Started Jul 22 05:48:09 PM PDT 24
Finished Jul 22 05:48:11 PM PDT 24
Peak memory 207096 kb
Host smart-7aa55a78-2591-48be-9682-7c929eaac045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013842669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1013842669
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.4185877073
Short name T237
Test name
Test status
Simulation time 473648744 ps
CPU time 3.86 seconds
Started Jul 22 05:48:06 PM PDT 24
Finished Jul 22 05:48:11 PM PDT 24
Peak memory 232920 kb
Host smart-53ae2aa4-cc94-48cb-9c1f-fb1105a2164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185877073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.4185877073
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3396948529
Short name T542
Test name
Test status
Simulation time 12398064 ps
CPU time 0.75 seconds
Started Jul 22 05:48:19 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 205860 kb
Host smart-59415a77-67cf-42c2-a87d-4ff76bb33e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396948529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
396948529
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.299935107
Short name T429
Test name
Test status
Simulation time 41379791 ps
CPU time 2.11 seconds
Started Jul 22 05:48:12 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 224700 kb
Host smart-98ceb634-8dad-42af-88e2-5a860ddaa409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299935107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.299935107
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1395558688
Short name T325
Test name
Test status
Simulation time 18383162 ps
CPU time 0.77 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 207040 kb
Host smart-646940e3-7d6f-4c9d-bf70-dfbb35bc9c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395558688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1395558688
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.435718334
Short name T554
Test name
Test status
Simulation time 82563500 ps
CPU time 0.88 seconds
Started Jul 22 05:48:49 PM PDT 24
Finished Jul 22 05:48:51 PM PDT 24
Peak memory 216096 kb
Host smart-ea17896b-ac16-421d-b5d3-ece4c90c7c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435718334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.435718334
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2495526072
Short name T830
Test name
Test status
Simulation time 5466998168 ps
CPU time 63.49 seconds
Started Jul 22 05:48:15 PM PDT 24
Finished Jul 22 05:49:19 PM PDT 24
Peak memory 252108 kb
Host smart-8f3317c9-9bc9-47be-82a7-37c96b725a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495526072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2495526072
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.942289196
Short name T180
Test name
Test status
Simulation time 17759688952 ps
CPU time 160.86 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:51:00 PM PDT 24
Peak memory 250412 kb
Host smart-baa0151c-2ab8-4f17-aa87-81201bd7ae7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942289196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
942289196
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.786014987
Short name T765
Test name
Test status
Simulation time 52395793 ps
CPU time 2.68 seconds
Started Jul 22 05:48:15 PM PDT 24
Finished Jul 22 05:48:19 PM PDT 24
Peak memory 224652 kb
Host smart-b35f2a14-fcf8-4083-b7df-bfdcb175f24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786014987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.786014987
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.3786435819
Short name T998
Test name
Test status
Simulation time 4241745070 ps
CPU time 43.64 seconds
Started Jul 22 05:48:12 PM PDT 24
Finished Jul 22 05:48:56 PM PDT 24
Peak memory 257540 kb
Host smart-3eb2a08a-5659-4190-984d-378ad3ef700c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786435819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.3786435819
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3735548928
Short name T404
Test name
Test status
Simulation time 487262332 ps
CPU time 5.07 seconds
Started Jul 22 05:48:17 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 232752 kb
Host smart-bd637d72-4806-447f-9221-3462961df74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735548928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3735548928
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3074865193
Short name T617
Test name
Test status
Simulation time 1914384864 ps
CPU time 16.38 seconds
Started Jul 22 05:48:19 PM PDT 24
Finished Jul 22 05:48:37 PM PDT 24
Peak memory 224640 kb
Host smart-381b6182-c04f-40a9-8b54-e7b1af0e5933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074865193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3074865193
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2972508877
Short name T209
Test name
Test status
Simulation time 1210246668 ps
CPU time 5.07 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 232912 kb
Host smart-35bd025c-8dad-47bd-a825-4c4298ef430e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972508877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2972508877
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3972206649
Short name T762
Test name
Test status
Simulation time 331537630 ps
CPU time 7.15 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:21 PM PDT 24
Peak memory 251796 kb
Host smart-4ac4696a-d07b-4886-b08c-008c02e7a255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972206649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3972206649
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1627667401
Short name T785
Test name
Test status
Simulation time 235122103 ps
CPU time 5.11 seconds
Started Jul 22 05:48:18 PM PDT 24
Finished Jul 22 05:48:23 PM PDT 24
Peak memory 219036 kb
Host smart-f9b6b8d9-3aed-4e3b-9904-972dbd05de19
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1627667401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1627667401
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.460526841
Short name T159
Test name
Test status
Simulation time 47954368 ps
CPU time 0.91 seconds
Started Jul 22 05:48:15 PM PDT 24
Finished Jul 22 05:48:16 PM PDT 24
Peak memory 206852 kb
Host smart-7f5c602d-495d-407f-be18-92333e48a12b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460526841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.460526841
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.1639149292
Short name T459
Test name
Test status
Simulation time 2722572452 ps
CPU time 4.88 seconds
Started Jul 22 05:48:17 PM PDT 24
Finished Jul 22 05:48:22 PM PDT 24
Peak memory 216388 kb
Host smart-5b482189-d67a-48c7-90ea-710d494e8594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639149292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.1639149292
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3760896379
Short name T490
Test name
Test status
Simulation time 20217137866 ps
CPU time 19.32 seconds
Started Jul 22 05:48:17 PM PDT 24
Finished Jul 22 05:48:37 PM PDT 24
Peak memory 217468 kb
Host smart-7592e05b-180c-4a84-893f-093219341b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760896379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3760896379
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.353631911
Short name T966
Test name
Test status
Simulation time 13084030 ps
CPU time 0.98 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 207188 kb
Host smart-9a57794c-8f3e-4306-95e5-03ac76c2005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353631911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.353631911
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1382507456
Short name T626
Test name
Test status
Simulation time 111780772 ps
CPU time 0.84 seconds
Started Jul 22 05:48:13 PM PDT 24
Finished Jul 22 05:48:15 PM PDT 24
Peak memory 206108 kb
Host smart-71c468f9-0f7e-43d7-a7f9-84414adc5f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382507456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1382507456
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4068207892
Short name T206
Test name
Test status
Simulation time 790692449 ps
CPU time 12.46 seconds
Started Jul 22 05:48:17 PM PDT 24
Finished Jul 22 05:48:30 PM PDT 24
Peak memory 232856 kb
Host smart-9b6f45f0-0901-4bca-9e11-67ac26c37c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068207892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4068207892
Directory /workspace/9.spi_device_upload/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%