Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2655288	1			T1	1		T2	1		T3	15
all_values[1]	2655288	1			T1	1		T2	1		T3	15
all_values[2]	2655288	1			T1	1		T2	1		T3	15
all_values[3]	2655288	1			T1	1		T2	1		T3	15
all_values[4]	2655288	1			T1	1		T2	1		T3	15
all_values[5]	2655288	1			T1	1		T2	1		T3	15
all_values[6]	2655288	1			T1	1		T2	1		T3	15
all_values[7]	2655288	1			T1	1		T2	1		T3	15

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20817681

1

T1

8

T2

8

T3

120

auto[1]

424623

1

T14

90

T15

48

T16

93

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21217515

1

T1

8

T2

8

T3

120

auto[1]

24789

1

T4

923

T6

26

T28

81

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2598613	1			T1	1		T2	1		T3	15
all_values[0]	auto[0]	auto[1]	11369	1			T4	544		T6	13		T28	47
all_values[0]	auto[1]	auto[0]	44708	1			T14	6		T15	3		T16	3
all_values[0]	auto[1]	auto[1]	598	1			T14	2		T15	5		T16	4
all_values[1]	auto[0]	auto[0]	2596947	1			T1	1		T2	1		T3	15
all_values[1]	auto[0]	auto[1]	7263	1			T4	264		T6	13		T28	17
all_values[1]	auto[1]	auto[0]	50663	1			T14	5		T15	4		T16	6
all_values[1]	auto[1]	auto[1]	415	1			T14	4		T15	4		T16	5
all_values[2]	auto[0]	auto[0]	2550979	1			T1	1		T2	1		T3	15
all_values[2]	auto[0]	auto[1]	2597	1			T4	115		T28	17		T29	69
all_values[2]	auto[1]	auto[0]	101369	1			T14	8		T15	1		T16	9
all_values[2]	auto[1]	auto[1]	343	1			T14	2		T15	2		T16	4
all_values[3]	auto[0]	auto[0]	2609677	1			T1	1		T2	1		T3	15
all_values[3]	auto[0]	auto[1]	239	1			T14	8		T15	1		T16	3
all_values[3]	auto[1]	auto[0]	45131	1			T14	5		T15	5		T16	6
all_values[3]	auto[1]	auto[1]	241	1			T14	6		T15	3		T16	7
all_values[4]	auto[0]	auto[0]	2584813	1			T1	1		T2	1		T3	15
all_values[4]	auto[0]	auto[1]	203	1			T14	7		T15	1		T16	5
all_values[4]	auto[1]	auto[0]	70048	1			T14	7		T15	4		T16	7
all_values[4]	auto[1]	auto[1]	224	1			T14	4		T15	3		T16	2
all_values[5]	auto[0]	auto[0]	2650166	1			T1	1		T2	1		T3	15
all_values[5]	auto[0]	auto[1]	193	1			T14	3		T15	3		T16	3
all_values[5]	auto[1]	auto[0]	4718	1			T14	7		T15	2		T16	12
all_values[5]	auto[1]	auto[1]	211	1			T14	7		T15	2		T16	5
all_values[6]	auto[0]	auto[0]	2587384	1			T1	1		T2	1		T3	15
all_values[6]	auto[0]	auto[1]	221	1			T14	9		T15	5		T16	4
all_values[6]	auto[1]	auto[0]	67459	1			T14	8		T15	2		T16	6
all_values[6]	auto[1]	auto[1]	224	1			T14	6		T15	2		T16	3
all_values[7]	auto[0]	auto[0]	2616780	1			T1	1		T2	1		T3	15
all_values[7]	auto[0]	auto[1]	237	1			T14	5		T15	3		T17	5
all_values[7]	auto[1]	auto[0]	38060	1			T14	10		T15	3		T16	9
all_values[7]	auto[1]	auto[1]	211	1			T14	3		T15	3		T16	5