Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35086	1			T1	6		T4	183		T6	91
auto[SpiFlashAddrCfg]	7211	1			T3	3		T4	56		T6	16
auto[SpiFlashAddr3b]	8937	1			T1	8		T3	1		T4	63
auto[SpiFlashAddr4b]	7550	1			T2	1		T3	3		T4	44

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33743

1

T2

1

T3

7

T4

226

auto[1]

25041

1

T1

14

T4

120

T6

69

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31916

1

T1

8

T3

1

T4

167

auto[1]

26868

1

T1

6

T2

1

T3

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39750	1			T1	8		T3	3		T4	226
values[1]	1076	1			T4	13		T6	4		T11	3
values[2]	1436	1			T4	3		T6	6		T11	1
values[3]	1379	1			T1	2		T4	15		T8	6
values[4]	1392	1			T4	11		T6	4		T7	2
values[5]	1368	1			T4	6		T6	1		T27	9
values[6]	1325	1			T4	3		T6	3		T8	2
values[7]	1428	1			T3	1		T4	4		T6	3
values[8]	9630	1			T1	4		T2	1		T3	3

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30624

1

T1

14

T7

55

T8

14

auto[1]

28160

1

T2

1

T3

7

T4

346

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

55620

1

T1

12

T2

1

T3

7

write

3164

1

T1

2

T4

22

T6

11

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19000

1

T1

6

T3

4

T4

134

valids[0x1]

39784

1

T1

8

T2

1

T3

3

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1585	1			T4	11		T6	5		T8	2
internal_process_ops[0x5a]	1530	1			T4	9		T6	5		T11	1
internal_process_ops[0x05]	21435	1			T1	2		T4	80		T6	50
internal_process_ops[0x35]	1541	1			T4	7		T6	3		T27	3
internal_process_ops[0x15]	1507	1			T1	4		T4	17		T6	6
internal_process_ops[0x03]	1041	1			T3	3		T4	3		T6	2
internal_process_ops[0x0b]	1018	1			T2	1		T4	1		T7	2
internal_process_ops[0x3b]	1027	1			T4	6		T6	1		T8	2
internal_process_ops[0x6b]	1029	1			T1	2		T3	2		T4	5
internal_process_ops[0xbb]	1066	1			T1	2		T3	1		T4	6
internal_process_ops[0xeb]	1024	1			T3	1		T4	2		T6	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57262

1

T1

12

T2

1

T3

7

auto[1]

1522

1

T1

2

T4

14

T6

3

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

56508

1

T1

14

T2

1

T3

7

auto[1]

2276

1

T4

23

T6

4

T7

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10644

1

T7

45

T8

2

T13

27

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5996

1

T1

6

T27

21

T28

187

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1990

1

T7

2

T8

2

T27

11

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1721

1

T27

24

T28

18

T37

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2530

1

T7

4

T8

2

T27

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2167

1

T1

6

T27

25

T28

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2127

1

T8

8

T13

8

T26

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1826

1

T27

7

T28

19

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

139

1

T13

2

T27

1

T28

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

86

1

T28

1

T41

3

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

111

1

T17

1

T41

2

T42

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

120

1

T27

2

T28

2

T39

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

125

1

T27

2

T28

2

T41

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

107

1

T27

2

T40

3

T41

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

94

1

T27

2

T28

1

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

76

1

T48

2

T153

1

T154

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

116

1

T7

4

T40

1

T17

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

78

1

T28

1

T40

4

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

93

1

T40

2

T149

1

T42

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

89

1

T1

2

T27

2

T28

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T27

2

T18

2

T114

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

111

1

T28

2

T40

2

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

87

1

T27

1

T18

3

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

95

1

T37

2

T17

2

T18

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10175

1

T4

134

T6

50

T11

9

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7468

1

T4

46

T6

39

T29

104

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1409

1

T3

3

T4

26

T6

8

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1297

1

T4

25

T6

4

T29

26

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1802

1

T3

1

T4

29

T6

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1653

1

T4

26

T6

11

T29

28

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1469

1

T2

1

T3

3

T4

23

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1346

1

T4

15

T6

7

T11

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

80

1

T4

1

T29

4

T36

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

81

1

T4

2

T29

1

T36

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

99

1

T6

2

T36

6

T44

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

87

1

T36

2

T47

1

T44

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

92

1

T4

2

T36

1

T43

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

90

1

T4

1

T6

1

T29

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

103

1

T4

2

T6

2

T29

5

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

107

1

T6

1

T44

3

T73

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

102

1

T4

2

T29

3

T36

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

107

1

T4

3

T29

2

T73

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

104

1

T6

2

T43

1

T73

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

96

1

T4

3

T36

2

T47

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

91

1

T4

1

T6

1

T36

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

96

1

T4

2

T6

1

T29

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

110

1

T6

1

T43

2

T73

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

96

1

T4

3

T29

3

T36

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3933	1			T7	2		T26	2		T27	25
auto[0]	values[0]	valids[0x1]	15751	1			T1	8		T7	47		T8	2
auto[0]	values[1]	valids[0x1]	540	1			T27	9		T28	8		T40	5
auto[0]	values[2]	valids[0x0]	507	1			T27	5		T28	9		T40	4
auto[0]	values[2]	valids[0x1]	307	1			T27	6		T40	3		T149	1
auto[0]	values[3]	valids[0x0]	500	1			T1	2		T8	4		T27	2
auto[0]	values[3]	valids[0x1]	301	1			T8	2		T27	2		T28	1
auto[0]	values[4]	valids[0x0]	494	1			T27	7		T28	2		T40	2
auto[0]	values[4]	valids[0x1]	307	1			T7	2		T27	2		T28	3
auto[0]	values[5]	valids[0x0]	519	1			T27	5		T28	7		T155	2
auto[0]	values[5]	valids[0x1]	299	1			T27	4		T28	6		T156	2
auto[0]	values[6]	valids[0x0]	490	1			T13	2		T27	7		T28	1
auto[0]	values[6]	valids[0x1]	294	1			T8	2		T28	2		T155	2
auto[0]	values[7]	valids[0x0]	566	1			T27	9		T28	4		T40	2
auto[0]	values[7]	valids[0x1]	256	1			T13	2		T27	3		T28	6
auto[0]	values[8]	valids[0x0]	3616	1			T1	4		T7	2		T8	2
auto[0]	values[8]	valids[0x1]	1944	1			T7	2		T8	2		T26	4
auto[1]	values[0]	valids[0x0]	3845	1			T4	63		T6	19		T11	7
auto[1]	values[0]	valids[0x1]	16221	1			T3	3		T4	163		T6	77
auto[1]	values[1]	valids[0x1]	536	1			T4	13		T6	4		T11	3
auto[1]	values[2]	valids[0x0]	362	1			T4	2		T6	4		T29	7
auto[1]	values[2]	valids[0x1]	260	1			T4	1		T6	2		T11	1
auto[1]	values[3]	valids[0x0]	337	1			T4	13		T29	3		T36	7
auto[1]	values[3]	valids[0x1]	241	1			T4	2		T29	2		T36	3
auto[1]	values[4]	valids[0x0]	348	1			T4	6		T6	2		T11	2
auto[1]	values[4]	valids[0x1]	243	1			T4	5		T6	2		T29	2
auto[1]	values[5]	valids[0x0]	330	1			T4	4		T29	17		T36	4
auto[1]	values[5]	valids[0x1]	220	1			T4	2		T6	1		T29	4
auto[1]	values[6]	valids[0x0]	328	1			T4	2		T6	2		T11	3
auto[1]	values[6]	valids[0x1]	213	1			T4	1		T6	1		T29	2
auto[1]	values[7]	valids[0x0]	374	1			T3	1		T4	3		T6	2
auto[1]	values[7]	valids[0x1]	232	1			T4	1		T6	1		T36	4
auto[1]	values[8]	valids[0x0]	2451	1			T3	3		T4	41		T6	17
auto[1]	values[8]	valids[0x1]	1619	1			T2	1		T4	24		T6	12