Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3322406

1

T1

1

T2

17921

T3

14493

auto[1]

32070

1

T4

66

T6

46

T7

39

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

928156

1

T1

1

T2

17921

T3

14493

auto[1]

2426320

1

T4

15033

T6

4044

T7

6005

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	701585	1			T1	1		T2	564		T3	10
auto[524288:1048575]	357110	1			T2	2630		T3	2713		T4	1059
auto[1048576:1572863]	419150	1			T2	1718		T3	6235		T4	2010
auto[1572864:2097151]	324714	1			T2	352		T4	2125		T27	4978
auto[2097152:2621439]	429076	1			T2	2248		T4	1689		T6	550
auto[2621440:3145727]	387371	1			T2	4673		T3	139		T4	4852
auto[3145728:3670015]	352777	1			T2	5736		T3	1		T4	310
auto[3670016:4194303]	382693	1			T3	5395		T4	775		T6	400

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2459300

1

T1

1

T2

15

T3

71

auto[1]

895176

1

T2

17906

T3

14422

T4

3

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2930334

1

T1

1

T2

17921

T3

14493

auto[1]

424142

1

T4

4440

T6

2860

T27

5862

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	202255	1			T1	1		T2	564		T3	10
auto[0]	auto[0]	auto[0:524287]	auto[1]	423400	1			T4	2310		T6	259		T7	5970
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	95838	1			T2	2630		T3	2713		T4	3
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	203968	1			T4	512		T6	5		T27	257
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	134000	1			T2	1718		T3	6235		T4	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	237658	1			T4	2000		T27	256		T28	213
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	100601	1			T2	352		T4	11		T27	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	175880	1			T4	2091		T27	2018		T28	1961
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	114985	1			T2	2248		T4	11		T6	6
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	264131	1			T4	645		T6	516		T28	3095
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	84882	1			T2	4673		T3	139		T4	17
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	246297	1			T4	2400		T27	519		T28	2023
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	79818	1			T2	5736		T3	1		T4	4
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	224752	1			T4	6		T6	2		T27	259
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	99627	1			T3	5395		T4	4		T6	10
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	217057	1			T4	640		T6	388		T27	2694
auto[0]	auto[1]	auto[0:524287]	auto[0]	1924	1			T4	1		T27	1		T28	9
auto[0]	auto[1]	auto[0:524287]	auto[1]	69263	1			T4	1		T28	1258		T36	768
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1346	1			T4	2		T6	1		T27	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	52072	1			T4	541		T6	2831		T27	2706
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2989	1			T4	1		T29	1		T36	35
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	40772	1			T4	5		T29	514		T36	384
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	610	1			T4	5		T27	2		T28	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43715	1			T27	2955		T28	257		T44	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	650	1			T4	2		T6	4		T27	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	46429	1			T4	1024		T6	1		T27	166
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	905	1			T4	8		T27	1		T43	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	52235	1			T4	2408		T43	1		T44	3144
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1203	1			T4	9		T29	2		T36	32
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	43024	1			T4	278		T29	768		T43	8
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	2782	1			T4	2		T27	4		T36	25
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	57338	1			T4	129		T27	6		T28	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	474	1			T4	1		T6	1		T7	4
auto[1]	auto[0]	auto[0:524287]	auto[1]	3369	1			T4	4		T6	2		T7	35
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	398	1			T6	1		T27	1		T29	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1808	1			T6	17		T27	4		T29	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	386	1			T29	1		T43	1		T44	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2657	1			T29	5		T43	1		T44	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	337	1			T4	5		T28	2		T29	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2126	1			T4	13		T28	69		T29	40
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	364	1			T4	3		T36	3		T44	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2079	1			T4	4		T44	4		T40	375
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	341	1			T4	4		T27	2		T29	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2174	1			T4	5		T27	13		T29	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	363	1			T4	2		T27	3		T29	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2899	1			T4	1		T27	33		T29	43
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	355	1			T6	1		T28	1		T29	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	5055	1			T6	1		T28	11		T29	21
auto[1]	auto[1]	auto[0:524287]	auto[0]	97	1			T4	1		T28	1		T36	3
auto[1]	auto[1]	auto[0:524287]	auto[1]	803	1			T4	2		T28	12		T18	2
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	95	1			T4	1		T36	5		T40	7
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	1585	1			T40	970		T15	12		T16	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	97	1			T44	1		T40	5		T42	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	591	1			T44	2		T42	20		T20	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	84	1			T28	1		T40	14		T41	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	1361	1			T28	1		T40	358		T41	10
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	78	1			T6	1		T40	4		T73	8
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	360	1			T6	22		T42	12		T153	28
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	108	1			T4	2		T43	1		T44	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	429	1			T4	8		T44	1		T73	74
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	97	1			T4	4		T36	5		T42	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	621	1			T4	6		T42	62		T181	27
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	67	1			T27	1		T20	1		T169	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	412	1			T27	16		T20	3		T169	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2018018	1			T1	1		T2	15		T3	71
auto[0]	auto[0]	auto[1]	887131	1			T2	17906		T3	14422		T4	2
auto[0]	auto[1]	auto[0]	409857	1			T4	4416		T6	2837		T27	5845
auto[0]	auto[1]	auto[1]	7400	1			T208	295		T41	1		T42	1
auto[1]	auto[0]	auto[0]	24684	1			T4	41		T6	21		T7	37
auto[1]	auto[0]	auto[1]	501	1			T4	1		T6	2		T7	2
auto[1]	auto[1]	auto[0]	6741	1			T4	24		T6	22		T27	17
auto[1]	auto[1]	auto[1]	144	1			T6	1		T36	3		T40	4