Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2655288	1			T1	1		T2	1		T3	15
all_pins[1]	2655288	1			T1	1		T2	1		T3	15
all_pins[2]	2655288	1			T1	1		T2	1		T3	15
all_pins[3]	2655288	1			T1	1		T2	1		T3	15
all_pins[4]	2655288	1			T1	1		T2	1		T3	15
all_pins[5]	2655288	1			T1	1		T2	1		T3	15
all_pins[6]	2655288	1			T1	1		T2	1		T3	15
all_pins[7]	2655288	1			T1	1		T2	1		T3	15

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21172270	1			T1	8		T2	8		T3	120
values[0x1]	70034	1			T14	34		T15	24		T16	35
transitions[0x0=>0x1]	69009	1			T14	26		T15	18		T16	25
transitions[0x1=>0x0]	69024	1			T14	26		T15	18		T16	25

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2654655	1			T1	1		T2	1		T3	15
all_pins[0]	values[0x1]	633	1			T14	2		T15	5		T16	4
all_pins[0]	transitions[0x0=>0x1]	545	1			T14	1		T15	3		T16	2
all_pins[0]	transitions[0x1=>0x0]	359	1			T14	3		T15	2		T16	3
all_pins[1]	values[0x0]	2654841	1			T1	1		T2	1		T3	15
all_pins[1]	values[0x1]	447	1			T14	4		T15	4		T16	5
all_pins[1]	transitions[0x0=>0x1]	316	1			T14	3		T15	4		T16	4
all_pins[1]	transitions[0x1=>0x0]	231	1			T14	1		T15	2		T16	3
all_pins[2]	values[0x0]	2654926	1			T1	1		T2	1		T3	15
all_pins[2]	values[0x1]	362	1			T14	2		T15	2		T16	4
all_pins[2]	transitions[0x0=>0x1]	320	1			T14	2		T15	1		T16	4
all_pins[2]	transitions[0x1=>0x0]	199	1			T14	6		T15	2		T16	7
all_pins[3]	values[0x0]	2655047	1			T1	1		T2	1		T3	15
all_pins[3]	values[0x1]	241	1			T14	6		T15	3		T16	7
all_pins[3]	transitions[0x0=>0x1]	180	1			T14	5		T15	2		T16	6
all_pins[3]	transitions[0x1=>0x0]	163	1			T14	3		T15	2		T16	1
all_pins[4]	values[0x0]	2655064	1			T1	1		T2	1		T3	15
all_pins[4]	values[0x1]	224	1			T14	4		T15	3		T16	2
all_pins[4]	transitions[0x0=>0x1]	167	1			T14	3		T15	3		T16	1
all_pins[4]	transitions[0x1=>0x0]	627	1			T14	6		T15	2		T16	4
all_pins[5]	values[0x0]	2654604	1			T1	1		T2	1		T3	15
all_pins[5]	values[0x1]	684	1			T14	7		T15	2		T16	5
all_pins[5]	transitions[0x0=>0x1]	167	1			T14	5		T15	1		T16	4
all_pins[5]	transitions[0x1=>0x0]	66715	1			T14	4		T15	1		T16	2
all_pins[6]	values[0x0]	2588056	1			T1	1		T2	1		T3	15
all_pins[6]	values[0x1]	67232	1			T14	6		T15	2		T16	3
all_pins[6]	transitions[0x0=>0x1]	67168	1			T14	5		T15	2		T19	1
all_pins[6]	transitions[0x1=>0x0]	147	1			T14	2		T15	3		T16	2
all_pins[7]	values[0x0]	2655077	1			T1	1		T2	1		T3	15
all_pins[7]	values[0x1]	211	1			T14	3		T15	3		T16	5
all_pins[7]	transitions[0x0=>0x1]	146	1			T14	2		T15	2		T16	4
all_pins[7]	transitions[0x1=>0x0]	583	1			T14	1		T15	4		T16	3